1 #ifndef __BDK_CSRS_RST_H__
2 #define __BDK_CSRS_RST_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44 #include <bdk-minimal.h>
45 #include <libbdk-arch/bdk-csr.h>
46
47 /**
48 * @file
49 *
50 * Configuration and status register (CSR) address and type definitions for
51 * Cavium RST.
52 *
53 * This file is auto generated. Do not edit.
54 *
55 */
56
57 /**
58 * Enumeration rst_bar_e
59 *
60 * RST Base Address Register Enumeration
61 * Enumerates the base address registers.
62 */
63 #define BDK_RST_BAR_E_RST_PF_BAR0_CN8 (0x87e006000000ll)
64 #define BDK_RST_BAR_E_RST_PF_BAR0_CN8_SIZE 0x800000ull
65 #define BDK_RST_BAR_E_RST_PF_BAR0_CN9 (0x87e006000000ll)
66 #define BDK_RST_BAR_E_RST_PF_BAR0_CN9_SIZE 0x10000ull
67 #define BDK_RST_BAR_E_RST_PF_BAR2 (0x87e00a000000ll)
68 #define BDK_RST_BAR_E_RST_PF_BAR2_SIZE 0x10000ull
69 #define BDK_RST_BAR_E_RST_PF_BAR4 (0x87e006f00000ll)
70 #define BDK_RST_BAR_E_RST_PF_BAR4_SIZE 0x100000ull
71
72 /**
73 * Enumeration rst_boot_fail_e
74 *
75 * RST Boot Failure Code Enumeration
76 * Enumerates the reasons for boot failure, returned to post-boot code
77 * in argument register 0 and blinked on GPIO\<11\>.
78 */
79 #define BDK_RST_BOOT_FAIL_E_AUTH (6)
80 #define BDK_RST_BOOT_FAIL_E_BUS_ERROR (0xb)
81 #define BDK_RST_BOOT_FAIL_E_DEVICE (3)
82 #define BDK_RST_BOOT_FAIL_E_GOOD_CN8 (0)
83 #define BDK_RST_BOOT_FAIL_E_GOOD_CN9 (1)
84 #define BDK_RST_BOOT_FAIL_E_HASH (8)
85 #define BDK_RST_BOOT_FAIL_E_KEY (7)
86 #define BDK_RST_BOOT_FAIL_E_MAGIC (4)
87 #define BDK_RST_BOOT_FAIL_E_MCORE (5)
88 #define BDK_RST_BOOT_FAIL_E_METH (2)
89 #define BDK_RST_BOOT_FAIL_E_SCRIPT_ACC_ERROR (0xa)
90 #define BDK_RST_BOOT_FAIL_E_SCRIPT_INVALID (9)
91 #define BDK_RST_BOOT_FAIL_E_UNINIT (0)
92
93 /**
94 * Enumeration rst_boot_method_e
95 *
96 * RST Primary Boot-strap Method Enumeration
97 * Enumerates the primary (first choice) and secondary (second choice) boot
98 * device. Primary boot method is selected with the straps
99 * GPIO_STRAP_PIN_E::BOOT_METHOD2..0, and secondary is selected with the straps
100 * GPIO_STRAP_PIN_E::BOOT_METHOD5..3.
101 *
102 * To disable the secondary method, use ::REMOTE.
103 */
104 #define BDK_RST_BOOT_METHOD_E_CCPI0 (9)
105 #define BDK_RST_BOOT_METHOD_E_CCPI1 (0xa)
106 #define BDK_RST_BOOT_METHOD_E_CCPI2 (0xb)
107 #define BDK_RST_BOOT_METHOD_E_EMMC_CS0 (0)
108 #define BDK_RST_BOOT_METHOD_E_EMMC_CS1 (1)
109 #define BDK_RST_BOOT_METHOD_E_EMMC_LS (3)
110 #define BDK_RST_BOOT_METHOD_E_EMMC_SS (2)
111 #define BDK_RST_BOOT_METHOD_E_PCIE0 (0xc)
112 #define BDK_RST_BOOT_METHOD_E_PCIE2 (0xd)
113 #define BDK_RST_BOOT_METHOD_E_REMOTE_CN8 (8)
114 #define BDK_RST_BOOT_METHOD_E_REMOTE_CN9 (7)
115 #define BDK_RST_BOOT_METHOD_E_SPI0_CS0 (2)
116 #define BDK_RST_BOOT_METHOD_E_SPI0_CS1 (3)
117 #define BDK_RST_BOOT_METHOD_E_SPI1_CS0 (4)
118 #define BDK_RST_BOOT_METHOD_E_SPI1_CS1 (5)
119 #define BDK_RST_BOOT_METHOD_E_SPI24 (5)
120 #define BDK_RST_BOOT_METHOD_E_SPI32 (6)
121
122 /**
123 * Enumeration rst_dev_e
124 *
125 * Programmable Reset Device Enumeration
126 * Enumerates devices that have programmable reset domains, and index {a} of RST_DEV_MAP().
127 */
128 #define BDK_RST_DEV_E_AVS (1)
129 #define BDK_RST_DEV_E_CGXX(a) (0x12 + (a))
130 #define BDK_RST_DEV_E_EMMC (0x19)
131 #define BDK_RST_DEV_E_GSERX(a) (0x1a + (a))
132 #define BDK_RST_DEV_E_MPIX(a) (2 + (a))
133 #define BDK_RST_DEV_E_NCSI (0)
134 #define BDK_RST_DEV_E_PEMX(a) (0x28 + (a))
135 #define BDK_RST_DEV_E_ROC_OCLA (0x18)
136 #define BDK_RST_DEV_E_SGPIO (0x17)
137 #define BDK_RST_DEV_E_SMI (0x16)
138 #define BDK_RST_DEV_E_TWSX(a) (4 + (a))
139 #define BDK_RST_DEV_E_UAAX(a) (0xa + (a))
140
141 /**
142 * Enumeration rst_domain_e
143 *
144 * RST Domain Enumeration
145 * This enumerates the values of RST_DEV_MAP()[DMN].
146 */
147 #define BDK_RST_DOMAIN_E_CHIP (0)
148 #define BDK_RST_DOMAIN_E_CORE (1)
149 #define BDK_RST_DOMAIN_E_MCP (2)
150 #define BDK_RST_DOMAIN_E_OFF (4)
151 #define BDK_RST_DOMAIN_E_SCP (3)
152
153 /**
154 * Enumeration rst_int_vec_e
155 *
156 * RST MSI-X Vector Enumeration
157 * Enumerates the MSI-X interrupt vectors.
158 */
159 #define BDK_RST_INT_VEC_E_INTS (0)
160
161 /**
162 * Enumeration rst_source_e
163 *
164 * RST Cause Enumeration
165 * Enumerates the reset sources for both reset domain mapping and cause of last reset,
166 * corresponding to the bit numbers of RST_LBOOT.
167 */
168 #define BDK_RST_SOURCE_E_CHIPKILL (4)
169 #define BDK_RST_SOURCE_E_CHIP_RESET_PIN (2)
170 #define BDK_RST_SOURCE_E_CHIP_SOFT (3)
171 #define BDK_RST_SOURCE_E_COLD_SOFT (1)
172 #define BDK_RST_SOURCE_E_CORE_RESET_PIN (0xb)
173 #define BDK_RST_SOURCE_E_CORE_SOFT (0xc)
174 #define BDK_RST_SOURCE_E_CORE_WDOG (0xd)
175 #define BDK_RST_SOURCE_E_DCOK_PIN (0)
176 #define BDK_RST_SOURCE_E_MCP_RESET_PIN (8)
177 #define BDK_RST_SOURCE_E_MCP_SOFT (9)
178 #define BDK_RST_SOURCE_E_MCP_WDOG (0xa)
179 #define BDK_RST_SOURCE_E_OCX (0xe)
180 #define BDK_RST_SOURCE_E_PEM_LINKDOWNX(a) (0x12 + 4 * (a))
181 #define BDK_RST_SOURCE_E_PEM_PFFLRX(a) (0x13 + 4 * (a))
182 #define BDK_RST_SOURCE_E_PERST_PINX(a) (0x11 + 4 * (a))
183 #define BDK_RST_SOURCE_E_PERST_SOFTX(a) (0x10 + 4 * (a))
184 #define BDK_RST_SOURCE_E_RSVD_F (0xf)
185 #define BDK_RST_SOURCE_E_SCP_RESET_PIN (5)
186 #define BDK_RST_SOURCE_E_SCP_SOFT (6)
187 #define BDK_RST_SOURCE_E_SCP_WDOG (7)
188
189 /**
190 * Structure rst_boot_stat_s
191 *
192 * BOOT_STATUS field Structure
193 * The rom boot code stores this data in the RST_BOOT_STATUS register, once per each boot attempt.
194 */
195 union bdk_rst_boot_stat_s
196 {
197 uint32_t u;
198 struct bdk_rst_boot_stat_s_s
199 {
200 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
201 uint32_t reserved_16_31 : 16;
202 uint32_t trusted : 1; /**< [ 15: 15] This was a trusted-mode boot. */
203 uint32_t primary : 1; /**< [ 14: 14] This was a boot from the primary device. */
204 uint32_t scr_done : 1; /**< [ 13: 13] The ROM script ran to completion on this boot. */
205 uint32_t reserved_7_12 : 6;
206 uint32_t boot_method : 3; /**< [ 6: 4] The boot method for this boot attempt RST_BOOT_METHOD_E. */
207 uint32_t fail : 4; /**< [ 3: 0] The failure code for this boot attempt RST_BOOT_FAIL_E. */
208 #else /* Word 0 - Little Endian */
209 uint32_t fail : 4; /**< [ 3: 0] The failure code for this boot attempt RST_BOOT_FAIL_E. */
210 uint32_t boot_method : 3; /**< [ 6: 4] The boot method for this boot attempt RST_BOOT_METHOD_E. */
211 uint32_t reserved_7_12 : 6;
212 uint32_t scr_done : 1; /**< [ 13: 13] The ROM script ran to completion on this boot. */
213 uint32_t primary : 1; /**< [ 14: 14] This was a boot from the primary device. */
214 uint32_t trusted : 1; /**< [ 15: 15] This was a trusted-mode boot. */
215 uint32_t reserved_16_31 : 16;
216 #endif /* Word 0 - End */
217 } s;
218 /* struct bdk_rst_boot_stat_s_s cn; */
219 };
220
221 /**
222 * Structure rst_pp_pwr_s
223 *
224 * INTERNAL: Core Reset Power Delivery Structure
225 *
226 * This structure specifies the layout of RTL reset and power delivery. It is not visible to software.
227 */
228 union bdk_rst_pp_pwr_s
229 {
230 uint32_t u;
231 struct bdk_rst_pp_pwr_s_s
232 {
233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
234 uint32_t reserved_10_31 : 22;
235 uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid.. */
236 uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
237 uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
238 uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
239 uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
240 #else /* Word 0 - Little Endian */
241 uint32_t rst : 1; /**< [ 0: 0] Reset control for the core specified by PPVID. */
242 uint32_t pwrdwn : 1; /**< [ 1: 1] Core does not require power. */
243 uint32_t dbg_rst : 1; /**< [ 2: 2] Reset control for the core specified by PPVID. */
244 uint32_t ppvid : 6; /**< [ 8: 3] Virtual core number. */
245 uint32_t valid : 1; /**< [ 9: 9] Data transmitted on interface is valid.. */
246 uint32_t reserved_10_31 : 22;
247 #endif /* Word 0 - End */
248 } s;
249 /* struct bdk_rst_pp_pwr_s_s cn; */
250 };
251
252 /**
253 * Register (RSL) rst_ap#_affinity_const
254 *
255 * RST Virtual AP Affinity Map Register
256 * This register indicates the processor affinity identification and logical core
257 * number mapping to physical core numbers. This is indexed by logical core number.
258 *
259 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
260 */
261 union bdk_rst_apx_affinity_const
262 {
263 uint64_t u;
264 struct bdk_rst_apx_affinity_const_s
265 {
266 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
267 uint64_t reserved_56_63 : 8;
268 uint64_t core : 8; /**< [ 55: 48](RO) Physical core number. */
269 uint64_t reserved_44_47 : 4;
270 uint64_t phy_clu : 4; /**< [ 43: 40](RO) Physical cluster number. */
271 uint64_t reserved_36_39 : 4;
272 uint64_t phy_core : 4; /**< [ 35: 32](RO) Physical core-within-cluster number. */
273 uint64_t fov : 1; /**< [ 31: 31](RO) Set to indicate if the fields are valid. */
274 uint64_t u : 1; /**< [ 30: 30](RO) Set to indicate processors are part of a multprocessor system. */
275 uint64_t reserved_25_29 : 5;
276 uint64_t mt : 1; /**< [ 24: 24](RO) Set to indicate multithreaded and [AFF0] is thread number in core. */
277 uint64_t aff2 : 8; /**< [ 23: 16](RO/H) Affinity 2 for this logical core number. In CNXXXX, the node id. */
278 uint64_t aff1 : 8; /**< [ 15: 8](RO/H) Affinity 1 for this logical core number. In CNXXXX, the logical cluster id. */
279 uint64_t aff0 : 8; /**< [ 7: 0](RO/H) Affinity 0 for this logical core number. In CNXXXX, the logical core number within a cluster. */
280 #else /* Word 0 - Little Endian */
281 uint64_t aff0 : 8; /**< [ 7: 0](RO/H) Affinity 0 for this logical core number. In CNXXXX, the logical core number within a cluster. */
282 uint64_t aff1 : 8; /**< [ 15: 8](RO/H) Affinity 1 for this logical core number. In CNXXXX, the logical cluster id. */
283 uint64_t aff2 : 8; /**< [ 23: 16](RO/H) Affinity 2 for this logical core number. In CNXXXX, the node id. */
284 uint64_t mt : 1; /**< [ 24: 24](RO) Set to indicate multithreaded and [AFF0] is thread number in core. */
285 uint64_t reserved_25_29 : 5;
286 uint64_t u : 1; /**< [ 30: 30](RO) Set to indicate processors are part of a multprocessor system. */
287 uint64_t fov : 1; /**< [ 31: 31](RO) Set to indicate if the fields are valid. */
288 uint64_t phy_core : 4; /**< [ 35: 32](RO) Physical core-within-cluster number. */
289 uint64_t reserved_36_39 : 4;
290 uint64_t phy_clu : 4; /**< [ 43: 40](RO) Physical cluster number. */
291 uint64_t reserved_44_47 : 4;
292 uint64_t core : 8; /**< [ 55: 48](RO) Physical core number. */
293 uint64_t reserved_56_63 : 8;
294 #endif /* Word 0 - End */
295 } s;
296 /* struct bdk_rst_apx_affinity_const_s cn; */
297 };
298 typedef union bdk_rst_apx_affinity_const bdk_rst_apx_affinity_const_t;
299
300 static inline uint64_t BDK_RST_APX_AFFINITY_CONST(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_APX_AFFINITY_CONST(unsigned long a)301 static inline uint64_t BDK_RST_APX_AFFINITY_CONST(unsigned long a)
302 {
303 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=23))
304 return 0x87e006001000ll + 8ll * ((a) & 0x1f);
305 __bdk_csr_fatal("RST_APX_AFFINITY_CONST", 1, a, 0, 0, 0);
306 }
307
308 #define typedef_BDK_RST_APX_AFFINITY_CONST(a) bdk_rst_apx_affinity_const_t
309 #define bustype_BDK_RST_APX_AFFINITY_CONST(a) BDK_CSR_TYPE_RSL
310 #define basename_BDK_RST_APX_AFFINITY_CONST(a) "RST_APX_AFFINITY_CONST"
311 #define device_bar_BDK_RST_APX_AFFINITY_CONST(a) 0x0 /* PF_BAR0 */
312 #define busnum_BDK_RST_APX_AFFINITY_CONST(a) (a)
313 #define arguments_BDK_RST_APX_AFFINITY_CONST(a) (a),-1,-1,-1
314
315 /**
316 * Register (RSL) rst_bist_active
317 *
318 * RST BIST Active Status Register
319 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
320 */
321 union bdk_rst_bist_active
322 {
323 uint64_t u;
324 struct bdk_rst_bist_active_s
325 {
326 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
327 uint64_t reserved_6_63 : 58;
328 uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
329 accociated with this group are being tested. */
330 uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
331 accociated with this access are being tested. */
332 uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories accociated with
333 the SCP domain are being tested. */
334 uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories accociated with
335 the MCP domain are being tested. */
336 uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories accociated with
337 the core domain are being tested. */
338 uint64_t reserved_0 : 1;
339 #else /* Word 0 - Little Endian */
340 uint64_t reserved_0 : 1;
341 uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain BIST in progress. When set, memories accociated with
342 the core domain are being tested. */
343 uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain BIST in progress. When set, memories accociated with
344 the MCP domain are being tested. */
345 uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain BIST in progress. When set, memories accociated with
346 the SCP domain are being tested. */
347 uint64_t csr : 1; /**< [ 4: 4](RO/H) BIST in progress due to access to RST_DEV_MAP(). When set, memories
348 accociated with this access are being tested. */
349 uint64_t ap : 1; /**< [ 5: 5](RO/H) BIST in progress due to AP cores being put into reset. When set, memories
350 accociated with this group are being tested. */
351 uint64_t reserved_6_63 : 58;
352 #endif /* Word 0 - End */
353 } s;
354 /* struct bdk_rst_bist_active_s cn; */
355 };
356 typedef union bdk_rst_bist_active bdk_rst_bist_active_t;
357
358 #define BDK_RST_BIST_ACTIVE BDK_RST_BIST_ACTIVE_FUNC()
359 static inline uint64_t BDK_RST_BIST_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_BIST_ACTIVE_FUNC(void)360 static inline uint64_t BDK_RST_BIST_ACTIVE_FUNC(void)
361 {
362 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
363 return 0x87e006001890ll;
364 __bdk_csr_fatal("RST_BIST_ACTIVE", 0, 0, 0, 0, 0);
365 }
366
367 #define typedef_BDK_RST_BIST_ACTIVE bdk_rst_bist_active_t
368 #define bustype_BDK_RST_BIST_ACTIVE BDK_CSR_TYPE_RSL
369 #define basename_BDK_RST_BIST_ACTIVE "RST_BIST_ACTIVE"
370 #define device_bar_BDK_RST_BIST_ACTIVE 0x0 /* PF_BAR0 */
371 #define busnum_BDK_RST_BIST_ACTIVE 0
372 #define arguments_BDK_RST_BIST_ACTIVE -1,-1,-1,-1
373
374 /**
375 * Register (RSL) rst_bist_timer
376 *
377 * INTERNAL: RST BIST Timer Register
378 *
379 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
380 */
381 union bdk_rst_bist_timer
382 {
383 uint64_t u;
384 struct bdk_rst_bist_timer_s
385 {
386 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
387 uint64_t reserved_29_63 : 35;
388 uint64_t count : 29; /**< [ 28: 0](RO) Number of 50 MHz reference clocks that have elapsed during BIST and repair during the last
389 reset.
390 If MSB is set the BIST chain did not complete as expected. */
391 #else /* Word 0 - Little Endian */
392 uint64_t count : 29; /**< [ 28: 0](RO) Number of 50 MHz reference clocks that have elapsed during BIST and repair during the last
393 reset.
394 If MSB is set the BIST chain did not complete as expected. */
395 uint64_t reserved_29_63 : 35;
396 #endif /* Word 0 - End */
397 } s;
398 /* struct bdk_rst_bist_timer_s cn8; */
399 struct bdk_rst_bist_timer_cn9
400 {
401 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
402 uint64_t reserved_29_63 : 35;
403 uint64_t count : 29; /**< [ 28: 0](RO/H) Number of 100 MHz reference clocks that have elapsed during the
404 last BIST operation. If MSB is set the BIST did not
405 complete as expected. */
406 #else /* Word 0 - Little Endian */
407 uint64_t count : 29; /**< [ 28: 0](RO/H) Number of 100 MHz reference clocks that have elapsed during the
408 last BIST operation. If MSB is set the BIST did not
409 complete as expected. */
410 uint64_t reserved_29_63 : 35;
411 #endif /* Word 0 - End */
412 } cn9;
413 };
414 typedef union bdk_rst_bist_timer bdk_rst_bist_timer_t;
415
416 #define BDK_RST_BIST_TIMER BDK_RST_BIST_TIMER_FUNC()
417 static inline uint64_t BDK_RST_BIST_TIMER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_BIST_TIMER_FUNC(void)418 static inline uint64_t BDK_RST_BIST_TIMER_FUNC(void)
419 {
420 return 0x87e006001760ll;
421 }
422
423 #define typedef_BDK_RST_BIST_TIMER bdk_rst_bist_timer_t
424 #define bustype_BDK_RST_BIST_TIMER BDK_CSR_TYPE_RSL
425 #define basename_BDK_RST_BIST_TIMER "RST_BIST_TIMER"
426 #define device_bar_BDK_RST_BIST_TIMER 0x0 /* PF_BAR0 */
427 #define busnum_BDK_RST_BIST_TIMER 0
428 #define arguments_BDK_RST_BIST_TIMER -1,-1,-1,-1
429
430 /**
431 * Register (RSL) rst_boot
432 *
433 * RST Boot Register
434 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
435 */
436 union bdk_rst_boot
437 {
438 uint64_t u;
439 struct bdk_rst_boot_s
440 {
441 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
442 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
443 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
444 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
445 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
446 uint64_t reserved_61_62 : 2;
447 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
448 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
449 strap GPIO_STRAP\<10\> are set. */
450 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
451 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
452 RST_BOOT[CHIPKILL]=1. */
453 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
454 uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
455 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
456 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
457 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
458
459 Software must write a one to this bit when the chain of trust is broken. */
460 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
461 allowed in the part.
462 This state persists across soft and warm resets.
463
464 Internal:
465 This state will persist across a simulation */
466 uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
467 the EJTAG TAP controller will be disabled. This field does not
468 control the SCP EJTAG interface (See EJTAGDIS).
469 This field resets to one in trusted mode otherwise it is cleared.
470 This field is reinitialized with a cold domain reset. */
471 uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
472 of MCP and SCP devices is routed directly to GPIO pins. When
473 cleared these devices are included in the standard JTAG chain.
474 The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
475 This field is reinitialized with a cold domain reset.
476 Reset value is determined by GPIO strap pin number
477 GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
478 uint64_t reserved_47_52 : 6;
479 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
480 ref-clock speed should always be 50 MHz.
481
482 Internal:
483 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
484 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
485 pins and the smaller value is used. */
486 uint64_t reserved_39 : 1;
487 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
488 The value ref-clock speed should always be 50 MHz.
489
490 Internal:
491 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
492 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
493 pins and the smaller value is used. */
494 uint64_t reserved_24_32 : 9;
495 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Last boot cause mask for PEM5 and PEM4; resets only with PLL_DC_OK.
496 \<23\> = Warm reset due to Cntl5 link-down or hot-reset.
497 \<22\> = Warm reset due to Cntl4 link-down or hot-reset.
498 \<21\> = Cntl5 reset due to PERST5_L pin.
499 \<20\> = Cntl4 reset due to PERST4_L pin.
500 \<19\> = Warm reset due to PERST5_L pin.
501 \<18\> = Warm reset due to PERST4_L pin. */
502 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
503 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
504 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
505 \<15\> = Cntl3 reset due to PERST3_L pin.
506 \<14\> = Cntl2 reset due to PERST2_L pin.
507 \<13\> = Warm reset due to PERST3_L pin.
508 \<12\> = Warm reset due to PERST2_L pin. */
509 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
510 \<11\> = Soft reset due to watchdog.
511 \<10\> = Soft reset due to RST_SOFT_RST write.
512 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
513 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
514 \<7\> = Cntl1 reset due to PERST1_L pin.
515 \<6\> = Cntl0 reset due to PERST0_L pin.
516 \<5\> = Warm reset due to PERST1_L pin.
517 \<4\> = Warm reset due to PERST0_L pin.
518 \<3\> = Warm reset due to CHIP_RESET_L pin.
519 \<2\> = Cold reset due to PLL_DC_OK pin. */
520 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
521 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
522 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
523 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
524 for the cold reset. */
525 #else /* Word 0 - Little Endian */
526 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
527 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
528 for the cold reset. */
529 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
530 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
531 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
532 \<11\> = Soft reset due to watchdog.
533 \<10\> = Soft reset due to RST_SOFT_RST write.
534 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
535 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
536 \<7\> = Cntl1 reset due to PERST1_L pin.
537 \<6\> = Cntl0 reset due to PERST0_L pin.
538 \<5\> = Warm reset due to PERST1_L pin.
539 \<4\> = Warm reset due to PERST0_L pin.
540 \<3\> = Warm reset due to CHIP_RESET_L pin.
541 \<2\> = Cold reset due to PLL_DC_OK pin. */
542 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
543 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
544 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
545 \<15\> = Cntl3 reset due to PERST3_L pin.
546 \<14\> = Cntl2 reset due to PERST2_L pin.
547 \<13\> = Warm reset due to PERST3_L pin.
548 \<12\> = Warm reset due to PERST2_L pin. */
549 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Last boot cause mask for PEM5 and PEM4; resets only with PLL_DC_OK.
550 \<23\> = Warm reset due to Cntl5 link-down or hot-reset.
551 \<22\> = Warm reset due to Cntl4 link-down or hot-reset.
552 \<21\> = Cntl5 reset due to PERST5_L pin.
553 \<20\> = Cntl4 reset due to PERST4_L pin.
554 \<19\> = Warm reset due to PERST5_L pin.
555 \<18\> = Warm reset due to PERST4_L pin. */
556 uint64_t reserved_24_32 : 9;
557 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
558 The value ref-clock speed should always be 50 MHz.
559
560 Internal:
561 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
562 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
563 pins and the smaller value is used. */
564 uint64_t reserved_39 : 1;
565 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
566 ref-clock speed should always be 50 MHz.
567
568 Internal:
569 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
570 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
571 pins and the smaller value is used. */
572 uint64_t reserved_47_52 : 6;
573 uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
574 of MCP and SCP devices is routed directly to GPIO pins. When
575 cleared these devices are included in the standard JTAG chain.
576 The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
577 This field is reinitialized with a cold domain reset.
578 Reset value is determined by GPIO strap pin number
579 GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
580 uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
581 the EJTAG TAP controller will be disabled. This field does not
582 control the SCP EJTAG interface (See EJTAGDIS).
583 This field resets to one in trusted mode otherwise it is cleared.
584 This field is reinitialized with a cold domain reset. */
585 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
586 allowed in the part.
587 This state persists across soft and warm resets.
588
589 Internal:
590 This state will persist across a simulation */
591 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
592 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
593 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
594
595 Software must write a one to this bit when the chain of trust is broken. */
596 uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
597 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
598 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
599 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
600 RST_BOOT[CHIPKILL]=1. */
601 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
602 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
603 strap GPIO_STRAP\<10\> are set. */
604 uint64_t reserved_61_62 : 2;
605 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
606 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
607 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
608 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
609 #endif /* Word 0 - End */
610 } s;
611 struct bdk_rst_boot_cn9
612 {
613 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
614 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
615 expires, chip domain reset is asserted.
616 The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
617 This feature is effectively a delayed reset.
618 This field is reinitialized with a chip domain reset. */
619 uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
620 JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
621 This field resets to one in trusted mode otherwise it is cleared.
622 This field is reinitialized with a cold domain reset. */
623 uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
624 the EJTAG TAP controller will be disabled. This field does not
625 control the MCP EJTAG interface (See [MCP_JTAGDIS]).
626 This field resets to one in trusted mode otherwise it is cleared.
627 This field is reinitialized with a cold domain reset. */
628 uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
629 either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
630 GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
631 uint64_t reserved_58_59 : 2;
632 uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
633 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
634 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
635 Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
636 It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
637 Software must set this bit when the chain of trust is broken.
638 This field is reinitialized with a cold domain reset. */
639 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
640 allowed in the part.
641 This field is reinitialized with a cold domain reset.
642
643 Internal:
644 The field is actually reset only after DCOK has been left
645 deasserted for an extended period of time. */
646 uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
647 the EJTAG TAP controller will be disabled. This field does not
648 control the SCP EJTAG interface (See EJTAGDIS).
649 This field resets to one in trusted mode otherwise it is cleared.
650 This field is reinitialized with a cold domain reset. */
651 uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
652 of MCP and SCP devices is routed directly to GPIO pins. When
653 cleared these devices are included in the standard JTAG chain.
654 The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
655 This field is reinitialized with a cold domain reset.
656 Reset value is determined by GPIO strap pin number
657 GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
658 uint64_t reserved_47_52 : 6;
659 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
660 See RST_CORE_PLL for details on programming and initial values.
661
662 Internal:
663 [C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
664 uint64_t reserved_39 : 1;
665 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
666 See RST_PNR_PLL for details on programming and initial values.
667
668 Internal:
669 [PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
670 uint64_t reserved_31_32 : 2;
671 uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier. Clock frequency = [CPT_MUL] * 50 MHz.
672 See RST_CPT_PLL for details on programming and initial values.
673
674 Internal:
675 [CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
676 uint64_t reserved_2_23 : 22;
677 uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
678 RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
679 will automatically come out of reset once the reset source has
680 been deasserted.
681 The initial value is set when [RBOOT_PIN] is true and
682 trustzone has not been enabled.
683 This field is reinitialized with a cold domain reset.
684
685 Internal:
686 This field is cleared when jtg__rst_disable_remote is active. */
687 uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
688 when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
689 #else /* Word 0 - Little Endian */
690 uint64_t rboot_pin : 1; /**< [ 0: 0](RO) Remote boot strap. The value is set when primary boot method is RST_BOOT_METHOD_E::REMOTE
691 when the GPIO pins are sampled on the rising edge of PLL_DCOK. */
692 uint64_t rboot : 1; /**< [ 1: 1](R/W/H) Remote boot. If set, indicates that SCP will require a write to
693 RST_SCP_DOMAIN_W1C to bring it out of reset. Otherwise it
694 will automatically come out of reset once the reset source has
695 been deasserted.
696 The initial value is set when [RBOOT_PIN] is true and
697 trustzone has not been enabled.
698 This field is reinitialized with a cold domain reset.
699
700 Internal:
701 This field is cleared when jtg__rst_disable_remote is active. */
702 uint64_t reserved_2_23 : 22;
703 uint64_t cpt_mul : 7; /**< [ 30: 24](RO/H) Current crypto-clock multiplier. Clock frequency = [CPT_MUL] * 50 MHz.
704 See RST_CPT_PLL for details on programming and initial values.
705
706 Internal:
707 [CPT_MUL] is a copy of RST_CPT_PLL[CUR_MUL]. */
708 uint64_t reserved_31_32 : 2;
709 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Current coprocessor-clock multiplier. Clock frequency = [PNR_MUL] * 50 MHz.
710 See RST_PNR_PLL for details on programming and initial values.
711
712 Internal:
713 [PNR_MUL] is a copy of RST_PNR_PLL[CUR_MUL]. */
714 uint64_t reserved_39 : 1;
715 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Current core-clock multiplier. Clock frequency = [C_MUL] * 50 MHz.
716 See RST_CORE_PLL for details on programming and initial values.
717
718 Internal:
719 [C_MUL] is a copy of RST_CORE_PLL[CUR_MUL]. */
720 uint64_t reserved_47_52 : 6;
721 uint64_t gpio_ejtag : 1; /**< [ 53: 53](R/W/H) Use GPIO pins for EJTAG. When set, the EJTAG chain consisting
722 of MCP and SCP devices is routed directly to GPIO pins. When
723 cleared these devices are included in the standard JTAG chain.
724 The specific GPIO pins are selected with GPIO_BIT_CFG()[PIN_SEL].
725 This field is reinitialized with a cold domain reset.
726 Reset value is determined by GPIO strap pin number
727 GPIO_STRAP_PIN_E::MCP_DBG_ON_GPIO. */
728 uint64_t mcp_jtagdis : 1; /**< [ 54: 54](R/W/H) MCP JTAG debugger disable. When set, the MCP Debug interface of
729 the EJTAG TAP controller will be disabled. This field does not
730 control the SCP EJTAG interface (See EJTAGDIS).
731 This field resets to one in trusted mode otherwise it is cleared.
732 This field is reinitialized with a cold domain reset. */
733 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When set and FUSF_CTL[ROT_LCK] = 1, scan is not
734 allowed in the part.
735 This field is reinitialized with a cold domain reset.
736
737 Internal:
738 The field is actually reset only after DCOK has been left
739 deasserted for an extended period of time. */
740 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set, FUSF_SSK(),
741 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
742 Resets to one if FUSF_CTL[FJ_DIS_HUK] is set and not in trusted mode.
743 It is also set anytime scan mode is activated while FUSF_CTL[FJ_DIS_HUK] is set.
744 Software must set this bit when the chain of trust is broken.
745 This field is reinitialized with a cold domain reset. */
746 uint64_t vrm_err : 1; /**< [ 57: 57](R/W1) Reserved. */
747 uint64_t reserved_58_59 : 2;
748 uint64_t trusted_mode : 1; /**< [ 60: 60](RO/H) When set, chip is operating as a trusted device. This bit is asserted when
749 either FUSF_CTL[TZ_FORCE2], or the trusted mode strap on GPIO number
750 GPIO_STRAP_PIN_E::TRUSTED_MODE is set. */
751 uint64_t scp_jtagdis : 1; /**< [ 61: 61](R/W/H) SCP JTAG debugger disable. When set, the SCP debug interface of
752 the EJTAG TAP controller will be disabled. This field does not
753 control the MCP EJTAG interface (See [MCP_JTAGDIS]).
754 This field resets to one in trusted mode otherwise it is cleared.
755 This field is reinitialized with a cold domain reset. */
756 uint64_t jtagdis : 1; /**< [ 62: 62](R/W/H) JTAG access disable. When set, the debug access port of the
757 JTAG TAP controller will be disabled, i.e. DAP_IMP_DAR will be zero.
758 This field resets to one in trusted mode otherwise it is cleared.
759 This field is reinitialized with a cold domain reset. */
760 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A zero-to-one transition of CHIPKILL starts the CHIPKILL timer. When set and the timer
761 expires, chip domain reset is asserted.
762 The length of the CHIPKILL timer is specified by RST_CKILL[TIMER].
763 This feature is effectively a delayed reset.
764 This field is reinitialized with a chip domain reset. */
765 #endif /* Word 0 - End */
766 } cn9;
767 struct bdk_rst_boot_cn81xx
768 {
769 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
770 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
771 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
772 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
773 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
774 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
775 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
776 in trusted-mode, else 0. */
777 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
778 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
779 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
780 strap GPIO_STRAP\<10\> are set. */
781 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
782 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
783 RST_BOOT[CHIPKILL]=1. */
784 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
785 uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
786 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
787 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
788 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
789
790 Software must write a one to this bit when the chain of trust is broken. */
791 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
792 allowed in the part.
793 This state persists across soft and warm resets.
794
795 Internal:
796 This state will persist across a simulation */
797 uint64_t reserved_47_54 : 8;
798 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
799 ref-clock speed should always be 50 MHz.
800
801 Internal:
802 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
803 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
804 pins and the smaller value is used. */
805 uint64_t reserved_39 : 1;
806 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
807 The value ref-clock speed should always be 50 MHz.
808
809 Internal:
810 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
811 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
812 pins and the smaller value is used. */
813 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
814 Internal:
815 Last boot cause mask for CCPI; resets only with PLL_DC_OK.
816 \<32\> = Warm reset due to CCPI link 2 going down.
817 \<31\> = Warm reset due to CCPI link 1 going down.
818 \<30\> = Warm reset due to CCPI link 0 going down. */
819 uint64_t reserved_26_29 : 4;
820 uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
821 uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
822 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
823 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
824 \<17\> = Reserved
825 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
826 \<15\> = Reserved
827 \<14\> = Cntl2 reset due to PERST2_L pin.
828 \<13\> = Reserved
829 \<12\> = Warm reset due to PERST2_L pin. */
830 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
831 \<11\> = Soft reset due to watchdog.
832 \<10\> = Soft reset due to RST_SOFT_RST write.
833 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
834 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
835 \<7\> = Cntl1 reset due to PERST1_L pin.
836 \<6\> = Cntl0 reset due to PERST0_L pin.
837 \<5\> = Warm reset due to PERST1_L pin.
838 \<4\> = Warm reset due to PERST0_L pin.
839 \<3\> = Warm reset due to CHIP_RESET_L pin.
840 \<2\> = Cold reset due to PLL_DC_OK pin. */
841 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
842 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
843 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
844 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
845 for the cold reset. */
846 #else /* Word 0 - Little Endian */
847 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
848 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
849 for the cold reset. */
850 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
851 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
852 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
853 \<11\> = Soft reset due to watchdog.
854 \<10\> = Soft reset due to RST_SOFT_RST write.
855 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
856 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
857 \<7\> = Cntl1 reset due to PERST1_L pin.
858 \<6\> = Cntl0 reset due to PERST0_L pin.
859 \<5\> = Warm reset due to PERST1_L pin.
860 \<4\> = Warm reset due to PERST0_L pin.
861 \<3\> = Warm reset due to CHIP_RESET_L pin.
862 \<2\> = Cold reset due to PLL_DC_OK pin. */
863 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM2; resets only with PLL_DC_OK.
864 \<17\> = Reserved
865 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
866 \<15\> = Reserved
867 \<14\> = Cntl2 reset due to PERST2_L pin.
868 \<13\> = Reserved
869 \<12\> = Warm reset due to PERST2_L pin. */
870 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
871 uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
872 uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
873 uint64_t reserved_26_29 : 4;
874 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
875 Internal:
876 Last boot cause mask for CCPI; resets only with PLL_DC_OK.
877 \<32\> = Warm reset due to CCPI link 2 going down.
878 \<31\> = Warm reset due to CCPI link 1 going down.
879 \<30\> = Warm reset due to CCPI link 0 going down. */
880 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
881 The value ref-clock speed should always be 50 MHz.
882
883 Internal:
884 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
885 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
886 pins and the smaller value is used. */
887 uint64_t reserved_39 : 1;
888 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
889 ref-clock speed should always be 50 MHz.
890
891 Internal:
892 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
893 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
894 pins and the smaller value is used. */
895 uint64_t reserved_47_54 : 8;
896 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
897 allowed in the part.
898 This state persists across soft and warm resets.
899
900 Internal:
901 This state will persist across a simulation */
902 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
903 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
904 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
905
906 Software must write a one to this bit when the chain of trust is broken. */
907 uint64_t vrm_err : 1; /**< [ 57: 57](RO) Reserved. */
908 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
909 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
910 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
911 RST_BOOT[CHIPKILL]=1. */
912 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
913 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
914 strap GPIO_STRAP\<10\> are set. */
915 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
916 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
917 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
918 in trusted-mode, else 0. */
919 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
920 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
921 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
922 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
923 #endif /* Word 0 - End */
924 } cn81xx;
925 struct bdk_rst_boot_cn88xx
926 {
927 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
928 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
929 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
930 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
931 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
932 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
933 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
934 in trusted-mode, else 0. */
935 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
936 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
937 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
938 strap GPIO_STRAP\<10\> are set. */
939 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
940 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
941 RST_BOOT[CHIPKILL]=1. */
942 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
943 uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
944 asserted. PLLs were released automatically. */
945 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
946 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
947 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
948
949 Software must write a one to this bit when the chain of trust is broken. */
950 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
951 allowed in the part.
952 This state persists across soft and warm resets.
953
954 Internal:
955 This state will persist across a simulation */
956 uint64_t reserved_47_54 : 8;
957 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
958 ref-clock speed should always be 50 MHz.
959
960 Internal:
961 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
962 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
963 pins and the smaller value is used. */
964 uint64_t reserved_39 : 1;
965 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
966 The value ref-clock speed should always be 50 MHz.
967
968 Internal:
969 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
970 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
971 pins and the smaller value is used. */
972 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Last boot cause mask for CCPI; resets only with PLL_DC_OK.
973 \<32\> = Warm reset due to CCPI link 2 going down.
974 \<31\> = Warm reset due to CCPI link 1 going down.
975 \<30\> = Warm reset due to CCPI link 0 going down. */
976 uint64_t reserved_26_29 : 4;
977 uint64_t reserved_24_25 : 2;
978 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Last boot cause mask for PEM5 and PEM4; resets only with PLL_DC_OK.
979 \<23\> = Warm reset due to Cntl5 link-down or hot-reset.
980 \<22\> = Warm reset due to Cntl4 link-down or hot-reset.
981 \<21\> = Cntl5 reset due to PERST5_L pin.
982 \<20\> = Cntl4 reset due to PERST4_L pin.
983 \<19\> = Warm reset due to PERST5_L pin.
984 \<18\> = Warm reset due to PERST4_L pin. */
985 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
986 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
987 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
988 \<15\> = Cntl3 reset due to PERST3_L pin.
989 \<14\> = Cntl2 reset due to PERST2_L pin.
990 \<13\> = Warm reset due to PERST3_L pin.
991 \<12\> = Warm reset due to PERST2_L pin. */
992 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
993 \<11\> = Soft reset due to watchdog.
994 \<10\> = Soft reset due to RST_SOFT_RST write.
995 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
996 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
997 \<7\> = Cntl1 reset due to PERST1_L pin.
998 \<6\> = Cntl0 reset due to PERST0_L pin.
999 \<5\> = Warm reset due to PERST1_L pin.
1000 \<4\> = Warm reset due to PERST0_L pin.
1001 \<3\> = Warm reset due to CHIP_RESET_L pin.
1002 \<2\> = Cold reset due to PLL_DC_OK pin. */
1003 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
1004 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
1005 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
1006 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
1007 for the cold reset. */
1008 #else /* Word 0 - Little Endian */
1009 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
1010 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
1011 for the cold reset. */
1012 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
1013 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
1014 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
1015 \<11\> = Soft reset due to watchdog.
1016 \<10\> = Soft reset due to RST_SOFT_RST write.
1017 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
1018 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
1019 \<7\> = Cntl1 reset due to PERST1_L pin.
1020 \<6\> = Cntl0 reset due to PERST0_L pin.
1021 \<5\> = Warm reset due to PERST1_L pin.
1022 \<4\> = Warm reset due to PERST0_L pin.
1023 \<3\> = Warm reset due to CHIP_RESET_L pin.
1024 \<2\> = Cold reset due to PLL_DC_OK pin. */
1025 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
1026 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
1027 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
1028 \<15\> = Cntl3 reset due to PERST3_L pin.
1029 \<14\> = Cntl2 reset due to PERST2_L pin.
1030 \<13\> = Warm reset due to PERST3_L pin.
1031 \<12\> = Warm reset due to PERST2_L pin. */
1032 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Last boot cause mask for PEM5 and PEM4; resets only with PLL_DC_OK.
1033 \<23\> = Warm reset due to Cntl5 link-down or hot-reset.
1034 \<22\> = Warm reset due to Cntl4 link-down or hot-reset.
1035 \<21\> = Cntl5 reset due to PERST5_L pin.
1036 \<20\> = Cntl4 reset due to PERST4_L pin.
1037 \<19\> = Warm reset due to PERST5_L pin.
1038 \<18\> = Warm reset due to PERST4_L pin. */
1039 uint64_t reserved_24_25 : 2;
1040 uint64_t reserved_26_29 : 4;
1041 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Last boot cause mask for CCPI; resets only with PLL_DC_OK.
1042 \<32\> = Warm reset due to CCPI link 2 going down.
1043 \<31\> = Warm reset due to CCPI link 1 going down.
1044 \<30\> = Warm reset due to CCPI link 0 going down. */
1045 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
1046 The value ref-clock speed should always be 50 MHz.
1047
1048 Internal:
1049 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
1050 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
1051 pins and the smaller value is used. */
1052 uint64_t reserved_39 : 1;
1053 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
1054 ref-clock speed should always be 50 MHz.
1055
1056 Internal:
1057 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
1058 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
1059 pins and the smaller value is used. */
1060 uint64_t reserved_47_54 : 8;
1061 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
1062 allowed in the part.
1063 This state persists across soft and warm resets.
1064
1065 Internal:
1066 This state will persist across a simulation */
1067 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
1068 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
1069 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
1070
1071 Software must write a one to this bit when the chain of trust is broken. */
1072 uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
1073 asserted. PLLs were released automatically. */
1074 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
1075 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
1076 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
1077 RST_BOOT[CHIPKILL]=1. */
1078 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
1079 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
1080 strap GPIO_STRAP\<10\> are set. */
1081 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
1082 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
1083 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
1084 in trusted-mode, else 0. */
1085 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
1086 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
1087 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
1088 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
1089 #endif /* Word 0 - End */
1090 } cn88xx;
1091 struct bdk_rst_boot_cn83xx
1092 {
1093 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1094 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
1095 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
1096 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
1097 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
1098 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
1099 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
1100 in trusted-mode, else 0. */
1101 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
1102 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
1103 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
1104 strap GPIO_STRAP\<10\> are set. */
1105 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
1106 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
1107 RST_BOOT[CHIPKILL]=1. */
1108 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
1109 uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
1110 asserted. PLLs were released automatically. */
1111 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
1112 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
1113 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
1114
1115 Software must write a one to this bit when the chain of trust is broken. */
1116 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
1117 allowed in the part.
1118 This state persists across soft and warm resets.
1119
1120 Internal:
1121 This state will persist across a simulation */
1122 uint64_t reserved_47_54 : 8;
1123 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
1124 ref-clock speed should always be 50 MHz.
1125
1126 Internal:
1127 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
1128 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
1129 pins and the smaller value is used. */
1130 uint64_t reserved_39 : 1;
1131 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
1132 The value ref-clock speed should always be 50 MHz.
1133
1134 Internal:
1135 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
1136 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
1137 pins and the smaller value is used. */
1138 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
1139 Internal:
1140 Last boot cause mask for CCPI; resets only with PLL_DC_OK.
1141 \<32\> = Warm reset due to CCPI link 2 going down.
1142 \<31\> = Warm reset due to CCPI link 1 going down.
1143 \<30\> = Warm reset due to CCPI link 0 going down. */
1144 uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
1145 \<29\> = Warm reset due to PF FLR on PEM3.
1146 \<28\> = Warm reset due to PF FLR on PEM2.
1147 \<27\> = Warm reset due to PF FLR on PEM1.
1148 \<26\> = Warm reset due to PF FLR on PEM0. */
1149 uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
1150 uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
1151 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
1152 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
1153 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
1154 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
1155 \<15\> = Cntl3 reset due to PERST3_L pin.
1156 \<14\> = Cntl2 reset due to PERST2_L pin.
1157 \<13\> = Warm reset due to PERST3_L pin.
1158 \<12\> = Warm reset due to PERST2_L pin. */
1159 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
1160 \<11\> = Soft reset due to watchdog.
1161 \<10\> = Soft reset due to RST_SOFT_RST write.
1162 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
1163 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
1164 \<7\> = Cntl1 reset due to PERST1_L pin.
1165 \<6\> = Cntl0 reset due to PERST0_L pin.
1166 \<5\> = Warm reset due to PERST1_L pin.
1167 \<4\> = Warm reset due to PERST0_L pin.
1168 \<3\> = Warm reset due to CHIP_RESET_L pin.
1169 \<2\> = Cold reset due to PLL_DC_OK pin. */
1170 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
1171 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
1172 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
1173 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
1174 for the cold reset. */
1175 #else /* Word 0 - Little Endian */
1176 uint64_t rboot_pin : 1; /**< [ 0: 0](RO/H) Remote Boot strap. Indicates the state of remote boot as initially determined by
1177 GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE. If set core 0 will remain in reset
1178 for the cold reset. */
1179 uint64_t rboot : 1; /**< [ 1: 1](R/W) Remote boot. If set, indicates that core 0 will remain in reset after a
1180 chip warm/soft reset. The initial value mimics the setting of the [RBOOT_PIN]. */
1181 uint64_t lboot : 10; /**< [ 11: 2](R/W1C/H) Last boot cause mask for PEM1 and PEM0; resets only with PLL_DC_OK.
1182 \<11\> = Soft reset due to watchdog.
1183 \<10\> = Soft reset due to RST_SOFT_RST write.
1184 \<9\> = Warm reset due to Cntl1 link-down or hot-reset.
1185 \<8\> = Warm reset due to Cntl0 link-down or hot-reset.
1186 \<7\> = Cntl1 reset due to PERST1_L pin.
1187 \<6\> = Cntl0 reset due to PERST0_L pin.
1188 \<5\> = Warm reset due to PERST1_L pin.
1189 \<4\> = Warm reset due to PERST0_L pin.
1190 \<3\> = Warm reset due to CHIP_RESET_L pin.
1191 \<2\> = Cold reset due to PLL_DC_OK pin. */
1192 uint64_t lboot_ext23 : 6; /**< [ 17: 12](R/W1C/H) Last boot cause mask for PEM3 and PEM2; resets only with PLL_DC_OK.
1193 \<17\> = Warm reset due to Cntl3 link-down or hot-reset.
1194 \<16\> = Warm reset due to Cntl2 link-down or hot-reset.
1195 \<15\> = Cntl3 reset due to PERST3_L pin.
1196 \<14\> = Cntl2 reset due to PERST2_L pin.
1197 \<13\> = Warm reset due to PERST3_L pin.
1198 \<12\> = Warm reset due to PERST2_L pin. */
1199 uint64_t lboot_ext45 : 6; /**< [ 23: 18](R/W1C/H) Reserved. */
1200 uint64_t lboot_jtg : 1; /**< [ 24: 24](R/W1C/H) Last boot cause was write to JTG reset. */
1201 uint64_t lboot_ckill : 1; /**< [ 25: 25](R/W1C/H) Last boot cause was chip kill timer expiring. See RST_BOOT[CHIPKILL]. */
1202 uint64_t lboot_pf_flr : 4; /**< [ 29: 26](R/W1C/H) Last boot cause was caused by a PF Function Level Reset event.
1203 \<29\> = Warm reset due to PF FLR on PEM3.
1204 \<28\> = Warm reset due to PF FLR on PEM2.
1205 \<27\> = Warm reset due to PF FLR on PEM1.
1206 \<26\> = Warm reset due to PF FLR on PEM0. */
1207 uint64_t lboot_oci : 3; /**< [ 32: 30](R/W1C/H) Reserved.
1208 Internal:
1209 Last boot cause mask for CCPI; resets only with PLL_DC_OK.
1210 \<32\> = Warm reset due to CCPI link 2 going down.
1211 \<31\> = Warm reset due to CCPI link 1 going down.
1212 \<30\> = Warm reset due to CCPI link 0 going down. */
1213 uint64_t pnr_mul : 6; /**< [ 38: 33](RO/H) Coprocessor-clock multiplier. [PNR_MUL] = (coprocessor-clock speed) /(ref-clock speed).
1214 The value ref-clock speed should always be 50 MHz.
1215
1216 Internal:
1217 [PNR_MUL] is set from the pi_pnr_pll_mul pins plus 6 and is limited by a set of
1218 fuses[122:119]. If the fuse value is \> 0, it is compared with the pi_pnr_pll_mul[4:1]
1219 pins and the smaller value is used. */
1220 uint64_t reserved_39 : 1;
1221 uint64_t c_mul : 7; /**< [ 46: 40](RO/H) Core-clock multiplier. [C_MUL] = (core-clock speed) / (ref-clock speed). The value
1222 ref-clock speed should always be 50 MHz.
1223
1224 Internal:
1225 [C_MUL] is set from the pi_pll_mul pins plus 6 and is limited by a set of
1226 fuses[127:123]. If the fuse value is \> 0, it is compared with the pi_pll_mul[5:1]
1227 pins and the smaller value is used. */
1228 uint64_t reserved_47_54 : 8;
1229 uint64_t dis_scan : 1; /**< [ 55: 55](R/W1S) Disable scan. When written to 1, and FUSF_CTL[ROT_LCK] = 1, reads as 1 and scan is not
1230 allowed in the part.
1231 This state persists across soft and warm resets.
1232
1233 Internal:
1234 This state will persist across a simulation */
1235 uint64_t dis_huk : 1; /**< [ 56: 56](R/W1S) Disable HUK. Secure only and W1S set-only. When set FUSF_SSK(),
1236 FUSF_HUK(), FUSF_EK(), and FUSF_SW() cannot be read.
1237 Resets to (!trusted_mode && FUSF_CTL[FJ_DIS_HUK]).
1238
1239 Software must write a one to this bit when the chain of trust is broken. */
1240 uint64_t vrm_err : 1; /**< [ 57: 57](RO) VRM error. VRM did not complete operations within 5.25ms of PLL_DC_OK being
1241 asserted. PLLs were released automatically. */
1242 uint64_t jt_tstmode : 1; /**< [ 58: 58](RO) JTAG test mode. */
1243 uint64_t ckill_ppdis : 1; /**< [ 59: 59](R/W) Chipkill core disable. When set to 1, cores other than core 0 will immediately
1244 be disabled when RST_BOOT[CHIPKILL] is set. Writes have no effect when
1245 RST_BOOT[CHIPKILL]=1. */
1246 uint64_t trusted_mode : 1; /**< [ 60: 60](RO) When set, chip is operating as a trusted device. This bit is asserted when
1247 either MIO_FUS_DAT2[TRUSTZONE_EN], FUSF_CTL[TZ_FORCE2], or the trusted-mode
1248 strap GPIO_STRAP\<10\> are set. */
1249 uint64_t ejtagdis : 1; /**< [ 61: 61](R/W) Reserved. */
1250 uint64_t jtcsrdis : 1; /**< [ 62: 62](R/W) JTAG CSR disable. When set to 1, during the next warm or soft reset the JTAG TAP
1251 controller will be disabled, i.e. DAP_IMP_DAR will be 0. This field resets to 1
1252 in trusted-mode, else 0. */
1253 uint64_t chipkill : 1; /**< [ 63: 63](R/W1S) A 0-to-1 transition of CHIPKILL starts the CHIPKILL timer. When CHIPKILL=1 and the timer
1254 expires, chip reset is asserted internally. The CHIPKILL timer can be stopped only by
1255 a reset (cold, warm, soft). The length of the CHIPKILL timer is specified by
1256 RST_CKILL[TIMER]. This feature is effectively a delayed warm reset. */
1257 #endif /* Word 0 - End */
1258 } cn83xx;
1259 };
1260 typedef union bdk_rst_boot bdk_rst_boot_t;
1261
1262 #define BDK_RST_BOOT BDK_RST_BOOT_FUNC()
1263 static inline uint64_t BDK_RST_BOOT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_BOOT_FUNC(void)1264 static inline uint64_t BDK_RST_BOOT_FUNC(void)
1265 {
1266 return 0x87e006001600ll;
1267 }
1268
1269 #define typedef_BDK_RST_BOOT bdk_rst_boot_t
1270 #define bustype_BDK_RST_BOOT BDK_CSR_TYPE_RSL
1271 #define basename_BDK_RST_BOOT "RST_BOOT"
1272 #define device_bar_BDK_RST_BOOT 0x0 /* PF_BAR0 */
1273 #define busnum_BDK_RST_BOOT 0
1274 #define arguments_BDK_RST_BOOT -1,-1,-1,-1
1275
1276 /**
1277 * Register (RSL) rst_boot_status
1278 *
1279 * RST Boot Status Register
1280 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1281 */
1282 union bdk_rst_boot_status
1283 {
1284 uint64_t u;
1285 struct bdk_rst_boot_status_s
1286 {
1287 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1288 uint64_t stat3 : 16; /**< [ 63: 48](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1289 boot. Accessible via JTG/DTX with offset 17.
1290
1291 This field is always reinitialized on a chip domain reset. */
1292 uint64_t stat2 : 16; /**< [ 47: 32](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1293 boot. Accessible via JTG/DTX with offset 16.
1294
1295 This field is always reinitialized on a chip domain reset. */
1296 uint64_t stat1 : 16; /**< [ 31: 16](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1297 boot. Accessible via JTG/DTX with offset 13.
1298
1299 This field is always reinitialized on a chip domain reset. */
1300 uint64_t stat0 : 16; /**< [ 15: 0](R/W) JTAG accessable boot status word zero. Used by software to indicate progress of
1301 boot. Accessable via JTG/DTX with offset 12.
1302
1303 This field is always reinitialized on a chip domain reset. */
1304 #else /* Word 0 - Little Endian */
1305 uint64_t stat0 : 16; /**< [ 15: 0](R/W) JTAG accessable boot status word zero. Used by software to indicate progress of
1306 boot. Accessable via JTG/DTX with offset 12.
1307
1308 This field is always reinitialized on a chip domain reset. */
1309 uint64_t stat1 : 16; /**< [ 31: 16](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1310 boot. Accessible via JTG/DTX with offset 13.
1311
1312 This field is always reinitialized on a chip domain reset. */
1313 uint64_t stat2 : 16; /**< [ 47: 32](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1314 boot. Accessible via JTG/DTX with offset 16.
1315
1316 This field is always reinitialized on a chip domain reset. */
1317 uint64_t stat3 : 16; /**< [ 63: 48](R/W) JTAG accessible boot status word one. Used by software to indicate progress of
1318 boot. Accessible via JTG/DTX with offset 17.
1319
1320 This field is always reinitialized on a chip domain reset. */
1321 #endif /* Word 0 - End */
1322 } s;
1323 /* struct bdk_rst_boot_status_s cn; */
1324 };
1325 typedef union bdk_rst_boot_status bdk_rst_boot_status_t;
1326
1327 #define BDK_RST_BOOT_STATUS BDK_RST_BOOT_STATUS_FUNC()
1328 static inline uint64_t BDK_RST_BOOT_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_BOOT_STATUS_FUNC(void)1329 static inline uint64_t BDK_RST_BOOT_STATUS_FUNC(void)
1330 {
1331 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1332 return 0x87e006001800ll;
1333 __bdk_csr_fatal("RST_BOOT_STATUS", 0, 0, 0, 0, 0);
1334 }
1335
1336 #define typedef_BDK_RST_BOOT_STATUS bdk_rst_boot_status_t
1337 #define bustype_BDK_RST_BOOT_STATUS BDK_CSR_TYPE_RSL
1338 #define basename_BDK_RST_BOOT_STATUS "RST_BOOT_STATUS"
1339 #define device_bar_BDK_RST_BOOT_STATUS 0x0 /* PF_BAR0 */
1340 #define busnum_BDK_RST_BOOT_STATUS 0
1341 #define arguments_BDK_RST_BOOT_STATUS -1,-1,-1,-1
1342
1343 /**
1344 * Register (RSL) rst_cfg
1345 *
1346 * RST Configuration Register
1347 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1348 */
1349 union bdk_rst_cfg
1350 {
1351 uint64_t u;
1352 struct bdk_rst_cfg_s
1353 {
1354 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1355 uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
1356 uint64_t reserved_3_5 : 3;
1357 uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
1358 does not change this field. */
1359 uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
1360 change this field. Note that a cold reset always performs a full BIST. */
1361 uint64_t reserved_0 : 1;
1362 #else /* Word 0 - Little Endian */
1363 uint64_t reserved_0 : 1;
1364 uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
1365 change this field. Note that a cold reset always performs a full BIST. */
1366 uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
1367 does not change this field. */
1368 uint64_t reserved_3_5 : 3;
1369 uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
1370 #endif /* Word 0 - End */
1371 } s;
1372 struct bdk_rst_cfg_cn8
1373 {
1374 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1375 uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
1376 uint64_t reserved_3_5 : 3;
1377 uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
1378 does not change this field. */
1379 uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
1380 change this field. Note that a cold reset always performs a full BIST. */
1381 uint64_t soft_clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST during soft reset, instead of a full BIST. A warm/soft reset does not
1382 change this field. Note that a cold reset always performs a full BIST. */
1383 #else /* Word 0 - Little Endian */
1384 uint64_t soft_clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST during soft reset, instead of a full BIST. A warm/soft reset does not
1385 change this field. Note that a cold reset always performs a full BIST. */
1386 uint64_t warm_clr_bist : 1; /**< [ 1: 1](R/W) Perform clear BIST during warm reset, instead of a full BIST. A warm/soft reset does not
1387 change this field. Note that a cold reset always performs a full BIST. */
1388 uint64_t cntl_clr_bist : 1; /**< [ 2: 2](R/W) Perform clear BIST during control-only reset, instead of a full BIST. A warm/soft reset
1389 does not change this field. */
1390 uint64_t reserved_3_5 : 3;
1391 uint64_t bist_delay : 58; /**< [ 63: 6](RO/H) Reserved. */
1392 #endif /* Word 0 - End */
1393 } cn8;
1394 struct bdk_rst_cfg_cn9
1395 {
1396 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1397 uint64_t reserved_1_63 : 63;
1398 uint64_t clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST on each chip domain reset, instead of a full BIST.
1399 Note that the first BIST during a cold domain reset is always a full BIST.
1400 This field is reinitialized with a cold domain reset. */
1401 #else /* Word 0 - Little Endian */
1402 uint64_t clr_bist : 1; /**< [ 0: 0](R/W) Perform clear BIST on each chip domain reset, instead of a full BIST.
1403 Note that the first BIST during a cold domain reset is always a full BIST.
1404 This field is reinitialized with a cold domain reset. */
1405 uint64_t reserved_1_63 : 63;
1406 #endif /* Word 0 - End */
1407 } cn9;
1408 };
1409 typedef union bdk_rst_cfg bdk_rst_cfg_t;
1410
1411 #define BDK_RST_CFG BDK_RST_CFG_FUNC()
1412 static inline uint64_t BDK_RST_CFG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CFG_FUNC(void)1413 static inline uint64_t BDK_RST_CFG_FUNC(void)
1414 {
1415 return 0x87e006001610ll;
1416 }
1417
1418 #define typedef_BDK_RST_CFG bdk_rst_cfg_t
1419 #define bustype_BDK_RST_CFG BDK_CSR_TYPE_RSL
1420 #define basename_BDK_RST_CFG "RST_CFG"
1421 #define device_bar_BDK_RST_CFG 0x0 /* PF_BAR0 */
1422 #define busnum_BDK_RST_CFG 0
1423 #define arguments_BDK_RST_CFG -1,-1,-1,-1
1424
1425 /**
1426 * Register (RSL) rst_chip_domain_w1s
1427 *
1428 * RST Chip Domain Soft Pulse Reset Register
1429 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1430 */
1431 union bdk_rst_chip_domain_w1s
1432 {
1433 uint64_t u;
1434 struct bdk_rst_chip_domain_w1s_s
1435 {
1436 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1437 uint64_t reserved_1_63 : 63;
1438 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Soft reset of entire chip.
1439 When set to one, places the entire chip into reset. At the completion
1440 of the reset the field is cleared. This is similar to asserting and
1441 deasserting the CHIP_RESET_L pin.
1442 When performing a reset, set this bit and then read any register to
1443 confirm that chip is out of reset.
1444 This field is always reinitialized on a chip domain reset. */
1445 #else /* Word 0 - Little Endian */
1446 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Soft reset of entire chip.
1447 When set to one, places the entire chip into reset. At the completion
1448 of the reset the field is cleared. This is similar to asserting and
1449 deasserting the CHIP_RESET_L pin.
1450 When performing a reset, set this bit and then read any register to
1451 confirm that chip is out of reset.
1452 This field is always reinitialized on a chip domain reset. */
1453 uint64_t reserved_1_63 : 63;
1454 #endif /* Word 0 - End */
1455 } s;
1456 /* struct bdk_rst_chip_domain_w1s_s cn; */
1457 };
1458 typedef union bdk_rst_chip_domain_w1s bdk_rst_chip_domain_w1s_t;
1459
1460 #define BDK_RST_CHIP_DOMAIN_W1S BDK_RST_CHIP_DOMAIN_W1S_FUNC()
1461 static inline uint64_t BDK_RST_CHIP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CHIP_DOMAIN_W1S_FUNC(void)1462 static inline uint64_t BDK_RST_CHIP_DOMAIN_W1S_FUNC(void)
1463 {
1464 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1465 return 0x87e006001810ll;
1466 __bdk_csr_fatal("RST_CHIP_DOMAIN_W1S", 0, 0, 0, 0, 0);
1467 }
1468
1469 #define typedef_BDK_RST_CHIP_DOMAIN_W1S bdk_rst_chip_domain_w1s_t
1470 #define bustype_BDK_RST_CHIP_DOMAIN_W1S BDK_CSR_TYPE_RSL
1471 #define basename_BDK_RST_CHIP_DOMAIN_W1S "RST_CHIP_DOMAIN_W1S"
1472 #define device_bar_BDK_RST_CHIP_DOMAIN_W1S 0x0 /* PF_BAR0 */
1473 #define busnum_BDK_RST_CHIP_DOMAIN_W1S 0
1474 #define arguments_BDK_RST_CHIP_DOMAIN_W1S -1,-1,-1,-1
1475
1476 /**
1477 * Register (RSL) rst_ckill
1478 *
1479 * RST Chipkill Timer Register
1480 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1481 */
1482 union bdk_rst_ckill
1483 {
1484 uint64_t u;
1485 struct bdk_rst_ckill_s
1486 {
1487 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1488 uint64_t reserved_47_63 : 17;
1489 uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in coprocessor-clock cycles. Read requests return
1490 current chipkill timer. Write operations have no effect when RST_BOOT[CHIPKILL]
1491 = 1. */
1492 #else /* Word 0 - Little Endian */
1493 uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in coprocessor-clock cycles. Read requests return
1494 current chipkill timer. Write operations have no effect when RST_BOOT[CHIPKILL]
1495 = 1. */
1496 uint64_t reserved_47_63 : 17;
1497 #endif /* Word 0 - End */
1498 } s;
1499 /* struct bdk_rst_ckill_s cn8; */
1500 struct bdk_rst_ckill_cn9
1501 {
1502 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1503 uint64_t reserved_47_63 : 17;
1504 uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in 100 MHz PLL reference clocks. Read
1505 requests return current chip kill timer. Write operations have
1506 no effect when RST_BOOT[CHIPKILL] is set.
1507 This field is always reinitialized on a chip domain reset. */
1508 #else /* Word 0 - Little Endian */
1509 uint64_t timer : 47; /**< [ 46: 0](R/W/H) Chipkill timer measured in 100 MHz PLL reference clocks. Read
1510 requests return current chip kill timer. Write operations have
1511 no effect when RST_BOOT[CHIPKILL] is set.
1512 This field is always reinitialized on a chip domain reset. */
1513 uint64_t reserved_47_63 : 17;
1514 #endif /* Word 0 - End */
1515 } cn9;
1516 };
1517 typedef union bdk_rst_ckill bdk_rst_ckill_t;
1518
1519 #define BDK_RST_CKILL BDK_RST_CKILL_FUNC()
1520 static inline uint64_t BDK_RST_CKILL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CKILL_FUNC(void)1521 static inline uint64_t BDK_RST_CKILL_FUNC(void)
1522 {
1523 return 0x87e006001638ll;
1524 }
1525
1526 #define typedef_BDK_RST_CKILL bdk_rst_ckill_t
1527 #define bustype_BDK_RST_CKILL BDK_CSR_TYPE_RSL
1528 #define basename_BDK_RST_CKILL "RST_CKILL"
1529 #define device_bar_BDK_RST_CKILL 0x0 /* PF_BAR0 */
1530 #define busnum_BDK_RST_CKILL 0
1531 #define arguments_BDK_RST_CKILL -1,-1,-1,-1
1532
1533 /**
1534 * Register (RSL) rst_cold_data#
1535 *
1536 * RST Cold Reset Data Registers
1537 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1538 */
1539 union bdk_rst_cold_datax
1540 {
1541 uint64_t u;
1542 struct bdk_rst_cold_datax_s
1543 {
1544 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1545 uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through warm reset. */
1546 #else /* Word 0 - Little Endian */
1547 uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through warm reset. */
1548 #endif /* Word 0 - End */
1549 } s;
1550 /* struct bdk_rst_cold_datax_s cn8; */
1551 struct bdk_rst_cold_datax_cn9
1552 {
1553 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1554 uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through chip, core,
1555 MCP and SCP domain resets.
1556 This field is always reinitialized on a cold domain reset. */
1557 #else /* Word 0 - Little Endian */
1558 uint64_t data : 64; /**< [ 63: 0](R/W) Scratch data registers preserved through chip, core,
1559 MCP and SCP domain resets.
1560 This field is always reinitialized on a cold domain reset. */
1561 #endif /* Word 0 - End */
1562 } cn9;
1563 };
1564 typedef union bdk_rst_cold_datax bdk_rst_cold_datax_t;
1565
1566 static inline uint64_t BDK_RST_COLD_DATAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_COLD_DATAX(unsigned long a)1567 static inline uint64_t BDK_RST_COLD_DATAX(unsigned long a)
1568 {
1569 if (a<=5)
1570 return 0x87e0060017c0ll + 8ll * ((a) & 0x7);
1571 __bdk_csr_fatal("RST_COLD_DATAX", 1, a, 0, 0, 0);
1572 }
1573
1574 #define typedef_BDK_RST_COLD_DATAX(a) bdk_rst_cold_datax_t
1575 #define bustype_BDK_RST_COLD_DATAX(a) BDK_CSR_TYPE_RSL
1576 #define basename_BDK_RST_COLD_DATAX(a) "RST_COLD_DATAX"
1577 #define device_bar_BDK_RST_COLD_DATAX(a) 0x0 /* PF_BAR0 */
1578 #define busnum_BDK_RST_COLD_DATAX(a) (a)
1579 #define arguments_BDK_RST_COLD_DATAX(a) (a),-1,-1,-1
1580
1581 /**
1582 * Register (RSL) rst_cold_domain_w1s
1583 *
1584 * RST Cold Domain Pulse Reset Register
1585 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1586 */
1587 union bdk_rst_cold_domain_w1s
1588 {
1589 uint64_t u;
1590 struct bdk_rst_cold_domain_w1s_s
1591 {
1592 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1593 uint64_t reserved_1_63 : 63;
1594 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Soft reset of entire chip emulating a cold domain reset.
1595 When set to one, places the entire chip into reset. At the completion
1596 of the reset the field is cleared.
1597 This action is similar to deasserting and asserting PLL_DCOK with the
1598 exception that external pins are not sampled again.
1599 When performing a reset, set this bit and
1600 then read any register to confirm that chip is out of reset.
1601 This field is always reinitialized on a cold domain reset. */
1602 #else /* Word 0 - Little Endian */
1603 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Soft reset of entire chip emulating a cold domain reset.
1604 When set to one, places the entire chip into reset. At the completion
1605 of the reset the field is cleared.
1606 This action is similar to deasserting and asserting PLL_DCOK with the
1607 exception that external pins are not sampled again.
1608 When performing a reset, set this bit and
1609 then read any register to confirm that chip is out of reset.
1610 This field is always reinitialized on a cold domain reset. */
1611 uint64_t reserved_1_63 : 63;
1612 #endif /* Word 0 - End */
1613 } s;
1614 /* struct bdk_rst_cold_domain_w1s_s cn; */
1615 };
1616 typedef union bdk_rst_cold_domain_w1s bdk_rst_cold_domain_w1s_t;
1617
1618 #define BDK_RST_COLD_DOMAIN_W1S BDK_RST_COLD_DOMAIN_W1S_FUNC()
1619 static inline uint64_t BDK_RST_COLD_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_COLD_DOMAIN_W1S_FUNC(void)1620 static inline uint64_t BDK_RST_COLD_DOMAIN_W1S_FUNC(void)
1621 {
1622 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1623 return 0x87e006001808ll;
1624 __bdk_csr_fatal("RST_COLD_DOMAIN_W1S", 0, 0, 0, 0, 0);
1625 }
1626
1627 #define typedef_BDK_RST_COLD_DOMAIN_W1S bdk_rst_cold_domain_w1s_t
1628 #define bustype_BDK_RST_COLD_DOMAIN_W1S BDK_CSR_TYPE_RSL
1629 #define basename_BDK_RST_COLD_DOMAIN_W1S "RST_COLD_DOMAIN_W1S"
1630 #define device_bar_BDK_RST_COLD_DOMAIN_W1S 0x0 /* PF_BAR0 */
1631 #define busnum_BDK_RST_COLD_DOMAIN_W1S 0
1632 #define arguments_BDK_RST_COLD_DOMAIN_W1S -1,-1,-1,-1
1633
1634 /**
1635 * Register (RSL) rst_const
1636 *
1637 * RST Constant Register
1638 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1639 */
1640 union bdk_rst_const
1641 {
1642 uint64_t u;
1643 struct bdk_rst_const_s
1644 {
1645 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1646 uint64_t reserved_16_63 : 48;
1647 uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
1648 uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST, and size of RST_CTL(), RST_SOFT_PRST(). */
1649 #else /* Word 0 - Little Endian */
1650 uint64_t pems : 8; /**< [ 7: 0](RO) Number of PEMs supported by RST, and size of RST_CTL(), RST_SOFT_PRST(). */
1651 uint64_t rst_devs : 8; /**< [ 15: 8](RO) Number of RST_DEV_E enumeration values supported, and size of RST_DEV_MAP(). */
1652 uint64_t reserved_16_63 : 48;
1653 #endif /* Word 0 - End */
1654 } s;
1655 /* struct bdk_rst_const_s cn; */
1656 };
1657 typedef union bdk_rst_const bdk_rst_const_t;
1658
1659 #define BDK_RST_CONST BDK_RST_CONST_FUNC()
1660 static inline uint64_t BDK_RST_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CONST_FUNC(void)1661 static inline uint64_t BDK_RST_CONST_FUNC(void)
1662 {
1663 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1664 return 0x87e0060018f8ll;
1665 __bdk_csr_fatal("RST_CONST", 0, 0, 0, 0, 0);
1666 }
1667
1668 #define typedef_BDK_RST_CONST bdk_rst_const_t
1669 #define bustype_BDK_RST_CONST BDK_CSR_TYPE_RSL
1670 #define basename_BDK_RST_CONST "RST_CONST"
1671 #define device_bar_BDK_RST_CONST 0x0 /* PF_BAR0 */
1672 #define busnum_BDK_RST_CONST 0
1673 #define arguments_BDK_RST_CONST -1,-1,-1,-1
1674
1675 /**
1676 * Register (RSL) rst_core_domain_w1c
1677 *
1678 * RST Core Domain Soft Reset Clear Register
1679 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1680 */
1681 union bdk_rst_core_domain_w1c
1682 {
1683 uint64_t u;
1684 struct bdk_rst_core_domain_w1c_s
1685 {
1686 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1687 uint64_t reserved_1_63 : 63;
1688 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of AP cores, cache, NCB and associated logic.
1689 When set to one, the soft reset of the core is removed.
1690 Reads of this register show the soft reset state. Not the actual core domain reset.
1691 Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
1692 the actual reset state. To compensate for delays in reset, this field should only
1693 be set if RST_RESET_ACTIVE[CORE] is set.
1694 This field is always reinitialized on a chip domain reset. */
1695 #else /* Word 0 - Little Endian */
1696 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of AP cores, cache, NCB and associated logic.
1697 When set to one, the soft reset of the core is removed.
1698 Reads of this register show the soft reset state. Not the actual core domain reset.
1699 Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
1700 the actual reset state. To compensate for delays in reset, this field should only
1701 be set if RST_RESET_ACTIVE[CORE] is set.
1702 This field is always reinitialized on a chip domain reset. */
1703 uint64_t reserved_1_63 : 63;
1704 #endif /* Word 0 - End */
1705 } s;
1706 /* struct bdk_rst_core_domain_w1c_s cn; */
1707 };
1708 typedef union bdk_rst_core_domain_w1c bdk_rst_core_domain_w1c_t;
1709
1710 #define BDK_RST_CORE_DOMAIN_W1C BDK_RST_CORE_DOMAIN_W1C_FUNC()
1711 static inline uint64_t BDK_RST_CORE_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CORE_DOMAIN_W1C_FUNC(void)1712 static inline uint64_t BDK_RST_CORE_DOMAIN_W1C_FUNC(void)
1713 {
1714 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1715 return 0x87e006001828ll;
1716 __bdk_csr_fatal("RST_CORE_DOMAIN_W1C", 0, 0, 0, 0, 0);
1717 }
1718
1719 #define typedef_BDK_RST_CORE_DOMAIN_W1C bdk_rst_core_domain_w1c_t
1720 #define bustype_BDK_RST_CORE_DOMAIN_W1C BDK_CSR_TYPE_RSL
1721 #define basename_BDK_RST_CORE_DOMAIN_W1C "RST_CORE_DOMAIN_W1C"
1722 #define device_bar_BDK_RST_CORE_DOMAIN_W1C 0x0 /* PF_BAR0 */
1723 #define busnum_BDK_RST_CORE_DOMAIN_W1C 0
1724 #define arguments_BDK_RST_CORE_DOMAIN_W1C -1,-1,-1,-1
1725
1726 /**
1727 * Register (RSL) rst_core_domain_w1s
1728 *
1729 * RST Core Domain Soft Reset Set Register
1730 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1731 */
1732 union bdk_rst_core_domain_w1s
1733 {
1734 uint64_t u;
1735 struct bdk_rst_core_domain_w1s_s
1736 {
1737 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1738 uint64_t reserved_1_63 : 63;
1739 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of AP cores, cache, NCB and associated logic.
1740 When set to one, all logic associated with the core domain is placed in reset.
1741 Reads of this register show the soft reset state. Not the actual core domain reset.
1742 Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
1743 the actual reset state.
1744 It is typically cleared by writing to RST_CORE_DOMAIN_W1C.
1745 This field is always reinitialized on a chip domain reset. */
1746 #else /* Word 0 - Little Endian */
1747 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of AP cores, cache, NCB and associated logic.
1748 When set to one, all logic associated with the core domain is placed in reset.
1749 Reads of this register show the soft reset state. Not the actual core domain reset.
1750 Other factors may keep the reset active, reading RST_RESET_ACTIVE[CORE] shows
1751 the actual reset state.
1752 It is typically cleared by writing to RST_CORE_DOMAIN_W1C.
1753 This field is always reinitialized on a chip domain reset. */
1754 uint64_t reserved_1_63 : 63;
1755 #endif /* Word 0 - End */
1756 } s;
1757 /* struct bdk_rst_core_domain_w1s_s cn; */
1758 };
1759 typedef union bdk_rst_core_domain_w1s bdk_rst_core_domain_w1s_t;
1760
1761 #define BDK_RST_CORE_DOMAIN_W1S BDK_RST_CORE_DOMAIN_W1S_FUNC()
1762 static inline uint64_t BDK_RST_CORE_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CORE_DOMAIN_W1S_FUNC(void)1763 static inline uint64_t BDK_RST_CORE_DOMAIN_W1S_FUNC(void)
1764 {
1765 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1766 return 0x87e006001820ll;
1767 __bdk_csr_fatal("RST_CORE_DOMAIN_W1S", 0, 0, 0, 0, 0);
1768 }
1769
1770 #define typedef_BDK_RST_CORE_DOMAIN_W1S bdk_rst_core_domain_w1s_t
1771 #define bustype_BDK_RST_CORE_DOMAIN_W1S BDK_CSR_TYPE_RSL
1772 #define basename_BDK_RST_CORE_DOMAIN_W1S "RST_CORE_DOMAIN_W1S"
1773 #define device_bar_BDK_RST_CORE_DOMAIN_W1S 0x0 /* PF_BAR0 */
1774 #define busnum_BDK_RST_CORE_DOMAIN_W1S 0
1775 #define arguments_BDK_RST_CORE_DOMAIN_W1S -1,-1,-1,-1
1776
1777 /**
1778 * Register (RSL) rst_core_pll
1779 *
1780 * RST Core Clock PLL Control Register
1781 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1782 */
1783 union bdk_rst_core_pll
1784 {
1785 uint64_t u;
1786 struct bdk_rst_core_pll_s
1787 {
1788 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1789 uint64_t reserved_51_63 : 13;
1790 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
1791 0x0 = Core clock divided by 16.
1792 0x1 = Core clock tree output divided by 16.
1793 0x2 = PLL0 output divided by 16.
1794 0x3 = PLL1 output divided by 16.
1795
1796 This field is always reinitialized on a cold domain reset. */
1797 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
1798 reset at least 10 PLL reference clocks prior
1799 to changing [COUT_SEL]. It should remain under reset for at least 10
1800 PLL reference clocks after [COUT_SEL] changes.
1801 This field is always reinitialized on a cold domain reset. */
1802 uint64_t reserved_45_47 : 3;
1803 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
1804 powers down the inactive PLL after the switch has occured.
1805 When cleared, the inactive PLL remains in operation.
1806 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
1807 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
1808
1809 Note that a powered down PLL requires an additional 575 reference
1810 clocks to become active. This time is automatically added by the
1811 hardware.
1812 This field is always reinitialized on a cold domain reset. */
1813 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
1814 When set to a nonzero value, the hardware will wait for
1815 any PLL programming to complete and then switch to the inactive
1816 PLL after the specified number of PLL reference clocks. Hardware
1817 will add additional clocks if required.
1818 This field is always reinitialized on a chip domain reset.
1819
1820 Internal:
1821 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
1822 Additional time will be added to wakeup powered down AP cores but that
1823 time not be included in this count. */
1824 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
1825 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
1826 uint64_t reserved_23_29 : 7;
1827 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
1828 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
1829 used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
1830 This field is always reinitialized on a cold domain reset. */
1831 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
1832 clears bit when both pll is updated and any delay specified
1833 in [DLY_SWITCH] has completed.
1834 This field is always reinitialized on a chip domain reset. */
1835 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
1836 actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
1837 a minimum setting of 300 MHz.
1838 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
1839 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
1840 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
1841 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
1842 immediately after a cold or chip domain reset. In both cases, value
1843 is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
1844 #else /* Word 0 - Little Endian */
1845 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Core clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
1846 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
1847 immediately after a cold or chip domain reset. In both cases, value
1848 is limited by RST_PLL_LIMIT[CORE_MAX_MUL]. */
1849 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
1850 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Core PLL frequency to be program in 50 MHz increments. The
1851 actual value used is limited by RST_PLL_LIMIT[CORE_MAX_MUL] and
1852 a minimum setting of 300 MHz.
1853 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
1854 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
1855 clears bit when both pll is updated and any delay specified
1856 in [DLY_SWITCH] has completed.
1857 This field is always reinitialized on a chip domain reset. */
1858 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Core clock multiplier to be used during a core or chip domain
1859 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
1860 used is limited by RST_PLL_LIMIT[CORE_MAX_MUL].
1861 This field is always reinitialized on a cold domain reset. */
1862 uint64_t reserved_23_29 : 7;
1863 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) Core PLL0 power down. When set PLL is currently powered down. */
1864 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) Core PLL1 power down. When set PLL is currently powered down. */
1865 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
1866 When set to a nonzero value, the hardware will wait for
1867 any PLL programming to complete and then switch to the inactive
1868 PLL after the specified number of PLL reference clocks. Hardware
1869 will add additional clocks if required.
1870 This field is always reinitialized on a chip domain reset.
1871
1872 Internal:
1873 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
1874 Additional time will be added to wakeup powered down AP cores but that
1875 time not be included in this count. */
1876 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
1877 powers down the inactive PLL after the switch has occured.
1878 When cleared, the inactive PLL remains in operation.
1879 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
1880 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
1881
1882 Note that a powered down PLL requires an additional 575 reference
1883 clocks to become active. This time is automatically added by the
1884 hardware.
1885 This field is always reinitialized on a cold domain reset. */
1886 uint64_t reserved_45_47 : 3;
1887 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Core clockout reset. The core clockout should be placed in
1888 reset at least 10 PLL reference clocks prior
1889 to changing [COUT_SEL]. It should remain under reset for at least 10
1890 PLL reference clocks after [COUT_SEL] changes.
1891 This field is always reinitialized on a cold domain reset. */
1892 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Core clockout select.
1893 0x0 = Core clock divided by 16.
1894 0x1 = Core clock tree output divided by 16.
1895 0x2 = PLL0 output divided by 16.
1896 0x3 = PLL1 output divided by 16.
1897
1898 This field is always reinitialized on a cold domain reset. */
1899 uint64_t reserved_51_63 : 13;
1900 #endif /* Word 0 - End */
1901 } s;
1902 /* struct bdk_rst_core_pll_s cn; */
1903 };
1904 typedef union bdk_rst_core_pll bdk_rst_core_pll_t;
1905
1906 #define BDK_RST_CORE_PLL BDK_RST_CORE_PLL_FUNC()
1907 static inline uint64_t BDK_RST_CORE_PLL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CORE_PLL_FUNC(void)1908 static inline uint64_t BDK_RST_CORE_PLL_FUNC(void)
1909 {
1910 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1911 return 0x87e00a001780ll;
1912 __bdk_csr_fatal("RST_CORE_PLL", 0, 0, 0, 0, 0);
1913 }
1914
1915 #define typedef_BDK_RST_CORE_PLL bdk_rst_core_pll_t
1916 #define bustype_BDK_RST_CORE_PLL BDK_CSR_TYPE_RSL
1917 #define basename_BDK_RST_CORE_PLL "RST_CORE_PLL"
1918 #define device_bar_BDK_RST_CORE_PLL 0x2 /* PF_BAR2 */
1919 #define busnum_BDK_RST_CORE_PLL 0
1920 #define arguments_BDK_RST_CORE_PLL -1,-1,-1,-1
1921
1922 /**
1923 * Register (RSL) rst_cpt_pll
1924 *
1925 * RST Crypto Clock PLL Control Register
1926 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
1927 */
1928 union bdk_rst_cpt_pll
1929 {
1930 uint64_t u;
1931 struct bdk_rst_cpt_pll_s
1932 {
1933 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1934 uint64_t reserved_51_63 : 13;
1935 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Cypto clockout select.
1936 0x0 = Crypto clock divided by 16.
1937 0x1 = Crypto clock tree output divided by 16.
1938 0x2 = PLL0 output divided by 16.
1939 0x3 = PLL1 output divided by 16.
1940
1941 This field is always reinitialized on a cold domain reset. */
1942 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
1943 reset at least 10 PLL reference clocks prior
1944 to changing [COUT_SEL]. It should remain under reset for at least 10
1945 PLL reference clocks after [COUT_SEL] changes.
1946 This field is always reinitialized on a cold domain reset. */
1947 uint64_t reserved_45_47 : 3;
1948 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
1949 powers down the inactive PLL after the switch has occured.
1950 When cleared, the inactive PLL remains in operation.
1951 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
1952 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
1953
1954 Note that a powered down PLL requires an additional 575 reference
1955 clocks to become active. This time is automatically added by the
1956 hardware.
1957 This field is always reinitialized on a cold domain reset. */
1958 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
1959 When set to a nonzero value, the hardware will wait for
1960 any PLL programming to complete and then switch to the inactive
1961 PLL after the specified number of PLL reference clocks. Hardware
1962 will add additional clocks if required.
1963 This field is always reinitialized on a chip domain reset.
1964
1965 Internal:
1966 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
1967 Additional time will be added to wakeup powered down AP cores but that
1968 time not be included in this count. */
1969 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
1970 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
1971 uint64_t reserved_23_29 : 7;
1972 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
1973 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
1974 used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
1975 This field is always reinitialized on a cold domain reset. */
1976 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
1977 clears bit when both pll is updated and any delay specified
1978 in [DLY_SWITCH] has completed.
1979 This field is always reinitialized on a chip domain reset. */
1980 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
1981 actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
1982 a minimum setting of 200 MHz.
1983 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
1984 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
1985 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
1986 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
1987 immediately after a cold or chip domain reset. In both cases, value
1988 is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
1989 #else /* Word 0 - Little Endian */
1990 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Crypto clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
1991 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
1992 immediately after a cold or chip domain reset. In both cases, value
1993 is limited by RST_PLL_LIMIT[CPT_MAX_MUL]. */
1994 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
1995 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Crypto PLL frequency to be program in 50 MHz increments. The
1996 actual value used is limited by RST_PLL_LIMIT[CPT_MAX_MUL] and
1997 a minimum setting of 200 MHz.
1998 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
1999 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
2000 clears bit when both pll is updated and any delay specified
2001 in [DLY_SWITCH] has completed.
2002 This field is always reinitialized on a chip domain reset. */
2003 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Crypto clock multiplier to be used during a core or chip domain
2004 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
2005 used is limited by RST_PLL_LIMIT[CPT_MAX_MUL].
2006 This field is always reinitialized on a cold domain reset. */
2007 uint64_t reserved_23_29 : 7;
2008 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) CPT PLL0 power down. When set PLL is currently powered down. */
2009 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) CPT PLL1 power down. When set PLL is currently powered down. */
2010 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
2011 When set to a nonzero value, the hardware will wait for
2012 any PLL programming to complete and then switch to the inactive
2013 PLL after the specified number of PLL reference clocks. Hardware
2014 will add additional clocks if required.
2015 This field is always reinitialized on a chip domain reset.
2016
2017 Internal:
2018 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
2019 Additional time will be added to wakeup powered down AP cores but that
2020 time not be included in this count. */
2021 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
2022 powers down the inactive PLL after the switch has occured.
2023 When cleared, the inactive PLL remains in operation.
2024 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
2025 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
2026
2027 Note that a powered down PLL requires an additional 575 reference
2028 clocks to become active. This time is automatically added by the
2029 hardware.
2030 This field is always reinitialized on a cold domain reset. */
2031 uint64_t reserved_45_47 : 3;
2032 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Crypto clockout reset. The crypto clockout should be placed in
2033 reset at least 10 PLL reference clocks prior
2034 to changing [COUT_SEL]. It should remain under reset for at least 10
2035 PLL reference clocks after [COUT_SEL] changes.
2036 This field is always reinitialized on a cold domain reset. */
2037 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Cypto clockout select.
2038 0x0 = Crypto clock divided by 16.
2039 0x1 = Crypto clock tree output divided by 16.
2040 0x2 = PLL0 output divided by 16.
2041 0x3 = PLL1 output divided by 16.
2042
2043 This field is always reinitialized on a cold domain reset. */
2044 uint64_t reserved_51_63 : 13;
2045 #endif /* Word 0 - End */
2046 } s;
2047 /* struct bdk_rst_cpt_pll_s cn; */
2048 };
2049 typedef union bdk_rst_cpt_pll bdk_rst_cpt_pll_t;
2050
2051 #define BDK_RST_CPT_PLL BDK_RST_CPT_PLL_FUNC()
2052 static inline uint64_t BDK_RST_CPT_PLL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_CPT_PLL_FUNC(void)2053 static inline uint64_t BDK_RST_CPT_PLL_FUNC(void)
2054 {
2055 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2056 return 0x87e00a001778ll;
2057 __bdk_csr_fatal("RST_CPT_PLL", 0, 0, 0, 0, 0);
2058 }
2059
2060 #define typedef_BDK_RST_CPT_PLL bdk_rst_cpt_pll_t
2061 #define bustype_BDK_RST_CPT_PLL BDK_CSR_TYPE_RSL
2062 #define basename_BDK_RST_CPT_PLL "RST_CPT_PLL"
2063 #define device_bar_BDK_RST_CPT_PLL 0x2 /* PF_BAR2 */
2064 #define busnum_BDK_RST_CPT_PLL 0
2065 #define arguments_BDK_RST_CPT_PLL -1,-1,-1,-1
2066
2067 /**
2068 * Register (RSL) rst_ctl#
2069 *
2070 * RST Controllers Registers
2071 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2072 */
2073 union bdk_rst_ctlx
2074 {
2075 uint64_t u;
2076 struct bdk_rst_ctlx_s
2077 {
2078 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2079 uint64_t reserved_14_63 : 50;
2080 uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset and
2081 PERST events. See [PF_FLR_CHIP], [RST_LINK] and [RST_CHIP].
2082
2083 0 = Chip domain reset.
2084 1 = Core domain reset.
2085
2086 On cold reset, this field is initialized as follows:
2087 _ 0 when RST_CTL()[HOST_MODE] = 0.
2088 _ 1 when RST_CTL()[HOST_MODE] = 1. */
2089 uint64_t reserved_11_12 : 2;
2090 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
2091 reset like CHIP_RESET_L. A warm/soft reset does not change this field.
2092 On cold reset, this field is initialized as follows:
2093
2094 _ 0 when RST_CTL()[HOST_MODE] = 1.
2095
2096 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2097 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2098 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2099 controller, and (provided properly configured) the link should come back up
2100 automatically.
2101 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2102 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2103 until software clears RST_SOFT_PRST()[SOFT_PRST].
2104
2105 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2106 0. */
2107 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2108 (i.e. the controller is held in reset) when
2109 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2110 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2111 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2112 reset causes a warm chip reset.
2113
2114 On cold reset, this field is initialized as follows:
2115
2116 _ 0 when RST_CTL()[HOST_MODE] = 1.
2117
2118 _ 1 when RST_CTL()[HOST_MODE] = 0.
2119
2120 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2121 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2122 uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
2123 uint64_t reserved_4_5 : 2;
2124 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2125 reset, this field is initialized as follows:
2126
2127 _ 0 when RST_CTL()[HOST_MODE] = 0.
2128
2129 _ 1 when RST_CTL()[HOST_MODE] = 1.
2130
2131 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2132 the corresponding PERST*_L pin. */
2133 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2134 not change this field. On cold reset, this field is initialized as follows:
2135
2136 _ 0 when RST_CTL()[HOST_MODE] = 1.
2137
2138 _ 1 when RST_CTL()[HOST_MODE] = 0.
2139
2140 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2141 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2142
2143 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2144 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2145 a controller reset sequence.)
2146
2147 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2148
2149 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2150 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2151 does not change this field. On cold reset, this field is initialized to 0.
2152
2153 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2154
2155 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2156 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2157
2158 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2159
2160 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2161 #else /* Word 0 - Little Endian */
2162 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2163
2164 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2165
2166 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2167 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2168 does not change this field. On cold reset, this field is initialized to 0.
2169
2170 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2171
2172 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2173 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2174 not change this field. On cold reset, this field is initialized as follows:
2175
2176 _ 0 when RST_CTL()[HOST_MODE] = 1.
2177
2178 _ 1 when RST_CTL()[HOST_MODE] = 0.
2179
2180 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2181 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2182
2183 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2184 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2185 a controller reset sequence.)
2186
2187 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2188
2189 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2190 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2191 reset, this field is initialized as follows:
2192
2193 _ 0 when RST_CTL()[HOST_MODE] = 0.
2194
2195 _ 1 when RST_CTL()[HOST_MODE] = 1.
2196
2197 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2198 the corresponding PERST*_L pin. */
2199 uint64_t reserved_4_5 : 2;
2200 uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
2201 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2202 reset causes a warm chip reset.
2203
2204 On cold reset, this field is initialized as follows:
2205
2206 _ 0 when RST_CTL()[HOST_MODE] = 1.
2207
2208 _ 1 when RST_CTL()[HOST_MODE] = 0.
2209
2210 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2211 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2212 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2213 (i.e. the controller is held in reset) when
2214 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2215 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2216 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2217 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2218 controller, and (provided properly configured) the link should come back up
2219 automatically.
2220 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2221 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2222 until software clears RST_SOFT_PRST()[SOFT_PRST].
2223
2224 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2225 0. */
2226 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
2227 reset like CHIP_RESET_L. A warm/soft reset does not change this field.
2228 On cold reset, this field is initialized as follows:
2229
2230 _ 0 when RST_CTL()[HOST_MODE] = 1.
2231
2232 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2233 uint64_t reserved_11_12 : 2;
2234 uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset and
2235 PERST events. See [PF_FLR_CHIP], [RST_LINK] and [RST_CHIP].
2236
2237 0 = Chip domain reset.
2238 1 = Core domain reset.
2239
2240 On cold reset, this field is initialized as follows:
2241 _ 0 when RST_CTL()[HOST_MODE] = 0.
2242 _ 1 when RST_CTL()[HOST_MODE] = 1. */
2243 uint64_t reserved_14_63 : 50;
2244 #endif /* Word 0 - End */
2245 } s;
2246 struct bdk_rst_ctlx_cn9
2247 {
2248 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2249 uint64_t reserved_14_63 : 50;
2250 uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset and
2251 PERST events. See [PF_FLR_CHIP], [RST_LINK] and [RST_CHIP].
2252
2253 0 = Chip domain reset.
2254 1 = Core domain reset.
2255
2256 On cold reset, this field is initialized as follows:
2257 _ 0 when RST_CTL()[HOST_MODE] = 0.
2258 _ 1 when RST_CTL()[HOST_MODE] = 1. */
2259 uint64_t reserved_11_12 : 2;
2260 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
2261 0 = PF FLR events will not cause a reset.
2262 1 = A PF FLR event received by the PCIe logic causes the internal reset
2263 specified by [RESET_TYPE].
2264
2265 On cold reset, this field is initialized as follows:
2266 _ 0 when RST_CTL()[HOST_MODE] = 1.
2267 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2268 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2269 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2270 controller, and (provided properly configured) the link should come back up
2271 automatically.
2272 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2273 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2274 until software clears RST_SOFT_PRST()[SOFT_PRST].
2275
2276 A warm/soft reset does not change this field. On cold reset, this field is
2277 initialized to 0. */
2278 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2279 (i.e. the controller is held in reset) when
2280 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2281 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2282 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
2283 0 = Link down or hot reset do not cause a chip/core domain reset.
2284 1 = A link-down or hot-reset event on the PCIe interface causes the internal
2285 reset specified by [RESET_TYPE].
2286
2287 The field is initialized as follows:
2288 _ 0 when RST_CTL()[HOST_MODE] is set.
2289 _ 1 when RST_CTL()[HOST_MODE] is cleared.
2290
2291 Note that a link-down or hot reset event can never cause a domain reset when the
2292 controller is already in reset (i.e. when [RST_DONE] = 0). */
2293 uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
2294 indicating PEMn is root complex (host). */
2295 uint64_t reserved_4_5 : 2;
2296 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
2297 This field is always reinitialized on a cold domain reset.
2298 The field is initialized as follows:
2299 _ 0 when RST_CTL()[HOST_MODE] is cleared.
2300 _ 1 when RST_CTL()[HOST_MODE] is set. */
2301 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
2302 This field is always reinitialized on a cold domain reset.
2303 The field is initialized as follows:
2304 _ 0 when RST_CTL()[HOST_MODE] is set.
2305 _ 1 when RST_CTL()[HOST_MODE] is cleared.
2306
2307 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2308 controller and (optionally, based on [RST_CHIP]) cause a domain reset.
2309
2310 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2311 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2312 a controller reset sequence.)
2313
2314 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2315
2316 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2317 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
2318 logic will generate an internal reset specified by [RESET_TYPE]
2319 when the corresponding PERST*_L pin is asserted. When cleared or
2320 when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
2321
2322 During a cold domain reset this field is initialized to zero. */
2323 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2324
2325 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2326 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2327 #else /* Word 0 - Little Endian */
2328 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2329
2330 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2331 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2332 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) PERST internal reset enable. When set along with [RST_RCV],
2333 logic will generate an internal reset specified by [RESET_TYPE]
2334 when the corresponding PERST*_L pin is asserted. When cleared or
2335 when [RST_RCV] is cleared, the PERST*_L does not cause an internal reset.
2336
2337 During a cold domain reset this field is initialized to zero. */
2338 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received.
2339 This field is always reinitialized on a cold domain reset.
2340 The field is initialized as follows:
2341 _ 0 when RST_CTL()[HOST_MODE] is set.
2342 _ 1 when RST_CTL()[HOST_MODE] is cleared.
2343
2344 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2345 controller and (optionally, based on [RST_CHIP]) cause a domain reset.
2346
2347 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2348 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2349 a controller reset sequence.)
2350
2351 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2352
2353 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2354 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven.
2355 This field is always reinitialized on a cold domain reset.
2356 The field is initialized as follows:
2357 _ 0 when RST_CTL()[HOST_MODE] is cleared.
2358 _ 1 when RST_CTL()[HOST_MODE] is set. */
2359 uint64_t reserved_4_5 : 2;
2360 uint64_t host_mode : 1; /**< [ 6: 6](RO/H) Read-only access to the corresponding PEM()_CFG[HOSTMD] field
2361 indicating PEMn is root complex (host). */
2362 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Link down / hot reset event internal reset enable.
2363 0 = Link down or hot reset do not cause a chip/core domain reset.
2364 1 = A link-down or hot-reset event on the PCIe interface causes the internal
2365 reset specified by [RESET_TYPE].
2366
2367 The field is initialized as follows:
2368 _ 0 when RST_CTL()[HOST_MODE] is set.
2369 _ 1 when RST_CTL()[HOST_MODE] is cleared.
2370
2371 Note that a link-down or hot reset event can never cause a domain reset when the
2372 controller is already in reset (i.e. when [RST_DONE] = 0). */
2373 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2374 (i.e. the controller is held in reset) when
2375 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2376 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2377 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2378 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2379 controller, and (provided properly configured) the link should come back up
2380 automatically.
2381 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2382 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2383 until software clears RST_SOFT_PRST()[SOFT_PRST].
2384
2385 A warm/soft reset does not change this field. On cold reset, this field is
2386 initialized to 0. */
2387 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) PF FLR internal reset enable.
2388 0 = PF FLR events will not cause a reset.
2389 1 = A PF FLR event received by the PCIe logic causes the internal reset
2390 specified by [RESET_TYPE].
2391
2392 On cold reset, this field is initialized as follows:
2393 _ 0 when RST_CTL()[HOST_MODE] = 1.
2394 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2395 uint64_t reserved_11_12 : 2;
2396 uint64_t reset_type : 1; /**< [ 13: 13](R/W) Type of reset generated internally by PCI MAC PF FLR, link down/hot reset and
2397 PERST events. See [PF_FLR_CHIP], [RST_LINK] and [RST_CHIP].
2398
2399 0 = Chip domain reset.
2400 1 = Core domain reset.
2401
2402 On cold reset, this field is initialized as follows:
2403 _ 0 when RST_CTL()[HOST_MODE] = 0.
2404 _ 1 when RST_CTL()[HOST_MODE] = 1. */
2405 uint64_t reserved_14_63 : 50;
2406 #endif /* Word 0 - End */
2407 } cn9;
2408 struct bdk_rst_ctlx_cn81xx
2409 {
2410 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2411 uint64_t reserved_10_63 : 54;
2412 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2413 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2414 controller, and (provided properly configured) the link should come back up
2415 automatically.
2416 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2417 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2418 until software clears RST_SOFT_PRST()[SOFT_PRST].
2419
2420 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2421 0. */
2422 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2423 (i.e. the controller is held in reset) when
2424 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2425 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2426 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2427 reset causes a warm chip reset.
2428
2429 On cold reset, this field is initialized as follows:
2430
2431 _ 0 when RST_CTL()[HOST_MODE] = 1.
2432
2433 _ 1 when RST_CTL()[HOST_MODE] = 0.
2434
2435 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2436 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2437 uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
2438 uint64_t reserved_4_5 : 2;
2439 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2440 reset, this field is initialized as follows:
2441
2442 _ 0 when RST_CTL()[HOST_MODE] = 0.
2443
2444 _ 1 when RST_CTL()[HOST_MODE] = 1.
2445
2446 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2447 the corresponding PERST*_L pin. */
2448 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2449 not change this field. On cold reset, this field is initialized as follows:
2450
2451 _ 0 when RST_CTL()[HOST_MODE] = 1.
2452
2453 _ 1 when RST_CTL()[HOST_MODE] = 0.
2454
2455 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2456 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2457
2458 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2459 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2460 a controller reset sequence.)
2461
2462 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2463
2464 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2465 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2466 does not change this field. On cold reset, this field is initialized to 0.
2467
2468 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2469
2470 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2471 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2472
2473 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2474
2475 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2476 #else /* Word 0 - Little Endian */
2477 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2478
2479 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2480
2481 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2482 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2483 does not change this field. On cold reset, this field is initialized to 0.
2484
2485 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2486
2487 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2488 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2489 not change this field. On cold reset, this field is initialized as follows:
2490
2491 _ 0 when RST_CTL()[HOST_MODE] = 1.
2492
2493 _ 1 when RST_CTL()[HOST_MODE] = 0.
2494
2495 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2496 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2497
2498 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2499 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2500 a controller reset sequence.)
2501
2502 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2503
2504 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2505 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2506 reset, this field is initialized as follows:
2507
2508 _ 0 when RST_CTL()[HOST_MODE] = 0.
2509
2510 _ 1 when RST_CTL()[HOST_MODE] = 1.
2511
2512 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2513 the corresponding PERST*_L pin. */
2514 uint64_t reserved_4_5 : 2;
2515 uint64_t host_mode : 1; /**< [ 6: 6](RO) For all controllers this field is set as host. */
2516 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2517 reset causes a warm chip reset.
2518
2519 On cold reset, this field is initialized as follows:
2520
2521 _ 0 when RST_CTL()[HOST_MODE] = 1.
2522
2523 _ 1 when RST_CTL()[HOST_MODE] = 0.
2524
2525 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2526 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2527 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2528 (i.e. the controller is held in reset) when
2529 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2530 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2531 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2532 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2533 controller, and (provided properly configured) the link should come back up
2534 automatically.
2535 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2536 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2537 until software clears RST_SOFT_PRST()[SOFT_PRST].
2538
2539 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2540 0. */
2541 uint64_t reserved_10_63 : 54;
2542 #endif /* Word 0 - End */
2543 } cn81xx;
2544 /* struct bdk_rst_ctlx_cn81xx cn88xx; */
2545 struct bdk_rst_ctlx_cn83xx
2546 {
2547 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2548 uint64_t reserved_11_63 : 53;
2549 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
2550 reset like CHIP_RESET_L. A warm/soft reset does not change this field.
2551 On cold reset, this field is initialized as follows:
2552
2553 _ 0 when RST_CTL()[HOST_MODE] = 1.
2554
2555 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2556 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2557 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2558 controller, and (provided properly configured) the link should come back up
2559 automatically.
2560 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2561 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2562 until software clears RST_SOFT_PRST()[SOFT_PRST].
2563
2564 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2565 0. */
2566 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2567 (i.e. the controller is held in reset) when
2568 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2569 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2570 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2571 reset causes a warm chip reset.
2572
2573 On cold reset, this field is initialized as follows:
2574
2575 _ 0 when RST_CTL()[HOST_MODE] = 1.
2576
2577 _ 1 when RST_CTL()[HOST_MODE] = 0.
2578
2579 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2580 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2581 uint64_t host_mode : 1; /**< [ 6: 6](RO) Read-only access to the corresponding PEM()_CFG[HOSTMD] field indicating PEMn is root
2582 complex (host). For controllers 0 and 2 the initial value is determined by straps. For
2583 controllers 1 and 3 this field is initially set as host. */
2584 uint64_t reserved_4_5 : 2;
2585 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2586 reset, this field is initialized as follows:
2587
2588 _ 0 when RST_CTL()[HOST_MODE] = 0.
2589
2590 _ 1 when RST_CTL()[HOST_MODE] = 1.
2591
2592 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2593 the corresponding PERST*_L pin. */
2594 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2595 not change this field. On cold reset, this field is initialized as follows:
2596
2597 _ 0 when RST_CTL()[HOST_MODE] = 1.
2598
2599 _ 1 when RST_CTL()[HOST_MODE] = 0.
2600
2601 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2602 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2603
2604 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2605 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2606 a controller reset sequence.)
2607
2608 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2609
2610 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2611 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2612 does not change this field. On cold reset, this field is initialized to 0.
2613
2614 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2615
2616 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2617 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2618
2619 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2620
2621 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2622 #else /* Word 0 - Little Endian */
2623 uint64_t rst_val : 1; /**< [ 0: 0](RO/H) Read-only access to PERST*_L. Unpredictable when [RST_RCV] = 0.
2624
2625 Reads as 1 when [RST_RCV] = 1 and the PERST*_L pin is asserted.
2626
2627 Reads as 0 when [RST_RCV] = 1 and the PERST*_L pin is not asserted. */
2628 uint64_t rst_chip : 1; /**< [ 1: 1](R/W) Controls whether PERST*_L causes a chip warm reset like CHIP_RESET_L. A warm/soft reset
2629 does not change this field. On cold reset, this field is initialized to 0.
2630
2631 When [RST_RCV] = 0, [RST_CHIP] is ignored.
2632
2633 When [RST_RCV] = 1, [RST_CHIP] = 1, and PERST*_L asserts, a chip warm reset is generated. */
2634 uint64_t rst_rcv : 1; /**< [ 2: 2](R/W) Reset received. Controls whether PERST*_L is received. A warm/soft reset does
2635 not change this field. On cold reset, this field is initialized as follows:
2636
2637 _ 0 when RST_CTL()[HOST_MODE] = 1.
2638
2639 _ 1 when RST_CTL()[HOST_MODE] = 0.
2640
2641 When [RST_RCV] = 1, the PERST*_L value is received and can be used to reset the
2642 controller and (optionally, based on [RST_CHIP]) warm reset the chip.
2643
2644 When [RST_RCV] = 1 (and [RST_CHIP] = 0), RST_INT[PERST*] gets set when the PERST*_L
2645 pin asserts. (This interrupt can alert software whenever the external reset pin initiates
2646 a controller reset sequence.)
2647
2648 [RST_VAL] gives the PERST*_L pin value when [RST_RCV] = 1.
2649
2650 When [RST_RCV] = 0, the PERST*_L pin value is ignored. */
2651 uint64_t rst_drv : 1; /**< [ 3: 3](R/W) Controls whether PERST*_L is driven. A warm/soft reset does not change this field. On cold
2652 reset, this field is initialized as follows:
2653
2654 _ 0 when RST_CTL()[HOST_MODE] = 0.
2655
2656 _ 1 when RST_CTL()[HOST_MODE] = 1.
2657
2658 When set, CNXXXX drives the corresponding PERST*_L pin. Otherwise, CNXXXX does not drive
2659 the corresponding PERST*_L pin. */
2660 uint64_t reserved_4_5 : 2;
2661 uint64_t host_mode : 1; /**< [ 6: 6](RO) Read-only access to the corresponding PEM()_CFG[HOSTMD] field indicating PEMn is root
2662 complex (host). For controllers 0 and 2 the initial value is determined by straps. For
2663 controllers 1 and 3 this field is initially set as host. */
2664 uint64_t rst_link : 1; /**< [ 7: 7](R/W) Reset on link down. When set, a corresponding controller link-down reset or hot
2665 reset causes a warm chip reset.
2666
2667 On cold reset, this field is initialized as follows:
2668
2669 _ 0 when RST_CTL()[HOST_MODE] = 1.
2670
2671 _ 1 when RST_CTL()[HOST_MODE] = 0.
2672
2673 Note that a link-down or hot-reset event can never cause a warm chip reset when the
2674 controller is in reset (i.e. can never cause a warm reset when [RST_DONE] = 0). */
2675 uint64_t rst_done : 1; /**< [ 8: 8](RO/H) Reset done. Indicates the controller reset status. [RST_DONE] is always 0
2676 (i.e. the controller is held in reset) when
2677 * RST_SOFT_PRST()[SOFT_PRST] = 1, or
2678 * [RST_RCV] = 1 and PERST*_L pin is asserted. */
2679 uint64_t prst_link : 1; /**< [ 9: 9](R/W) PEM reset on link down.
2680 0 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2681 controller, and (provided properly configured) the link should come back up
2682 automatically.
2683 1 = Link-down or hot-reset will set RST_INT[RST_LINK] for the corresponding
2684 controller, and set RST_SOFT_PRST()[SOFT_PRST]. This will hold the link in reset
2685 until software clears RST_SOFT_PRST()[SOFT_PRST].
2686
2687 A warm/soft reset does not change this field. On cold reset, this field is initialized to
2688 0. */
2689 uint64_t pf_flr_chip : 1; /**< [ 10: 10](R/W) Controls whether corresponding controller PF Function Level Reset causes a chip warm
2690 reset like CHIP_RESET_L. A warm/soft reset does not change this field.
2691 On cold reset, this field is initialized as follows:
2692
2693 _ 0 when RST_CTL()[HOST_MODE] = 1.
2694
2695 _ 1 when RST_CTL()[HOST_MODE] = 0. */
2696 uint64_t reserved_11_63 : 53;
2697 #endif /* Word 0 - End */
2698 } cn83xx;
2699 };
2700 typedef union bdk_rst_ctlx bdk_rst_ctlx_t;
2701
2702 static inline uint64_t BDK_RST_CTLX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_CTLX(unsigned long a)2703 static inline uint64_t BDK_RST_CTLX(unsigned long a)
2704 {
2705 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=2))
2706 return 0x87e006001640ll + 8ll * ((a) & 0x3);
2707 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
2708 return 0x87e006001640ll + 8ll * ((a) & 0x3);
2709 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
2710 return 0x87e006001640ll + 8ll * ((a) & 0x7);
2711 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
2712 return 0x87e006001640ll + 8ll * ((a) & 0x3);
2713 __bdk_csr_fatal("RST_CTLX", 1, a, 0, 0, 0);
2714 }
2715
2716 #define typedef_BDK_RST_CTLX(a) bdk_rst_ctlx_t
2717 #define bustype_BDK_RST_CTLX(a) BDK_CSR_TYPE_RSL
2718 #define basename_BDK_RST_CTLX(a) "RST_CTLX"
2719 #define device_bar_BDK_RST_CTLX(a) 0x0 /* PF_BAR0 */
2720 #define busnum_BDK_RST_CTLX(a) (a)
2721 #define arguments_BDK_RST_CTLX(a) (a),-1,-1,-1
2722
2723 /**
2724 * Register (RSL) rst_dbg_reset
2725 *
2726 * RST Debug Logic Reset Register
2727 * This register contains the reset control for each core's debug logic.
2728 * Debug reset is not supported in pass 2.
2729 */
2730 union bdk_rst_dbg_reset
2731 {
2732 uint64_t u;
2733 struct bdk_rst_dbg_reset_s
2734 {
2735 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2736 uint64_t reserved_48_63 : 16;
2737 uint64_t rst : 48; /**< [ 47: 0](R/W) Debug logic reset for each core:
2738 0 = Debug logic operates normally.
2739 1 = Holds the debug logic in its reset state.
2740
2741 The register is reset to 0 only during cold reset, the value is unaffected by
2742 warm and soft reset. */
2743 #else /* Word 0 - Little Endian */
2744 uint64_t rst : 48; /**< [ 47: 0](R/W) Debug logic reset for each core:
2745 0 = Debug logic operates normally.
2746 1 = Holds the debug logic in its reset state.
2747
2748 The register is reset to 0 only during cold reset, the value is unaffected by
2749 warm and soft reset. */
2750 uint64_t reserved_48_63 : 16;
2751 #endif /* Word 0 - End */
2752 } s;
2753 /* struct bdk_rst_dbg_reset_s cn88xxp1; */
2754 struct bdk_rst_dbg_reset_cn81xx
2755 {
2756 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2757 uint64_t reserved_4_63 : 60;
2758 uint64_t rst : 4; /**< [ 3: 0](R/W) Reserved. */
2759 #else /* Word 0 - Little Endian */
2760 uint64_t rst : 4; /**< [ 3: 0](R/W) Reserved. */
2761 uint64_t reserved_4_63 : 60;
2762 #endif /* Word 0 - End */
2763 } cn81xx;
2764 struct bdk_rst_dbg_reset_cn83xx
2765 {
2766 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2767 uint64_t reserved_24_63 : 40;
2768 uint64_t rst : 24; /**< [ 23: 0](R/W) Reserved. */
2769 #else /* Word 0 - Little Endian */
2770 uint64_t rst : 24; /**< [ 23: 0](R/W) Reserved. */
2771 uint64_t reserved_24_63 : 40;
2772 #endif /* Word 0 - End */
2773 } cn83xx;
2774 struct bdk_rst_dbg_reset_cn88xxp2
2775 {
2776 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2777 uint64_t reserved_48_63 : 16;
2778 uint64_t rst : 48; /**< [ 47: 0](R/W) Reserved. */
2779 #else /* Word 0 - Little Endian */
2780 uint64_t rst : 48; /**< [ 47: 0](R/W) Reserved. */
2781 uint64_t reserved_48_63 : 16;
2782 #endif /* Word 0 - End */
2783 } cn88xxp2;
2784 };
2785 typedef union bdk_rst_dbg_reset bdk_rst_dbg_reset_t;
2786
2787 #define BDK_RST_DBG_RESET BDK_RST_DBG_RESET_FUNC()
2788 static inline uint64_t BDK_RST_DBG_RESET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_DBG_RESET_FUNC(void)2789 static inline uint64_t BDK_RST_DBG_RESET_FUNC(void)
2790 {
2791 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2792 return 0x87e006001750ll;
2793 __bdk_csr_fatal("RST_DBG_RESET", 0, 0, 0, 0, 0);
2794 }
2795
2796 #define typedef_BDK_RST_DBG_RESET bdk_rst_dbg_reset_t
2797 #define bustype_BDK_RST_DBG_RESET BDK_CSR_TYPE_RSL
2798 #define basename_BDK_RST_DBG_RESET "RST_DBG_RESET"
2799 #define device_bar_BDK_RST_DBG_RESET 0x0 /* PF_BAR0 */
2800 #define busnum_BDK_RST_DBG_RESET 0
2801 #define arguments_BDK_RST_DBG_RESET -1,-1,-1,-1
2802
2803 /**
2804 * Register (RSL) rst_debug
2805 *
2806 * RST Debug Register
2807 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2808 */
2809 union bdk_rst_debug
2810 {
2811 uint64_t u;
2812 struct bdk_rst_debug_s
2813 {
2814 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2815 uint64_t reserved_4_63 : 60;
2816 uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
2817 Setting this field will force all DLLs to track clock changes.
2818 For diagnostic use only.
2819
2820 This field is always reinitialized on a cold domain reset. */
2821 uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
2822 Setting this field will force all clocks on while they are in reset and
2823 will dramatically increase power consumption.
2824 For diagnostic use only.
2825 This field is always reinitialized on a cold domain reset. */
2826 uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
2827 For diagnostic use only.
2828 This field is always reinitialized on a cold domain reset.
2829
2830 Internal:
2831 Forces store-n-forward across clock domains. */
2832 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
2833 #else /* Word 0 - Little Endian */
2834 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
2835 uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
2836 For diagnostic use only.
2837 This field is always reinitialized on a cold domain reset.
2838
2839 Internal:
2840 Forces store-n-forward across clock domains. */
2841 uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
2842 Setting this field will force all clocks on while they are in reset and
2843 will dramatically increase power consumption.
2844 For diagnostic use only.
2845 This field is always reinitialized on a cold domain reset. */
2846 uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
2847 Setting this field will force all DLLs to track clock changes.
2848 For diagnostic use only.
2849
2850 This field is always reinitialized on a cold domain reset. */
2851 uint64_t reserved_4_63 : 60;
2852 #endif /* Word 0 - End */
2853 } s;
2854 struct bdk_rst_debug_cn8
2855 {
2856 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2857 uint64_t reserved_1_63 : 63;
2858 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
2859 #else /* Word 0 - Little Endian */
2860 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on. For diagnostic use only. */
2861 uint64_t reserved_1_63 : 63;
2862 #endif /* Word 0 - End */
2863 } cn8;
2864 struct bdk_rst_debug_cn9
2865 {
2866 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2867 uint64_t reserved_4_63 : 60;
2868 uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
2869 Setting this field will force all DLLs to track clock changes.
2870 For diagnostic use only.
2871
2872 This field is always reinitialized on a cold domain reset. */
2873 uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
2874 Setting this field will force all clocks on while they are in reset and
2875 will dramatically increase power consumption.
2876 For diagnostic use only.
2877 This field is always reinitialized on a cold domain reset. */
2878 uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
2879 For diagnostic use only.
2880 This field is always reinitialized on a cold domain reset.
2881
2882 Internal:
2883 Forces store-n-forward across clock domains. */
2884 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
2885 For diagnostic use only.
2886 This field is always reinitialized on a cold domain reset. */
2887 #else /* Word 0 - Little Endian */
2888 uint64_t clk_on : 1; /**< [ 0: 0](R/W) Force conditional clock used for interrupt logic to always be on.
2889 For diagnostic use only.
2890 This field is always reinitialized on a cold domain reset. */
2891 uint64_t clk_cng : 1; /**< [ 1: 1](R/W) Force clock-changing indicator on.
2892 For diagnostic use only.
2893 This field is always reinitialized on a cold domain reset.
2894
2895 Internal:
2896 Forces store-n-forward across clock domains. */
2897 uint64_t clkena_on : 1; /**< [ 2: 2](R/W) Force global clock enable on.
2898 Setting this field will force all clocks on while they are in reset and
2899 will dramatically increase power consumption.
2900 For diagnostic use only.
2901 This field is always reinitialized on a cold domain reset. */
2902 uint64_t dll_csr_wakeup : 1; /**< [ 3: 3](R/W) Forces DLL setting to unlock.
2903 Setting this field will force all DLLs to track clock changes.
2904 For diagnostic use only.
2905
2906 This field is always reinitialized on a cold domain reset. */
2907 uint64_t reserved_4_63 : 60;
2908 #endif /* Word 0 - End */
2909 } cn9;
2910 };
2911 typedef union bdk_rst_debug bdk_rst_debug_t;
2912
2913 #define BDK_RST_DEBUG BDK_RST_DEBUG_FUNC()
2914 static inline uint64_t BDK_RST_DEBUG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_DEBUG_FUNC(void)2915 static inline uint64_t BDK_RST_DEBUG_FUNC(void)
2916 {
2917 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
2918 return 0x87e0060017b0ll;
2919 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
2920 return 0x87e0060017b0ll;
2921 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
2922 return 0x87e0060017b0ll;
2923 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
2924 return 0x87e0060017b0ll;
2925 __bdk_csr_fatal("RST_DEBUG", 0, 0, 0, 0, 0);
2926 }
2927
2928 #define typedef_BDK_RST_DEBUG bdk_rst_debug_t
2929 #define bustype_BDK_RST_DEBUG BDK_CSR_TYPE_RSL
2930 #define basename_BDK_RST_DEBUG "RST_DEBUG"
2931 #define device_bar_BDK_RST_DEBUG 0x0 /* PF_BAR0 */
2932 #define busnum_BDK_RST_DEBUG 0
2933 #define arguments_BDK_RST_DEBUG -1,-1,-1,-1
2934
2935 /**
2936 * Register (RSL) rst_delay
2937 *
2938 * RST Delay Register
2939 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
2940 */
2941 union bdk_rst_delay
2942 {
2943 uint64_t u;
2944 struct bdk_rst_delay_s
2945 {
2946 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2947 uint64_t reserved_32_63 : 32;
2948 uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
2949 the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
2950 reset does not change this field.
2951 This must be at least 0x200 coprocessor-clock cycles. */
2952 uint64_t reserved_0_15 : 16;
2953 #else /* Word 0 - Little Endian */
2954 uint64_t reserved_0_15 : 16;
2955 uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
2956 the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
2957 reset does not change this field.
2958 This must be at least 0x200 coprocessor-clock cycles. */
2959 uint64_t reserved_32_63 : 32;
2960 #endif /* Word 0 - End */
2961 } s;
2962 struct bdk_rst_delay_cn8
2963 {
2964 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2965 uint64_t reserved_32_63 : 32;
2966 uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
2967 the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
2968 reset does not change this field.
2969 This must be at least 0x200 coprocessor-clock cycles. */
2970 uint64_t soft_rst_dly : 16; /**< [ 15: 0](R/W) Soft reset delay. A soft reset immediately causes an early soft-reset notification, but
2971 the assertion of soft reset is delayed this many coprocessor-clock cycles. A warm/soft
2972 reset does not change this field.
2973 This must be at least 0x200 coprocessor-clock cycles. */
2974 #else /* Word 0 - Little Endian */
2975 uint64_t soft_rst_dly : 16; /**< [ 15: 0](R/W) Soft reset delay. A soft reset immediately causes an early soft-reset notification, but
2976 the assertion of soft reset is delayed this many coprocessor-clock cycles. A warm/soft
2977 reset does not change this field.
2978 This must be at least 0x200 coprocessor-clock cycles. */
2979 uint64_t warm_rst_dly : 16; /**< [ 31: 16](R/W) Warm reset delay. A warm reset immediately causes an early warm-reset notification, but
2980 the assertion of warm reset is delayed this many coprocessor-clock cycles. A warm/soft
2981 reset does not change this field.
2982 This must be at least 0x200 coprocessor-clock cycles. */
2983 uint64_t reserved_32_63 : 32;
2984 #endif /* Word 0 - End */
2985 } cn8;
2986 struct bdk_rst_delay_cn9
2987 {
2988 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2989 uint64_t reserved_16_63 : 48;
2990 uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
2991 notification to the dDR interface. The assertion of the domain reset is delayed
2992 by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
2993 Typical value is 4 uS once DDR has been initialized.
2994 This field is reinitialized with a cold domain reset. */
2995 #else /* Word 0 - Little Endian */
2996 uint64_t rst_dly : 16; /**< [ 15: 0](R/W) Reset delay. Chip and core domain resets immediately causes an early reset
2997 notification to the dDR interface. The assertion of the domain reset is delayed
2998 by this many 100 MHz PLL reference clocks. The minimum value is 1 uS.
2999 Typical value is 4 uS once DDR has been initialized.
3000 This field is reinitialized with a cold domain reset. */
3001 uint64_t reserved_16_63 : 48;
3002 #endif /* Word 0 - End */
3003 } cn9;
3004 };
3005 typedef union bdk_rst_delay bdk_rst_delay_t;
3006
3007 #define BDK_RST_DELAY BDK_RST_DELAY_FUNC()
3008 static inline uint64_t BDK_RST_DELAY_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_DELAY_FUNC(void)3009 static inline uint64_t BDK_RST_DELAY_FUNC(void)
3010 {
3011 return 0x87e006001608ll;
3012 }
3013
3014 #define typedef_BDK_RST_DELAY bdk_rst_delay_t
3015 #define bustype_BDK_RST_DELAY BDK_CSR_TYPE_RSL
3016 #define basename_BDK_RST_DELAY "RST_DELAY"
3017 #define device_bar_BDK_RST_DELAY 0x0 /* PF_BAR0 */
3018 #define busnum_BDK_RST_DELAY 0
3019 #define arguments_BDK_RST_DELAY -1,-1,-1,-1
3020
3021 /**
3022 * Register (RSL) rst_dev_map#
3023 *
3024 * RST Device Map Register
3025 * This register configures the reset domain of devices. Index {a} is enumerated by RST_DEV_E.
3026 * Writes to these registers should only occur when all the bits ofRST_BIST_ACTIVE are clear.
3027 * See RST_BIST_ACTIVE for details.
3028 * Only one RST_DEV_MAP should be written at a time.
3029 *
3030 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3031 */
3032 union bdk_rst_dev_mapx
3033 {
3034 uint64_t u;
3035 struct bdk_rst_dev_mapx_s
3036 {
3037 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3038 uint64_t reserved_3_63 : 61;
3039 uint64_t dmn : 3; /**< [ 2: 0](R/W) Map of programmable devices to reset domains. When the specified domain reset
3040 occurs the corresponding device will reset. Devices are numbered according to
3041 RST_DEV_E.
3042
3043 GSERs should be mapped to the same domain as the PEM, CGX or NCSI device they are
3044 associated with.
3045
3046 If any PCIEx_EP_STRAP is set then all RST_DEV_MAP(GSERx) are mapped to chip reset.
3047
3048 See RST_DOMAIN_E for field encodings.
3049
3050 This field is always reinitialized on a cold domain reset.
3051
3052 Internal:
3053 RST_DEV_MAP()[DMN] resets to core domain for everything except AVS, EMM, MPI\<1:0\>
3054 and NCSI which reset to SCP domain and GSER which are set to chip in EP mode.
3055
3056 This is based on cold reset so software could e.g. choose to put a PEM GSER into
3057 endpoint based on knowledge outside the straps (that RST uses to reset this
3058 table). */
3059 #else /* Word 0 - Little Endian */
3060 uint64_t dmn : 3; /**< [ 2: 0](R/W) Map of programmable devices to reset domains. When the specified domain reset
3061 occurs the corresponding device will reset. Devices are numbered according to
3062 RST_DEV_E.
3063
3064 GSERs should be mapped to the same domain as the PEM, CGX or NCSI device they are
3065 associated with.
3066
3067 If any PCIEx_EP_STRAP is set then all RST_DEV_MAP(GSERx) are mapped to chip reset.
3068
3069 See RST_DOMAIN_E for field encodings.
3070
3071 This field is always reinitialized on a cold domain reset.
3072
3073 Internal:
3074 RST_DEV_MAP()[DMN] resets to core domain for everything except AVS, EMM, MPI\<1:0\>
3075 and NCSI which reset to SCP domain and GSER which are set to chip in EP mode.
3076
3077 This is based on cold reset so software could e.g. choose to put a PEM GSER into
3078 endpoint based on knowledge outside the straps (that RST uses to reset this
3079 table). */
3080 uint64_t reserved_3_63 : 61;
3081 #endif /* Word 0 - End */
3082 } s;
3083 /* struct bdk_rst_dev_mapx_s cn; */
3084 };
3085 typedef union bdk_rst_dev_mapx bdk_rst_dev_mapx_t;
3086
3087 static inline uint64_t BDK_RST_DEV_MAPX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_DEV_MAPX(unsigned long a)3088 static inline uint64_t BDK_RST_DEV_MAPX(unsigned long a)
3089 {
3090 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=47))
3091 return 0x87e00a001a00ll + 8ll * ((a) & 0x3f);
3092 __bdk_csr_fatal("RST_DEV_MAPX", 1, a, 0, 0, 0);
3093 }
3094
3095 #define typedef_BDK_RST_DEV_MAPX(a) bdk_rst_dev_mapx_t
3096 #define bustype_BDK_RST_DEV_MAPX(a) BDK_CSR_TYPE_RSL
3097 #define basename_BDK_RST_DEV_MAPX(a) "RST_DEV_MAPX"
3098 #define device_bar_BDK_RST_DEV_MAPX(a) 0x2 /* PF_BAR2 */
3099 #define busnum_BDK_RST_DEV_MAPX(a) (a)
3100 #define arguments_BDK_RST_DEV_MAPX(a) (a),-1,-1,-1
3101
3102 /**
3103 * Register (RSL) rst_eco
3104 *
3105 * INTERNAL: RST ECO Register
3106 *
3107 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3108 */
3109 union bdk_rst_eco
3110 {
3111 uint64_t u;
3112 struct bdk_rst_eco_s
3113 {
3114 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3115 uint64_t reserved_32_63 : 32;
3116 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops. */
3117 #else /* Word 0 - Little Endian */
3118 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops. */
3119 uint64_t reserved_32_63 : 32;
3120 #endif /* Word 0 - End */
3121 } s;
3122 /* struct bdk_rst_eco_s cn8; */
3123 struct bdk_rst_eco_cn9
3124 {
3125 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3126 uint64_t reserved_32_63 : 32;
3127 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops.
3128 This field is always reinitialized on a cold domain reset. */
3129 #else /* Word 0 - Little Endian */
3130 uint64_t eco_rw : 32; /**< [ 31: 0](R/W) ECO flops.
3131 This field is always reinitialized on a cold domain reset. */
3132 uint64_t reserved_32_63 : 32;
3133 #endif /* Word 0 - End */
3134 } cn9;
3135 };
3136 typedef union bdk_rst_eco bdk_rst_eco_t;
3137
3138 #define BDK_RST_ECO BDK_RST_ECO_FUNC()
3139 static inline uint64_t BDK_RST_ECO_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_ECO_FUNC(void)3140 static inline uint64_t BDK_RST_ECO_FUNC(void)
3141 {
3142 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
3143 return 0x87e0060017b8ll;
3144 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
3145 return 0x87e0060017b8ll;
3146 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
3147 return 0x87e0060017b8ll;
3148 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3149 return 0x87e0060017b8ll;
3150 __bdk_csr_fatal("RST_ECO", 0, 0, 0, 0, 0);
3151 }
3152
3153 #define typedef_BDK_RST_ECO bdk_rst_eco_t
3154 #define bustype_BDK_RST_ECO BDK_CSR_TYPE_RSL
3155 #define basename_BDK_RST_ECO "RST_ECO"
3156 #define device_bar_BDK_RST_ECO 0x0 /* PF_BAR0 */
3157 #define busnum_BDK_RST_ECO 0
3158 #define arguments_BDK_RST_ECO -1,-1,-1,-1
3159
3160 /**
3161 * Register (RSL) rst_int
3162 *
3163 * RST Interrupt Register
3164 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3165 */
3166 union bdk_rst_int
3167 {
3168 uint64_t u;
3169 struct bdk_rst_int_s
3170 {
3171 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3172 uint64_t reserved_35_63 : 29;
3173 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) SCP domain entered reset.
3174 This field is reinitialized with a chip domain reset. */
3175 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) MCP domain entered reset.
3176 This field is reinitialized with a chip domain reset. */
3177 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Core domain entered reset.
3178 This field is reinitialized with a chip domain reset. */
3179 uint64_t reserved_6_31 : 26;
3180 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3181 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3182 #else /* Word 0 - Little Endian */
3183 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3184 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3185 uint64_t reserved_6_31 : 26;
3186 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Core domain entered reset.
3187 This field is reinitialized with a chip domain reset. */
3188 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) MCP domain entered reset.
3189 This field is reinitialized with a chip domain reset. */
3190 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) SCP domain entered reset.
3191 This field is reinitialized with a chip domain reset. */
3192 uint64_t reserved_35_63 : 29;
3193 #endif /* Word 0 - End */
3194 } s;
3195 struct bdk_rst_int_cn9
3196 {
3197 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3198 uint64_t reserved_35_63 : 29;
3199 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) SCP domain entered reset.
3200 This field is reinitialized with a chip domain reset. */
3201 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) MCP domain entered reset.
3202 This field is reinitialized with a chip domain reset. */
3203 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Core domain entered reset.
3204 This field is reinitialized with a chip domain reset. */
3205 uint64_t reserved_20_31 : 12;
3206 uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3207 corresponds to each controller.
3208 This field is reinitialized with a chip domain reset. */
3209 uint64_t reserved_4_15 : 12;
3210 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3211 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
3212 This field is reinitialized with a chip domain reset. */
3213 #else /* Word 0 - Little Endian */
3214 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3215 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller.
3216 This field is reinitialized with a chip domain reset. */
3217 uint64_t reserved_4_15 : 12;
3218 uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3219 corresponds to each controller.
3220 This field is reinitialized with a chip domain reset. */
3221 uint64_t reserved_20_31 : 12;
3222 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Core domain entered reset.
3223 This field is reinitialized with a chip domain reset. */
3224 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) MCP domain entered reset.
3225 This field is reinitialized with a chip domain reset. */
3226 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) SCP domain entered reset.
3227 This field is reinitialized with a chip domain reset. */
3228 uint64_t reserved_35_63 : 29;
3229 #endif /* Word 0 - End */
3230 } cn9;
3231 struct bdk_rst_int_cn81xx
3232 {
3233 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3234 uint64_t reserved_11_63 : 53;
3235 uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3236 corresponds to each controller. */
3237 uint64_t reserved_3_7 : 5;
3238 uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3239 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3240 #else /* Word 0 - Little Endian */
3241 uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3242 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3243 uint64_t reserved_3_7 : 5;
3244 uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3245 corresponds to each controller. */
3246 uint64_t reserved_11_63 : 53;
3247 #endif /* Word 0 - End */
3248 } cn81xx;
3249 struct bdk_rst_int_cn88xx
3250 {
3251 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3252 uint64_t reserved_14_63 : 50;
3253 uint64_t perst : 6; /**< [ 13: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3254 corresponds to each controller. */
3255 uint64_t reserved_6_7 : 2;
3256 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3257 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3258 #else /* Word 0 - Little Endian */
3259 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3260 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3261 uint64_t reserved_6_7 : 2;
3262 uint64_t perst : 6; /**< [ 13: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3263 corresponds to each controller. */
3264 uint64_t reserved_14_63 : 50;
3265 #endif /* Word 0 - End */
3266 } cn88xx;
3267 struct bdk_rst_int_cn83xx
3268 {
3269 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3270 uint64_t reserved_12_63 : 52;
3271 uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3272 corresponds to each controller. */
3273 uint64_t reserved_4_7 : 4;
3274 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3275 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3276 #else /* Word 0 - Little Endian */
3277 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) A controller link-down/hot-reset occurred while RST_CTL()[RST_LINK] = 0. Software must
3278 assert then deassert RST_SOFT_PRST()[SOFT_PRST]. One bit corresponds to each controller. */
3279 uint64_t reserved_4_7 : 4;
3280 uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) PERST*_L asserted while RST_CTL()[RST_RCV] = 1 and RST_CTL()[RST_CHIP] = 0. One bit
3281 corresponds to each controller. */
3282 uint64_t reserved_12_63 : 52;
3283 #endif /* Word 0 - End */
3284 } cn83xx;
3285 };
3286 typedef union bdk_rst_int bdk_rst_int_t;
3287
3288 #define BDK_RST_INT BDK_RST_INT_FUNC()
3289 static inline uint64_t BDK_RST_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_INT_FUNC(void)3290 static inline uint64_t BDK_RST_INT_FUNC(void)
3291 {
3292 return 0x87e006001628ll;
3293 }
3294
3295 #define typedef_BDK_RST_INT bdk_rst_int_t
3296 #define bustype_BDK_RST_INT BDK_CSR_TYPE_RSL
3297 #define basename_BDK_RST_INT "RST_INT"
3298 #define device_bar_BDK_RST_INT 0x0 /* PF_BAR0 */
3299 #define busnum_BDK_RST_INT 0
3300 #define arguments_BDK_RST_INT -1,-1,-1,-1
3301
3302 /**
3303 * Register (RSL) rst_int_ena_w1c
3304 *
3305 * RST Interrupt Enable Clear Register
3306 * This register clears interrupt enable bits.
3307 */
3308 union bdk_rst_int_ena_w1c
3309 {
3310 uint64_t u;
3311 struct bdk_rst_int_ena_w1c_s
3312 {
3313 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3314 uint64_t reserved_35_63 : 29;
3315 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
3316 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
3317 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
3318 uint64_t reserved_6_31 : 26;
3319 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3320 #else /* Word 0 - Little Endian */
3321 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3322 uint64_t reserved_6_31 : 26;
3323 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
3324 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
3325 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
3326 uint64_t reserved_35_63 : 29;
3327 #endif /* Word 0 - End */
3328 } s;
3329 struct bdk_rst_int_ena_w1c_cn9
3330 {
3331 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3332 uint64_t reserved_35_63 : 29;
3333 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
3334 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
3335 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
3336 uint64_t reserved_20_31 : 12;
3337 uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3338 uint64_t reserved_4_15 : 12;
3339 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3340 #else /* Word 0 - Little Endian */
3341 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3342 uint64_t reserved_4_15 : 12;
3343 uint64_t perst : 4; /**< [ 19: 16](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3344 uint64_t reserved_20_31 : 12;
3345 uint64_t core_reset : 1; /**< [ 32: 32](R/W1C/H) Reads or clears enable for RST_INT[CORE_RESET]. */
3346 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1C/H) Reads or clears enable for RST_INT[MCP_RESET]. */
3347 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1C/H) Reads or clears enable for RST_INT[SCP_RESET]. */
3348 uint64_t reserved_35_63 : 29;
3349 #endif /* Word 0 - End */
3350 } cn9;
3351 struct bdk_rst_int_ena_w1c_cn81xx
3352 {
3353 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3354 uint64_t reserved_11_63 : 53;
3355 uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3356 uint64_t reserved_3_7 : 5;
3357 uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3358 #else /* Word 0 - Little Endian */
3359 uint64_t rst_link : 3; /**< [ 2: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3360 uint64_t reserved_3_7 : 5;
3361 uint64_t perst : 3; /**< [ 10: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3362 uint64_t reserved_11_63 : 53;
3363 #endif /* Word 0 - End */
3364 } cn81xx;
3365 struct bdk_rst_int_ena_w1c_cn88xx
3366 {
3367 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3368 uint64_t reserved_14_63 : 50;
3369 uint64_t perst : 6; /**< [ 13: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3370 uint64_t reserved_6_7 : 2;
3371 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3372 #else /* Word 0 - Little Endian */
3373 uint64_t rst_link : 6; /**< [ 5: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3374 uint64_t reserved_6_7 : 2;
3375 uint64_t perst : 6; /**< [ 13: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3376 uint64_t reserved_14_63 : 50;
3377 #endif /* Word 0 - End */
3378 } cn88xx;
3379 struct bdk_rst_int_ena_w1c_cn83xx
3380 {
3381 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3382 uint64_t reserved_12_63 : 52;
3383 uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3384 uint64_t reserved_4_7 : 4;
3385 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3386 #else /* Word 0 - Little Endian */
3387 uint64_t rst_link : 4; /**< [ 3: 0](R/W1C/H) Reads or clears enable for RST_INT[RST_LINK]. */
3388 uint64_t reserved_4_7 : 4;
3389 uint64_t perst : 4; /**< [ 11: 8](R/W1C/H) Reads or clears enable for RST_INT[PERST]. */
3390 uint64_t reserved_12_63 : 52;
3391 #endif /* Word 0 - End */
3392 } cn83xx;
3393 };
3394 typedef union bdk_rst_int_ena_w1c bdk_rst_int_ena_w1c_t;
3395
3396 #define BDK_RST_INT_ENA_W1C BDK_RST_INT_ENA_W1C_FUNC()
3397 static inline uint64_t BDK_RST_INT_ENA_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_INT_ENA_W1C_FUNC(void)3398 static inline uint64_t BDK_RST_INT_ENA_W1C_FUNC(void)
3399 {
3400 return 0x87e0060016a8ll;
3401 }
3402
3403 #define typedef_BDK_RST_INT_ENA_W1C bdk_rst_int_ena_w1c_t
3404 #define bustype_BDK_RST_INT_ENA_W1C BDK_CSR_TYPE_RSL
3405 #define basename_BDK_RST_INT_ENA_W1C "RST_INT_ENA_W1C"
3406 #define device_bar_BDK_RST_INT_ENA_W1C 0x0 /* PF_BAR0 */
3407 #define busnum_BDK_RST_INT_ENA_W1C 0
3408 #define arguments_BDK_RST_INT_ENA_W1C -1,-1,-1,-1
3409
3410 /**
3411 * Register (RSL) rst_int_ena_w1s
3412 *
3413 * RST Interrupt Enable Set Register
3414 * This register sets interrupt enable bits.
3415 */
3416 union bdk_rst_int_ena_w1s
3417 {
3418 uint64_t u;
3419 struct bdk_rst_int_ena_w1s_s
3420 {
3421 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3422 uint64_t reserved_35_63 : 29;
3423 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
3424 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
3425 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
3426 uint64_t reserved_6_31 : 26;
3427 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3428 #else /* Word 0 - Little Endian */
3429 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3430 uint64_t reserved_6_31 : 26;
3431 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
3432 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
3433 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
3434 uint64_t reserved_35_63 : 29;
3435 #endif /* Word 0 - End */
3436 } s;
3437 struct bdk_rst_int_ena_w1s_cn9
3438 {
3439 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3440 uint64_t reserved_35_63 : 29;
3441 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
3442 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
3443 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
3444 uint64_t reserved_20_31 : 12;
3445 uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3446 uint64_t reserved_4_15 : 12;
3447 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3448 #else /* Word 0 - Little Endian */
3449 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3450 uint64_t reserved_4_15 : 12;
3451 uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3452 uint64_t reserved_20_31 : 12;
3453 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets enable for RST_INT[CORE_RESET]. */
3454 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets enable for RST_INT[MCP_RESET]. */
3455 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets enable for RST_INT[SCP_RESET]. */
3456 uint64_t reserved_35_63 : 29;
3457 #endif /* Word 0 - End */
3458 } cn9;
3459 struct bdk_rst_int_ena_w1s_cn81xx
3460 {
3461 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3462 uint64_t reserved_11_63 : 53;
3463 uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3464 uint64_t reserved_3_7 : 5;
3465 uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3466 #else /* Word 0 - Little Endian */
3467 uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3468 uint64_t reserved_3_7 : 5;
3469 uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3470 uint64_t reserved_11_63 : 53;
3471 #endif /* Word 0 - End */
3472 } cn81xx;
3473 struct bdk_rst_int_ena_w1s_cn88xx
3474 {
3475 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3476 uint64_t reserved_14_63 : 50;
3477 uint64_t perst : 6; /**< [ 13: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3478 uint64_t reserved_6_7 : 2;
3479 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3480 #else /* Word 0 - Little Endian */
3481 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3482 uint64_t reserved_6_7 : 2;
3483 uint64_t perst : 6; /**< [ 13: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3484 uint64_t reserved_14_63 : 50;
3485 #endif /* Word 0 - End */
3486 } cn88xx;
3487 struct bdk_rst_int_ena_w1s_cn83xx
3488 {
3489 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3490 uint64_t reserved_12_63 : 52;
3491 uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3492 uint64_t reserved_4_7 : 4;
3493 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3494 #else /* Word 0 - Little Endian */
3495 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets enable for RST_INT[RST_LINK]. */
3496 uint64_t reserved_4_7 : 4;
3497 uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets enable for RST_INT[PERST]. */
3498 uint64_t reserved_12_63 : 52;
3499 #endif /* Word 0 - End */
3500 } cn83xx;
3501 };
3502 typedef union bdk_rst_int_ena_w1s bdk_rst_int_ena_w1s_t;
3503
3504 #define BDK_RST_INT_ENA_W1S BDK_RST_INT_ENA_W1S_FUNC()
3505 static inline uint64_t BDK_RST_INT_ENA_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_INT_ENA_W1S_FUNC(void)3506 static inline uint64_t BDK_RST_INT_ENA_W1S_FUNC(void)
3507 {
3508 return 0x87e0060016a0ll;
3509 }
3510
3511 #define typedef_BDK_RST_INT_ENA_W1S bdk_rst_int_ena_w1s_t
3512 #define bustype_BDK_RST_INT_ENA_W1S BDK_CSR_TYPE_RSL
3513 #define basename_BDK_RST_INT_ENA_W1S "RST_INT_ENA_W1S"
3514 #define device_bar_BDK_RST_INT_ENA_W1S 0x0 /* PF_BAR0 */
3515 #define busnum_BDK_RST_INT_ENA_W1S 0
3516 #define arguments_BDK_RST_INT_ENA_W1S -1,-1,-1,-1
3517
3518 /**
3519 * Register (RSL) rst_int_w1s
3520 *
3521 * RST Interrupt Set Register
3522 * This register sets interrupt bits.
3523 */
3524 union bdk_rst_int_w1s
3525 {
3526 uint64_t u;
3527 struct bdk_rst_int_w1s_s
3528 {
3529 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3530 uint64_t reserved_35_63 : 29;
3531 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
3532 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
3533 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
3534 uint64_t reserved_6_31 : 26;
3535 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3536 #else /* Word 0 - Little Endian */
3537 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3538 uint64_t reserved_6_31 : 26;
3539 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
3540 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
3541 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
3542 uint64_t reserved_35_63 : 29;
3543 #endif /* Word 0 - End */
3544 } s;
3545 struct bdk_rst_int_w1s_cn9
3546 {
3547 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3548 uint64_t reserved_35_63 : 29;
3549 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
3550 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
3551 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
3552 uint64_t reserved_20_31 : 12;
3553 uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
3554 uint64_t reserved_4_15 : 12;
3555 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3556 #else /* Word 0 - Little Endian */
3557 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3558 uint64_t reserved_4_15 : 12;
3559 uint64_t perst : 4; /**< [ 19: 16](R/W1S/H) Reads or sets RST_INT[PERST]. */
3560 uint64_t reserved_20_31 : 12;
3561 uint64_t core_reset : 1; /**< [ 32: 32](R/W1S/H) Reads or sets RST_INT[CORE_RESET]. */
3562 uint64_t mcp_reset : 1; /**< [ 33: 33](R/W1S/H) Reads or sets RST_INT[MCP_RESET]. */
3563 uint64_t scp_reset : 1; /**< [ 34: 34](R/W1S/H) Reads or sets RST_INT[SCP_RESET]. */
3564 uint64_t reserved_35_63 : 29;
3565 #endif /* Word 0 - End */
3566 } cn9;
3567 struct bdk_rst_int_w1s_cn81xx
3568 {
3569 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3570 uint64_t reserved_11_63 : 53;
3571 uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3572 uint64_t reserved_3_7 : 5;
3573 uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3574 #else /* Word 0 - Little Endian */
3575 uint64_t rst_link : 3; /**< [ 2: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3576 uint64_t reserved_3_7 : 5;
3577 uint64_t perst : 3; /**< [ 10: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3578 uint64_t reserved_11_63 : 53;
3579 #endif /* Word 0 - End */
3580 } cn81xx;
3581 struct bdk_rst_int_w1s_cn88xx
3582 {
3583 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3584 uint64_t reserved_14_63 : 50;
3585 uint64_t perst : 6; /**< [ 13: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3586 uint64_t reserved_6_7 : 2;
3587 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3588 #else /* Word 0 - Little Endian */
3589 uint64_t rst_link : 6; /**< [ 5: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3590 uint64_t reserved_6_7 : 2;
3591 uint64_t perst : 6; /**< [ 13: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3592 uint64_t reserved_14_63 : 50;
3593 #endif /* Word 0 - End */
3594 } cn88xx;
3595 struct bdk_rst_int_w1s_cn83xx
3596 {
3597 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3598 uint64_t reserved_12_63 : 52;
3599 uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3600 uint64_t reserved_4_7 : 4;
3601 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3602 #else /* Word 0 - Little Endian */
3603 uint64_t rst_link : 4; /**< [ 3: 0](R/W1S/H) Reads or sets RST_INT[RST_LINK]. */
3604 uint64_t reserved_4_7 : 4;
3605 uint64_t perst : 4; /**< [ 11: 8](R/W1S/H) Reads or sets RST_INT[PERST]. */
3606 uint64_t reserved_12_63 : 52;
3607 #endif /* Word 0 - End */
3608 } cn83xx;
3609 };
3610 typedef union bdk_rst_int_w1s bdk_rst_int_w1s_t;
3611
3612 #define BDK_RST_INT_W1S BDK_RST_INT_W1S_FUNC()
3613 static inline uint64_t BDK_RST_INT_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_INT_W1S_FUNC(void)3614 static inline uint64_t BDK_RST_INT_W1S_FUNC(void)
3615 {
3616 return 0x87e006001630ll;
3617 }
3618
3619 #define typedef_BDK_RST_INT_W1S bdk_rst_int_w1s_t
3620 #define bustype_BDK_RST_INT_W1S BDK_CSR_TYPE_RSL
3621 #define basename_BDK_RST_INT_W1S "RST_INT_W1S"
3622 #define device_bar_BDK_RST_INT_W1S 0x0 /* PF_BAR0 */
3623 #define busnum_BDK_RST_INT_W1S 0
3624 #define arguments_BDK_RST_INT_W1S -1,-1,-1,-1
3625
3626 /**
3627 * Register (RSL) rst_lboot
3628 *
3629 * RST Last Boot Register
3630 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3631 */
3632 union bdk_rst_lboot
3633 {
3634 uint64_t u;
3635 struct bdk_rst_lboot_s
3636 {
3637 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3638 uint64_t reserved_48_63 : 16;
3639 uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
3640 cold domain reset.
3641 Bit numbers are enumerated by RST_SOURCE_E. */
3642 #else /* Word 0 - Little Endian */
3643 uint64_t lboot : 48; /**< [ 47: 0](R/W1C/H) Bit vector of last reset cause(es). The value reset with a
3644 cold domain reset.
3645 Bit numbers are enumerated by RST_SOURCE_E. */
3646 uint64_t reserved_48_63 : 16;
3647 #endif /* Word 0 - End */
3648 } s;
3649 /* struct bdk_rst_lboot_s cn; */
3650 };
3651 typedef union bdk_rst_lboot bdk_rst_lboot_t;
3652
3653 #define BDK_RST_LBOOT BDK_RST_LBOOT_FUNC()
3654 static inline uint64_t BDK_RST_LBOOT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_LBOOT_FUNC(void)3655 static inline uint64_t BDK_RST_LBOOT_FUNC(void)
3656 {
3657 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3658 return 0x87e006001620ll;
3659 __bdk_csr_fatal("RST_LBOOT", 0, 0, 0, 0, 0);
3660 }
3661
3662 #define typedef_BDK_RST_LBOOT bdk_rst_lboot_t
3663 #define bustype_BDK_RST_LBOOT BDK_CSR_TYPE_RSL
3664 #define basename_BDK_RST_LBOOT "RST_LBOOT"
3665 #define device_bar_BDK_RST_LBOOT 0x0 /* PF_BAR0 */
3666 #define busnum_BDK_RST_LBOOT 0
3667 #define arguments_BDK_RST_LBOOT -1,-1,-1,-1
3668
3669 /**
3670 * Register (RSL) rst_mcp_domain_w1c
3671 *
3672 * RST MCP Domain Soft Reset Clear Register
3673 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3674 */
3675 union bdk_rst_mcp_domain_w1c
3676 {
3677 uint64_t u;
3678 struct bdk_rst_mcp_domain_w1c_s
3679 {
3680 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3681 uint64_t reserved_1_63 : 63;
3682 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of the MCP processor and associated logic.
3683 When set to one, the soft reset of the mcp is removed.
3684 Reads of this register show the soft reset state. Not the actual mcp domain reset.
3685 Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
3686 the actual reset state. To compensate for delays in reset, this field should only
3687 be set if RST_RESET_ACTIVE[MCP] is set.
3688 This field is always reinitialized on a chip domain reset. */
3689 #else /* Word 0 - Little Endian */
3690 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of the MCP processor and associated logic.
3691 When set to one, the soft reset of the mcp is removed.
3692 Reads of this register show the soft reset state. Not the actual mcp domain reset.
3693 Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
3694 the actual reset state. To compensate for delays in reset, this field should only
3695 be set if RST_RESET_ACTIVE[MCP] is set.
3696 This field is always reinitialized on a chip domain reset. */
3697 uint64_t reserved_1_63 : 63;
3698 #endif /* Word 0 - End */
3699 } s;
3700 /* struct bdk_rst_mcp_domain_w1c_s cn; */
3701 };
3702 typedef union bdk_rst_mcp_domain_w1c bdk_rst_mcp_domain_w1c_t;
3703
3704 #define BDK_RST_MCP_DOMAIN_W1C BDK_RST_MCP_DOMAIN_W1C_FUNC()
3705 static inline uint64_t BDK_RST_MCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_MCP_DOMAIN_W1C_FUNC(void)3706 static inline uint64_t BDK_RST_MCP_DOMAIN_W1C_FUNC(void)
3707 {
3708 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3709 return 0x87e006001838ll;
3710 __bdk_csr_fatal("RST_MCP_DOMAIN_W1C", 0, 0, 0, 0, 0);
3711 }
3712
3713 #define typedef_BDK_RST_MCP_DOMAIN_W1C bdk_rst_mcp_domain_w1c_t
3714 #define bustype_BDK_RST_MCP_DOMAIN_W1C BDK_CSR_TYPE_RSL
3715 #define basename_BDK_RST_MCP_DOMAIN_W1C "RST_MCP_DOMAIN_W1C"
3716 #define device_bar_BDK_RST_MCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
3717 #define busnum_BDK_RST_MCP_DOMAIN_W1C 0
3718 #define arguments_BDK_RST_MCP_DOMAIN_W1C -1,-1,-1,-1
3719
3720 /**
3721 * Register (RSL) rst_mcp_domain_w1s
3722 *
3723 * RST MCP Domain Soft Reset Set Register
3724 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3725 */
3726 union bdk_rst_mcp_domain_w1s
3727 {
3728 uint64_t u;
3729 struct bdk_rst_mcp_domain_w1s_s
3730 {
3731 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3732 uint64_t reserved_1_63 : 63;
3733 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of MCP core and associated logic.
3734 When set to one, all logic associated with the mcp domain is placed in reset.
3735 Reads of this register show the soft reset state. Not the actual mcp domain reset.
3736 Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
3737 the actual reset state.
3738 It is typically cleared by writing to RST_MCP_DOMAIN_W1C.
3739 This field is always reinitialized on a chip domain reset. */
3740 #else /* Word 0 - Little Endian */
3741 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of MCP core and associated logic.
3742 When set to one, all logic associated with the mcp domain is placed in reset.
3743 Reads of this register show the soft reset state. Not the actual mcp domain reset.
3744 Other factors may keep the reset active, reading RST_RESET_ACTIVE[MCP] shows
3745 the actual reset state.
3746 It is typically cleared by writing to RST_MCP_DOMAIN_W1C.
3747 This field is always reinitialized on a chip domain reset. */
3748 uint64_t reserved_1_63 : 63;
3749 #endif /* Word 0 - End */
3750 } s;
3751 /* struct bdk_rst_mcp_domain_w1s_s cn; */
3752 };
3753 typedef union bdk_rst_mcp_domain_w1s bdk_rst_mcp_domain_w1s_t;
3754
3755 #define BDK_RST_MCP_DOMAIN_W1S BDK_RST_MCP_DOMAIN_W1S_FUNC()
3756 static inline uint64_t BDK_RST_MCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_MCP_DOMAIN_W1S_FUNC(void)3757 static inline uint64_t BDK_RST_MCP_DOMAIN_W1S_FUNC(void)
3758 {
3759 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3760 return 0x87e006001830ll;
3761 __bdk_csr_fatal("RST_MCP_DOMAIN_W1S", 0, 0, 0, 0, 0);
3762 }
3763
3764 #define typedef_BDK_RST_MCP_DOMAIN_W1S bdk_rst_mcp_domain_w1s_t
3765 #define bustype_BDK_RST_MCP_DOMAIN_W1S BDK_CSR_TYPE_RSL
3766 #define basename_BDK_RST_MCP_DOMAIN_W1S "RST_MCP_DOMAIN_W1S"
3767 #define device_bar_BDK_RST_MCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
3768 #define busnum_BDK_RST_MCP_DOMAIN_W1S 0
3769 #define arguments_BDK_RST_MCP_DOMAIN_W1S -1,-1,-1,-1
3770
3771 /**
3772 * Register (RSL) rst_msix_pba#
3773 *
3774 * RST MSI-X Pending Bit Array Registers
3775 * This register is the MSI-X PBA table; the bit number is indexed by the RST_INT_VEC_E
3776 * enumeration.
3777 *
3778 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3779 */
3780 union bdk_rst_msix_pbax
3781 {
3782 uint64_t u;
3783 struct bdk_rst_msix_pbax_s
3784 {
3785 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3786 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
3787 RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0. */
3788 #else /* Word 0 - Little Endian */
3789 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
3790 RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0. */
3791 #endif /* Word 0 - End */
3792 } s;
3793 /* struct bdk_rst_msix_pbax_s cn8; */
3794 struct bdk_rst_msix_pbax_cn9
3795 {
3796 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3797 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
3798 RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0.
3799 This field is always reinitialized on a chip domain reset. */
3800 #else /* Word 0 - Little Endian */
3801 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for the associated RST_MSIX_VEC()_CTL, enumerated by
3802 RST_INT_VEC_E. Bits that have no associated RST_INT_VEC_E are 0.
3803 This field is always reinitialized on a chip domain reset. */
3804 #endif /* Word 0 - End */
3805 } cn9;
3806 };
3807 typedef union bdk_rst_msix_pbax bdk_rst_msix_pbax_t;
3808
3809 static inline uint64_t BDK_RST_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_MSIX_PBAX(unsigned long a)3810 static inline uint64_t BDK_RST_MSIX_PBAX(unsigned long a)
3811 {
3812 if (a==0)
3813 return 0x87e006ff0000ll + 8ll * ((a) & 0x0);
3814 __bdk_csr_fatal("RST_MSIX_PBAX", 1, a, 0, 0, 0);
3815 }
3816
3817 #define typedef_BDK_RST_MSIX_PBAX(a) bdk_rst_msix_pbax_t
3818 #define bustype_BDK_RST_MSIX_PBAX(a) BDK_CSR_TYPE_RSL
3819 #define basename_BDK_RST_MSIX_PBAX(a) "RST_MSIX_PBAX"
3820 #define device_bar_BDK_RST_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
3821 #define busnum_BDK_RST_MSIX_PBAX(a) (a)
3822 #define arguments_BDK_RST_MSIX_PBAX(a) (a),-1,-1,-1
3823
3824 /**
3825 * Register (RSL) rst_msix_vec#_addr
3826 *
3827 * RST MSI-X Vector-Table Address Register
3828 * This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
3829 *
3830 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3831 */
3832 union bdk_rst_msix_vecx_addr
3833 {
3834 uint64_t u;
3835 struct bdk_rst_msix_vecx_addr_s
3836 {
3837 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3838 uint64_t reserved_53_63 : 11;
3839 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3840 uint64_t reserved_1 : 1;
3841 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3842 0 = This vector can be read or written by either secure or nonsecure states.
3843 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3844 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3845 by the nonsecure world.
3846
3847 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3848 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3849 set, all vectors are secure and function as if [SECVEC] was set. */
3850 #else /* Word 0 - Little Endian */
3851 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3852 0 = This vector can be read or written by either secure or nonsecure states.
3853 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3854 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3855 by the nonsecure world.
3856
3857 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3858 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3859 set, all vectors are secure and function as if [SECVEC] was set. */
3860 uint64_t reserved_1 : 1;
3861 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3862 uint64_t reserved_53_63 : 11;
3863 #endif /* Word 0 - End */
3864 } s;
3865 struct bdk_rst_msix_vecx_addr_cn8
3866 {
3867 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3868 uint64_t reserved_49_63 : 15;
3869 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3870 uint64_t reserved_1 : 1;
3871 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3872 0 = This vector can be read or written by either secure or nonsecure states.
3873 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3874 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3875 by the nonsecure world.
3876
3877 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3878 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3879 set, all vectors are secure and function as if [SECVEC] was set. */
3880 #else /* Word 0 - Little Endian */
3881 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3882 0 = This vector can be read or written by either secure or nonsecure states.
3883 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3884 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3885 by the nonsecure world.
3886
3887 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3888 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3889 set, all vectors are secure and function as if [SECVEC] was set. */
3890 uint64_t reserved_1 : 1;
3891 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3892 uint64_t reserved_49_63 : 15;
3893 #endif /* Word 0 - End */
3894 } cn8;
3895 struct bdk_rst_msix_vecx_addr_cn9
3896 {
3897 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3898 uint64_t reserved_53_63 : 11;
3899 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
3900 This field is always reinitialized on a chip domain reset. */
3901 uint64_t reserved_1 : 1;
3902 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3903 0 = This vector can be read or written by either secure or nonsecure states.
3904 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3905 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
3906 a fault when accessed by the nonsecure world.
3907
3908 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3909 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3910 set, all vectors are secure and function as if [SECVEC] was set.
3911 This field is always reinitialized on a chip domain reset. */
3912 #else /* Word 0 - Little Endian */
3913 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3914 0 = This vector can be read or written by either secure or nonsecure states.
3915 1 = This vector's RST_MSIX_VEC()_ADDR, RST_MSIX_VEC()_CTL, and
3916 corresponding bit of RST_MSIX_PBA() are RAZ/WI and does not cause
3917 a fault when accessed by the nonsecure world.
3918
3919 If PCCPF_RST_VSEC_SCTL[MSIX_SEC] (for documentation, see
3920 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3921 set, all vectors are secure and function as if [SECVEC] was set.
3922 This field is always reinitialized on a chip domain reset. */
3923 uint64_t reserved_1 : 1;
3924 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector.
3925 This field is always reinitialized on a chip domain reset. */
3926 uint64_t reserved_53_63 : 11;
3927 #endif /* Word 0 - End */
3928 } cn9;
3929 };
3930 typedef union bdk_rst_msix_vecx_addr bdk_rst_msix_vecx_addr_t;
3931
3932 static inline uint64_t BDK_RST_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_MSIX_VECX_ADDR(unsigned long a)3933 static inline uint64_t BDK_RST_MSIX_VECX_ADDR(unsigned long a)
3934 {
3935 if (a==0)
3936 return 0x87e006f00000ll + 0x10ll * ((a) & 0x0);
3937 __bdk_csr_fatal("RST_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
3938 }
3939
3940 #define typedef_BDK_RST_MSIX_VECX_ADDR(a) bdk_rst_msix_vecx_addr_t
3941 #define bustype_BDK_RST_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_RSL
3942 #define basename_BDK_RST_MSIX_VECX_ADDR(a) "RST_MSIX_VECX_ADDR"
3943 #define device_bar_BDK_RST_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
3944 #define busnum_BDK_RST_MSIX_VECX_ADDR(a) (a)
3945 #define arguments_BDK_RST_MSIX_VECX_ADDR(a) (a),-1,-1,-1
3946
3947 /**
3948 * Register (RSL) rst_msix_vec#_ctl
3949 *
3950 * RST MSI-X Vector-Table Control and Data Register
3951 * This register is the MSI-X vector table, indexed by the RST_INT_VEC_E enumeration.
3952 *
3953 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
3954 */
3955 union bdk_rst_msix_vecx_ctl
3956 {
3957 uint64_t u;
3958 struct bdk_rst_msix_vecx_ctl_s
3959 {
3960 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3961 uint64_t reserved_33_63 : 31;
3962 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
3963 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
3964 #else /* Word 0 - Little Endian */
3965 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
3966 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
3967 uint64_t reserved_33_63 : 31;
3968 #endif /* Word 0 - End */
3969 } s;
3970 struct bdk_rst_msix_vecx_ctl_cn8
3971 {
3972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3973 uint64_t reserved_33_63 : 31;
3974 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
3975 uint64_t reserved_20_31 : 12;
3976 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
3977 #else /* Word 0 - Little Endian */
3978 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
3979 uint64_t reserved_20_31 : 12;
3980 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
3981 uint64_t reserved_33_63 : 31;
3982 #endif /* Word 0 - End */
3983 } cn8;
3984 struct bdk_rst_msix_vecx_ctl_cn9
3985 {
3986 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3987 uint64_t reserved_33_63 : 31;
3988 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector.
3989 This field is always reinitialized on a chip domain reset. */
3990 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector.
3991 This field is always reinitialized on a chip domain reset. */
3992 #else /* Word 0 - Little Endian */
3993 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector.
3994 This field is always reinitialized on a chip domain reset. */
3995 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector.
3996 This field is always reinitialized on a chip domain reset. */
3997 uint64_t reserved_33_63 : 31;
3998 #endif /* Word 0 - End */
3999 } cn9;
4000 };
4001 typedef union bdk_rst_msix_vecx_ctl bdk_rst_msix_vecx_ctl_t;
4002
4003 static inline uint64_t BDK_RST_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_MSIX_VECX_CTL(unsigned long a)4004 static inline uint64_t BDK_RST_MSIX_VECX_CTL(unsigned long a)
4005 {
4006 if (a==0)
4007 return 0x87e006f00008ll + 0x10ll * ((a) & 0x0);
4008 __bdk_csr_fatal("RST_MSIX_VECX_CTL", 1, a, 0, 0, 0);
4009 }
4010
4011 #define typedef_BDK_RST_MSIX_VECX_CTL(a) bdk_rst_msix_vecx_ctl_t
4012 #define bustype_BDK_RST_MSIX_VECX_CTL(a) BDK_CSR_TYPE_RSL
4013 #define basename_BDK_RST_MSIX_VECX_CTL(a) "RST_MSIX_VECX_CTL"
4014 #define device_bar_BDK_RST_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
4015 #define busnum_BDK_RST_MSIX_VECX_CTL(a) (a)
4016 #define arguments_BDK_RST_MSIX_VECX_CTL(a) (a),-1,-1,-1
4017
4018 /**
4019 * Register (RSL) rst_ocx
4020 *
4021 * RST OCX Register
4022 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4023 */
4024 union bdk_rst_ocx
4025 {
4026 uint64_t u;
4027 struct bdk_rst_ocx_s
4028 {
4029 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4030 uint64_t reserved_3_63 : 61;
4031 uint64_t rst_link : 3; /**< [ 2: 0](R/W) Controls whether corresponding OCX link going down causes a chip reset. A warm/soft reset
4032 does not change this field. On cold reset, this field is initialized to 0. See
4033 OCX_COM_LINK()_CTL for a description of what events can contribute to the link_down
4034 condition. */
4035 #else /* Word 0 - Little Endian */
4036 uint64_t rst_link : 3; /**< [ 2: 0](R/W) Controls whether corresponding OCX link going down causes a chip reset. A warm/soft reset
4037 does not change this field. On cold reset, this field is initialized to 0. See
4038 OCX_COM_LINK()_CTL for a description of what events can contribute to the link_down
4039 condition. */
4040 uint64_t reserved_3_63 : 61;
4041 #endif /* Word 0 - End */
4042 } s;
4043 struct bdk_rst_ocx_cn9
4044 {
4045 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4046 uint64_t reserved_1_63 : 63;
4047 uint64_t rst_link : 1; /**< [ 0: 0](R/W) Controls whether the OCX CCPI link going down causes a reset.
4048 This field is reinitialized with a core domain reset. */
4049 #else /* Word 0 - Little Endian */
4050 uint64_t rst_link : 1; /**< [ 0: 0](R/W) Controls whether the OCX CCPI link going down causes a reset.
4051 This field is reinitialized with a core domain reset. */
4052 uint64_t reserved_1_63 : 63;
4053 #endif /* Word 0 - End */
4054 } cn9;
4055 struct bdk_rst_ocx_cn81xx
4056 {
4057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4058 uint64_t reserved_3_63 : 61;
4059 uint64_t rst_link : 3; /**< [ 2: 0](R/W) Reserved. */
4060 #else /* Word 0 - Little Endian */
4061 uint64_t rst_link : 3; /**< [ 2: 0](R/W) Reserved. */
4062 uint64_t reserved_3_63 : 61;
4063 #endif /* Word 0 - End */
4064 } cn81xx;
4065 /* struct bdk_rst_ocx_s cn88xx; */
4066 /* struct bdk_rst_ocx_cn81xx cn83xx; */
4067 };
4068 typedef union bdk_rst_ocx bdk_rst_ocx_t;
4069
4070 #define BDK_RST_OCX BDK_RST_OCX_FUNC()
4071 static inline uint64_t BDK_RST_OCX_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_OCX_FUNC(void)4072 static inline uint64_t BDK_RST_OCX_FUNC(void)
4073 {
4074 return 0x87e006001618ll;
4075 }
4076
4077 #define typedef_BDK_RST_OCX bdk_rst_ocx_t
4078 #define bustype_BDK_RST_OCX BDK_CSR_TYPE_RSL
4079 #define basename_BDK_RST_OCX "RST_OCX"
4080 #define device_bar_BDK_RST_OCX 0x0 /* PF_BAR0 */
4081 #define busnum_BDK_RST_OCX 0
4082 #define arguments_BDK_RST_OCX -1,-1,-1,-1
4083
4084 /**
4085 * Register (RSL) rst_osc_cntr
4086 *
4087 * INTERNAL: RST Internal Ring-Oscillator Counter Register
4088 *
4089 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4090 */
4091 union bdk_rst_osc_cntr
4092 {
4093 uint64_t u;
4094 struct bdk_rst_osc_cntr_s
4095 {
4096 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4097 uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count. Updated every 16 reference clocks. */
4098 #else /* Word 0 - Little Endian */
4099 uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count. Updated every 16 reference clocks. */
4100 #endif /* Word 0 - End */
4101 } s;
4102 /* struct bdk_rst_osc_cntr_s cn8; */
4103 struct bdk_rst_osc_cntr_cn9
4104 {
4105 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4106 uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count.
4107 Updated every 16 PLL reference clocks. */
4108 #else /* Word 0 - Little Endian */
4109 uint64_t cnt : 64; /**< [ 63: 0](RO/H) Internal ring-oscillator clock count.
4110 Updated every 16 PLL reference clocks. */
4111 #endif /* Word 0 - End */
4112 } cn9;
4113 };
4114 typedef union bdk_rst_osc_cntr bdk_rst_osc_cntr_t;
4115
4116 #define BDK_RST_OSC_CNTR BDK_RST_OSC_CNTR_FUNC()
4117 static inline uint64_t BDK_RST_OSC_CNTR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_OSC_CNTR_FUNC(void)4118 static inline uint64_t BDK_RST_OSC_CNTR_FUNC(void)
4119 {
4120 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
4121 return 0x87e006001778ll;
4122 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
4123 return 0x87e006001778ll;
4124 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
4125 return 0x87e006001778ll;
4126 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4127 return 0x87e006001768ll;
4128 __bdk_csr_fatal("RST_OSC_CNTR", 0, 0, 0, 0, 0);
4129 }
4130
4131 #define typedef_BDK_RST_OSC_CNTR bdk_rst_osc_cntr_t
4132 #define bustype_BDK_RST_OSC_CNTR BDK_CSR_TYPE_RSL
4133 #define basename_BDK_RST_OSC_CNTR "RST_OSC_CNTR"
4134 #define device_bar_BDK_RST_OSC_CNTR 0x0 /* PF_BAR0 */
4135 #define busnum_BDK_RST_OSC_CNTR 0
4136 #define arguments_BDK_RST_OSC_CNTR -1,-1,-1,-1
4137
4138 /**
4139 * Register (RSL) rst_out_ctl
4140 *
4141 * RST External Reset Control Register
4142 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4143 */
4144 union bdk_rst_out_ctl
4145 {
4146 uint64_t u;
4147 struct bdk_rst_out_ctl_s
4148 {
4149 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4150 uint64_t reserved_4_63 : 60;
4151 uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
4152 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4153 field is set by software then it must also be cleared to deassert the pin.
4154 The pin is also automatically asserted and deasserted by hardware during a SCP
4155 domain reset.
4156 This field is always reinitialized on an SCP domain reset. */
4157 uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
4158 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4159 field is set by software then it must also be cleared to deassert the pin.
4160 The pin is also automatically asserted and deasserted by hardware during a MCP
4161 domain reset.
4162 This field is always reinitialized on an MCP domain reset. */
4163 uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
4164 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4165 field is set by software then it must also be cleared to deassert the pin.
4166 The pin is also automatically asserted and deasserted by hardware during a core
4167 domain reset.
4168 This field is always reinitialized on a core domain reset. */
4169 uint64_t reserved_0 : 1;
4170 #else /* Word 0 - Little Endian */
4171 uint64_t reserved_0 : 1;
4172 uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
4173 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4174 field is set by software then it must also be cleared to deassert the pin.
4175 The pin is also automatically asserted and deasserted by hardware during a core
4176 domain reset.
4177 This field is always reinitialized on a core domain reset. */
4178 uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
4179 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4180 field is set by software then it must also be cleared to deassert the pin.
4181 The pin is also automatically asserted and deasserted by hardware during a MCP
4182 domain reset.
4183 This field is always reinitialized on an MCP domain reset. */
4184 uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
4185 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4186 field is set by software then it must also be cleared to deassert the pin.
4187 The pin is also automatically asserted and deasserted by hardware during a SCP
4188 domain reset.
4189 This field is always reinitialized on an SCP domain reset. */
4190 uint64_t reserved_4_63 : 60;
4191 #endif /* Word 0 - End */
4192 } s;
4193 struct bdk_rst_out_ctl_cn8
4194 {
4195 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4196 uint64_t reserved_1_63 : 63;
4197 uint64_t soft_rst : 1; /**< [ 0: 0](R/W) Soft reset. When set to 1 by software, this field drives the CHIP_RESET_OUT_L pin
4198 active low. In this case the field must also be cleared by software to deassert
4199 the pin. The pin is also automatically asserted and deasserted by hardware
4200 during a cold/warm/soft reset. */
4201 #else /* Word 0 - Little Endian */
4202 uint64_t soft_rst : 1; /**< [ 0: 0](R/W) Soft reset. When set to 1 by software, this field drives the CHIP_RESET_OUT_L pin
4203 active low. In this case the field must also be cleared by software to deassert
4204 the pin. The pin is also automatically asserted and deasserted by hardware
4205 during a cold/warm/soft reset. */
4206 uint64_t reserved_1_63 : 63;
4207 #endif /* Word 0 - End */
4208 } cn8;
4209 struct bdk_rst_out_ctl_cn9
4210 {
4211 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4212 uint64_t reserved_4_63 : 60;
4213 uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
4214 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4215 field is set by software then it must also be cleared to deassert the pin.
4216 The pin is also automatically asserted and deasserted by hardware during a SCP
4217 domain reset.
4218 This field is always reinitialized on an SCP domain reset. */
4219 uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
4220 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4221 field is set by software then it must also be cleared to deassert the pin.
4222 The pin is also automatically asserted and deasserted by hardware during a MCP
4223 domain reset.
4224 This field is always reinitialized on an MCP domain reset. */
4225 uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
4226 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4227 field is set by software then it must also be cleared to deassert the pin.
4228 The pin is also automatically asserted and deasserted by hardware during a core
4229 domain reset.
4230 This field is always reinitialized on a core domain reset. */
4231 uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
4232 CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
4233 cleared to deassert the pin. The pin is also automatically asserted and deasserted by
4234 hardware during a chip domain reset.
4235 This field is always reinitialized on a chip domain reset. */
4236 #else /* Word 0 - Little Endian */
4237 uint64_t chip_rst : 1; /**< [ 0: 0](R/W) Chip domain reset output. When set to one by software, this field drives the
4238 CHIP_RESET_OUT_L pin active low. If this field is set my software then it must also be
4239 cleared to deassert the pin. The pin is also automatically asserted and deasserted by
4240 hardware during a chip domain reset.
4241 This field is always reinitialized on a chip domain reset. */
4242 uint64_t core_rst : 1; /**< [ 1: 1](R/W) Core reset output. When set by software, this field drives the GPIO_PIN_SEL_E::CORE_RESET_OUT
4243 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4244 field is set by software then it must also be cleared to deassert the pin.
4245 The pin is also automatically asserted and deasserted by hardware during a core
4246 domain reset.
4247 This field is always reinitialized on a core domain reset. */
4248 uint64_t mcp_rst : 1; /**< [ 2: 2](R/W) MCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::MCP_RESET_OUT
4249 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4250 field is set by software then it must also be cleared to deassert the pin.
4251 The pin is also automatically asserted and deasserted by hardware during a MCP
4252 domain reset.
4253 This field is always reinitialized on an MCP domain reset. */
4254 uint64_t scp_rst : 1; /**< [ 3: 3](R/W) SCP reset output. When set by software, this field drives the GPIO_PIN_SEL_E::SCP_RESET_OUT
4255 selectable pin active. The pin can be assigned using GPIO_BIT_CFG(). If this
4256 field is set by software then it must also be cleared to deassert the pin.
4257 The pin is also automatically asserted and deasserted by hardware during a SCP
4258 domain reset.
4259 This field is always reinitialized on an SCP domain reset. */
4260 uint64_t reserved_4_63 : 60;
4261 #endif /* Word 0 - End */
4262 } cn9;
4263 };
4264 typedef union bdk_rst_out_ctl bdk_rst_out_ctl_t;
4265
4266 #define BDK_RST_OUT_CTL BDK_RST_OUT_CTL_FUNC()
4267 static inline uint64_t BDK_RST_OUT_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_OUT_CTL_FUNC(void)4268 static inline uint64_t BDK_RST_OUT_CTL_FUNC(void)
4269 {
4270 return 0x87e006001688ll;
4271 }
4272
4273 #define typedef_BDK_RST_OUT_CTL bdk_rst_out_ctl_t
4274 #define bustype_BDK_RST_OUT_CTL BDK_CSR_TYPE_RSL
4275 #define basename_BDK_RST_OUT_CTL "RST_OUT_CTL"
4276 #define device_bar_BDK_RST_OUT_CTL 0x0 /* PF_BAR0 */
4277 #define busnum_BDK_RST_OUT_CTL 0
4278 #define arguments_BDK_RST_OUT_CTL -1,-1,-1,-1
4279
4280 /**
4281 * Register (RSL) rst_pll_limit
4282 *
4283 * RST PLL Maximum Frequency Limit Register
4284 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4285 */
4286 union bdk_rst_pll_limit
4287 {
4288 uint64_t u;
4289 struct bdk_rst_pll_limit_s
4290 {
4291 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4292 uint64_t reserved_23_63 : 41;
4293 uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier.
4294 This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
4295 A value of zero is considered unlimited. Once the value
4296 of this field is nonzero, any new values written into this field
4297 cannot exceed the previous value. Values 1-3 are considered illegal
4298 since the minimum PLL frequency is 200 MHz.
4299
4300 Internal:
4301 The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
4302 uint64_t reserved_15 : 1;
4303 uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
4304 This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
4305 A value of zero is considered unlimited. Once the value
4306 of this field is nonzero, any new values written into this field
4307 cannot exceed the previous value. Values 1-5 are considered illegal
4308 since the minimum PLL frequency is 300 MHz.
4309
4310 Internal:
4311 The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
4312 uint64_t reserved_7 : 1;
4313 uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
4314 This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
4315 A value of zero is considered unlimited. Once the value
4316 of this field is nonzero, any new values written into this field
4317 cannot exceed the previous value. Values 1-5 are considered illegal
4318 since the minimum PLL frequency is 300 MHz.
4319
4320 Internal:
4321 The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
4322 reset. */
4323 #else /* Word 0 - Little Endian */
4324 uint64_t pnr_max_mul : 7; /**< [ 6: 0](R/W/H) Coprocessor clock maximum PLL multiplier.
4325 This field is used to limit the RST_PNR_PLL[CUR_MUL] value.
4326 A value of zero is considered unlimited. Once the value
4327 of this field is nonzero, any new values written into this field
4328 cannot exceed the previous value. Values 1-5 are considered illegal
4329 since the minimum PLL frequency is 300 MHz.
4330
4331 Internal:
4332 The field is initialized to FUS_FUSE_NUM_E::PNR_MAX_MUL() fuses on a chip domain
4333 reset. */
4334 uint64_t reserved_7 : 1;
4335 uint64_t core_max_mul : 7; /**< [ 14: 8](R/W/H) Core clock maximum PLL multiplier.
4336 This field is used to limit the RST_CORE_PLL[CUR_MUL] value.
4337 A value of zero is considered unlimited. Once the value
4338 of this field is nonzero, any new values written into this field
4339 cannot exceed the previous value. Values 1-5 are considered illegal
4340 since the minimum PLL frequency is 300 MHz.
4341
4342 Internal:
4343 The field is initialized to FUS_FUSE_NUM_E::CORE_MAX_MUL() fuses on a chip domain reset. */
4344 uint64_t reserved_15 : 1;
4345 uint64_t cpt_max_mul : 7; /**< [ 22: 16](R/W/H) Crypto clock maximum PLL multiplier.
4346 This field is used to limit the RST_CPT_PLL[CUR_MUL] value.
4347 A value of zero is considered unlimited. Once the value
4348 of this field is nonzero, any new values written into this field
4349 cannot exceed the previous value. Values 1-3 are considered illegal
4350 since the minimum PLL frequency is 200 MHz.
4351
4352 Internal:
4353 The field is initialized to FUS_FUSE_NUM_E::CPT_MAX_MUL() fuses on a chip domain reset. */
4354 uint64_t reserved_23_63 : 41;
4355 #endif /* Word 0 - End */
4356 } s;
4357 /* struct bdk_rst_pll_limit_s cn; */
4358 };
4359 typedef union bdk_rst_pll_limit bdk_rst_pll_limit_t;
4360
4361 #define BDK_RST_PLL_LIMIT BDK_RST_PLL_LIMIT_FUNC()
4362 static inline uint64_t BDK_RST_PLL_LIMIT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PLL_LIMIT_FUNC(void)4363 static inline uint64_t BDK_RST_PLL_LIMIT_FUNC(void)
4364 {
4365 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4366 return 0x87e00a001790ll;
4367 __bdk_csr_fatal("RST_PLL_LIMIT", 0, 0, 0, 0, 0);
4368 }
4369
4370 #define typedef_BDK_RST_PLL_LIMIT bdk_rst_pll_limit_t
4371 #define bustype_BDK_RST_PLL_LIMIT BDK_CSR_TYPE_RSL
4372 #define basename_BDK_RST_PLL_LIMIT "RST_PLL_LIMIT"
4373 #define device_bar_BDK_RST_PLL_LIMIT 0x2 /* PF_BAR2 */
4374 #define busnum_BDK_RST_PLL_LIMIT 0
4375 #define arguments_BDK_RST_PLL_LIMIT -1,-1,-1,-1
4376
4377 /**
4378 * Register (RSL) rst_pnr_pll
4379 *
4380 * RST Coprocessor Clock PLL Control Register
4381 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4382 */
4383 union bdk_rst_pnr_pll
4384 {
4385 uint64_t u;
4386 struct bdk_rst_pnr_pll_s
4387 {
4388 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4389 uint64_t reserved_51_63 : 13;
4390 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
4391 0x0 = Coprocessor clock divided by 16.
4392 0x1 = Coprocessor clock tree output divided by 16.
4393 0x2 = PLL0 output divided by 16.
4394 0x3 = PLL1 output divided by 16.
4395
4396 This field is always reinitialized on a cold domain reset. */
4397 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
4398 reset at least 10 PLL reference clocks prior
4399 to changing [COUT_SEL]. It should remain under reset for at least 10
4400 PLL reference clocks after [COUT_SEL] changes.
4401 This field is always reinitialized on a cold domain reset. */
4402 uint64_t reserved_45_47 : 3;
4403 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
4404 powers down the inactive PLL after the switch has occured.
4405 When cleared, the inactive PLL remains in operation.
4406 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
4407 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
4408
4409 Note that a powered down PLL requires an additional 575 reference
4410 clocks to become active. This time is automatically added by the
4411 hardware.
4412 This field is always reinitialized on a cold domain reset. */
4413 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
4414 When set to a nonzero value, the hardware will wait for
4415 any PLL programming to complete and then switch to the inactive
4416 PLL after the specified number of PLL reference clocks. Hardware
4417 will add additional clocks if required.
4418 This field is always reinitialized on a cold domain reset.
4419
4420 Internal:
4421 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
4422 Additional time will be added to wakeup powered down AP cores but that
4423 time not be included in this count. */
4424 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
4425 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
4426 uint64_t reserved_23_29 : 7;
4427 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
4428 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
4429 used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
4430 This field is always reinitialized on a cold domain reset. */
4431 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
4432 clears bit when both pll is updated and any delay specified
4433 in [DLY_SWITCH] has completed.
4434 This field is always reinitialized on a chip domain reset. */
4435 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
4436 actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
4437 a minimum setting of 300 MHz.
4438 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
4439 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
4440 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
4441 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
4442 immediately after a cold or chip domain reset. In both cases, value
4443 is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
4444 #else /* Word 0 - Little Endian */
4445 uint64_t cur_mul : 7; /**< [ 6: 0](RO/H) Coprocessor clock frequency. Actual frequency is [CUR_MUL] * 50 MHz.
4446 Value will reflect [NXT_MUL] after [DLY_SWITCH] has completed or [INIT_MUL]
4447 immediately after a cold or chip domain reset. In both cases, value
4448 is limited by RST_PLL_LIMIT[PNR_MAX_MUL]. */
4449 uint64_t active_pll : 1; /**< [ 7: 7](RO) Indicates which physical PLL is in use. For diagnostic use only. */
4450 uint64_t nxt_mul : 7; /**< [ 14: 8](R/W) Coprocessor PLL frequency to be program in 50 MHz increments. The
4451 actual value used is limited by RST_PLL_LIMIT[PNR_MAX_MUL] and
4452 a minimum setting of 300 MHz.
4453 Value will match [INIT_MUL] immediately after a cold or chip domain reset. */
4454 uint64_t nxt_pgm : 1; /**< [ 15: 15](R/W/H) Program non-active PLL using [NXT_MUL]. Hardware automatically
4455 clears bit when both pll is updated and any delay specified
4456 in [DLY_SWITCH] has completed.
4457 This field is always reinitialized on a chip domain reset. */
4458 uint64_t init_mul : 7; /**< [ 22: 16](R/W) Coprocessor clock multiplier to be used during a core or chip domain
4459 reset. Actual frequency is [INIT_MUL] * 50 MHz. The actual value
4460 used is limited by RST_PLL_LIMIT[PNR_MAX_MUL].
4461 This field is always reinitialized on a cold domain reset. */
4462 uint64_t reserved_23_29 : 7;
4463 uint64_t pll0_pd : 1; /**< [ 30: 30](RO) PNR PLL0 power down. When set PLL is currently powered down. */
4464 uint64_t pll1_pd : 1; /**< [ 31: 31](RO) PNR PLL1 power down. When set PLL is currently powered down. */
4465 uint64_t dly_switch : 12; /**< [ 43: 32](R/W/H) Switch the active PLL after delaying this number of 100 MHz clocks.
4466 When set to a nonzero value, the hardware will wait for
4467 any PLL programming to complete and then switch to the inactive
4468 PLL after the specified number of PLL reference clocks. Hardware
4469 will add additional clocks if required.
4470 This field is always reinitialized on a cold domain reset.
4471
4472 Internal:
4473 Hardware will add counts to maintain 256 cpt_clk/sclk/rclk notification to hardware.
4474 Additional time will be added to wakeup powered down AP cores but that
4475 time not be included in this count. */
4476 uint64_t pd_switch : 1; /**< [ 44: 44](R/W) PLL powerdown on switch. When set, hardware automatically
4477 powers down the inactive PLL after the switch has occured.
4478 When cleared, the inactive PLL remains in operation.
4479 If [PD_SWITCH] is written to a one while both [DLY_SWITCH] and
4480 [NXT_PGM] are cleared then the inactive PLL will immediately powerdown.
4481
4482 Note that a powered down PLL requires an additional 575 reference
4483 clocks to become active. This time is automatically added by the
4484 hardware.
4485 This field is always reinitialized on a cold domain reset. */
4486 uint64_t reserved_45_47 : 3;
4487 uint64_t cout_reset : 1; /**< [ 48: 48](R/W) Coprocessor clockout reset. The coprocessor clockout should be placed in
4488 reset at least 10 PLL reference clocks prior
4489 to changing [COUT_SEL]. It should remain under reset for at least 10
4490 PLL reference clocks after [COUT_SEL] changes.
4491 This field is always reinitialized on a cold domain reset. */
4492 uint64_t cout_sel : 2; /**< [ 50: 49](R/W) Coprocessor clockout select.
4493 0x0 = Coprocessor clock divided by 16.
4494 0x1 = Coprocessor clock tree output divided by 16.
4495 0x2 = PLL0 output divided by 16.
4496 0x3 = PLL1 output divided by 16.
4497
4498 This field is always reinitialized on a cold domain reset. */
4499 uint64_t reserved_51_63 : 13;
4500 #endif /* Word 0 - End */
4501 } s;
4502 /* struct bdk_rst_pnr_pll_s cn; */
4503 };
4504 typedef union bdk_rst_pnr_pll bdk_rst_pnr_pll_t;
4505
4506 #define BDK_RST_PNR_PLL BDK_RST_PNR_PLL_FUNC()
4507 static inline uint64_t BDK_RST_PNR_PLL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PNR_PLL_FUNC(void)4508 static inline uint64_t BDK_RST_PNR_PLL_FUNC(void)
4509 {
4510 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4511 return 0x87e00a001788ll;
4512 __bdk_csr_fatal("RST_PNR_PLL", 0, 0, 0, 0, 0);
4513 }
4514
4515 #define typedef_BDK_RST_PNR_PLL bdk_rst_pnr_pll_t
4516 #define bustype_BDK_RST_PNR_PLL BDK_CSR_TYPE_RSL
4517 #define basename_BDK_RST_PNR_PLL "RST_PNR_PLL"
4518 #define device_bar_BDK_RST_PNR_PLL 0x2 /* PF_BAR2 */
4519 #define busnum_BDK_RST_PNR_PLL 0
4520 #define arguments_BDK_RST_PNR_PLL -1,-1,-1,-1
4521
4522 /**
4523 * Register (RSL) rst_power_dbg
4524 *
4525 * RST Core-Power Debug-Control Register
4526 */
4527 union bdk_rst_power_dbg
4528 {
4529 uint64_t u;
4530 struct bdk_rst_power_dbg_s
4531 {
4532 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4533 uint64_t reserved_3_63 : 61;
4534 uint64_t str : 3; /**< [ 2: 0](R/W) Reserved.
4535 Internal:
4536 Internal power driver strength. Resets only on cold reset. */
4537 #else /* Word 0 - Little Endian */
4538 uint64_t str : 3; /**< [ 2: 0](R/W) Reserved.
4539 Internal:
4540 Internal power driver strength. Resets only on cold reset. */
4541 uint64_t reserved_3_63 : 61;
4542 #endif /* Word 0 - End */
4543 } s;
4544 /* struct bdk_rst_power_dbg_s cn; */
4545 };
4546 typedef union bdk_rst_power_dbg bdk_rst_power_dbg_t;
4547
4548 #define BDK_RST_POWER_DBG BDK_RST_POWER_DBG_FUNC()
4549 static inline uint64_t BDK_RST_POWER_DBG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_POWER_DBG_FUNC(void)4550 static inline uint64_t BDK_RST_POWER_DBG_FUNC(void)
4551 {
4552 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
4553 return 0x87e006001708ll;
4554 __bdk_csr_fatal("RST_POWER_DBG", 0, 0, 0, 0, 0);
4555 }
4556
4557 #define typedef_BDK_RST_POWER_DBG bdk_rst_power_dbg_t
4558 #define bustype_BDK_RST_POWER_DBG BDK_CSR_TYPE_RSL
4559 #define basename_BDK_RST_POWER_DBG "RST_POWER_DBG"
4560 #define device_bar_BDK_RST_POWER_DBG 0x0 /* PF_BAR0 */
4561 #define busnum_BDK_RST_POWER_DBG 0
4562 #define arguments_BDK_RST_POWER_DBG -1,-1,-1,-1
4563
4564 /**
4565 * Register (RSL) rst_pp_available
4566 *
4567 * RST Core Availablity Register
4568 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4569 */
4570 union bdk_rst_pp_available
4571 {
4572 uint64_t u;
4573 struct bdk_rst_pp_available_s
4574 {
4575 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4576 uint64_t reserved_48_63 : 16;
4577 uint64_t present : 48; /**< [ 47: 0](RO) Each bit set indicates a physical core is present. */
4578 #else /* Word 0 - Little Endian */
4579 uint64_t present : 48; /**< [ 47: 0](RO) Each bit set indicates a physical core is present. */
4580 uint64_t reserved_48_63 : 16;
4581 #endif /* Word 0 - End */
4582 } s;
4583 struct bdk_rst_pp_available_cn9
4584 {
4585 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4586 uint64_t reserved_24_63 : 40;
4587 uint64_t present : 24; /**< [ 23: 0](RO) Each bit set indicates a physical core is present. */
4588 #else /* Word 0 - Little Endian */
4589 uint64_t present : 24; /**< [ 23: 0](RO) Each bit set indicates a physical core is present. */
4590 uint64_t reserved_24_63 : 40;
4591 #endif /* Word 0 - End */
4592 } cn9;
4593 struct bdk_rst_pp_available_cn81xx
4594 {
4595 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4596 uint64_t reserved_4_63 : 60;
4597 uint64_t present : 4; /**< [ 3: 0](RO) Each bit set indicates a physical core is present. */
4598 #else /* Word 0 - Little Endian */
4599 uint64_t present : 4; /**< [ 3: 0](RO) Each bit set indicates a physical core is present. */
4600 uint64_t reserved_4_63 : 60;
4601 #endif /* Word 0 - End */
4602 } cn81xx;
4603 /* struct bdk_rst_pp_available_s cn88xx; */
4604 /* struct bdk_rst_pp_available_cn9 cn83xx; */
4605 };
4606 typedef union bdk_rst_pp_available bdk_rst_pp_available_t;
4607
4608 #define BDK_RST_PP_AVAILABLE BDK_RST_PP_AVAILABLE_FUNC()
4609 static inline uint64_t BDK_RST_PP_AVAILABLE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PP_AVAILABLE_FUNC(void)4610 static inline uint64_t BDK_RST_PP_AVAILABLE_FUNC(void)
4611 {
4612 return 0x87e006001738ll;
4613 }
4614
4615 #define typedef_BDK_RST_PP_AVAILABLE bdk_rst_pp_available_t
4616 #define bustype_BDK_RST_PP_AVAILABLE BDK_CSR_TYPE_RSL
4617 #define basename_BDK_RST_PP_AVAILABLE "RST_PP_AVAILABLE"
4618 #define device_bar_BDK_RST_PP_AVAILABLE 0x0 /* PF_BAR0 */
4619 #define busnum_BDK_RST_PP_AVAILABLE 0
4620 #define arguments_BDK_RST_PP_AVAILABLE -1,-1,-1,-1
4621
4622 /**
4623 * Register (RSL) rst_pp_pending
4624 *
4625 * RST Cores Reset Pending Register
4626 * This register contains the reset status for each core.
4627 *
4628 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4629 */
4630 union bdk_rst_pp_pending
4631 {
4632 uint64_t u;
4633 struct bdk_rst_pp_pending_s
4634 {
4635 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4636 uint64_t reserved_48_63 : 16;
4637 uint64_t pend : 48; /**< [ 47: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4638 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4639 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4640 management.
4641
4642 The upper bits of this field remain accessible but will have no effect if the cores
4643 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4644 #else /* Word 0 - Little Endian */
4645 uint64_t pend : 48; /**< [ 47: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4646 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4647 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4648 management.
4649
4650 The upper bits of this field remain accessible but will have no effect if the cores
4651 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4652 uint64_t reserved_48_63 : 16;
4653 #endif /* Word 0 - End */
4654 } s;
4655 struct bdk_rst_pp_pending_cn9
4656 {
4657 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4658 uint64_t reserved_24_63 : 40;
4659 uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4660 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4661 reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
4662 management.
4663 This field is always reinitialized on a core domain reset.
4664
4665 The upper bits of this field remain accessible but will have no effect if the cores
4666 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4667 #else /* Word 0 - Little Endian */
4668 uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4669 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4670 reset a delay of 32K core-clock cycles between each core reset applies to satisfy power
4671 management.
4672 This field is always reinitialized on a core domain reset.
4673
4674 The upper bits of this field remain accessible but will have no effect if the cores
4675 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4676 uint64_t reserved_24_63 : 40;
4677 #endif /* Word 0 - End */
4678 } cn9;
4679 struct bdk_rst_pp_pending_cn81xx
4680 {
4681 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4682 uint64_t reserved_4_63 : 60;
4683 uint64_t pend : 4; /**< [ 3: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4684 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4685 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4686 management.
4687
4688 The upper bits of this field remain accessible but will have no effect if the cores
4689 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4690 #else /* Word 0 - Little Endian */
4691 uint64_t pend : 4; /**< [ 3: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4692 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4693 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4694 management.
4695
4696 The upper bits of this field remain accessible but will have no effect if the cores
4697 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4698 uint64_t reserved_4_63 : 60;
4699 #endif /* Word 0 - End */
4700 } cn81xx;
4701 /* struct bdk_rst_pp_pending_s cn88xx; */
4702 struct bdk_rst_pp_pending_cn83xx
4703 {
4704 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4705 uint64_t reserved_24_63 : 40;
4706 uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4707 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4708 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4709 management.
4710
4711 The upper bits of this field remain accessible but will have no effect if the cores
4712 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4713 #else /* Word 0 - Little Endian */
4714 uint64_t pend : 24; /**< [ 23: 0](RO/H) Set if corresponding core is waiting to change its reset state. Normally a reset change
4715 occurs immediately but if RST_PP_POWER[GATE] = 1 and the core is released from
4716 reset a delay of 64K core-clock cycles between each core reset applies to satisfy power
4717 management.
4718
4719 The upper bits of this field remain accessible but will have no effect if the cores
4720 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4721 uint64_t reserved_24_63 : 40;
4722 #endif /* Word 0 - End */
4723 } cn83xx;
4724 };
4725 typedef union bdk_rst_pp_pending bdk_rst_pp_pending_t;
4726
4727 #define BDK_RST_PP_PENDING BDK_RST_PP_PENDING_FUNC()
4728 static inline uint64_t BDK_RST_PP_PENDING_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PP_PENDING_FUNC(void)4729 static inline uint64_t BDK_RST_PP_PENDING_FUNC(void)
4730 {
4731 return 0x87e006001748ll;
4732 }
4733
4734 #define typedef_BDK_RST_PP_PENDING bdk_rst_pp_pending_t
4735 #define bustype_BDK_RST_PP_PENDING BDK_CSR_TYPE_RSL
4736 #define basename_BDK_RST_PP_PENDING "RST_PP_PENDING"
4737 #define device_bar_BDK_RST_PP_PENDING 0x0 /* PF_BAR0 */
4738 #define busnum_BDK_RST_PP_PENDING 0
4739 #define arguments_BDK_RST_PP_PENDING -1,-1,-1,-1
4740
4741 /**
4742 * Register (RSL) rst_pp_power
4743 *
4744 * RST Core-Power Gating-Control Register
4745 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4746 */
4747 union bdk_rst_pp_power
4748 {
4749 uint64_t u;
4750 struct bdk_rst_pp_power_s
4751 {
4752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4753 uint64_t reserved_48_63 : 16;
4754 uint64_t gate : 48; /**< [ 47: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4755 set,
4756 the core
4757 has voltage removed to save power. In typical operation these bits are set up during
4758 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4759 changed when the corresponding core is in reset.
4760
4761 The upper bits of this field remain accessible but will have no effect if the cores
4762 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4763 #else /* Word 0 - Little Endian */
4764 uint64_t gate : 48; /**< [ 47: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4765 set,
4766 the core
4767 has voltage removed to save power. In typical operation these bits are set up during
4768 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4769 changed when the corresponding core is in reset.
4770
4771 The upper bits of this field remain accessible but will have no effect if the cores
4772 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4773 uint64_t reserved_48_63 : 16;
4774 #endif /* Word 0 - End */
4775 } s;
4776 struct bdk_rst_pp_power_cn9
4777 {
4778 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4779 uint64_t reserved_24_63 : 40;
4780 uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding
4781 RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
4782 In typical operation these bits are set up during initialization and the
4783 AP core resets are controlled through RST_PP_RESET. These bits can only be
4784 changed when the corresponding AP core is in reset.
4785
4786 The upper bits of this field remain accessible but will have no effect if the cores
4787 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
4788 This field is always reinitialized on a core domain reset. */
4789 #else /* Word 0 - Little Endian */
4790 uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding
4791 RST_PP_RESET bit are set, the AP core is reduced to minimum power consumption.
4792 In typical operation these bits are set up during initialization and the
4793 AP core resets are controlled through RST_PP_RESET. These bits can only be
4794 changed when the corresponding AP core is in reset.
4795
4796 The upper bits of this field remain accessible but will have no effect if the cores
4797 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores.
4798 This field is always reinitialized on a core domain reset. */
4799 uint64_t reserved_24_63 : 40;
4800 #endif /* Word 0 - End */
4801 } cn9;
4802 struct bdk_rst_pp_power_cn81xx
4803 {
4804 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4805 uint64_t reserved_4_63 : 60;
4806 uint64_t gate : 4; /**< [ 3: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4807 set,
4808 the core
4809 has voltage removed to save power. In typical operation these bits are set up during
4810 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4811 changed when the corresponding core is in reset.
4812
4813 The upper bits of this field remain accessible but will have no effect if the cores
4814 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4815 #else /* Word 0 - Little Endian */
4816 uint64_t gate : 4; /**< [ 3: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4817 set,
4818 the core
4819 has voltage removed to save power. In typical operation these bits are set up during
4820 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4821 changed when the corresponding core is in reset.
4822
4823 The upper bits of this field remain accessible but will have no effect if the cores
4824 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4825 uint64_t reserved_4_63 : 60;
4826 #endif /* Word 0 - End */
4827 } cn81xx;
4828 /* struct bdk_rst_pp_power_s cn88xx; */
4829 struct bdk_rst_pp_power_cn83xx
4830 {
4831 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4832 uint64_t reserved_24_63 : 40;
4833 uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4834 set,
4835 the core
4836 has voltage removed to save power. In typical operation these bits are set up during
4837 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4838 changed when the corresponding core is in reset.
4839
4840 The upper bits of this field remain accessible but will have no effect if the cores
4841 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4842 #else /* Word 0 - Little Endian */
4843 uint64_t gate : 24; /**< [ 23: 0](R/W) Power down enable. When a bit in this field and the corresponding RST_PP_RESET bit are
4844 set,
4845 the core
4846 has voltage removed to save power. In typical operation these bits are set up during
4847 initialization and core resets are controlled through RST_PP_RESET. These bits can only be
4848 changed when the corresponding core is in reset.
4849
4850 The upper bits of this field remain accessible but will have no effect if the cores
4851 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4852 uint64_t reserved_24_63 : 40;
4853 #endif /* Word 0 - End */
4854 } cn83xx;
4855 };
4856 typedef union bdk_rst_pp_power bdk_rst_pp_power_t;
4857
4858 #define BDK_RST_PP_POWER BDK_RST_PP_POWER_FUNC()
4859 static inline uint64_t BDK_RST_PP_POWER_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PP_POWER_FUNC(void)4860 static inline uint64_t BDK_RST_PP_POWER_FUNC(void)
4861 {
4862 return 0x87e006001700ll;
4863 }
4864
4865 #define typedef_BDK_RST_PP_POWER bdk_rst_pp_power_t
4866 #define bustype_BDK_RST_PP_POWER BDK_CSR_TYPE_RSL
4867 #define basename_BDK_RST_PP_POWER "RST_PP_POWER"
4868 #define device_bar_BDK_RST_PP_POWER 0x0 /* PF_BAR0 */
4869 #define busnum_BDK_RST_PP_POWER 0
4870 #define arguments_BDK_RST_PP_POWER -1,-1,-1,-1
4871
4872 /**
4873 * Register (RSL) rst_pp_power_stat
4874 *
4875 * RST Core-Power Status Register
4876 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4877 */
4878 union bdk_rst_pp_power_stat
4879 {
4880 uint64_t u;
4881 struct bdk_rst_pp_power_stat_s
4882 {
4883 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4884 uint64_t reserved_48_63 : 16;
4885 uint64_t down : 48; /**< [ 47: 0](RO/H) Reserved.
4886 Internal:
4887 Core Powerdown. When set, each bit indicates the core is currently powered down.
4888 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4889 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4890 core should be reset again by setting the RST_PP_RESET and then clearing it.
4891
4892 The upper bits of this field remain accessible but will have no effect if the cores
4893 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4894 #else /* Word 0 - Little Endian */
4895 uint64_t down : 48; /**< [ 47: 0](RO/H) Reserved.
4896 Internal:
4897 Core Powerdown. When set, each bit indicates the core is currently powered down.
4898 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4899 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4900 core should be reset again by setting the RST_PP_RESET and then clearing it.
4901
4902 The upper bits of this field remain accessible but will have no effect if the cores
4903 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4904 uint64_t reserved_48_63 : 16;
4905 #endif /* Word 0 - End */
4906 } s;
4907 struct bdk_rst_pp_power_stat_cn9
4908 {
4909 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4910 uint64_t reserved_24_63 : 40;
4911 uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
4912 Internal:
4913 Core Powerdown. When set, each bit indicates the core is currently powered down.
4914 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4915 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4916 core should be reset again by setting the RST_PP_RESET and then clearing it.
4917
4918 The upper bits of this field remain accessible but will have no effect if the cores
4919 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4920 #else /* Word 0 - Little Endian */
4921 uint64_t down : 24; /**< [ 23: 0](RO/H) Reserved.
4922 Internal:
4923 Core Powerdown. When set, each bit indicates the core is currently powered down.
4924 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4925 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4926 core should be reset again by setting the RST_PP_RESET and then clearing it.
4927
4928 The upper bits of this field remain accessible but will have no effect if the cores
4929 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4930 uint64_t reserved_24_63 : 40;
4931 #endif /* Word 0 - End */
4932 } cn9;
4933 struct bdk_rst_pp_power_stat_cn81xx
4934 {
4935 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4936 uint64_t reserved_4_63 : 60;
4937 uint64_t down : 4; /**< [ 3: 0](RO/H) Reserved.
4938 Internal:
4939 Core Powerdown. When set, each bit indicates the core is currently powered down.
4940 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4941 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4942 core should be reset again by setting the RST_PP_RESET and then clearing it.
4943
4944 The upper bits of this field remain accessible but will have no effect if the cores
4945 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4946 #else /* Word 0 - Little Endian */
4947 uint64_t down : 4; /**< [ 3: 0](RO/H) Reserved.
4948 Internal:
4949 Core Powerdown. When set, each bit indicates the core is currently powered down.
4950 Typically this occurs when the corresponding RST_PP_RESET and RST_PP_POWER bits are set.
4951 If the core is powered down when RST_PP_PENDING and RST_PP_RESET are both clear then the
4952 core should be reset again by setting the RST_PP_RESET and then clearing it.
4953
4954 The upper bits of this field remain accessible but will have no effect if the cores
4955 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
4956 uint64_t reserved_4_63 : 60;
4957 #endif /* Word 0 - End */
4958 } cn81xx;
4959 /* struct bdk_rst_pp_power_stat_s cn88xx; */
4960 /* struct bdk_rst_pp_power_stat_cn9 cn83xx; */
4961 };
4962 typedef union bdk_rst_pp_power_stat bdk_rst_pp_power_stat_t;
4963
4964 #define BDK_RST_PP_POWER_STAT BDK_RST_PP_POWER_STAT_FUNC()
4965 static inline uint64_t BDK_RST_PP_POWER_STAT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PP_POWER_STAT_FUNC(void)4966 static inline uint64_t BDK_RST_PP_POWER_STAT_FUNC(void)
4967 {
4968 return 0x87e006001710ll;
4969 }
4970
4971 #define typedef_BDK_RST_PP_POWER_STAT bdk_rst_pp_power_stat_t
4972 #define bustype_BDK_RST_PP_POWER_STAT BDK_CSR_TYPE_RSL
4973 #define basename_BDK_RST_PP_POWER_STAT "RST_PP_POWER_STAT"
4974 #define device_bar_BDK_RST_PP_POWER_STAT 0x0 /* PF_BAR0 */
4975 #define busnum_BDK_RST_PP_POWER_STAT 0
4976 #define arguments_BDK_RST_PP_POWER_STAT -1,-1,-1,-1
4977
4978 /**
4979 * Register (RSL) rst_pp_reset
4980 *
4981 * RST Core Reset Register
4982 * This register contains the reset control for each core.
4983 * Write operations to this register should occur only if
4984 * RST_PP_PENDING is cleared.
4985 *
4986 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
4987 */
4988 union bdk_rst_pp_reset
4989 {
4990 uint64_t u;
4991 struct bdk_rst_pp_reset_s
4992 {
4993 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4994 uint64_t reserved_0_63 : 64;
4995 #else /* Word 0 - Little Endian */
4996 uint64_t reserved_0_63 : 64;
4997 #endif /* Word 0 - End */
4998 } s;
4999 struct bdk_rst_pp_reset_cn9
5000 {
5001 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5002 uint64_t reserved_24_63 : 40;
5003 uint64_t rst : 24; /**< [ 23: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
5004 writing a zero releases it from reset. These bits may also be cleared by
5005 either DAP or CIC activity.
5006 This field is always reinitialized on a core domain reset. */
5007 #else /* Word 0 - Little Endian */
5008 uint64_t rst : 24; /**< [ 23: 0](R/W/H) AP core resets. Writing a one holds the corresponding AP core in reset,
5009 writing a zero releases it from reset. These bits may also be cleared by
5010 either DAP or CIC activity.
5011 This field is always reinitialized on a core domain reset. */
5012 uint64_t reserved_24_63 : 40;
5013 #endif /* Word 0 - End */
5014 } cn9;
5015 struct bdk_rst_pp_reset_cn81xx
5016 {
5017 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5018 uint64_t reserved_4_63 : 60;
5019 uint64_t rst : 3; /**< [ 3: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5020 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5021 activity.
5022
5023 The upper bits of this field remain accessible but will have no effect if the cores
5024 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5025 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5026 This bit may also be cleared by either DAP or CIC activity. */
5027 #else /* Word 0 - Little Endian */
5028 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5029 This bit may also be cleared by either DAP or CIC activity. */
5030 uint64_t rst : 3; /**< [ 3: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5031 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5032 activity.
5033
5034 The upper bits of this field remain accessible but will have no effect if the cores
5035 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5036 uint64_t reserved_4_63 : 60;
5037 #endif /* Word 0 - End */
5038 } cn81xx;
5039 struct bdk_rst_pp_reset_cn88xx
5040 {
5041 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5042 uint64_t reserved_48_63 : 16;
5043 uint64_t rst : 47; /**< [ 47: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5044 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5045 activity.
5046
5047 The upper bits of this field remain accessible but will have no effect if the cores
5048 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5049 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5050 This bit may also be cleared by either DAP or CIC activity. */
5051 #else /* Word 0 - Little Endian */
5052 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5053 This bit may also be cleared by either DAP or CIC activity. */
5054 uint64_t rst : 47; /**< [ 47: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5055 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5056 activity.
5057
5058 The upper bits of this field remain accessible but will have no effect if the cores
5059 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5060 uint64_t reserved_48_63 : 16;
5061 #endif /* Word 0 - End */
5062 } cn88xx;
5063 struct bdk_rst_pp_reset_cn83xx
5064 {
5065 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5066 uint64_t reserved_24_63 : 40;
5067 uint64_t rst : 23; /**< [ 23: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5068 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5069 activity.
5070
5071 The upper bits of this field remain accessible but will have no effect if the cores
5072 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5073 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5074 This bit may also be cleared by either DAP or CIC activity. */
5075 #else /* Word 0 - Little Endian */
5076 uint64_t rst0 : 1; /**< [ 0: 0](R/W/H) Core reset for core 0, depends on if GPIO_STRAP\<2:0\> = RST_BOOT_METHOD_E::REMOTE.
5077 This bit may also be cleared by either DAP or CIC activity. */
5078 uint64_t rst : 23; /**< [ 23: 1](R/W/H) Core reset for cores 1 and above. Writing a 1 holds the corresponding core in reset,
5079 writing a 0 releases from reset. These bits may also be cleared by either DAP or CIC
5080 activity.
5081
5082 The upper bits of this field remain accessible but will have no effect if the cores
5083 are disabled. The number of bits set in RST_PP_AVAILABLE indicate the number of cores. */
5084 uint64_t reserved_24_63 : 40;
5085 #endif /* Word 0 - End */
5086 } cn83xx;
5087 };
5088 typedef union bdk_rst_pp_reset bdk_rst_pp_reset_t;
5089
5090 #define BDK_RST_PP_RESET BDK_RST_PP_RESET_FUNC()
5091 static inline uint64_t BDK_RST_PP_RESET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_PP_RESET_FUNC(void)5092 static inline uint64_t BDK_RST_PP_RESET_FUNC(void)
5093 {
5094 return 0x87e006001740ll;
5095 }
5096
5097 #define typedef_BDK_RST_PP_RESET bdk_rst_pp_reset_t
5098 #define bustype_BDK_RST_PP_RESET BDK_CSR_TYPE_RSL
5099 #define basename_BDK_RST_PP_RESET "RST_PP_RESET"
5100 #define device_bar_BDK_RST_PP_RESET 0x0 /* PF_BAR0 */
5101 #define busnum_BDK_RST_PP_RESET 0
5102 #define arguments_BDK_RST_PP_RESET -1,-1,-1,-1
5103
5104 /**
5105 * Register (RSL) rst_ref_check
5106 *
5107 * INTERNAL: RST Reference Clock Checker Register
5108 *
5109 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5110 */
5111 union bdk_rst_ref_check
5112 {
5113 uint64_t u;
5114 struct bdk_rst_ref_check_s
5115 {
5116 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5117 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5118 * Reference clock was outside operating range of 25 to 100 MHz.
5119 * Reference clock increased or decreased in frequency. */
5120 uint64_t reserved_48_62 : 15;
5121 uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
5122 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5123 while reference clock was high.
5124 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5125 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5126 while reference clock was low.
5127 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5128 #else /* Word 0 - Little Endian */
5129 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5130 while reference clock was low.
5131 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5132 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5133 while reference clock was high.
5134 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5135 uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
5136 uint64_t reserved_48_62 : 15;
5137 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5138 * Reference clock was outside operating range of 25 to 100 MHz.
5139 * Reference clock increased or decreased in frequency. */
5140 #endif /* Word 0 - End */
5141 } s;
5142 struct bdk_rst_ref_check_cn9
5143 {
5144 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5145 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5146 * Reference clock was outside operating range of 85 to 115 MHz.
5147 * Reference increased or decreased in frequency. */
5148 uint64_t reserved_48_62 : 15;
5149 uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
5150 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5151 while reference clock was high.
5152 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5153 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5154 while reference clock was low.
5155 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5156 #else /* Word 0 - Little Endian */
5157 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5158 while reference clock was low.
5159 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5160 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5161 while reference clock was high.
5162 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5163 uint64_t pcycle : 16; /**< [ 47: 32](RO/H) Previous cycle count. Sum of last [CNT0] and [CNT1]. */
5164 uint64_t reserved_48_62 : 15;
5165 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5166 * Reference clock was outside operating range of 85 to 115 MHz.
5167 * Reference increased or decreased in frequency. */
5168 #endif /* Word 0 - End */
5169 } cn9;
5170 struct bdk_rst_ref_check_cn81xx
5171 {
5172 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5173 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5174 * Reference clock was outside operating range of 25 to 100 MHz.
5175 * Reference clock increased or decreased in frequency. */
5176 uint64_t reserved_48_62 : 15;
5177 uint64_t reserved_32_47 : 16;
5178 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5179 while reference clock was high.
5180 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5181 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5182 while reference clock was low.
5183 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5184 #else /* Word 0 - Little Endian */
5185 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5186 while reference clock was low.
5187 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5188 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5189 while reference clock was high.
5190 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5191 uint64_t reserved_32_47 : 16;
5192 uint64_t reserved_48_62 : 15;
5193 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5194 * Reference clock was outside operating range of 25 to 100 MHz.
5195 * Reference clock increased or decreased in frequency. */
5196 #endif /* Word 0 - End */
5197 } cn81xx;
5198 struct bdk_rst_ref_check_cn88xx
5199 {
5200 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5201 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5202 * Reference clock was outside operating range of 25 to 100 MHz.
5203 * Reference clock duty cycle outside 50% +/- 20%.
5204 * Reference increased or decreased in frequency. */
5205 uint64_t reserved_48_62 : 15;
5206 uint64_t reserved_32_47 : 16;
5207 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5208 while reference clock was high.
5209 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5210 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5211 while reference clock was low.
5212 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5213 #else /* Word 0 - Little Endian */
5214 uint64_t cnt0 : 16; /**< [ 15: 0](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5215 while reference clock was low.
5216 When used with [CNT1] the internal ring-oscillator frequency can be determined. */
5217 uint64_t cnt1 : 16; /**< [ 31: 16](RO/H) Number of internal ring-oscillator clock pulses counted over 16 reference clocks
5218 while reference clock was high.
5219 When used with [CNT0] the internal ring-oscillator frequency can be determined. */
5220 uint64_t reserved_32_47 : 16;
5221 uint64_t reserved_48_62 : 15;
5222 uint64_t range : 1; /**< [ 63: 63](RO/H) Reference ever out of range. Set when either:
5223 * Reference clock was outside operating range of 25 to 100 MHz.
5224 * Reference clock duty cycle outside 50% +/- 20%.
5225 * Reference increased or decreased in frequency. */
5226 #endif /* Word 0 - End */
5227 } cn88xx;
5228 /* struct bdk_rst_ref_check_s cn83xx; */
5229 };
5230 typedef union bdk_rst_ref_check bdk_rst_ref_check_t;
5231
5232 #define BDK_RST_REF_CHECK BDK_RST_REF_CHECK_FUNC()
5233 static inline uint64_t BDK_RST_REF_CHECK_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_REF_CHECK_FUNC(void)5234 static inline uint64_t BDK_RST_REF_CHECK_FUNC(void)
5235 {
5236 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX))
5237 return 0x87e006001770ll;
5238 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX))
5239 return 0x87e006001770ll;
5240 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X))
5241 return 0x87e006001770ll;
5242 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5243 return 0x87e006001770ll;
5244 __bdk_csr_fatal("RST_REF_CHECK", 0, 0, 0, 0, 0);
5245 }
5246
5247 #define typedef_BDK_RST_REF_CHECK bdk_rst_ref_check_t
5248 #define bustype_BDK_RST_REF_CHECK BDK_CSR_TYPE_RSL
5249 #define basename_BDK_RST_REF_CHECK "RST_REF_CHECK"
5250 #define device_bar_BDK_RST_REF_CHECK 0x0 /* PF_BAR0 */
5251 #define busnum_BDK_RST_REF_CHECK 0
5252 #define arguments_BDK_RST_REF_CHECK -1,-1,-1,-1
5253
5254 /**
5255 * Register (RSL) rst_ref_cntr
5256 *
5257 * RST Reference-Counter Register
5258 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5259 */
5260 union bdk_rst_ref_cntr
5261 {
5262 uint64_t u;
5263 struct bdk_rst_ref_cntr_s
5264 {
5265 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5266 uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Count. The counter is initialized to 0x0 during a cold reset and is otherwise continuously
5267 running.
5268 CNT is incremented every reference-clock cycle (i.e. at 50 MHz). */
5269 #else /* Word 0 - Little Endian */
5270 uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Count. The counter is initialized to 0x0 during a cold reset and is otherwise continuously
5271 running.
5272 CNT is incremented every reference-clock cycle (i.e. at 50 MHz). */
5273 #endif /* Word 0 - End */
5274 } s;
5275 /* struct bdk_rst_ref_cntr_s cn8; */
5276 struct bdk_rst_ref_cntr_cn9
5277 {
5278 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5279 uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Reference count. [CNT] is incremented every 100 MHz reference clock.
5280 This field is always reinitialized on a cold domain reset. */
5281 #else /* Word 0 - Little Endian */
5282 uint64_t cnt : 64; /**< [ 63: 0](R/W/H) Reference count. [CNT] is incremented every 100 MHz reference clock.
5283 This field is always reinitialized on a cold domain reset. */
5284 #endif /* Word 0 - End */
5285 } cn9;
5286 };
5287 typedef union bdk_rst_ref_cntr bdk_rst_ref_cntr_t;
5288
5289 #define BDK_RST_REF_CNTR BDK_RST_REF_CNTR_FUNC()
5290 static inline uint64_t BDK_RST_REF_CNTR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_REF_CNTR_FUNC(void)5291 static inline uint64_t BDK_RST_REF_CNTR_FUNC(void)
5292 {
5293 return 0x87e006001758ll;
5294 }
5295
5296 #define typedef_BDK_RST_REF_CNTR bdk_rst_ref_cntr_t
5297 #define bustype_BDK_RST_REF_CNTR BDK_CSR_TYPE_RSL
5298 #define basename_BDK_RST_REF_CNTR "RST_REF_CNTR"
5299 #define device_bar_BDK_RST_REF_CNTR 0x0 /* PF_BAR0 */
5300 #define busnum_BDK_RST_REF_CNTR 0
5301 #define arguments_BDK_RST_REF_CNTR -1,-1,-1,-1
5302
5303 /**
5304 * Register (RSL) rst_refc_ctl
5305 *
5306 * RST Common Reference Clock Input Control Register
5307 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5308 */
5309 union bdk_rst_refc_ctl
5310 {
5311 uint64_t u;
5312 struct bdk_rst_refc_ctl_s
5313 {
5314 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5315 uint64_t reserved_9_63 : 55;
5316 uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Common clock 2 termination select.
5317 X0 = No termination.
5318 01 = LVPECL termination.
5319 11 = HCSL termination.
5320
5321 The field is initialized on a cold domain reset. */
5322 uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Common clock 2 receiver power down.
5323 When set, receiver is powered down.
5324 The field is initialized on a cold domain reset.
5325
5326 Internal:
5327 The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
5328 uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Common clock 1 termination select.
5329 X0 = No termination.
5330 01 = LVPECL termination.
5331 11 = HCSL termination.
5332
5333 The field is initialized on a cold domain reset. */
5334 uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Common clock 1 receiver power down.
5335 When set, receiver is powered down.
5336 The field is initialized on a cold domain reset.
5337
5338 Internal:
5339 The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
5340 uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
5341 X0 = No termination.
5342 01 = LVPECL termination.
5343 11 = HCSL termination.
5344
5345 The field is initialized on a cold domain reset. */
5346 uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
5347 Never powered down. Reads as zero. */
5348 #else /* Word 0 - Little Endian */
5349 uint64_t cclk0_pwdn : 1; /**< [ 0: 0](RAZ) Common clock 0 receiver power down.
5350 Never powered down. Reads as zero. */
5351 uint64_t cclk0_sel : 2; /**< [ 2: 1](RO/H) Common clock 0 termination select determined by hardware.
5352 X0 = No termination.
5353 01 = LVPECL termination.
5354 11 = HCSL termination.
5355
5356 The field is initialized on a cold domain reset. */
5357 uint64_t cclk1_pwdn : 1; /**< [ 3: 3](R/W) Common clock 1 receiver power down.
5358 When set, receiver is powered down.
5359 The field is initialized on a cold domain reset.
5360
5361 Internal:
5362 The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
5363 uint64_t cclk1_sel : 2; /**< [ 5: 4](R/W) Common clock 1 termination select.
5364 X0 = No termination.
5365 01 = LVPECL termination.
5366 11 = HCSL termination.
5367
5368 The field is initialized on a cold domain reset. */
5369 uint64_t cclk2_pwdn : 1; /**< [ 6: 6](R/W) Common clock 2 receiver power down.
5370 When set, receiver is powered down.
5371 The field is initialized on a cold domain reset.
5372
5373 Internal:
5374 The receiver is also forced into powerdown when jtg__rst_pll.iddq_mode is set. */
5375 uint64_t cclk2_sel : 2; /**< [ 8: 7](R/W) Common clock 2 termination select.
5376 X0 = No termination.
5377 01 = LVPECL termination.
5378 11 = HCSL termination.
5379
5380 The field is initialized on a cold domain reset. */
5381 uint64_t reserved_9_63 : 55;
5382 #endif /* Word 0 - End */
5383 } s;
5384 /* struct bdk_rst_refc_ctl_s cn; */
5385 };
5386 typedef union bdk_rst_refc_ctl bdk_rst_refc_ctl_t;
5387
5388 #define BDK_RST_REFC_CTL BDK_RST_REFC_CTL_FUNC()
5389 static inline uint64_t BDK_RST_REFC_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_REFC_CTL_FUNC(void)5390 static inline uint64_t BDK_RST_REFC_CTL_FUNC(void)
5391 {
5392 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5393 return 0x87e00a001798ll;
5394 __bdk_csr_fatal("RST_REFC_CTL", 0, 0, 0, 0, 0);
5395 }
5396
5397 #define typedef_BDK_RST_REFC_CTL bdk_rst_refc_ctl_t
5398 #define bustype_BDK_RST_REFC_CTL BDK_CSR_TYPE_RSL
5399 #define basename_BDK_RST_REFC_CTL "RST_REFC_CTL"
5400 #define device_bar_BDK_RST_REFC_CTL 0x2 /* PF_BAR2 */
5401 #define busnum_BDK_RST_REFC_CTL 0
5402 #define arguments_BDK_RST_REFC_CTL -1,-1,-1,-1
5403
5404 /**
5405 * Register (RSL) rst_reset_active
5406 *
5407 * RST Domain Reset Active Status Register
5408 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5409 */
5410 union bdk_rst_reset_active
5411 {
5412 uint64_t u;
5413 struct bdk_rst_reset_active_s
5414 {
5415 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5416 uint64_t reserved_4_63 : 60;
5417 uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
5418 Default reset value is zero after a chip reset. */
5419 uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
5420 Default reset value is one after a chip reset. */
5421 uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
5422 Default reset value is one after a chip reset. */
5423 uint64_t reserved_0 : 1;
5424 #else /* Word 0 - Little Endian */
5425 uint64_t reserved_0 : 1;
5426 uint64_t core : 1; /**< [ 1: 1](RO/H) Core domain reset status. When set, core domain is in reset.
5427 Default reset value is one after a chip reset. */
5428 uint64_t mcp : 1; /**< [ 2: 2](RO/H) MCP domain reset status. When set, MCP domain is in reset.
5429 Default reset value is one after a chip reset. */
5430 uint64_t scp : 1; /**< [ 3: 3](RO/H) SCP domain reset status. When set, SCP domain is in reset.
5431 Default reset value is zero after a chip reset. */
5432 uint64_t reserved_4_63 : 60;
5433 #endif /* Word 0 - End */
5434 } s;
5435 /* struct bdk_rst_reset_active_s cn; */
5436 };
5437 typedef union bdk_rst_reset_active bdk_rst_reset_active_t;
5438
5439 #define BDK_RST_RESET_ACTIVE BDK_RST_RESET_ACTIVE_FUNC()
5440 static inline uint64_t BDK_RST_RESET_ACTIVE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_RESET_ACTIVE_FUNC(void)5441 static inline uint64_t BDK_RST_RESET_ACTIVE_FUNC(void)
5442 {
5443 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5444 return 0x87e006001888ll;
5445 __bdk_csr_fatal("RST_RESET_ACTIVE", 0, 0, 0, 0, 0);
5446 }
5447
5448 #define typedef_BDK_RST_RESET_ACTIVE bdk_rst_reset_active_t
5449 #define bustype_BDK_RST_RESET_ACTIVE BDK_CSR_TYPE_RSL
5450 #define basename_BDK_RST_RESET_ACTIVE "RST_RESET_ACTIVE"
5451 #define device_bar_BDK_RST_RESET_ACTIVE 0x0 /* PF_BAR0 */
5452 #define busnum_BDK_RST_RESET_ACTIVE 0
5453 #define arguments_BDK_RST_RESET_ACTIVE -1,-1,-1,-1
5454
5455 /**
5456 * Register (RSL) rst_scp_domain_w1c
5457 *
5458 * RST SCP Domain Soft Reset Clear Register
5459 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5460 */
5461 union bdk_rst_scp_domain_w1c
5462 {
5463 uint64_t u;
5464 struct bdk_rst_scp_domain_w1c_s
5465 {
5466 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5467 uint64_t reserved_1_63 : 63;
5468 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of the SCP processor and associated logic.
5469 When set to one, the soft reset of the scp is removed.
5470 Reads of this register show the soft reset state. Not the actual scp domain reset.
5471 Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
5472 the actual reset state. To compensate for delays in reset, this field should only
5473 be set if RST_RESET_ACTIVE[SCP] is set.
5474 This field is always reinitialized on a chip domain reset. */
5475 #else /* Word 0 - Little Endian */
5476 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1C/H) Clear soft reset of the SCP processor and associated logic.
5477 When set to one, the soft reset of the scp is removed.
5478 Reads of this register show the soft reset state. Not the actual scp domain reset.
5479 Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
5480 the actual reset state. To compensate for delays in reset, this field should only
5481 be set if RST_RESET_ACTIVE[SCP] is set.
5482 This field is always reinitialized on a chip domain reset. */
5483 uint64_t reserved_1_63 : 63;
5484 #endif /* Word 0 - End */
5485 } s;
5486 /* struct bdk_rst_scp_domain_w1c_s cn; */
5487 };
5488 typedef union bdk_rst_scp_domain_w1c bdk_rst_scp_domain_w1c_t;
5489
5490 #define BDK_RST_SCP_DOMAIN_W1C BDK_RST_SCP_DOMAIN_W1C_FUNC()
5491 static inline uint64_t BDK_RST_SCP_DOMAIN_W1C_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_SCP_DOMAIN_W1C_FUNC(void)5492 static inline uint64_t BDK_RST_SCP_DOMAIN_W1C_FUNC(void)
5493 {
5494 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5495 return 0x87e006001848ll;
5496 __bdk_csr_fatal("RST_SCP_DOMAIN_W1C", 0, 0, 0, 0, 0);
5497 }
5498
5499 #define typedef_BDK_RST_SCP_DOMAIN_W1C bdk_rst_scp_domain_w1c_t
5500 #define bustype_BDK_RST_SCP_DOMAIN_W1C BDK_CSR_TYPE_RSL
5501 #define basename_BDK_RST_SCP_DOMAIN_W1C "RST_SCP_DOMAIN_W1C"
5502 #define device_bar_BDK_RST_SCP_DOMAIN_W1C 0x0 /* PF_BAR0 */
5503 #define busnum_BDK_RST_SCP_DOMAIN_W1C 0
5504 #define arguments_BDK_RST_SCP_DOMAIN_W1C -1,-1,-1,-1
5505
5506 /**
5507 * Register (RSL) rst_scp_domain_w1s
5508 *
5509 * RST SCP Domain Soft Reset Set Register
5510 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5511 */
5512 union bdk_rst_scp_domain_w1s
5513 {
5514 uint64_t u;
5515 struct bdk_rst_scp_domain_w1s_s
5516 {
5517 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5518 uint64_t reserved_1_63 : 63;
5519 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of SCP core and associated logic.
5520 When set to one, all logic associated with the scp domain is placed in reset.
5521 If RST_BOOT[RBOOT] is set, the scp soft reset will stay asserted until
5522 RST_SCP_DOMAIN_W1C is written. Otherwise it will automatically deassert.
5523 Reads of this register show the soft reset state. Not the actual scp domain reset.
5524 Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
5525 the actual reset state.
5526 This field is always reinitialized on a chip domain reset. */
5527 #else /* Word 0 - Little Endian */
5528 uint64_t soft_rst : 1; /**< [ 0: 0](R/W1S/H) Set soft reset of SCP core and associated logic.
5529 When set to one, all logic associated with the scp domain is placed in reset.
5530 If RST_BOOT[RBOOT] is set, the scp soft reset will stay asserted until
5531 RST_SCP_DOMAIN_W1C is written. Otherwise it will automatically deassert.
5532 Reads of this register show the soft reset state. Not the actual scp domain reset.
5533 Other factors may keep the reset active, reading RST_RESET_ACTIVE[SCP] shows
5534 the actual reset state.
5535 This field is always reinitialized on a chip domain reset. */
5536 uint64_t reserved_1_63 : 63;
5537 #endif /* Word 0 - End */
5538 } s;
5539 /* struct bdk_rst_scp_domain_w1s_s cn; */
5540 };
5541 typedef union bdk_rst_scp_domain_w1s bdk_rst_scp_domain_w1s_t;
5542
5543 #define BDK_RST_SCP_DOMAIN_W1S BDK_RST_SCP_DOMAIN_W1S_FUNC()
5544 static inline uint64_t BDK_RST_SCP_DOMAIN_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_SCP_DOMAIN_W1S_FUNC(void)5545 static inline uint64_t BDK_RST_SCP_DOMAIN_W1S_FUNC(void)
5546 {
5547 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5548 return 0x87e006001840ll;
5549 __bdk_csr_fatal("RST_SCP_DOMAIN_W1S", 0, 0, 0, 0, 0);
5550 }
5551
5552 #define typedef_BDK_RST_SCP_DOMAIN_W1S bdk_rst_scp_domain_w1s_t
5553 #define bustype_BDK_RST_SCP_DOMAIN_W1S BDK_CSR_TYPE_RSL
5554 #define basename_BDK_RST_SCP_DOMAIN_W1S "RST_SCP_DOMAIN_W1S"
5555 #define device_bar_BDK_RST_SCP_DOMAIN_W1S 0x0 /* PF_BAR0 */
5556 #define busnum_BDK_RST_SCP_DOMAIN_W1S 0
5557 #define arguments_BDK_RST_SCP_DOMAIN_W1S -1,-1,-1,-1
5558
5559 /**
5560 * Register (RSL) rst_soft_prst#
5561 *
5562 * RST PCIe Soft Reset Registers
5563 * This register is accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5564 */
5565 union bdk_rst_soft_prstx
5566 {
5567 uint64_t u;
5568 struct bdk_rst_soft_prstx_s
5569 {
5570 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5571 uint64_t reserved_1_63 : 63;
5572 uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PCIe logic and corresponding common logic associated with the
5573 SLI controller in
5574 all modes, not just RC mode.
5575 * If RST_CTL()[HOST_MODE] = 0, [SOFT_PRST] resets to 0.
5576 * If RST_CTL()[HOST_MODE] = 1, [SOFT_PRST] resets to 1.
5577
5578 When CNXXXX is configured to drive PERST*_L (i.e.
5579 RST_CTL()[RST_DRV] = 1), this controls the output value on PERST*_L.
5580
5581 Internal:
5582 This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
5583 #else /* Word 0 - Little Endian */
5584 uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PCIe logic and corresponding common logic associated with the
5585 SLI controller in
5586 all modes, not just RC mode.
5587 * If RST_CTL()[HOST_MODE] = 0, [SOFT_PRST] resets to 0.
5588 * If RST_CTL()[HOST_MODE] = 1, [SOFT_PRST] resets to 1.
5589
5590 When CNXXXX is configured to drive PERST*_L (i.e.
5591 RST_CTL()[RST_DRV] = 1), this controls the output value on PERST*_L.
5592
5593 Internal:
5594 This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
5595 uint64_t reserved_1_63 : 63;
5596 #endif /* Word 0 - End */
5597 } s;
5598 /* struct bdk_rst_soft_prstx_s cn8; */
5599 struct bdk_rst_soft_prstx_cn9
5600 {
5601 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5602 uint64_t reserved_1_63 : 63;
5603 uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PEM and corresponding GSER SERDES logic.
5604 This field is always set on a cold domain reset, when the link goes down
5605 or on the corresponding PEM domain reset if RST_CTL()[HOST_MODE] is set.
5606
5607 When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
5608
5609 Internal:
5610 This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
5611 #else /* Word 0 - Little Endian */
5612 uint64_t soft_prst : 1; /**< [ 0: 0](R/W) Soft PCIe reset. Resets the PEM and corresponding GSER SERDES logic.
5613 This field is always set on a cold domain reset, when the link goes down
5614 or on the corresponding PEM domain reset if RST_CTL()[HOST_MODE] is set.
5615
5616 When RST_CTL()[RST_DRV] is set, this controls the output value on PERST*_L.
5617
5618 Internal:
5619 This bit is also forced high if the corresponding PEM Cripple Fuse is set. */
5620 uint64_t reserved_1_63 : 63;
5621 #endif /* Word 0 - End */
5622 } cn9;
5623 };
5624 typedef union bdk_rst_soft_prstx bdk_rst_soft_prstx_t;
5625
5626 static inline uint64_t BDK_RST_SOFT_PRSTX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_RST_SOFT_PRSTX(unsigned long a)5627 static inline uint64_t BDK_RST_SOFT_PRSTX(unsigned long a)
5628 {
5629 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=2))
5630 return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
5631 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=3))
5632 return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
5633 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=5))
5634 return 0x87e0060016c0ll + 8ll * ((a) & 0x7);
5635 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=3))
5636 return 0x87e0060016c0ll + 8ll * ((a) & 0x3);
5637 __bdk_csr_fatal("RST_SOFT_PRSTX", 1, a, 0, 0, 0);
5638 }
5639
5640 #define typedef_BDK_RST_SOFT_PRSTX(a) bdk_rst_soft_prstx_t
5641 #define bustype_BDK_RST_SOFT_PRSTX(a) BDK_CSR_TYPE_RSL
5642 #define basename_BDK_RST_SOFT_PRSTX(a) "RST_SOFT_PRSTX"
5643 #define device_bar_BDK_RST_SOFT_PRSTX(a) 0x0 /* PF_BAR0 */
5644 #define busnum_BDK_RST_SOFT_PRSTX(a) (a)
5645 #define arguments_BDK_RST_SOFT_PRSTX(a) (a),-1,-1,-1
5646
5647 /**
5648 * Register (RSL) rst_soft_rst
5649 *
5650 * RST Soft Reset Register
5651 */
5652 union bdk_rst_soft_rst
5653 {
5654 uint64_t u;
5655 struct bdk_rst_soft_rst_s
5656 {
5657 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5658 uint64_t reserved_1_63 : 63;
5659 uint64_t soft_rst : 1; /**< [ 0: 0](WO) Soft reset. When set to 1, resets the CNXXXX core. When performing a soft reset from a
5660 remote PCIe host,
5661 always read this register and wait for the results before setting [SOFT_RST] to 1. */
5662 #else /* Word 0 - Little Endian */
5663 uint64_t soft_rst : 1; /**< [ 0: 0](WO) Soft reset. When set to 1, resets the CNXXXX core. When performing a soft reset from a
5664 remote PCIe host,
5665 always read this register and wait for the results before setting [SOFT_RST] to 1. */
5666 uint64_t reserved_1_63 : 63;
5667 #endif /* Word 0 - End */
5668 } s;
5669 /* struct bdk_rst_soft_rst_s cn; */
5670 };
5671 typedef union bdk_rst_soft_rst bdk_rst_soft_rst_t;
5672
5673 #define BDK_RST_SOFT_RST BDK_RST_SOFT_RST_FUNC()
5674 static inline uint64_t BDK_RST_SOFT_RST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_SOFT_RST_FUNC(void)5675 static inline uint64_t BDK_RST_SOFT_RST_FUNC(void)
5676 {
5677 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
5678 return 0x87e006001680ll;
5679 __bdk_csr_fatal("RST_SOFT_RST", 0, 0, 0, 0, 0);
5680 }
5681
5682 #define typedef_BDK_RST_SOFT_RST bdk_rst_soft_rst_t
5683 #define bustype_BDK_RST_SOFT_RST BDK_CSR_TYPE_RSL
5684 #define basename_BDK_RST_SOFT_RST "RST_SOFT_RST"
5685 #define device_bar_BDK_RST_SOFT_RST 0x0 /* PF_BAR0 */
5686 #define busnum_BDK_RST_SOFT_RST 0
5687 #define arguments_BDK_RST_SOFT_RST -1,-1,-1,-1
5688
5689 /**
5690 * Register (RSL) rst_src_map
5691 *
5692 * RST Source Domain Map Register
5693 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5694 */
5695 union bdk_rst_src_map
5696 {
5697 uint64_t u;
5698 struct bdk_rst_src_map_s
5699 {
5700 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5701 uint64_t reserved_13_63 : 51;
5702 uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
5703 Internal:
5704 OCX linkdown mapped to chip domain reset.
5705 When RST_OCX[RST_LINK] is set:
5706 0 = OCX transition from link up to link down will cause a core domain reset.
5707 1 = OCX transition from link up to link down will cause both a core domain reset
5708 and a chip domain reset.
5709
5710 This field is always reinitialized on a cold domain reset. */
5711 uint64_t reserved_11 : 1;
5712 uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
5713 0 = Mapping disabled.
5714 1 = SCP reset pin or the SCP watchdog will additionally
5715 cause an mcp domain reset.
5716
5717 This field is always reinitialized on a cold domain reset. */
5718 uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
5719 0 = Mapping disabled.
5720 1 = SCP reset pin or the SCP watchdog will additionally
5721 cause a core domain reset.
5722
5723 This field is always reinitialized on a cold domain reset. */
5724 uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
5725 0 = Mapping disabled.
5726 1 = SCP reset pin or the SCP watchdog will additionally
5727 cause a chip domain reset.
5728
5729 This field is always reinitialized on a cold domain reset. */
5730 uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to scp domain reset.
5731 0 = Mapping disabled.
5732 1 = MCP reset pin or the MCP watchdog will additionally
5733 cause an scp domain reset.
5734
5735 This field is always reinitialized on a cold domain reset. */
5736 uint64_t reserved_6 : 1;
5737 uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
5738 0 = Mapping disabled.
5739 1 = MCP reset pin or the MCP watchdog will additionally
5740 cause a core domain reset.
5741
5742 This field is always reinitialized on a cold domain reset. */
5743 uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
5744 0 = Mapping disabled.
5745 1 = MCP reset pin or the MCP watchdog will additionally
5746 cause a chip domain reset.
5747
5748 This field is always reinitialized on a cold domain reset. */
5749 uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to scp domain reset.
5750 0 = Mapping disabled.
5751 1 = Core reset pin or the AP watchdog will additionally
5752 cause an scp domain reset.
5753
5754 This field is always reinitialized on a cold domain reset. */
5755 uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to mcp domain reset.
5756 0 = Mapping disabled.
5757 1 = Core reset pin or the AP watchdog will additionally
5758 cause an mcp domain reset.
5759
5760 This field is always reinitialized on a cold domain reset. */
5761 uint64_t reserved_1 : 1;
5762 uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
5763 0 = Mapping disabled.
5764 1 = Core reset pin or the AP watchdog will additionally
5765 cause a chip domain reset.
5766
5767 This field is always reinitialized on a cold domain reset. */
5768 #else /* Word 0 - Little Endian */
5769 uint64_t core_to_chip : 1; /**< [ 0: 0](R/W) Core watchdog and pin resets mapped to chip domain reset.
5770 0 = Mapping disabled.
5771 1 = Core reset pin or the AP watchdog will additionally
5772 cause a chip domain reset.
5773
5774 This field is always reinitialized on a cold domain reset. */
5775 uint64_t reserved_1 : 1;
5776 uint64_t core_to_mcp : 1; /**< [ 2: 2](R/W) Core watchdog and pin resets mapped to mcp domain reset.
5777 0 = Mapping disabled.
5778 1 = Core reset pin or the AP watchdog will additionally
5779 cause an mcp domain reset.
5780
5781 This field is always reinitialized on a cold domain reset. */
5782 uint64_t core_to_scp : 1; /**< [ 3: 3](R/W) Core watchdog and pin resets mapped to scp domain reset.
5783 0 = Mapping disabled.
5784 1 = Core reset pin or the AP watchdog will additionally
5785 cause an scp domain reset.
5786
5787 This field is always reinitialized on a cold domain reset. */
5788 uint64_t mcp_to_chip : 1; /**< [ 4: 4](R/W) MCP watchdog and pin resets mapped to chip domain reset.
5789 0 = Mapping disabled.
5790 1 = MCP reset pin or the MCP watchdog will additionally
5791 cause a chip domain reset.
5792
5793 This field is always reinitialized on a cold domain reset. */
5794 uint64_t mcp_to_core : 1; /**< [ 5: 5](R/W) MCP watchdog and pin resets mapped to core domain reset.
5795 0 = Mapping disabled.
5796 1 = MCP reset pin or the MCP watchdog will additionally
5797 cause a core domain reset.
5798
5799 This field is always reinitialized on a cold domain reset. */
5800 uint64_t reserved_6 : 1;
5801 uint64_t mcp_to_scp : 1; /**< [ 7: 7](R/W) MCP watchdog and pin resets mapped to scp domain reset.
5802 0 = Mapping disabled.
5803 1 = MCP reset pin or the MCP watchdog will additionally
5804 cause an scp domain reset.
5805
5806 This field is always reinitialized on a cold domain reset. */
5807 uint64_t scp_to_chip : 1; /**< [ 8: 8](R/W) SCP watchdog and pin resets mapped to chip domain reset.
5808 0 = Mapping disabled.
5809 1 = SCP reset pin or the SCP watchdog will additionally
5810 cause a chip domain reset.
5811
5812 This field is always reinitialized on a cold domain reset. */
5813 uint64_t scp_to_core : 1; /**< [ 9: 9](R/W) SCP watchdog and pin resets mapped to core domain reset.
5814 0 = Mapping disabled.
5815 1 = SCP reset pin or the SCP watchdog will additionally
5816 cause a core domain reset.
5817
5818 This field is always reinitialized on a cold domain reset. */
5819 uint64_t scp_to_mcp : 1; /**< [ 10: 10](R/W) SCP watchdog and pin resets mapped to MCP domain reset.
5820 0 = Mapping disabled.
5821 1 = SCP reset pin or the SCP watchdog will additionally
5822 cause an mcp domain reset.
5823
5824 This field is always reinitialized on a cold domain reset. */
5825 uint64_t reserved_11 : 1;
5826 uint64_t ocx_to_chip : 1; /**< [ 12: 12](R/W) Reserved.
5827 Internal:
5828 OCX linkdown mapped to chip domain reset.
5829 When RST_OCX[RST_LINK] is set:
5830 0 = OCX transition from link up to link down will cause a core domain reset.
5831 1 = OCX transition from link up to link down will cause both a core domain reset
5832 and a chip domain reset.
5833
5834 This field is always reinitialized on a cold domain reset. */
5835 uint64_t reserved_13_63 : 51;
5836 #endif /* Word 0 - End */
5837 } s;
5838 /* struct bdk_rst_src_map_s cn; */
5839 };
5840 typedef union bdk_rst_src_map bdk_rst_src_map_t;
5841
5842 #define BDK_RST_SRC_MAP BDK_RST_SRC_MAP_FUNC()
5843 static inline uint64_t BDK_RST_SRC_MAP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_SRC_MAP_FUNC(void)5844 static inline uint64_t BDK_RST_SRC_MAP_FUNC(void)
5845 {
5846 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5847 return 0x87e006001898ll;
5848 __bdk_csr_fatal("RST_SRC_MAP", 0, 0, 0, 0, 0);
5849 }
5850
5851 #define typedef_BDK_RST_SRC_MAP bdk_rst_src_map_t
5852 #define bustype_BDK_RST_SRC_MAP BDK_CSR_TYPE_RSL
5853 #define basename_BDK_RST_SRC_MAP "RST_SRC_MAP"
5854 #define device_bar_BDK_RST_SRC_MAP 0x0 /* PF_BAR0 */
5855 #define busnum_BDK_RST_SRC_MAP 0
5856 #define arguments_BDK_RST_SRC_MAP -1,-1,-1,-1
5857
5858 /**
5859 * Register (RSL) rst_sw_w1s
5860 *
5861 * RST Software W1S Data Register
5862 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5863 */
5864 union bdk_rst_sw_w1s
5865 {
5866 uint64_t u;
5867 struct bdk_rst_sw_w1s_s
5868 {
5869 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5870 uint64_t data : 64; /**< [ 63: 0](R/W1S) Data register that can be set by software and is only cleared
5871 on a chip domain reset.
5872 This field is always reinitialized on a chip domain reset. */
5873 #else /* Word 0 - Little Endian */
5874 uint64_t data : 64; /**< [ 63: 0](R/W1S) Data register that can be set by software and is only cleared
5875 on a chip domain reset.
5876 This field is always reinitialized on a chip domain reset. */
5877 #endif /* Word 0 - End */
5878 } s;
5879 /* struct bdk_rst_sw_w1s_s cn; */
5880 };
5881 typedef union bdk_rst_sw_w1s bdk_rst_sw_w1s_t;
5882
5883 #define BDK_RST_SW_W1S BDK_RST_SW_W1S_FUNC()
5884 static inline uint64_t BDK_RST_SW_W1S_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_SW_W1S_FUNC(void)5885 static inline uint64_t BDK_RST_SW_W1S_FUNC(void)
5886 {
5887 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
5888 return 0x87e0060017f0ll;
5889 __bdk_csr_fatal("RST_SW_W1S", 0, 0, 0, 0, 0);
5890 }
5891
5892 #define typedef_BDK_RST_SW_W1S bdk_rst_sw_w1s_t
5893 #define bustype_BDK_RST_SW_W1S BDK_CSR_TYPE_RSL
5894 #define basename_BDK_RST_SW_W1S "RST_SW_W1S"
5895 #define device_bar_BDK_RST_SW_W1S 0x0 /* PF_BAR0 */
5896 #define busnum_BDK_RST_SW_W1S 0
5897 #define arguments_BDK_RST_SW_W1S -1,-1,-1,-1
5898
5899 /**
5900 * Register (RSL) rst_thermal_alert
5901 *
5902 * RST Thermal Alert Register
5903 * This register is not accessible through ROM scripts; see SCR_WRITE32_S[ADDR].
5904 */
5905 union bdk_rst_thermal_alert
5906 {
5907 uint64_t u;
5908 struct bdk_rst_thermal_alert_s
5909 {
5910 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5911 uint64_t reserved_9_63 : 55;
5912 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
5913 set by either of the
5914 on-board temperature sensors reaching a failure threshold or writing this bit.
5915 The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
5916 the chip. */
5917 uint64_t reserved_2_7 : 6;
5918 uint64_t alert : 2; /**< [ 1: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
5919 failure threshold. */
5920 #else /* Word 0 - Little Endian */
5921 uint64_t alert : 2; /**< [ 1: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
5922 failure threshold. */
5923 uint64_t reserved_2_7 : 6;
5924 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
5925 set by either of the
5926 on-board temperature sensors reaching a failure threshold or writing this bit.
5927 The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
5928 the chip. */
5929 uint64_t reserved_9_63 : 55;
5930 #endif /* Word 0 - End */
5931 } s;
5932 struct bdk_rst_thermal_alert_cn9
5933 {
5934 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5935 uint64_t reserved_9_63 : 55;
5936 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set, drives the THERMAL_TRIP_L pin active low.
5937 This field is set by one of the on-board temperature sensors reaching a
5938 failure threshold or writing this bit.
5939 This field is always reinitialized on a cold domain reset. */
5940 uint64_t reserved_1_7 : 7;
5941 uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to one, indicates a temperature sensor is
5942 currently at the failure threshold. */
5943 #else /* Word 0 - Little Endian */
5944 uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to one, indicates a temperature sensor is
5945 currently at the failure threshold. */
5946 uint64_t reserved_1_7 : 7;
5947 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set, drives the THERMAL_TRIP_L pin active low.
5948 This field is set by one of the on-board temperature sensors reaching a
5949 failure threshold or writing this bit.
5950 This field is always reinitialized on a cold domain reset. */
5951 uint64_t reserved_9_63 : 55;
5952 #endif /* Word 0 - End */
5953 } cn9;
5954 struct bdk_rst_thermal_alert_cn81xx
5955 {
5956 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5957 uint64_t reserved_9_63 : 55;
5958 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
5959 set by either of the
5960 on-board temperature sensors reaching a failure threshold or writing this bit.
5961 The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
5962 the chip. */
5963 uint64_t reserved_1_7 : 7;
5964 uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
5965 failure threshold. */
5966 #else /* Word 0 - Little Endian */
5967 uint64_t alert : 1; /**< [ 0: 0](RO/H) Thermal alert status. When set to 1, indicates the temperature sensor is currently at the
5968 failure threshold. */
5969 uint64_t reserved_1_7 : 7;
5970 uint64_t trip : 1; /**< [ 8: 8](R/W1S/H) Thermal trip pin. When set to 1, drives the THERMAL_TRIP_N pin active low. This field is
5971 set by either of the
5972 on-board temperature sensors reaching a failure threshold or writing this bit.
5973 The bit can only be cleared by a deassertion of the PLL_DC_OK pin which completely resets
5974 the chip. */
5975 uint64_t reserved_9_63 : 55;
5976 #endif /* Word 0 - End */
5977 } cn81xx;
5978 /* struct bdk_rst_thermal_alert_s cn88xx; */
5979 /* struct bdk_rst_thermal_alert_cn81xx cn83xx; */
5980 };
5981 typedef union bdk_rst_thermal_alert bdk_rst_thermal_alert_t;
5982
5983 #define BDK_RST_THERMAL_ALERT BDK_RST_THERMAL_ALERT_FUNC()
5984 static inline uint64_t BDK_RST_THERMAL_ALERT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_THERMAL_ALERT_FUNC(void)5985 static inline uint64_t BDK_RST_THERMAL_ALERT_FUNC(void)
5986 {
5987 return 0x87e006001690ll;
5988 }
5989
5990 #define typedef_BDK_RST_THERMAL_ALERT bdk_rst_thermal_alert_t
5991 #define bustype_BDK_RST_THERMAL_ALERT BDK_CSR_TYPE_RSL
5992 #define basename_BDK_RST_THERMAL_ALERT "RST_THERMAL_ALERT"
5993 #define device_bar_BDK_RST_THERMAL_ALERT 0x0 /* PF_BAR0 */
5994 #define busnum_BDK_RST_THERMAL_ALERT 0
5995 #define arguments_BDK_RST_THERMAL_ALERT -1,-1,-1,-1
5996
5997 /**
5998 * Register (RSL) rst_tns_pll_ctl
5999 *
6000 * RST Network-Switch PLL-Control Register
6001 * This register controls the network-switch clock frequency.
6002 * The following sequence is the TNS PLL-bringup sequence:
6003 *
6004 * 1. Write a 0 to [RESET_N] and a 1 to [DIV_RESET].
6005 *
6006 * 2. Set [CLKF] and [PS_EN]. If jtg_test_mode.
6007 * then also write jtg__tns_pll_tm_en2, jtg__tns_pll_tm_en4, jtg__tns_pll_tm_en12 and
6008 * jtg__tns_pll_tm_en24.
6009 *
6010 * 3. Wait 128 reference-clock cycles.
6011 *
6012 * 4. Write 1 to [RESET_N].
6013 *
6014 * 5. Wait 1152 reference-clock cycles.
6015 *
6016 * 6. Write 0 to [DIV_RESET].
6017 *
6018 * 7. Wait 10 reference-clock cycles before bringing up the network interface.
6019 *
6020 * If test mode is going to be activated, wait an additional 8191 reference-clock cycles to allow
6021 * PLL clock
6022 * alignment.
6023 */
6024 union bdk_rst_tns_pll_ctl
6025 {
6026 uint64_t u;
6027 struct bdk_rst_tns_pll_ctl_s
6028 {
6029 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
6030 uint64_t reserved_29_63 : 35;
6031 uint64_t pll_fbslip : 1; /**< [ 28: 28](RO/H) PLL FBSLIP indication. */
6032 uint64_t pll_lock : 1; /**< [ 27: 27](RO/H) PLL LOCK indication. */
6033 uint64_t pll_rfslip : 1; /**< [ 26: 26](RO/H) PLL RFSLIP indication. */
6034 uint64_t reserved_23_25 : 3;
6035 uint64_t div_reset : 1; /**< [ 22: 22](R/W) Postscalar divider reset. */
6036 uint64_t ps_en : 4; /**< [ 21: 18](R/W) PLL postscalar divide ratio. Determines the network clock speed.
6037 0x0 = Divide TNS PLL by 1.
6038 0x1 = Divide TNS PLL by 2.
6039 0x2 = Divide TNS PLL by 3.
6040 0x3 = Divide TNS PLL by 4.
6041 0x4 = Divide TNS PLL by 5.
6042 0x5 = Divide TNS PLL by 6.
6043 0x6 = Divide TNS PLL by 7.
6044 0x7 = Divide TNS PLL by 8.
6045 0x8 = Divide TNS PLL by 10.
6046 0x9 = Divide TNS PLL by 12.
6047 0xA-0xF = Reserved.
6048
6049 [PS_EN] is not used when [DIV_RESET] = 1 */
6050 uint64_t reserved_15_17 : 3;
6051 uint64_t cout_rst : 1; /**< [ 14: 14](R/W) Clockout postscaler reset. This clockout postscaler should be placed in reset at
6052 least 10 reference-clock cycles prior to changing [COUT_SEL]. The clockout
6053 postscaler should remain under reset for at least 10 reference-clock cycles
6054 after [COUT_SEL] changes. */
6055 uint64_t cout_sel : 2; /**< [ 13: 12](R/W) PNR clockout select:
6056 0x0 = Network clock.
6057 0x1 = PS output.
6058 0x2 = PLL output.
6059 0x3 = UNDIVIDED core clock. */
6060 uint64_t reserved_8_11 : 4;
6061 uint64_t reset_n : 1; /**< [ 7: 7](R/W) PLL reset. */
6062 uint64_t clkf : 7; /**< [ 6: 0](R/W) PLL multiplier. Sets TNS clock frequency to 50 MHz * ([CLKF]+1) / ([PS_EN]+1). */
6063 #else /* Word 0 - Little Endian */
6064 uint64_t clkf : 7; /**< [ 6: 0](R/W) PLL multiplier. Sets TNS clock frequency to 50 MHz * ([CLKF]+1) / ([PS_EN]+1). */
6065 uint64_t reset_n : 1; /**< [ 7: 7](R/W) PLL reset. */
6066 uint64_t reserved_8_11 : 4;
6067 uint64_t cout_sel : 2; /**< [ 13: 12](R/W) PNR clockout select:
6068 0x0 = Network clock.
6069 0x1 = PS output.
6070 0x2 = PLL output.
6071 0x3 = UNDIVIDED core clock. */
6072 uint64_t cout_rst : 1; /**< [ 14: 14](R/W) Clockout postscaler reset. This clockout postscaler should be placed in reset at
6073 least 10 reference-clock cycles prior to changing [COUT_SEL]. The clockout
6074 postscaler should remain under reset for at least 10 reference-clock cycles
6075 after [COUT_SEL] changes. */
6076 uint64_t reserved_15_17 : 3;
6077 uint64_t ps_en : 4; /**< [ 21: 18](R/W) PLL postscalar divide ratio. Determines the network clock speed.
6078 0x0 = Divide TNS PLL by 1.
6079 0x1 = Divide TNS PLL by 2.
6080 0x2 = Divide TNS PLL by 3.
6081 0x3 = Divide TNS PLL by 4.
6082 0x4 = Divide TNS PLL by 5.
6083 0x5 = Divide TNS PLL by 6.
6084 0x6 = Divide TNS PLL by 7.
6085 0x7 = Divide TNS PLL by 8.
6086 0x8 = Divide TNS PLL by 10.
6087 0x9 = Divide TNS PLL by 12.
6088 0xA-0xF = Reserved.
6089
6090 [PS_EN] is not used when [DIV_RESET] = 1 */
6091 uint64_t div_reset : 1; /**< [ 22: 22](R/W) Postscalar divider reset. */
6092 uint64_t reserved_23_25 : 3;
6093 uint64_t pll_rfslip : 1; /**< [ 26: 26](RO/H) PLL RFSLIP indication. */
6094 uint64_t pll_lock : 1; /**< [ 27: 27](RO/H) PLL LOCK indication. */
6095 uint64_t pll_fbslip : 1; /**< [ 28: 28](RO/H) PLL FBSLIP indication. */
6096 uint64_t reserved_29_63 : 35;
6097 #endif /* Word 0 - End */
6098 } s;
6099 /* struct bdk_rst_tns_pll_ctl_s cn; */
6100 };
6101 typedef union bdk_rst_tns_pll_ctl bdk_rst_tns_pll_ctl_t;
6102
6103 #define BDK_RST_TNS_PLL_CTL BDK_RST_TNS_PLL_CTL_FUNC()
6104 static inline uint64_t BDK_RST_TNS_PLL_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_RST_TNS_PLL_CTL_FUNC(void)6105 static inline uint64_t BDK_RST_TNS_PLL_CTL_FUNC(void)
6106 {
6107 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX))
6108 return 0x87e006001780ll;
6109 __bdk_csr_fatal("RST_TNS_PLL_CTL", 0, 0, 0, 0, 0);
6110 }
6111
6112 #define typedef_BDK_RST_TNS_PLL_CTL bdk_rst_tns_pll_ctl_t
6113 #define bustype_BDK_RST_TNS_PLL_CTL BDK_CSR_TYPE_RSL
6114 #define basename_BDK_RST_TNS_PLL_CTL "RST_TNS_PLL_CTL"
6115 #define device_bar_BDK_RST_TNS_PLL_CTL 0x0 /* PF_BAR0 */
6116 #define busnum_BDK_RST_TNS_PLL_CTL 0
6117 #define arguments_BDK_RST_TNS_PLL_CTL -1,-1,-1,-1
6118
6119 #endif /* __BDK_CSRS_RST_H__ */
6120