1 #ifndef __BDK_CSRS_MIO_FUS_H__
2 #define __BDK_CSRS_MIO_FUS_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44 #include <bdk-minimal.h> /* FIXME: added by dhendrix */
45
46 /**
47 * @file
48 *
49 * Configuration and status register (CSR) address and type definitions for
50 * Cavium MIO_FUS.
51 *
52 * This file is auto generated. Do not edit.
53 *
54 */
55
56 /**
57 * Enumeration mio_fus_bar_e
58 *
59 * MIO FUS Base Address Register Enumeration
60 * Enumerates the base address registers.
61 */
62 #define BDK_MIO_FUS_BAR_E_MIO_FUS_PF_BAR0 (0x87e003000000ll)
63 #define BDK_MIO_FUS_BAR_E_MIO_FUS_PF_BAR0_SIZE 0x800000ull
64
65 /**
66 * Enumeration mio_fus_fuse_num_e
67 *
68 * INTERNAL: MIO FUS Fuse Number Enumeration
69 *
70 * Enumerates the fuse numbers.
71 */
72 #define BDK_MIO_FUS_FUSE_NUM_E_BAR2_SZ_CONF (0x54)
73 #define BDK_MIO_FUS_FUSE_NUM_E_BGX2_DIS (0xe5)
74 #define BDK_MIO_FUS_FUSE_NUM_E_BGX3_DIS (0xe6)
75 #define BDK_MIO_FUS_FUSE_NUM_E_BGX_DISX(a) (0x6c + (a))
76 #define BDK_MIO_FUS_FUSE_NUM_E_CHIP_IDX(a) (0x40 + (a))
77 #define BDK_MIO_FUS_FUSE_NUM_E_CMB_RCLK_BYP_SELECT (0x266)
78 #define BDK_MIO_FUS_FUSE_NUM_E_CMB_RCLK_BYP_SETTINGX(a) (0x25a + (a))
79 #define BDK_MIO_FUS_FUSE_NUM_E_CORE_PLL_MULX(a) (0x7b + (a))
80 #define BDK_MIO_FUS_FUSE_NUM_E_CPT0_ENG_DISX(a) (0x684 + (a))
81 #define BDK_MIO_FUS_FUSE_NUM_E_CPT1_ENG_DISX(a) (0x6b4 + (a))
82 #define BDK_MIO_FUS_FUSE_NUM_E_CPT_ENG_DISX(a) (0x680 + (a))
83 #define BDK_MIO_FUS_FUSE_NUM_E_DDF_DIS (0xe4)
84 #define BDK_MIO_FUS_FUSE_NUM_E_DESX(a) (0x3c0 + (a))
85 #define BDK_MIO_FUS_FUSE_NUM_E_DFA_INFO_CLMX(a) (0x5e + (a))
86 #define BDK_MIO_FUS_FUSE_NUM_E_DFA_INFO_DTEX(a) (0x5b + (a))
87 #define BDK_MIO_FUS_FUSE_NUM_E_DORM_CRYPTO (0x67)
88 #define BDK_MIO_FUS_FUSE_NUM_E_EAST_RCLK_BYP_SELECT (0x273)
89 #define BDK_MIO_FUS_FUSE_NUM_E_EAST_RCLK_BYP_SETTINGX(a) (0x267 + (a))
90 #define BDK_MIO_FUS_FUSE_NUM_E_EFUS_IGN (0x53)
91 #define BDK_MIO_FUS_FUSE_NUM_E_EFUS_LCK_DES (0x6a)
92 #define BDK_MIO_FUS_FUSE_NUM_E_EFUS_LCK_MAN (0x69)
93 #define BDK_MIO_FUS_FUSE_NUM_E_EFUS_LCK_PRD (0x68)
94 #define BDK_MIO_FUS_FUSE_NUM_E_EMA0X(a) (0x80 + (a))
95 #define BDK_MIO_FUS_FUSE_NUM_E_EMA1X(a) (0x8e + (a))
96 #define BDK_MIO_FUS_FUSE_NUM_E_GBL_PWR_THROTTLEX(a) (0xaf + (a))
97 #define BDK_MIO_FUS_FUSE_NUM_E_GLOBAL_RCLK_BYP_SELECT (0xa0)
98 #define BDK_MIO_FUS_FUSE_NUM_E_GLOBAL_RCLK_BYP_SETTINGX(a) (0x94 + (a))
99 #define BDK_MIO_FUS_FUSE_NUM_E_GLOBAL_SCLK_BYP_SELECT (0xe2)
100 #define BDK_MIO_FUS_FUSE_NUM_E_GLOBAL_SCLK_BYP_SETTINGX(a) (0xd6 + (a))
101 #define BDK_MIO_FUS_FUSE_NUM_E_GSERX(a) (0x400 + (a))
102 #define BDK_MIO_FUS_FUSE_NUM_E_L2C_CRIPX(a) (0x57 + (a))
103 #define BDK_MIO_FUS_FUSE_NUM_E_LMC_DIS (0x76)
104 #define BDK_MIO_FUS_FUSE_NUM_E_LMC_HALF (0x4b)
105 #define BDK_MIO_FUS_FUSE_NUM_E_MFG0X(a) (0x280 + (a))
106 #define BDK_MIO_FUS_FUSE_NUM_E_MFG1X(a) (0x2c0 + (a))
107 #define BDK_MIO_FUS_FUSE_NUM_E_MFG2X(a) (0x600 + (a))
108 #define BDK_MIO_FUS_FUSE_NUM_E_NOCRYPTO (0x50)
109 #define BDK_MIO_FUS_FUSE_NUM_E_NODFA_CP2 (0x5a)
110 #define BDK_MIO_FUS_FUSE_NUM_E_NOMUL (0x51)
111 #define BDK_MIO_FUS_FUSE_NUM_E_NOZIP (0x52)
112 #define BDK_MIO_FUS_FUSE_NUM_E_OCX_DIS (0x6b)
113 #define BDK_MIO_FUS_FUSE_NUM_E_PCI_NITROX (0xe7)
114 #define BDK_MIO_FUS_FUSE_NUM_E_PDFX(a) (0x340 + (a))
115 #define BDK_MIO_FUS_FUSE_NUM_E_PEM_DISX(a) (0x72 + (a))
116 #define BDK_MIO_FUS_FUSE_NUM_E_PLL_ALT_MATRIX (0x4a)
117 #define BDK_MIO_FUS_FUSE_NUM_E_PLL_BWADJ_DENOMX(a) (0x48 + (a))
118 #define BDK_MIO_FUS_FUSE_NUM_E_PLL_HALF_DIS (0x75)
119 #define BDK_MIO_FUS_FUSE_NUM_E_PNAMEX(a) (0x580 + (a))
120 #define BDK_MIO_FUS_FUSE_NUM_E_PNR_PLL_MULX(a) (0x77 + (a))
121 #define BDK_MIO_FUS_FUSE_NUM_E_POWER_LIMITX(a) (0x64 + (a))
122 #define BDK_MIO_FUS_FUSE_NUM_E_PP_AVAILABLEX(a) (0 + (a))
123 #define BDK_MIO_FUS_FUSE_NUM_E_PP_RCLK_BYP_SELECT (0x259)
124 #define BDK_MIO_FUS_FUSE_NUM_E_PP_RCLK_BYP_SETTINGX(a) (0x24d + (a))
125 #define BDK_MIO_FUS_FUSE_NUM_E_RAID_DIS (0x66)
126 #define BDK_MIO_FUS_FUSE_NUM_E_REDUNDANTX(a) (0x780 + (a))
127 #define BDK_MIO_FUS_FUSE_NUM_E_REFCLK_CHECK_CN81XX (0xc0)
128 #define BDK_MIO_FUS_FUSE_NUM_E_REFCLK_CHECK_CN88XX (0xc2)
129 #define BDK_MIO_FUS_FUSE_NUM_E_REFCLK_CHECK_CN83XX (0xc0)
130 #define BDK_MIO_FUS_FUSE_NUM_E_REPAIRX(a) (0x800 + (a))
131 #define BDK_MIO_FUS_FUSE_NUM_E_ROC_RCLK_BYP_SELECT (0xae)
132 #define BDK_MIO_FUS_FUSE_NUM_E_ROC_RCLK_BYP_SETTINGX(a) (0xa2 + (a))
133 #define BDK_MIO_FUS_FUSE_NUM_E_ROC_SCLK_BYP_SELECT (0xd5)
134 #define BDK_MIO_FUS_FUSE_NUM_E_ROC_SCLK_BYP_SETTINGX(a) (0xc9 + (a))
135 #define BDK_MIO_FUS_FUSE_NUM_E_ROM_INFOX(a) (0x276 + (a))
136 #define BDK_MIO_FUS_FUSE_NUM_E_RSVDX(a) (0xc6 + (a))
137 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD134X(a) (0x86 + (a))
138 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD1600X(a) (0x640 + (a))
139 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD1737X(a) (0x6c9 + (a))
140 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD1764X(a) (0x6e4 + (a))
141 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD183X(a) (0xb7 + (a))
142 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD189X(a) (0xbd + (a))
143 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD193X(a) (0xc1 + (a))
144 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD228X(a) (0xe4 + (a))
145 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD231X(a) (0xe7 + (a))
146 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD232X(a) (0xe8 + (a))
147 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD3056X(a) (0xbf0 + (a))
148 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD570X(a) (0x23a + (a))
149 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD628X(a) (0x274 + (a))
150 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD76X(a) (0x4c + (a))
151 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD91X(a) (0x5b + (a))
152 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD94X(a) (0x5e + (a))
153 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD98 (0x62)
154 #define BDK_MIO_FUS_FUSE_NUM_E_RSVD99 (0x63)
155 #define BDK_MIO_FUS_FUSE_NUM_E_RUN_PLATFORMX(a) (0xc3 + (a))
156 #define BDK_MIO_FUS_FUSE_NUM_E_SATA_DISX(a) (0x6e + (a))
157 #define BDK_MIO_FUS_FUSE_NUM_E_SERIALX(a) (0x380 + (a))
158 #define BDK_MIO_FUS_FUSE_NUM_E_TAD_RCLK_BYP_SELECT (0x24c)
159 #define BDK_MIO_FUS_FUSE_NUM_E_TAD_RCLK_BYP_SETTINGX(a) (0x240 + (a))
160 #define BDK_MIO_FUS_FUSE_NUM_E_TGGX(a) (0x300 + (a))
161 #define BDK_MIO_FUS_FUSE_NUM_E_TIM_DIS (0xe3)
162 #define BDK_MIO_FUS_FUSE_NUM_E_TNS_CRIPPLE (0xa1)
163 #define BDK_MIO_FUS_FUSE_NUM_E_TSENSE0X(a) (0x100 + (a))
164 #define BDK_MIO_FUS_FUSE_NUM_E_TSENSE1X(a) (0x680 + (a))
165 #define BDK_MIO_FUS_FUSE_NUM_E_TZ_MODE (0x4f)
166 #define BDK_MIO_FUS_FUSE_NUM_E_USE_INT_REFCLK (0x4e)
167 #define BDK_MIO_FUS_FUSE_NUM_E_VRMX(a) (0x200 + (a))
168 #define BDK_MIO_FUS_FUSE_NUM_E_ZIP_INFOX(a) (0x55 + (a))
169
170 /**
171 * Register (RSL) mio_fus_bnk_dat#
172 *
173 * MIO Fuse Bank Store Register
174 * The initial state of MIO_FUS_BNK_DAT(0..1) is as if bank6 were just read,
175 * i.e. DAT* = fus[895:768].
176 */
177 union bdk_mio_fus_bnk_datx
178 {
179 uint64_t u;
180 struct bdk_mio_fus_bnk_datx_s
181 {
182 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
183 uint64_t dat : 64; /**< [ 63: 0](R/W/H) Efuse bank store. For read operations, the DAT gets the fus bank last read. For write
184 operations, the DAT determines which fuses to blow. */
185 #else /* Word 0 - Little Endian */
186 uint64_t dat : 64; /**< [ 63: 0](R/W/H) Efuse bank store. For read operations, the DAT gets the fus bank last read. For write
187 operations, the DAT determines which fuses to blow. */
188 #endif /* Word 0 - End */
189 } s;
190 /* struct bdk_mio_fus_bnk_datx_s cn; */
191 };
192 typedef union bdk_mio_fus_bnk_datx bdk_mio_fus_bnk_datx_t;
193
194 static inline uint64_t BDK_MIO_FUS_BNK_DATX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_BNK_DATX(unsigned long a)195 static inline uint64_t BDK_MIO_FUS_BNK_DATX(unsigned long a)
196 {
197 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=1))
198 return 0x87e003001520ll + 8ll * ((a) & 0x1);
199 __bdk_csr_fatal("MIO_FUS_BNK_DATX", 1, a, 0, 0, 0);
200 }
201
202 #define typedef_BDK_MIO_FUS_BNK_DATX(a) bdk_mio_fus_bnk_datx_t
203 #define bustype_BDK_MIO_FUS_BNK_DATX(a) BDK_CSR_TYPE_RSL
204 #define basename_BDK_MIO_FUS_BNK_DATX(a) "MIO_FUS_BNK_DATX"
205 #define device_bar_BDK_MIO_FUS_BNK_DATX(a) 0x0 /* PF_BAR0 */
206 #define busnum_BDK_MIO_FUS_BNK_DATX(a) (a)
207 #define arguments_BDK_MIO_FUS_BNK_DATX(a) (a),-1,-1,-1
208
209 /**
210 * Register (RSL) mio_fus_dat0
211 *
212 * MIO Fuse Data Register 0
213 */
214 union bdk_mio_fus_dat0
215 {
216 uint64_t u;
217 struct bdk_mio_fus_dat0_s
218 {
219 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
220 uint64_t reserved_32_63 : 32;
221 uint64_t man_info : 32; /**< [ 31: 0](RO) Fuse information - manufacturing info [31:0]. */
222 #else /* Word 0 - Little Endian */
223 uint64_t man_info : 32; /**< [ 31: 0](RO) Fuse information - manufacturing info [31:0]. */
224 uint64_t reserved_32_63 : 32;
225 #endif /* Word 0 - End */
226 } s;
227 /* struct bdk_mio_fus_dat0_s cn; */
228 };
229 typedef union bdk_mio_fus_dat0 bdk_mio_fus_dat0_t;
230
231 #define BDK_MIO_FUS_DAT0 BDK_MIO_FUS_DAT0_FUNC()
232 static inline uint64_t BDK_MIO_FUS_DAT0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_DAT0_FUNC(void)233 static inline uint64_t BDK_MIO_FUS_DAT0_FUNC(void)
234 {
235 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
236 return 0x87e003001400ll;
237 __bdk_csr_fatal("MIO_FUS_DAT0", 0, 0, 0, 0, 0);
238 }
239
240 #define typedef_BDK_MIO_FUS_DAT0 bdk_mio_fus_dat0_t
241 #define bustype_BDK_MIO_FUS_DAT0 BDK_CSR_TYPE_RSL
242 #define basename_BDK_MIO_FUS_DAT0 "MIO_FUS_DAT0"
243 #define device_bar_BDK_MIO_FUS_DAT0 0x0 /* PF_BAR0 */
244 #define busnum_BDK_MIO_FUS_DAT0 0
245 #define arguments_BDK_MIO_FUS_DAT0 -1,-1,-1,-1
246
247 /**
248 * Register (RSL) mio_fus_dat1
249 *
250 * MIO Fuse Data Register 1
251 */
252 union bdk_mio_fus_dat1
253 {
254 uint64_t u;
255 struct bdk_mio_fus_dat1_s
256 {
257 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
258 uint64_t reserved_32_63 : 32;
259 uint64_t man_info : 32; /**< [ 31: 0](RO) Fuse information - manufacturing info [63:32]. */
260 #else /* Word 0 - Little Endian */
261 uint64_t man_info : 32; /**< [ 31: 0](RO) Fuse information - manufacturing info [63:32]. */
262 uint64_t reserved_32_63 : 32;
263 #endif /* Word 0 - End */
264 } s;
265 /* struct bdk_mio_fus_dat1_s cn; */
266 };
267 typedef union bdk_mio_fus_dat1 bdk_mio_fus_dat1_t;
268
269 #define BDK_MIO_FUS_DAT1 BDK_MIO_FUS_DAT1_FUNC()
270 static inline uint64_t BDK_MIO_FUS_DAT1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_DAT1_FUNC(void)271 static inline uint64_t BDK_MIO_FUS_DAT1_FUNC(void)
272 {
273 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
274 return 0x87e003001408ll;
275 __bdk_csr_fatal("MIO_FUS_DAT1", 0, 0, 0, 0, 0);
276 }
277
278 #define typedef_BDK_MIO_FUS_DAT1 bdk_mio_fus_dat1_t
279 #define bustype_BDK_MIO_FUS_DAT1 BDK_CSR_TYPE_RSL
280 #define basename_BDK_MIO_FUS_DAT1 "MIO_FUS_DAT1"
281 #define device_bar_BDK_MIO_FUS_DAT1 0x0 /* PF_BAR0 */
282 #define busnum_BDK_MIO_FUS_DAT1 0
283 #define arguments_BDK_MIO_FUS_DAT1 -1,-1,-1,-1
284
285 /**
286 * Register (RSL) mio_fus_dat2
287 *
288 * MIO Fuse Data Register 2
289 */
290 union bdk_mio_fus_dat2
291 {
292 uint64_t u;
293 struct bdk_mio_fus_dat2_s
294 {
295 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
296 uint64_t reserved_59_63 : 5;
297 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
298 Provides software a means of determining the platform at run time.
299 0x0 = Hardware.
300 0x1 = Emulator.
301 0x2 = RTL simulator.
302 0x3 = ASIM.
303 0x4-0x7 = reserved. */
304 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Controls global power throttling. MSB is a spare, and lower 7 bits indicate
305 N/128 power reduction. Small values have less throttling and higher
306 performance. 0x0 disables throttling. */
307 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
308 Internal:
309 fuse[99]. Fuse information - Ignore trusted-mode disable. */
310 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
311 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
312 Internal:
313 Fuse information - Power limit. */
314 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
315 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
316 Internal:
317 Tied to 0. */
318 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
319 uint64_t reserved_31 : 1;
320 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts.
321 Internal:
322 30 = fuse[75]. */
323 uint64_t reserved_29 : 1;
324 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
325 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
326 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
327
328 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
329
330 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
331 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
332 indicating this behavior.
333
334 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
335 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
336 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
337
338 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
339 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
340 uint64_t reserved_24 : 1;
341 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
342 \<23:22\> = Alternate package.
343 0x0 = CN81xx-xxxx-BG676.
344 0x1 = CN80xx-xxxx-BG555.
345 0x2 = CN80xx-xxxx-BG676.
346 0x3 = Reserved.
347
348 \<21:19\> = Major revision.
349
350 \<18:16\> = Minor revision.
351
352 For example:
353 \<pre\>
354 \<21:19\> \<18:16\> Description
355 ------- ------- -----------
356 0x0 0x0 Pass 1.0.
357 0x0 0x1 Pass 1.1.
358 0x0 0x2 Pass 1.2.
359 0x1 0x0 Pass 2.0.
360 0x1 0x1 Pass 2.1.
361 0x1 0x2 Pass 2.2.
362 ... ... ...
363 0x7 0x7 Pass 8.8.
364 \</pre\> */
365 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
366 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
367 \<13\> = BGX0 disable.
368 \<14\> = BGX1 disable. */
369 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
370 \<9\> = SATA0-3 disable.
371 \<10\> = SATA4-7 disable.
372 \<11\> = SATA8-11 disable.
373 \<12\> = SATA12-15 disable. */
374 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
375 \<6\> = PEM0-1 disable.
376 \<7\> = PEM2-3 disable
377 \<8\> = PEM4-5 disable. */
378 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
379 uint64_t tim_dis : 1; /**< [ 4: 4](RO) Fuse information TIM disable. */
380 uint64_t bgx3_dis : 1; /**< [ 3: 3](RO) Fuse information BGX3 disable. */
381 uint64_t bgx2_dis : 1; /**< [ 2: 2](RO) Fuse information BGX2 disable. */
382 uint64_t ddf_dis : 1; /**< [ 1: 1](RO) Fuse information DDF disable. */
383 uint64_t reserved_0 : 1;
384 #else /* Word 0 - Little Endian */
385 uint64_t reserved_0 : 1;
386 uint64_t ddf_dis : 1; /**< [ 1: 1](RO) Fuse information DDF disable. */
387 uint64_t bgx2_dis : 1; /**< [ 2: 2](RO) Fuse information BGX2 disable. */
388 uint64_t bgx3_dis : 1; /**< [ 3: 3](RO) Fuse information BGX3 disable. */
389 uint64_t tim_dis : 1; /**< [ 4: 4](RO) Fuse information TIM disable. */
390 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
391 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
392 \<6\> = PEM0-1 disable.
393 \<7\> = PEM2-3 disable
394 \<8\> = PEM4-5 disable. */
395 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
396 \<9\> = SATA0-3 disable.
397 \<10\> = SATA4-7 disable.
398 \<11\> = SATA8-11 disable.
399 \<12\> = SATA12-15 disable. */
400 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
401 \<13\> = BGX0 disable.
402 \<14\> = BGX1 disable. */
403 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
404 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
405 \<23:22\> = Alternate package.
406 0x0 = CN81xx-xxxx-BG676.
407 0x1 = CN80xx-xxxx-BG555.
408 0x2 = CN80xx-xxxx-BG676.
409 0x3 = Reserved.
410
411 \<21:19\> = Major revision.
412
413 \<18:16\> = Minor revision.
414
415 For example:
416 \<pre\>
417 \<21:19\> \<18:16\> Description
418 ------- ------- -----------
419 0x0 0x0 Pass 1.0.
420 0x0 0x1 Pass 1.1.
421 0x0 0x2 Pass 1.2.
422 0x1 0x0 Pass 2.0.
423 0x1 0x1 Pass 2.1.
424 0x1 0x2 Pass 2.2.
425 ... ... ...
426 0x7 0x7 Pass 8.8.
427 \</pre\> */
428 uint64_t reserved_24 : 1;
429 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
430 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
431
432 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
433
434 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
435 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
436 indicating this behavior.
437
438 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
439 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
440 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
441
442 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
443 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
444 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
445 uint64_t reserved_29 : 1;
446 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts.
447 Internal:
448 30 = fuse[75]. */
449 uint64_t reserved_31 : 1;
450 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
451 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
452 Internal:
453 Tied to 0. */
454 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
455 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
456 Internal:
457 Fuse information - Power limit. */
458 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
459 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
460 Internal:
461 fuse[99]. Fuse information - Ignore trusted-mode disable. */
462 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Controls global power throttling. MSB is a spare, and lower 7 bits indicate
463 N/128 power reduction. Small values have less throttling and higher
464 performance. 0x0 disables throttling. */
465 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
466 Provides software a means of determining the platform at run time.
467 0x0 = Hardware.
468 0x1 = Emulator.
469 0x2 = RTL simulator.
470 0x3 = ASIM.
471 0x4-0x7 = reserved. */
472 uint64_t reserved_59_63 : 5;
473 #endif /* Word 0 - End */
474 } s;
475 struct bdk_mio_fus_dat2_cn88xxp1
476 {
477 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
478 uint64_t reserved_59_63 : 5;
479 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
480 Provides software a means of determining the platform at run time.
481 0x0 = Hardware.
482 0x1 = Emulator.
483 0x2 = RTL simulator.
484 0x3 = ASIM.
485 0x4-0x7 = reserved. */
486 uint64_t reserved_48_55 : 8;
487 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
488 Internal:
489 fuse[99]. Fuse information - Ignore trusted-mode disable. */
490 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
491 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
492 Internal:
493 Fuse information - Power limit. */
494 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
495 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
496 Internal:
497 Tied to 0. */
498 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
499 uint64_t reserved_29_31 : 3;
500 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
501 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
502 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
503
504 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
505
506 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
507 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
508 indicating this behavior.
509
510 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
511 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
512 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
513
514 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
515 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
516 uint64_t reserved_24 : 1;
517 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
518 \<23:22\> = Alternate package.
519 \<21:19\> = Major revision.
520 \<18:16\> = Minor revision.
521
522 For example:
523 \<pre\>
524 \<21:19\> \<18:16\> Description
525 ------- ------- -----------
526 0x0 0x0 Pass 1.0.
527 0x0 0x1 Pass 1.1.
528 0x0 0x2 Pass 1.2.
529 0x1 0x0 Pass 2.0.
530 0x1 0x1 Pass 2.1.
531 0x1 0x2 Pass 2.2.
532 ... ... ...
533 0x7 0x7 Pass 8.8.
534 \</pre\> */
535 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
536 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
537 \<13\> = BGX0 disable.
538 \<14\> = BGX1 disable. */
539 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
540 \<9\> = SATA0-3 disable.
541 \<10\> = SATA4-7 disable.
542 \<11\> = SATA8-11 disable.
543 \<12\> = SATA12-15 disable. */
544 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
545 \<6\> = PEM0-1 disable.
546 \<7\> = PEM2-3 disable
547 \<8\> = PEM4-5 disable. */
548 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
549 uint64_t reserved_0_4 : 5;
550 #else /* Word 0 - Little Endian */
551 uint64_t reserved_0_4 : 5;
552 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
553 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
554 \<6\> = PEM0-1 disable.
555 \<7\> = PEM2-3 disable
556 \<8\> = PEM4-5 disable. */
557 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
558 \<9\> = SATA0-3 disable.
559 \<10\> = SATA4-7 disable.
560 \<11\> = SATA8-11 disable.
561 \<12\> = SATA12-15 disable. */
562 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
563 \<13\> = BGX0 disable.
564 \<14\> = BGX1 disable. */
565 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
566 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
567 \<23:22\> = Alternate package.
568 \<21:19\> = Major revision.
569 \<18:16\> = Minor revision.
570
571 For example:
572 \<pre\>
573 \<21:19\> \<18:16\> Description
574 ------- ------- -----------
575 0x0 0x0 Pass 1.0.
576 0x0 0x1 Pass 1.1.
577 0x0 0x2 Pass 1.2.
578 0x1 0x0 Pass 2.0.
579 0x1 0x1 Pass 2.1.
580 0x1 0x2 Pass 2.2.
581 ... ... ...
582 0x7 0x7 Pass 8.8.
583 \</pre\> */
584 uint64_t reserved_24 : 1;
585 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
586 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
587
588 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
589
590 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
591 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
592 indicating this behavior.
593
594 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
595 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
596 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
597
598 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
599 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
600 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
601 uint64_t reserved_29_31 : 3;
602 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
603 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
604 Internal:
605 Tied to 0. */
606 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
607 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
608 Internal:
609 Fuse information - Power limit. */
610 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
611 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
612 Internal:
613 fuse[99]. Fuse information - Ignore trusted-mode disable. */
614 uint64_t reserved_48_55 : 8;
615 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
616 Provides software a means of determining the platform at run time.
617 0x0 = Hardware.
618 0x1 = Emulator.
619 0x2 = RTL simulator.
620 0x3 = ASIM.
621 0x4-0x7 = reserved. */
622 uint64_t reserved_59_63 : 5;
623 #endif /* Word 0 - End */
624 } cn88xxp1;
625 struct bdk_mio_fus_dat2_cn81xx
626 {
627 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
628 uint64_t reserved_59_63 : 5;
629 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
630 Provides software a means of determining the platform at run time.
631 0x0 = Hardware.
632 0x1 = Emulator.
633 0x2 = RTL simulator.
634 0x3 = ASIM.
635 0x4-0x7 = reserved. */
636 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Reserved.
637 Internal:
638 Controls global power throttling. MSB is a spare, and lower 7 bits indicate
639 N/128 power reduction. Small values have less throttling and higher
640 performance. 0x0 disables throttling. */
641 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
642 Internal:
643 fuse[99]. Fuse information - Ignore trusted-mode disable. */
644 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
645 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
646 Internal:
647 Fuse information - Power limit. */
648 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
649 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
650 Internal:
651 Tied to 0. */
652 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
653 uint64_t reserved_31 : 1;
654 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts. In CN80XX always set.
655 Internal:
656 30 = fuse[75]. */
657 uint64_t reserved_29 : 1;
658 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
659 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
660 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
661
662 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
663
664 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
665 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
666 indicating this behavior.
667
668 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
669 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
670 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
671
672 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
673 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
674 uint64_t reserved_24 : 1;
675 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
676 \<23:22\> = Alternate package.
677 0x0 = CN81xx-xxxx-BG676.
678 0x1 = CN80xx-xxxx-BG555.
679 0x2 = CN80xx-xxxx-BG676.
680 0x3 = Reserved.
681
682 \<21:19\> = Major revision.
683
684 \<18:16\> = Minor revision.
685
686 For example:
687 \<pre\>
688 \<21:19\> \<18:16\> Description
689 ------- ------- -----------
690 0x0 0x0 Pass 1.0.
691 0x0 0x1 Pass 1.1.
692 0x0 0x2 Pass 1.2.
693 0x1 0x0 Pass 2.0.
694 0x1 0x1 Pass 2.1.
695 0x1 0x2 Pass 2.2.
696 ... ... ...
697 0x7 0x7 Pass 8.8.
698 \</pre\> */
699 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Reserved. */
700 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
701 \<13\> = BGX0 disable.
702 \<14\> = BGX1 disable. */
703 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
704 \<9\> = SATA0 disable.
705 \<10\> = SATA1 disable.
706 \<11\> = Reserved.
707 \<12\> = Reserved. */
708 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
709 \<6\> = PEM0 disable.
710 \<7\> = PEM1 disable
711 \<8\> = PEM2 disable. */
712 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC1 disabled. LMC1 not present in CN80XX/CN81XX, so clear. */
713 uint64_t reserved_0_4 : 5;
714 #else /* Word 0 - Little Endian */
715 uint64_t reserved_0_4 : 5;
716 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC1 disabled. LMC1 not present in CN80XX/CN81XX, so clear. */
717 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
718 \<6\> = PEM0 disable.
719 \<7\> = PEM1 disable
720 \<8\> = PEM2 disable. */
721 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
722 \<9\> = SATA0 disable.
723 \<10\> = SATA1 disable.
724 \<11\> = Reserved.
725 \<12\> = Reserved. */
726 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
727 \<13\> = BGX0 disable.
728 \<14\> = BGX1 disable. */
729 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Reserved. */
730 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
731 \<23:22\> = Alternate package.
732 0x0 = CN81xx-xxxx-BG676.
733 0x1 = CN80xx-xxxx-BG555.
734 0x2 = CN80xx-xxxx-BG676.
735 0x3 = Reserved.
736
737 \<21:19\> = Major revision.
738
739 \<18:16\> = Minor revision.
740
741 For example:
742 \<pre\>
743 \<21:19\> \<18:16\> Description
744 ------- ------- -----------
745 0x0 0x0 Pass 1.0.
746 0x0 0x1 Pass 1.1.
747 0x0 0x2 Pass 1.2.
748 0x1 0x0 Pass 2.0.
749 0x1 0x1 Pass 2.1.
750 0x1 0x2 Pass 2.2.
751 ... ... ...
752 0x7 0x7 Pass 8.8.
753 \</pre\> */
754 uint64_t reserved_24 : 1;
755 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
756 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
757
758 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
759
760 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
761 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
762 indicating this behavior.
763
764 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
765 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
766 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
767
768 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
769 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
770 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
771 uint64_t reserved_29 : 1;
772 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts. In CN80XX always set.
773 Internal:
774 30 = fuse[75]. */
775 uint64_t reserved_31 : 1;
776 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
777 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
778 Internal:
779 Tied to 0. */
780 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
781 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
782 Internal:
783 Fuse information - Power limit. */
784 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
785 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
786 Internal:
787 fuse[99]. Fuse information - Ignore trusted-mode disable. */
788 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Reserved.
789 Internal:
790 Controls global power throttling. MSB is a spare, and lower 7 bits indicate
791 N/128 power reduction. Small values have less throttling and higher
792 performance. 0x0 disables throttling. */
793 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
794 Provides software a means of determining the platform at run time.
795 0x0 = Hardware.
796 0x1 = Emulator.
797 0x2 = RTL simulator.
798 0x3 = ASIM.
799 0x4-0x7 = reserved. */
800 uint64_t reserved_59_63 : 5;
801 #endif /* Word 0 - End */
802 } cn81xx;
803 struct bdk_mio_fus_dat2_cn83xx
804 {
805 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
806 uint64_t reserved_59_63 : 5;
807 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
808 Provides software a means of determining the platform at run time.
809 0x0 = Hardware.
810 0x1 = Emulator.
811 0x2 = RTL simulator.
812 0x3 = ASIM.
813 0x4-0x7 = reserved. */
814 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Reserved.
815 Internal:
816 Controls global power throttling. MSB is a spare, and lower 7 bits indicate
817 N/128 power reduction. Small values have less throttling and higher
818 performance. 0x0 disables throttling. */
819 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
820 Internal:
821 fuse[99]. Fuse information - Ignore trusted-mode disable. */
822 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
823 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
824 Internal:
825 Fuse information - Power limit. */
826 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
827 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
828 Internal:
829 Tied to 0. */
830 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
831 uint64_t reserved_31 : 1;
832 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts.
833 Internal:
834 30 = fuse[75]. */
835 uint64_t reserved_29 : 1;
836 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
837 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
838 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
839
840 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
841
842 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
843 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
844 indicating this behavior.
845
846 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
847 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
848 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
849
850 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
851 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
852 uint64_t reserved_24 : 1;
853 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
854 \<23:22\> = Alternate package.
855 \<21:19\> = Major revision.
856 \<18:16\> = Minor revision.
857
858 For example:
859 \<pre\>
860 \<21:19\> \<18:16\> Description
861 ------- ------- -----------
862 0x0 0x0 Pass 1.0.
863 0x0 0x1 Pass 1.1.
864 0x0 0x2 Pass 1.2.
865 0x1 0x0 Pass 2.0.
866 0x1 0x1 Pass 2.1.
867 0x1 0x2 Pass 2.2.
868 ... ... ...
869 0x7 0x7 Pass 8.8.
870 \</pre\> */
871 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Reserved. */
872 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
873 \<13\> = BGX0 disable.
874 \<14\> = BGX1 disable. */
875 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
876 \<9\> = SATA0-1 disable.
877 \<10\> = SATA2-3 disable.
878 \<11\> = SATA4-5 disable.
879 \<12\> = Reserved. */
880 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
881 \<6\> = PEM0-1 disable.
882 \<7\> = PEM2 disable
883 \<8\> = PEM3 disable. */
884 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC1 disabled. */
885 uint64_t tim_dis : 1; /**< [ 4: 4](RO) Fuse information TIM disable. */
886 uint64_t bgx3_dis : 1; /**< [ 3: 3](RO) Fuse information BGX3 disable. */
887 uint64_t bgx2_dis : 1; /**< [ 2: 2](RO) Fuse information BGX2 disable. */
888 uint64_t ddf_dis : 1; /**< [ 1: 1](RO) Fuse information DDF disable. */
889 uint64_t reserved_0 : 1;
890 #else /* Word 0 - Little Endian */
891 uint64_t reserved_0 : 1;
892 uint64_t ddf_dis : 1; /**< [ 1: 1](RO) Fuse information DDF disable. */
893 uint64_t bgx2_dis : 1; /**< [ 2: 2](RO) Fuse information BGX2 disable. */
894 uint64_t bgx3_dis : 1; /**< [ 3: 3](RO) Fuse information BGX3 disable. */
895 uint64_t tim_dis : 1; /**< [ 4: 4](RO) Fuse information TIM disable. */
896 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC1 disabled. */
897 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
898 \<6\> = PEM0-1 disable.
899 \<7\> = PEM2 disable
900 \<8\> = PEM3 disable. */
901 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
902 \<9\> = SATA0-1 disable.
903 \<10\> = SATA2-3 disable.
904 \<11\> = SATA4-5 disable.
905 \<12\> = Reserved. */
906 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
907 \<13\> = BGX0 disable.
908 \<14\> = BGX1 disable. */
909 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Reserved. */
910 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
911 \<23:22\> = Alternate package.
912 \<21:19\> = Major revision.
913 \<18:16\> = Minor revision.
914
915 For example:
916 \<pre\>
917 \<21:19\> \<18:16\> Description
918 ------- ------- -----------
919 0x0 0x0 Pass 1.0.
920 0x0 0x1 Pass 1.1.
921 0x0 0x2 Pass 1.2.
922 0x1 0x0 Pass 2.0.
923 0x1 0x1 Pass 2.1.
924 0x1 0x2 Pass 2.2.
925 ... ... ...
926 0x7 0x7 Pass 8.8.
927 \</pre\> */
928 uint64_t reserved_24 : 1;
929 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
930 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
931
932 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
933
934 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
935 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
936 indicating this behavior.
937
938 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
939 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
940 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
941
942 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
943 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
944 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
945 uint64_t reserved_29 : 1;
946 uint64_t lmc_mode32 : 1; /**< [ 30: 30](RO) DRAM controller is limited to 32/36 bit wide parts.
947 Internal:
948 30 = fuse[75]. */
949 uint64_t reserved_31 : 1;
950 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
951 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
952 Internal:
953 Tied to 0. */
954 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
955 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
956 Internal:
957 Fuse information - Power limit. */
958 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
959 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
960 Internal:
961 fuse[99]. Fuse information - Ignore trusted-mode disable. */
962 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Reserved.
963 Internal:
964 Controls global power throttling. MSB is a spare, and lower 7 bits indicate
965 N/128 power reduction. Small values have less throttling and higher
966 performance. 0x0 disables throttling. */
967 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
968 Provides software a means of determining the platform at run time.
969 0x0 = Hardware.
970 0x1 = Emulator.
971 0x2 = RTL simulator.
972 0x3 = ASIM.
973 0x4-0x7 = reserved. */
974 uint64_t reserved_59_63 : 5;
975 #endif /* Word 0 - End */
976 } cn83xx;
977 struct bdk_mio_fus_dat2_cn88xxp2
978 {
979 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
980 uint64_t reserved_59_63 : 5;
981 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
982 Provides software a means of determining the platform at run time.
983 0x0 = Hardware.
984 0x1 = Emulator.
985 0x2 = RTL simulator.
986 0x3 = ASIM.
987 0x4-0x7 = reserved. */
988 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Controls global power throttling. MSB is a spare, and lower 7 bits indicate
989 N/128 power reduction. Small values have less throttling and higher
990 performance. 0x0 disables throttling. */
991 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
992 Internal:
993 fuse[99]. Fuse information - Ignore trusted-mode disable. */
994 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
995 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
996 Internal:
997 Fuse information - Power limit. */
998 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
999 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
1000 Internal:
1001 Tied to 0. */
1002 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
1003 uint64_t reserved_29_31 : 3;
1004 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
1005 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
1006 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
1007
1008 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
1009
1010 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
1011 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
1012 indicating this behavior.
1013
1014 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
1015 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
1016 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
1017
1018 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
1019 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
1020 uint64_t reserved_24 : 1;
1021 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
1022 \<23:22\> = Alternate package.
1023 \<21:19\> = Major revision.
1024 \<18:16\> = Minor revision.
1025
1026 For example:
1027 \<pre\>
1028 \<21:19\> \<18:16\> Description
1029 ------- ------- -----------
1030 0x0 0x0 Pass 1.0.
1031 0x0 0x1 Pass 1.1.
1032 0x0 0x2 Pass 1.2.
1033 0x1 0x0 Pass 2.0.
1034 0x1 0x1 Pass 2.1.
1035 0x1 0x2 Pass 2.2.
1036 ... ... ...
1037 0x7 0x7 Pass 8.8.
1038 \</pre\> */
1039 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
1040 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
1041 \<13\> = BGX0 disable.
1042 \<14\> = BGX1 disable. */
1043 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
1044 \<9\> = SATA0-3 disable.
1045 \<10\> = SATA4-7 disable.
1046 \<11\> = SATA8-11 disable.
1047 \<12\> = SATA12-15 disable. */
1048 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
1049 \<6\> = PEM0-1 disable.
1050 \<7\> = PEM2-3 disable
1051 \<8\> = PEM4-5 disable. */
1052 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
1053 uint64_t reserved_0_4 : 5;
1054 #else /* Word 0 - Little Endian */
1055 uint64_t reserved_0_4 : 5;
1056 uint64_t lmc_half : 1; /**< [ 5: 5](RO) Fuse information - LMC uses two channels rather than four. */
1057 uint64_t pem_dis : 3; /**< [ 8: 6](RO) Fuse information - PEM disable:
1058 \<6\> = PEM0-1 disable.
1059 \<7\> = PEM2-3 disable
1060 \<8\> = PEM4-5 disable. */
1061 uint64_t sata_dis : 4; /**< [ 12: 9](RO) Fuse information - SATA disable:
1062 \<9\> = SATA0-3 disable.
1063 \<10\> = SATA4-7 disable.
1064 \<11\> = SATA8-11 disable.
1065 \<12\> = SATA12-15 disable. */
1066 uint64_t bgx_dis : 2; /**< [ 14: 13](RO) Fuse information - BGX disable:
1067 \<13\> = BGX0 disable.
1068 \<14\> = BGX1 disable. */
1069 uint64_t ocx_dis : 1; /**< [ 15: 15](RO) Fuse information - OCX disable. */
1070 uint64_t chip_id : 8; /**< [ 23: 16](RO) Chip revision identifier.
1071 \<23:22\> = Alternate package.
1072 \<21:19\> = Major revision.
1073 \<18:16\> = Minor revision.
1074
1075 For example:
1076 \<pre\>
1077 \<21:19\> \<18:16\> Description
1078 ------- ------- -----------
1079 0x0 0x0 Pass 1.0.
1080 0x0 0x1 Pass 1.1.
1081 0x0 0x2 Pass 1.2.
1082 0x1 0x0 Pass 2.0.
1083 0x1 0x1 Pass 2.1.
1084 0x1 0x2 Pass 2.2.
1085 ... ... ...
1086 0x7 0x7 Pass 8.8.
1087 \</pre\> */
1088 uint64_t reserved_24 : 1;
1089 uint64_t trustzone_en : 1; /**< [ 25: 25](RO) Fuse information - TrustZone enable. */
1090 uint64_t nocrypto : 1; /**< [ 26: 26](RO) Fuse information - [DORM_CRYPTO] and [NOCRYPTO] together select the crypto mode:
1091
1092 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 0: AES/SHA/PMULL enabled.
1093
1094 _ [DORM_CRYPTO] = 0, [NOCRYPTO] = 1: The AES, SHA, and PMULL 1D/2D instructions will
1095 cause undefined exceptions, and AP_ID_AA64ISAR0_EL1[AES, SHA1, SHA2] are zero
1096 indicating this behavior.
1097
1098 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 0: Dormant encryption enable. AES/SHA/PMULL are
1099 disabled (as if [NOCRYPTO] = 1) until the appropriate key is written to
1100 RNM_EER_KEY, then they are enabled (as if [NOCRYPTO] = 1).
1101
1102 _ [DORM_CRYPTO] = 1, [NOCRYPTO] = 1: Reserved. */
1103 uint64_t nomul : 1; /**< [ 27: 27](RO) Fuse information - VMUL disable. */
1104 uint64_t nodfa_cp2 : 1; /**< [ 28: 28](RO) Fuse information - HFA disable (CP2). */
1105 uint64_t reserved_29_31 : 3;
1106 uint64_t raid_en : 1; /**< [ 32: 32](RO) Fuse information - RAID enabled. */
1107 uint64_t fus318 : 1; /**< [ 33: 33](RO) Reserved.
1108 Internal:
1109 Tied to 0. */
1110 uint64_t dorm_crypto : 1; /**< [ 34: 34](RO) Fuse information - Dormant encryption enable. See NOCRYPTO. */
1111 uint64_t power_limit : 2; /**< [ 36: 35](RO) Reserved.
1112 Internal:
1113 Fuse information - Power limit. */
1114 uint64_t rom_info : 10; /**< [ 46: 37](RO) Fuse information - ROM info. */
1115 uint64_t fus118 : 1; /**< [ 47: 47](RO) Reserved.
1116 Internal:
1117 fuse[99]. Fuse information - Ignore trusted-mode disable. */
1118 uint64_t gbl_pwr_throttle : 8; /**< [ 55: 48](RO) Controls global power throttling. MSB is a spare, and lower 7 bits indicate
1119 N/128 power reduction. Small values have less throttling and higher
1120 performance. 0x0 disables throttling. */
1121 uint64_t run_platform : 3; /**< [ 58: 56](RO) Fuses to indicate the run platform. Not to be blown in actual hardware.
1122 Provides software a means of determining the platform at run time.
1123 0x0 = Hardware.
1124 0x1 = Emulator.
1125 0x2 = RTL simulator.
1126 0x3 = ASIM.
1127 0x4-0x7 = reserved. */
1128 uint64_t reserved_59_63 : 5;
1129 #endif /* Word 0 - End */
1130 } cn88xxp2;
1131 };
1132 typedef union bdk_mio_fus_dat2 bdk_mio_fus_dat2_t;
1133
1134 #define BDK_MIO_FUS_DAT2 BDK_MIO_FUS_DAT2_FUNC()
1135 static inline uint64_t BDK_MIO_FUS_DAT2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_DAT2_FUNC(void)1136 static inline uint64_t BDK_MIO_FUS_DAT2_FUNC(void)
1137 {
1138 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1139 return 0x87e003001410ll;
1140 __bdk_csr_fatal("MIO_FUS_DAT2", 0, 0, 0, 0, 0);
1141 }
1142
1143 #define typedef_BDK_MIO_FUS_DAT2 bdk_mio_fus_dat2_t
1144 #define bustype_BDK_MIO_FUS_DAT2 BDK_CSR_TYPE_RSL
1145 #define basename_BDK_MIO_FUS_DAT2 "MIO_FUS_DAT2"
1146 #define device_bar_BDK_MIO_FUS_DAT2 0x0 /* PF_BAR0 */
1147 #define busnum_BDK_MIO_FUS_DAT2 0
1148 #define arguments_BDK_MIO_FUS_DAT2 -1,-1,-1,-1
1149
1150 /**
1151 * Register (RSL) mio_fus_dat3
1152 *
1153 * MIO Fuse Data3 Register
1154 */
1155 union bdk_mio_fus_dat3
1156 {
1157 uint64_t u;
1158 struct bdk_mio_fus_dat3_s
1159 {
1160 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1161 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1162 Internal:
1163 Default value is 0x11. Soft or hard blow of these fuses
1164 will XOR with this value. */
1165 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1166 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1167 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1168 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1169 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1170 0x0 = Selects CLKF/4.
1171 0x1 = Selects CLKF/2.
1172 0x2 = Selects CLKF/8. */
1173 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1174 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1175 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1176 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1177 0x0 = Full cache (16-way, 2 MB).
1178 0x1 = 3/4 ways (12-way, 1.5 MB).
1179 0x2 = 1/2 ways (8-way, 1 MB).
1180 0x3 = 1/4 ways (4-way, 512 KB).
1181 0x4-0x7 = Reserved. */
1182 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1183 to use the internal input reference clock. */
1184 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1185 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1186 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1187 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1188 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1189 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1190 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1191 Internal:
1192 Default value is 0x02. Soft or hard blow of these fuses
1193 will XOR with this value. */
1194 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1195 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1196 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1197 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) When set to 1, TNS switching functionality is permanently disabled. */
1198 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1199 value for PLL_MUL[5:1] straps. Any strap setting above this
1200 value will be ignored. A value of 0 indicates no hardware limit. */
1201 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1202 value for PNR_MUL[5:1] straps. Any strap setting above this
1203 value will be ignored. A value of 0 indicates no hardware limit. */
1204 #else /* Word 0 - Little Endian */
1205 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1206 value for PNR_MUL[5:1] straps. Any strap setting above this
1207 value will be ignored. A value of 0 indicates no hardware limit. */
1208 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1209 value for PLL_MUL[5:1] straps. Any strap setting above this
1210 value will be ignored. A value of 0 indicates no hardware limit. */
1211 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) When set to 1, TNS switching functionality is permanently disabled. */
1212 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1213 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1214 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1215 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1216 Internal:
1217 Default value is 0x02. Soft or hard blow of these fuses
1218 will XOR with this value. */
1219 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1220 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1221 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1222 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1223 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1224 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1225 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1226 to use the internal input reference clock. */
1227 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1228 0x0 = Full cache (16-way, 2 MB).
1229 0x1 = 3/4 ways (12-way, 1.5 MB).
1230 0x2 = 1/2 ways (8-way, 1 MB).
1231 0x3 = 1/4 ways (4-way, 512 KB).
1232 0x4-0x7 = Reserved. */
1233 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1234 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1235 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1236 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1237 0x0 = Selects CLKF/4.
1238 0x1 = Selects CLKF/2.
1239 0x2 = Selects CLKF/8. */
1240 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1241 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1242 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1243 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1244 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1245 Internal:
1246 Default value is 0x11. Soft or hard blow of these fuses
1247 will XOR with this value. */
1248 #endif /* Word 0 - End */
1249 } s;
1250 struct bdk_mio_fus_dat3_cn81xx
1251 {
1252 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1253 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1254 Internal:
1255 Default value is 0x11. Soft or hard blow of these fuses
1256 will XOR with this value. */
1257 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1258 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1259 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1260 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1261 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1262 0x0 = Selects CLKF/4.
1263 0x1 = Selects CLKF/2.
1264 0x2 = Selects CLKF/8. */
1265 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1266 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1267 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1268 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1269 0x0 = Full cache (16-way, 2 MB).
1270 0x1 = 3/4 ways (12-way, 1.5 MB).
1271 0x2 = 1/2 ways (8-way, 1 MB).
1272 0x3 = 1/4 ways (4-way, 512 KB).
1273 0x4-0x7 = Reserved. */
1274 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1275 to use the internal input reference clock. */
1276 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1277 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1278 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1279 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1280 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1281 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1282 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1283 Internal:
1284 Default value is 0x02. Soft or hard blow of these fuses
1285 will XOR with this value. */
1286 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1287 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1288 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1289 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) Reserved.
1290 Internal:
1291 When set to 1, TNS switching functionality is permanently disabled. */
1292 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1293 value for PLL_MUL[5:1] straps. Any strap setting above this
1294 value will be ignored. A value of 0 indicates no hardware limit. */
1295 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1296 value for PNR_MUL[5:1] straps. Any strap setting above this
1297 value will be ignored. A value of 0 indicates no hardware limit. */
1298 #else /* Word 0 - Little Endian */
1299 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1300 value for PNR_MUL[5:1] straps. Any strap setting above this
1301 value will be ignored. A value of 0 indicates no hardware limit. */
1302 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1303 value for PLL_MUL[5:1] straps. Any strap setting above this
1304 value will be ignored. A value of 0 indicates no hardware limit. */
1305 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) Reserved.
1306 Internal:
1307 When set to 1, TNS switching functionality is permanently disabled. */
1308 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1309 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1310 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1311 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1312 Internal:
1313 Default value is 0x02. Soft or hard blow of these fuses
1314 will XOR with this value. */
1315 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1316 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1317 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1318 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1319 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1320 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1321 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1322 to use the internal input reference clock. */
1323 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1324 0x0 = Full cache (16-way, 2 MB).
1325 0x1 = 3/4 ways (12-way, 1.5 MB).
1326 0x2 = 1/2 ways (8-way, 1 MB).
1327 0x3 = 1/4 ways (4-way, 512 KB).
1328 0x4-0x7 = Reserved. */
1329 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1330 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1331 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1332 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1333 0x0 = Selects CLKF/4.
1334 0x1 = Selects CLKF/2.
1335 0x2 = Selects CLKF/8. */
1336 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1337 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1338 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1339 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1340 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1341 Internal:
1342 Default value is 0x11. Soft or hard blow of these fuses
1343 will XOR with this value. */
1344 #endif /* Word 0 - End */
1345 } cn81xx;
1346 struct bdk_mio_fus_dat3_cn88xx
1347 {
1348 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1349 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1350 Internal:
1351 Default value is 0x11. Soft or hard blow of these fuses
1352 will XOR with this value. */
1353 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1354 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1355 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1356 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1357 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1358 0x0 = Selects CLKF/4.
1359 0x1 = Selects CLKF/2.
1360 0x2 = Selects CLKF/8. */
1361 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1362 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1363 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1364 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1365 0x0 = Full cache (16-way, 16 MB).
1366 0x1 = 3/4 ways (12-way, 12 MB).
1367 0x2 = 1/2 ways (8-way, 8 MB).
1368 0x3 = 1/4 ways (4-way, 4MB).
1369 0x4-0x7 = Reserved. */
1370 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1371 to use the internal input reference clock. */
1372 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1373 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1374 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1375 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1376 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1377 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1378 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1379 Internal:
1380 Default value is 0x02. Soft or hard blow of these fuses
1381 will XOR with this value. */
1382 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1383 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1384 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1385 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) When set to 1, TNS switching functionality is permanently disabled. */
1386 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1387 value for PLL_MUL[5:1] straps. Any strap setting above this
1388 value will be ignored. A value of 0 indicates no hardware limit. */
1389 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1390 value for PNR_MUL[5:1] straps. Any strap setting above this
1391 value will be ignored. A value of 0 indicates no hardware limit. */
1392 #else /* Word 0 - Little Endian */
1393 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1394 value for PNR_MUL[5:1] straps. Any strap setting above this
1395 value will be ignored. A value of 0 indicates no hardware limit. */
1396 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1397 value for PLL_MUL[5:1] straps. Any strap setting above this
1398 value will be ignored. A value of 0 indicates no hardware limit. */
1399 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) When set to 1, TNS switching functionality is permanently disabled. */
1400 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1401 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1402 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1403 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1404 Internal:
1405 Default value is 0x02. Soft or hard blow of these fuses
1406 will XOR with this value. */
1407 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1408 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1409 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1410 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1411 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1412 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1413 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1414 to use the internal input reference clock. */
1415 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1416 0x0 = Full cache (16-way, 16 MB).
1417 0x1 = 3/4 ways (12-way, 12 MB).
1418 0x2 = 1/2 ways (8-way, 8 MB).
1419 0x3 = 1/4 ways (4-way, 4MB).
1420 0x4-0x7 = Reserved. */
1421 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1422 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1423 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1424 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1425 0x0 = Selects CLKF/4.
1426 0x1 = Selects CLKF/2.
1427 0x2 = Selects CLKF/8. */
1428 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1429 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1430 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1431 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1432 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1433 Internal:
1434 Default value is 0x11. Soft or hard blow of these fuses
1435 will XOR with this value. */
1436 #endif /* Word 0 - End */
1437 } cn88xx;
1438 struct bdk_mio_fus_dat3_cn83xx
1439 {
1440 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1441 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1442 Internal:
1443 Default value is 0x11. Soft or hard blow of these fuses
1444 will XOR with this value. */
1445 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1446 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1447 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1448 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1449 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1450 0x0 = Selects CLKF/4.
1451 0x1 = Selects CLKF/2.
1452 0x2 = Selects CLKF/8. */
1453 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1454 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1455 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1456 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1457 0x0 = Full cache (16-way, 8 MB).
1458 0x1 = 3/4 ways (12-way, 6 MB).
1459 0x2 = 1/2 ways (8-way, 4 MB).
1460 0x3 = 1/4 ways (4-way, 2 MB).
1461 0x4-0x7 = Reserved. */
1462 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1463 to use the internal input reference clock. */
1464 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1465 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1466 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1467 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1468 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1469 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1470 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1471 Internal:
1472 Default value is 0x02. Soft or hard blow of these fuses
1473 will XOR with this value. */
1474 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1475 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1476 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1477 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) Reserved.
1478 Internal:
1479 When set to 1, TNS switching functionality is permanently disabled. */
1480 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1481 value for PLL_MUL[5:1] straps. Any strap setting above this
1482 value will be ignored. A value of 0 indicates no hardware limit. */
1483 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1484 value for PNR_MUL[5:1] straps. Any strap setting above this
1485 value will be ignored. A value of 0 indicates no hardware limit. */
1486 #else /* Word 0 - Little Endian */
1487 uint64_t pnr_pll_mul : 4; /**< [ 3: 0](RO) Coprocessor-clock PLL multiplier hardware limit. Indicates maximum
1488 value for PNR_MUL[5:1] straps. Any strap setting above this
1489 value will be ignored. A value of 0 indicates no hardware limit. */
1490 uint64_t core_pll_mul : 5; /**< [ 8: 4](RO) Core-clock PLL multiplier hardware limit. Indicates maximum
1491 value for PLL_MUL[5:1] straps. Any strap setting above this
1492 value will be ignored. A value of 0 indicates no hardware limit. */
1493 uint64_t tns_cripple : 1; /**< [ 9: 9](RO) Reserved.
1494 Internal:
1495 When set to 1, TNS switching functionality is permanently disabled. */
1496 uint64_t hna_info_clm : 4; /**< [ 13: 10](RO) Fuse information - HNA information (cluster mask). */
1497 uint64_t hna_info_dte : 3; /**< [ 16: 14](RO) Fuse information - HNA information (DTE). */
1498 uint64_t nohna_dte : 1; /**< [ 17: 17](RO) Fuse information - HNA disable (DTE). */
1499 uint64_t ema1 : 6; /**< [ 23: 18](RO) Fuse information - EMA1.
1500 Internal:
1501 Default value is 0x02. Soft or hard blow of these fuses
1502 will XOR with this value. */
1503 uint64_t nodfa_dte : 1; /**< [ 24: 24](RO) Fuse information - HFA disable (HTE). */
1504 uint64_t nozip : 1; /**< [ 25: 25](RO) Fuse information - ZIP disable. */
1505 uint64_t efus_ign : 1; /**< [ 26: 26](RO) Fuse information - efuse ignore. */
1506 uint64_t efus_lck : 1; /**< [ 27: 27](RO) Fuse information - efuse lockdown. */
1507 uint64_t bar2_sz_conf : 1; /**< [ 28: 28](RO) Fuse information - When 0, BAR2 size conforms to PCIe specification. */
1508 uint64_t zip_info : 2; /**< [ 30: 29](RO) Fuse information - ZIP information. */
1509 uint64_t use_int_refclk : 1; /**< [ 31: 31](RO) If set, use the PLL output as the low-jitter reference clock to the rclk DLLs. Default is
1510 to use the internal input reference clock. */
1511 uint64_t l2c_crip : 3; /**< [ 34: 32](RO) Fuse information - L2C cripple:
1512 0x0 = Full cache (16-way, 8 MB).
1513 0x1 = 3/4 ways (12-way, 6 MB).
1514 0x2 = 1/2 ways (8-way, 4 MB).
1515 0x3 = 1/4 ways (4-way, 2 MB).
1516 0x4-0x7 = Reserved. */
1517 uint64_t pll_half_dis : 1; /**< [ 35: 35](RO/H) Fuse information - coprocessor-clock PLL control. */
1518 uint64_t efus_lck_man : 1; /**< [ 36: 36](RO) Fuse information - efuse lockdown. */
1519 uint64_t efus_lck_rsv : 1; /**< [ 37: 37](RO) Fuse information - efuse lockdown. */
1520 uint64_t pll_bwadj_denom : 2; /**< [ 39: 38](RO) Select CLKF denominator for BWADJ value.
1521 0x0 = Selects CLKF/4.
1522 0x1 = Selects CLKF/2.
1523 0x2 = Selects CLKF/8. */
1524 uint64_t pll_alt_matrix : 1; /**< [ 40: 40](RO) Fuse information - Select alternate PLL matrix. */
1525 uint64_t dfa_info_clm : 4; /**< [ 44: 41](RO) Fuse information - HFA information (cluster mask). */
1526 uint64_t dfa_info_dte : 3; /**< [ 47: 45](RO) Fuse information - HFA information (HTE). */
1527 uint64_t pll_ctl : 10; /**< [ 57: 48](RO) Reserved. */
1528 uint64_t ema0 : 6; /**< [ 63: 58](RO) Fuse information - EMA0.
1529 Internal:
1530 Default value is 0x11. Soft or hard blow of these fuses
1531 will XOR with this value. */
1532 #endif /* Word 0 - End */
1533 } cn83xx;
1534 };
1535 typedef union bdk_mio_fus_dat3 bdk_mio_fus_dat3_t;
1536
1537 #define BDK_MIO_FUS_DAT3 BDK_MIO_FUS_DAT3_FUNC()
1538 static inline uint64_t BDK_MIO_FUS_DAT3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_DAT3_FUNC(void)1539 static inline uint64_t BDK_MIO_FUS_DAT3_FUNC(void)
1540 {
1541 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1542 return 0x87e003001418ll;
1543 __bdk_csr_fatal("MIO_FUS_DAT3", 0, 0, 0, 0, 0);
1544 }
1545
1546 #define typedef_BDK_MIO_FUS_DAT3 bdk_mio_fus_dat3_t
1547 #define bustype_BDK_MIO_FUS_DAT3 BDK_CSR_TYPE_RSL
1548 #define basename_BDK_MIO_FUS_DAT3 "MIO_FUS_DAT3"
1549 #define device_bar_BDK_MIO_FUS_DAT3 0x0 /* PF_BAR0 */
1550 #define busnum_BDK_MIO_FUS_DAT3 0
1551 #define arguments_BDK_MIO_FUS_DAT3 -1,-1,-1,-1
1552
1553 /**
1554 * Register (RSL) mio_fus_dat4
1555 *
1556 * MIO Fuse Data4 Register
1557 */
1558 union bdk_mio_fus_dat4
1559 {
1560 uint64_t u;
1561 struct bdk_mio_fus_dat4_s
1562 {
1563 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1564 uint64_t global_rclk_byp_select : 1; /**< [ 63: 63](RO) Reserved. */
1565 uint64_t global_rclk_byp_setting : 11;/**< [ 62: 52](RO) Bits\<11:1\>. Reserved. */
1566 uint64_t east_rclk_byp_select : 1; /**< [ 51: 51](RO) Reserved. */
1567 uint64_t east_rclk_byp_setting : 12; /**< [ 50: 39](RO) Reserved. */
1568 uint64_t cmb_rclk_byp_select : 1; /**< [ 38: 38](RO) Reserved. */
1569 uint64_t cmb_rclk_byp_setting : 12; /**< [ 37: 26](RO) Reserved. */
1570 uint64_t pp_rclk_byp_select : 1; /**< [ 25: 25](RO) Reserved. */
1571 uint64_t pp_rclk_byp_setting : 12; /**< [ 24: 13](RO) Reserved. */
1572 uint64_t tad_rclk_byp_select : 1; /**< [ 12: 12](RO) Reserved. */
1573 uint64_t tad_rclk_byp_setting : 12; /**< [ 11: 0](RO) Reserved. */
1574 #else /* Word 0 - Little Endian */
1575 uint64_t tad_rclk_byp_setting : 12; /**< [ 11: 0](RO) Reserved. */
1576 uint64_t tad_rclk_byp_select : 1; /**< [ 12: 12](RO) Reserved. */
1577 uint64_t pp_rclk_byp_setting : 12; /**< [ 24: 13](RO) Reserved. */
1578 uint64_t pp_rclk_byp_select : 1; /**< [ 25: 25](RO) Reserved. */
1579 uint64_t cmb_rclk_byp_setting : 12; /**< [ 37: 26](RO) Reserved. */
1580 uint64_t cmb_rclk_byp_select : 1; /**< [ 38: 38](RO) Reserved. */
1581 uint64_t east_rclk_byp_setting : 12; /**< [ 50: 39](RO) Reserved. */
1582 uint64_t east_rclk_byp_select : 1; /**< [ 51: 51](RO) Reserved. */
1583 uint64_t global_rclk_byp_setting : 11;/**< [ 62: 52](RO) Bits\<11:1\>. Reserved. */
1584 uint64_t global_rclk_byp_select : 1; /**< [ 63: 63](RO) Reserved. */
1585 #endif /* Word 0 - End */
1586 } s;
1587 /* struct bdk_mio_fus_dat4_s cn; */
1588 };
1589 typedef union bdk_mio_fus_dat4 bdk_mio_fus_dat4_t;
1590
1591 #define BDK_MIO_FUS_DAT4 BDK_MIO_FUS_DAT4_FUNC()
1592 static inline uint64_t BDK_MIO_FUS_DAT4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_DAT4_FUNC(void)1593 static inline uint64_t BDK_MIO_FUS_DAT4_FUNC(void)
1594 {
1595 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1596 return 0x87e003001420ll;
1597 __bdk_csr_fatal("MIO_FUS_DAT4", 0, 0, 0, 0, 0);
1598 }
1599
1600 #define typedef_BDK_MIO_FUS_DAT4 bdk_mio_fus_dat4_t
1601 #define bustype_BDK_MIO_FUS_DAT4 BDK_CSR_TYPE_RSL
1602 #define basename_BDK_MIO_FUS_DAT4 "MIO_FUS_DAT4"
1603 #define device_bar_BDK_MIO_FUS_DAT4 0x0 /* PF_BAR0 */
1604 #define busnum_BDK_MIO_FUS_DAT4 0
1605 #define arguments_BDK_MIO_FUS_DAT4 -1,-1,-1,-1
1606
1607 /**
1608 * Register (RSL) mio_fus_int
1609 *
1610 * INTERNAL: MIO Fuse Repair Interrupt Register
1611 */
1612 union bdk_mio_fus_int
1613 {
1614 uint64_t u;
1615 struct bdk_mio_fus_int_s
1616 {
1617 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1618 uint64_t reserved_2_63 : 62;
1619 uint64_t rpr_dbe : 1; /**< [ 1: 1](R/W1C/H) Internal:
1620 Indicates an uncorrectable double-bit-error occurred to RPR_MEM. */
1621 uint64_t rpr_sbe : 1; /**< [ 0: 0](R/W1C/H) Internal:
1622 Indicates a corrected single-bit-error occurred to RPR_MEM. */
1623 #else /* Word 0 - Little Endian */
1624 uint64_t rpr_sbe : 1; /**< [ 0: 0](R/W1C/H) Internal:
1625 Indicates a corrected single-bit-error occurred to RPR_MEM. */
1626 uint64_t rpr_dbe : 1; /**< [ 1: 1](R/W1C/H) Internal:
1627 Indicates an uncorrectable double-bit-error occurred to RPR_MEM. */
1628 uint64_t reserved_2_63 : 62;
1629 #endif /* Word 0 - End */
1630 } s;
1631 /* struct bdk_mio_fus_int_s cn; */
1632 };
1633 typedef union bdk_mio_fus_int bdk_mio_fus_int_t;
1634
1635 #define BDK_MIO_FUS_INT BDK_MIO_FUS_INT_FUNC()
1636 static inline uint64_t BDK_MIO_FUS_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_INT_FUNC(void)1637 static inline uint64_t BDK_MIO_FUS_INT_FUNC(void)
1638 {
1639 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1640 return 0x87e003001548ll;
1641 __bdk_csr_fatal("MIO_FUS_INT", 0, 0, 0, 0, 0);
1642 }
1643
1644 #define typedef_BDK_MIO_FUS_INT bdk_mio_fus_int_t
1645 #define bustype_BDK_MIO_FUS_INT BDK_CSR_TYPE_RSL
1646 #define basename_BDK_MIO_FUS_INT "MIO_FUS_INT"
1647 #define device_bar_BDK_MIO_FUS_INT 0x0 /* PF_BAR0 */
1648 #define busnum_BDK_MIO_FUS_INT 0
1649 #define arguments_BDK_MIO_FUS_INT -1,-1,-1,-1
1650
1651 /**
1652 * Register (RSL) mio_fus_pdf
1653 *
1654 * MIO Fuse Product Definition Field Register
1655 */
1656 union bdk_mio_fus_pdf
1657 {
1658 uint64_t u;
1659 struct bdk_mio_fus_pdf_s
1660 {
1661 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1662 uint64_t pdf : 64; /**< [ 63: 0](RO) Fuse information--product definition field. */
1663 #else /* Word 0 - Little Endian */
1664 uint64_t pdf : 64; /**< [ 63: 0](RO) Fuse information--product definition field. */
1665 #endif /* Word 0 - End */
1666 } s;
1667 /* struct bdk_mio_fus_pdf_s cn; */
1668 };
1669 typedef union bdk_mio_fus_pdf bdk_mio_fus_pdf_t;
1670
1671 #define BDK_MIO_FUS_PDF BDK_MIO_FUS_PDF_FUNC()
1672 static inline uint64_t BDK_MIO_FUS_PDF_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_PDF_FUNC(void)1673 static inline uint64_t BDK_MIO_FUS_PDF_FUNC(void)
1674 {
1675 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1676 return 0x87e003001428ll;
1677 __bdk_csr_fatal("MIO_FUS_PDF", 0, 0, 0, 0, 0);
1678 }
1679
1680 #define typedef_BDK_MIO_FUS_PDF bdk_mio_fus_pdf_t
1681 #define bustype_BDK_MIO_FUS_PDF BDK_CSR_TYPE_RSL
1682 #define basename_BDK_MIO_FUS_PDF "MIO_FUS_PDF"
1683 #define device_bar_BDK_MIO_FUS_PDF 0x0 /* PF_BAR0 */
1684 #define busnum_BDK_MIO_FUS_PDF 0
1685 #define arguments_BDK_MIO_FUS_PDF -1,-1,-1,-1
1686
1687 /**
1688 * Register (RSL) mio_fus_pll
1689 *
1690 * MIO Fuse PLL Register
1691 * This register contains PLL status and controls for the MSC_CLKOUT and
1692 * MSC_SYS_CLKOUT pins. The fields are reset to zero on a cold reset.
1693 * the values are preserved on both a warm and soft reset starting with pass 3.
1694 */
1695 union bdk_mio_fus_pll
1696 {
1697 uint64_t u;
1698 struct bdk_mio_fus_pll_s
1699 {
1700 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1701 uint64_t reserved_15_63 : 49;
1702 uint64_t core_status : 3; /**< [ 14: 12](RO) Core-clock PLL status information. */
1703 uint64_t reserved_11 : 1;
1704 uint64_t pnr_status : 3; /**< [ 10: 8](RO) Coprocessor-clock PLL status information. */
1705 uint64_t c_cout_rst : 1; /**< [ 7: 7](R/W) Core clockout postscaler reset. The core clockout postscaler
1706 should be placed in reset at least 10 reference-clock cycles prior
1707 to changing [C_COUT_SEL]. The core clockout postscaler should remain
1708 under reset for at least 10 reference-clock cycles after [C_COUT_SEL]
1709 changes. This field is reset to zero on a cold reset, it is preserved
1710 on both warm and soft resets. */
1711 uint64_t c_cout_sel : 2; /**< [ 6: 5](R/W) Core-clock output select:
1712 0x0 = Core clock.
1713 0x1 = PS output.
1714 0x2 = PLL output.
1715 0x3 = Undivided core clock. */
1716 uint64_t pnr_cout_rst : 1; /**< [ 4: 4](R/W) SYS clockout postscaler reset. The PNR clockout postscaler
1717 should be placed in reset at least 10 reference-clock cycles
1718 prior to changing [PNR_COUT_SEL]. The SYS clockout postscaler
1719 should remain under reset for at least 10 reference clock cycles
1720 after [PNR_COUT_SEL] changes. */
1721 uint64_t pnr_cout_sel : 2; /**< [ 3: 2](R/W) Coprocessor-clock output select:
1722 0x0 = Coprocessor clock.
1723 0x1 = PS output.
1724 0x2 = PLL output.
1725 0x3 = Undivided core clock. */
1726 uint64_t reserved_0_1 : 2;
1727 #else /* Word 0 - Little Endian */
1728 uint64_t reserved_0_1 : 2;
1729 uint64_t pnr_cout_sel : 2; /**< [ 3: 2](R/W) Coprocessor-clock output select:
1730 0x0 = Coprocessor clock.
1731 0x1 = PS output.
1732 0x2 = PLL output.
1733 0x3 = Undivided core clock. */
1734 uint64_t pnr_cout_rst : 1; /**< [ 4: 4](R/W) SYS clockout postscaler reset. The PNR clockout postscaler
1735 should be placed in reset at least 10 reference-clock cycles
1736 prior to changing [PNR_COUT_SEL]. The SYS clockout postscaler
1737 should remain under reset for at least 10 reference clock cycles
1738 after [PNR_COUT_SEL] changes. */
1739 uint64_t c_cout_sel : 2; /**< [ 6: 5](R/W) Core-clock output select:
1740 0x0 = Core clock.
1741 0x1 = PS output.
1742 0x2 = PLL output.
1743 0x3 = Undivided core clock. */
1744 uint64_t c_cout_rst : 1; /**< [ 7: 7](R/W) Core clockout postscaler reset. The core clockout postscaler
1745 should be placed in reset at least 10 reference-clock cycles prior
1746 to changing [C_COUT_SEL]. The core clockout postscaler should remain
1747 under reset for at least 10 reference-clock cycles after [C_COUT_SEL]
1748 changes. This field is reset to zero on a cold reset, it is preserved
1749 on both warm and soft resets. */
1750 uint64_t pnr_status : 3; /**< [ 10: 8](RO) Coprocessor-clock PLL status information. */
1751 uint64_t reserved_11 : 1;
1752 uint64_t core_status : 3; /**< [ 14: 12](RO) Core-clock PLL status information. */
1753 uint64_t reserved_15_63 : 49;
1754 #endif /* Word 0 - End */
1755 } s;
1756 /* struct bdk_mio_fus_pll_s cn; */
1757 };
1758 typedef union bdk_mio_fus_pll bdk_mio_fus_pll_t;
1759
1760 #define BDK_MIO_FUS_PLL BDK_MIO_FUS_PLL_FUNC()
1761 static inline uint64_t BDK_MIO_FUS_PLL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_PLL_FUNC(void)1762 static inline uint64_t BDK_MIO_FUS_PLL_FUNC(void)
1763 {
1764 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1765 return 0x87e003001580ll;
1766 __bdk_csr_fatal("MIO_FUS_PLL", 0, 0, 0, 0, 0);
1767 }
1768
1769 #define typedef_BDK_MIO_FUS_PLL bdk_mio_fus_pll_t
1770 #define bustype_BDK_MIO_FUS_PLL BDK_CSR_TYPE_RSL
1771 #define basename_BDK_MIO_FUS_PLL "MIO_FUS_PLL"
1772 #define device_bar_BDK_MIO_FUS_PLL 0x0 /* PF_BAR0 */
1773 #define busnum_BDK_MIO_FUS_PLL 0
1774 #define arguments_BDK_MIO_FUS_PLL -1,-1,-1,-1
1775
1776 /**
1777 * Register (RSL) mio_fus_pname#
1778 *
1779 * MIO Fuse Product Name Register
1780 * ""These registers contain a 24-character string representing the part number,
1781 * e.g. "CN8800-2000BG2601-CPT-PR".
1782 *
1783 * The string is represented in a RAD-40-like encoding, padded with trailing spaces
1784 * that must be removed. If the resulting string is empty, the product has not been
1785 * fused programmed and the name should be constructed from e.g. the core's device
1786 * number.
1787 *
1788 * Pseudocode for the decoding:
1789 * \<pre\>
1790 * datap = data_from_fuses;
1791 * // where bit 0 of byte 0 array is fuse 1408;
1792 * // i.e. bit 0 of MIO_FUS_PNAME(0)
1793 * void rad50_decode(const uint8_t* datap, char* bufferp) {
1794 * // Psudocode only - assumes datap sized to at least 16 bytes,
1795 * // and bufferp to at least 26 characters.
1796 * const char* CHAR_MAP = " ABCDEFGHIJKLMNOPQRSTUVWXYZ#.-0123456789";
1797 * char* cp = bufferp;
1798 * for (int i=0; i\<FUSE_BYTES; i+=2) {
1799 * // Data is stored little endian
1800 * uint16_t data = ((const uint16_t*)datap)[i/2];
1801 * ifndef MACHINE_LITTLE_ENDIAN
1802 * data = __swab16(data);
1803 * endif
1804 * *cp++ = CHAR_MAP[(data/40/40) % 40];
1805 * *cp++ = CHAR_MAP[(data/40) % 40];
1806 * *cp++ = CHAR_MAP[(data) % 40];
1807 * }
1808 * *cp++ = '\0';
1809 * for (cp = bufferp+strlen(bufferp)-1; cp\>=bufferp && isspace(*cp); --cp) *cp='\0';
1810 * }
1811 * \</pre\>"
1812 *
1813 * Internal:
1814 * Fuse[1535:1408]."
1815 */
1816 union bdk_mio_fus_pnamex
1817 {
1818 uint64_t u;
1819 struct bdk_mio_fus_pnamex_s
1820 {
1821 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1822 uint64_t dat : 64; /**< [ 63: 0](RO/H) Product name information. */
1823 #else /* Word 0 - Little Endian */
1824 uint64_t dat : 64; /**< [ 63: 0](RO/H) Product name information. */
1825 #endif /* Word 0 - End */
1826 } s;
1827 /* struct bdk_mio_fus_pnamex_s cn; */
1828 };
1829 typedef union bdk_mio_fus_pnamex bdk_mio_fus_pnamex_t;
1830
1831 static inline uint64_t BDK_MIO_FUS_PNAMEX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_PNAMEX(unsigned long a)1832 static inline uint64_t BDK_MIO_FUS_PNAMEX(unsigned long a)
1833 {
1834 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a<=1))
1835 return 0x87e003001440ll + 8ll * ((a) & 0x1);
1836 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1837 return 0x87e003001440ll + 8ll * ((a) & 0x1);
1838 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX_PASS2_X) && (a<=1))
1839 return 0x87e003001440ll + 8ll * ((a) & 0x1);
1840 __bdk_csr_fatal("MIO_FUS_PNAMEX", 1, a, 0, 0, 0);
1841 }
1842
1843 #define typedef_BDK_MIO_FUS_PNAMEX(a) bdk_mio_fus_pnamex_t
1844 #define bustype_BDK_MIO_FUS_PNAMEX(a) BDK_CSR_TYPE_RSL
1845 #define basename_BDK_MIO_FUS_PNAMEX(a) "MIO_FUS_PNAMEX"
1846 #define device_bar_BDK_MIO_FUS_PNAMEX(a) 0x0 /* PF_BAR0 */
1847 #define busnum_BDK_MIO_FUS_PNAMEX(a) (a)
1848 #define arguments_BDK_MIO_FUS_PNAMEX(a) (a),-1,-1,-1
1849
1850 /**
1851 * Register (RSL) mio_fus_prog
1852 *
1853 * INTERNAL: MIO Fuse Programming Register
1854 */
1855 union bdk_mio_fus_prog
1856 {
1857 uint64_t u;
1858 struct bdk_mio_fus_prog_s
1859 {
1860 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1861 uint64_t reserved_2_63 : 62;
1862 uint64_t sft : 1; /**< [ 1: 1](R/W/H) Internal:
1863 When set with [PROG], causes only the local storage to change and will
1864 not blow any fuses. A soft blow is still subject to lockdown fuses.
1865 Hardware will clear this bit when the program operation is complete.
1866 Soft blown fuses will become active after a either a soft or warm
1867 reset but will not persist through a cold reset. */
1868 uint64_t prog : 1; /**< [ 0: 0](R/W/H) Internal:
1869 When written to one by software, blow the fuse bank. Hardware will
1870 clear when the program operation is complete. To write a bank of
1871 fuses, software must set MIO_FUS_WADR[ADDR] to the bank to be
1872 programmed and then set each bit within MIO_FUS_BNK_DAT() to
1873 indicate which fuses to blow. Once ADDR, and DAT are set up,
1874 Software can write to MIO_FUS_PROG[PROG] to start the bank write
1875 and poll on [PROG]. Once [PROG] is clear, the bank write is complete.
1876 MIO_FUS_READ_TIMES[WRSTB_WH] determines the time for the operation
1877 to complete. New fuses will become active after a reset. */
1878 #else /* Word 0 - Little Endian */
1879 uint64_t prog : 1; /**< [ 0: 0](R/W/H) Internal:
1880 When written to one by software, blow the fuse bank. Hardware will
1881 clear when the program operation is complete. To write a bank of
1882 fuses, software must set MIO_FUS_WADR[ADDR] to the bank to be
1883 programmed and then set each bit within MIO_FUS_BNK_DAT() to
1884 indicate which fuses to blow. Once ADDR, and DAT are set up,
1885 Software can write to MIO_FUS_PROG[PROG] to start the bank write
1886 and poll on [PROG]. Once [PROG] is clear, the bank write is complete.
1887 MIO_FUS_READ_TIMES[WRSTB_WH] determines the time for the operation
1888 to complete. New fuses will become active after a reset. */
1889 uint64_t sft : 1; /**< [ 1: 1](R/W/H) Internal:
1890 When set with [PROG], causes only the local storage to change and will
1891 not blow any fuses. A soft blow is still subject to lockdown fuses.
1892 Hardware will clear this bit when the program operation is complete.
1893 Soft blown fuses will become active after a either a soft or warm
1894 reset but will not persist through a cold reset. */
1895 uint64_t reserved_2_63 : 62;
1896 #endif /* Word 0 - End */
1897 } s;
1898 /* struct bdk_mio_fus_prog_s cn; */
1899 };
1900 typedef union bdk_mio_fus_prog bdk_mio_fus_prog_t;
1901
1902 #define BDK_MIO_FUS_PROG BDK_MIO_FUS_PROG_FUNC()
1903 static inline uint64_t BDK_MIO_FUS_PROG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_PROG_FUNC(void)1904 static inline uint64_t BDK_MIO_FUS_PROG_FUNC(void)
1905 {
1906 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1907 return 0x87e003001510ll;
1908 __bdk_csr_fatal("MIO_FUS_PROG", 0, 0, 0, 0, 0);
1909 }
1910
1911 #define typedef_BDK_MIO_FUS_PROG bdk_mio_fus_prog_t
1912 #define bustype_BDK_MIO_FUS_PROG BDK_CSR_TYPE_RSL
1913 #define basename_BDK_MIO_FUS_PROG "MIO_FUS_PROG"
1914 #define device_bar_BDK_MIO_FUS_PROG 0x0 /* PF_BAR0 */
1915 #define busnum_BDK_MIO_FUS_PROG 0
1916 #define arguments_BDK_MIO_FUS_PROG -1,-1,-1,-1
1917
1918 /**
1919 * Register (RSL) mio_fus_prog_times
1920 *
1921 * INTERNAL: MIO Fuse Program Times Register
1922 */
1923 union bdk_mio_fus_prog_times
1924 {
1925 uint64_t u;
1926 struct bdk_mio_fus_prog_times_s
1927 {
1928 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1929 uint64_t reserved_35_63 : 29;
1930 uint64_t vgate_pin : 1; /**< [ 34: 34](RO) Internal:
1931 Efuse vgate pin (L6G). */
1932 uint64_t fsrc_pin : 1; /**< [ 33: 33](RO) Internal:
1933 Efuse fsource pin (L6G). */
1934 uint64_t prog_pin : 1; /**< [ 32: 32](RO) Internal:
1935 Efuse program pin (IFB). */
1936 uint64_t reserved_0_31 : 32;
1937 #else /* Word 0 - Little Endian */
1938 uint64_t reserved_0_31 : 32;
1939 uint64_t prog_pin : 1; /**< [ 32: 32](RO) Internal:
1940 Efuse program pin (IFB). */
1941 uint64_t fsrc_pin : 1; /**< [ 33: 33](RO) Internal:
1942 Efuse fsource pin (L6G). */
1943 uint64_t vgate_pin : 1; /**< [ 34: 34](RO) Internal:
1944 Efuse vgate pin (L6G). */
1945 uint64_t reserved_35_63 : 29;
1946 #endif /* Word 0 - End */
1947 } s;
1948 /* struct bdk_mio_fus_prog_times_s cn; */
1949 };
1950 typedef union bdk_mio_fus_prog_times bdk_mio_fus_prog_times_t;
1951
1952 #define BDK_MIO_FUS_PROG_TIMES BDK_MIO_FUS_PROG_TIMES_FUNC()
1953 static inline uint64_t BDK_MIO_FUS_PROG_TIMES_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_PROG_TIMES_FUNC(void)1954 static inline uint64_t BDK_MIO_FUS_PROG_TIMES_FUNC(void)
1955 {
1956 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
1957 return 0x87e003001518ll;
1958 __bdk_csr_fatal("MIO_FUS_PROG_TIMES", 0, 0, 0, 0, 0);
1959 }
1960
1961 #define typedef_BDK_MIO_FUS_PROG_TIMES bdk_mio_fus_prog_times_t
1962 #define bustype_BDK_MIO_FUS_PROG_TIMES BDK_CSR_TYPE_RSL
1963 #define basename_BDK_MIO_FUS_PROG_TIMES "MIO_FUS_PROG_TIMES"
1964 #define device_bar_BDK_MIO_FUS_PROG_TIMES 0x0 /* PF_BAR0 */
1965 #define busnum_BDK_MIO_FUS_PROG_TIMES 0
1966 #define arguments_BDK_MIO_FUS_PROG_TIMES -1,-1,-1,-1
1967
1968 /**
1969 * Register (RSL) mio_fus_rcmd
1970 *
1971 * MIO Fuse Read Command Register
1972 * To read an efuse, software writes [ADDR,PEND] with
1973 * the byte address of the fuse in question, then software can poll
1974 * [PEND]. When [PEND] = 0, then [DAT] is valid.
1975 * In addition, if the efuse read went to the efuse banks, software can
1976 * read MIO_FUS_BNK_DAT() which contains all 128 fuses in the bank
1977 * associated in ADDR. Fuses 1023..960 are never accessible on pass 1 parts.
1978 * In addition, fuses 1023..960 are not accessible if
1979 * MIO_FUS_DAT2[DORM_CRYPTO] is enabled.
1980 */
1981 union bdk_mio_fus_rcmd
1982 {
1983 uint64_t u;
1984 struct bdk_mio_fus_rcmd_s
1985 {
1986 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1987 uint64_t reserved_24_63 : 40;
1988 uint64_t dat : 8; /**< [ 23: 16](RO/H) Eight bits of fuse data. */
1989 uint64_t reserved_13_15 : 3;
1990 uint64_t pend : 1; /**< [ 12: 12](R/W/H) Software sets this bit to 1 on a write operation that starts
1991 the fuse read operation. Hardware clears this bit when the read
1992 operation is complete and [DAT] is valid. MIO_FUS_READ_TIMES[RDSTB_WH]
1993 determines the time for the operation to complete. */
1994 uint64_t reserved_11 : 1;
1995 uint64_t addr_hi : 2; /**< [ 10: 9](R/W) Upper fuse address bits to extend space beyond 2k fuses.
1996 Valid range is 0x0-0x3. Software should not change this
1997 field while [PEND] is set. It should wait for
1998 the hardware to clear it. */
1999 uint64_t efuse : 1; /**< [ 8: 8](R/W) Efuse storage. When set, the return data is from the efuse
2000 directly rather than the local storage. */
2001 uint64_t addr : 8; /**< [ 7: 0](R/W) Address. Specifies the byte address of the fuse to read.
2002 Software should not change this field while [PEND]
2003 is set. It must wait for the hardware to clear it. */
2004 #else /* Word 0 - Little Endian */
2005 uint64_t addr : 8; /**< [ 7: 0](R/W) Address. Specifies the byte address of the fuse to read.
2006 Software should not change this field while [PEND]
2007 is set. It must wait for the hardware to clear it. */
2008 uint64_t efuse : 1; /**< [ 8: 8](R/W) Efuse storage. When set, the return data is from the efuse
2009 directly rather than the local storage. */
2010 uint64_t addr_hi : 2; /**< [ 10: 9](R/W) Upper fuse address bits to extend space beyond 2k fuses.
2011 Valid range is 0x0-0x3. Software should not change this
2012 field while [PEND] is set. It should wait for
2013 the hardware to clear it. */
2014 uint64_t reserved_11 : 1;
2015 uint64_t pend : 1; /**< [ 12: 12](R/W/H) Software sets this bit to 1 on a write operation that starts
2016 the fuse read operation. Hardware clears this bit when the read
2017 operation is complete and [DAT] is valid. MIO_FUS_READ_TIMES[RDSTB_WH]
2018 determines the time for the operation to complete. */
2019 uint64_t reserved_13_15 : 3;
2020 uint64_t dat : 8; /**< [ 23: 16](RO/H) Eight bits of fuse data. */
2021 uint64_t reserved_24_63 : 40;
2022 #endif /* Word 0 - End */
2023 } s;
2024 /* struct bdk_mio_fus_rcmd_s cn; */
2025 };
2026 typedef union bdk_mio_fus_rcmd bdk_mio_fus_rcmd_t;
2027
2028 #define BDK_MIO_FUS_RCMD BDK_MIO_FUS_RCMD_FUNC()
2029 static inline uint64_t BDK_MIO_FUS_RCMD_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_RCMD_FUNC(void)2030 static inline uint64_t BDK_MIO_FUS_RCMD_FUNC(void)
2031 {
2032 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2033 return 0x87e003001500ll;
2034 __bdk_csr_fatal("MIO_FUS_RCMD", 0, 0, 0, 0, 0);
2035 }
2036
2037 #define typedef_BDK_MIO_FUS_RCMD bdk_mio_fus_rcmd_t
2038 #define bustype_BDK_MIO_FUS_RCMD BDK_CSR_TYPE_RSL
2039 #define basename_BDK_MIO_FUS_RCMD "MIO_FUS_RCMD"
2040 #define device_bar_BDK_MIO_FUS_RCMD 0x0 /* PF_BAR0 */
2041 #define busnum_BDK_MIO_FUS_RCMD 0
2042 #define arguments_BDK_MIO_FUS_RCMD -1,-1,-1,-1
2043
2044 /**
2045 * Register (RSL) mio_fus_read_times
2046 *
2047 * MIO Fuse Read Times Register
2048 * IFB fuses are 0 to 1791. The reset values are for IFB fuses for PLL_REF_CLK up to 100MHz when
2049 * the core PLL is engaged. If any of the formulas below result in a value less than 0x0, the
2050 * corresponding timing parameter should be set to 0.
2051 *
2052 * Prior to issuing a read operation to the fuse banks (via MIO_FUS_RCMD), this register should
2053 * be written with the timing parameters that will be read.
2054 * This register should not be written while MIO_FUS_RCMD[PEND] = 1.
2055 */
2056 union bdk_mio_fus_read_times
2057 {
2058 uint64_t u;
2059 struct bdk_mio_fus_read_times_s
2060 {
2061 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2062 uint64_t reserved_32_63 : 32;
2063 uint64_t done : 4; /**< [ 31: 28](R/W) Hold time of CSB, PGENB, and LOAD with respect to falling edge of STROBE for read and
2064 write mode in PLL_REF_CLK + 1 cycles. Timing specs are th_CS = 6ns, th_PG = 10ns, th_LD_p
2065 = 7ns. Default of 0x0 yields 20ns for a PLL_REF_CLK of 50 MHz, 10ns at 100MHz. */
2066 uint64_t ahd : 4; /**< [ 27: 24](R/W) Hold time of A with respect to falling edge of STROBE for read and write modes in
2067 PLL_REF_CLK + 2 cycles. Timing spec of tsu_A_r and tsu_A_p is 3ns min. Default of 0x0
2068 yields 40ns for a PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2069 uint64_t wrstb_wh : 12; /**< [ 23: 12](R/W) Pulse width high of STROBE in write mode in PLL_REF_CLK + 1 cycles. Timing spec of
2070 twh_SB_p is 9.8us max. Default of 0x1F3 yields 10 us at PLL_REF_CLK of 50 MHz. */
2071 uint64_t rdstb_wh : 4; /**< [ 11: 8](R/W) Pulse width high of STROBE in read mode in PLL_REF_CLK + 1 cycles. Timing spec of twh_SB_p
2072 is 20ns min. Default of 0x1 yields 40 ns at PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2073 uint64_t asu : 4; /**< [ 7: 4](R/W) Setup time of A to rising edge of STROBE for read and write modes in PLL_REF_CLK cycles.
2074 Timing spec of tsu_A_r and tsu_A_p is 12 ns min. Default of 0x1 yields 40 ns at
2075 PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2076 uint64_t setup : 4; /**< [ 3: 0](R/W) Setup time of CSB, PGENB, LOAD to rising edge of STROBE in read and write modes in
2077 PLL_REF_CLK + 1 cycles. tsu_CS = 16ns, tsu_PG = 14ns, tsu_LD_r = 10ns. Default of 0x0
2078 yields 20 ns plus ASU cycles at PLL_REF_CLK of 50 MHz, 10ns + ASU at 100MHz. */
2079 #else /* Word 0 - Little Endian */
2080 uint64_t setup : 4; /**< [ 3: 0](R/W) Setup time of CSB, PGENB, LOAD to rising edge of STROBE in read and write modes in
2081 PLL_REF_CLK + 1 cycles. tsu_CS = 16ns, tsu_PG = 14ns, tsu_LD_r = 10ns. Default of 0x0
2082 yields 20 ns plus ASU cycles at PLL_REF_CLK of 50 MHz, 10ns + ASU at 100MHz. */
2083 uint64_t asu : 4; /**< [ 7: 4](R/W) Setup time of A to rising edge of STROBE for read and write modes in PLL_REF_CLK cycles.
2084 Timing spec of tsu_A_r and tsu_A_p is 12 ns min. Default of 0x1 yields 40 ns at
2085 PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2086 uint64_t rdstb_wh : 4; /**< [ 11: 8](R/W) Pulse width high of STROBE in read mode in PLL_REF_CLK + 1 cycles. Timing spec of twh_SB_p
2087 is 20ns min. Default of 0x1 yields 40 ns at PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2088 uint64_t wrstb_wh : 12; /**< [ 23: 12](R/W) Pulse width high of STROBE in write mode in PLL_REF_CLK + 1 cycles. Timing spec of
2089 twh_SB_p is 9.8us max. Default of 0x1F3 yields 10 us at PLL_REF_CLK of 50 MHz. */
2090 uint64_t ahd : 4; /**< [ 27: 24](R/W) Hold time of A with respect to falling edge of STROBE for read and write modes in
2091 PLL_REF_CLK + 2 cycles. Timing spec of tsu_A_r and tsu_A_p is 3ns min. Default of 0x0
2092 yields 40ns for a PLL_REF_CLK of 50 MHz, 20ns at 100MHz. */
2093 uint64_t done : 4; /**< [ 31: 28](R/W) Hold time of CSB, PGENB, and LOAD with respect to falling edge of STROBE for read and
2094 write mode in PLL_REF_CLK + 1 cycles. Timing specs are th_CS = 6ns, th_PG = 10ns, th_LD_p
2095 = 7ns. Default of 0x0 yields 20ns for a PLL_REF_CLK of 50 MHz, 10ns at 100MHz. */
2096 uint64_t reserved_32_63 : 32;
2097 #endif /* Word 0 - End */
2098 } s;
2099 /* struct bdk_mio_fus_read_times_s cn; */
2100 };
2101 typedef union bdk_mio_fus_read_times bdk_mio_fus_read_times_t;
2102
2103 #define BDK_MIO_FUS_READ_TIMES BDK_MIO_FUS_READ_TIMES_FUNC()
2104 static inline uint64_t BDK_MIO_FUS_READ_TIMES_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_READ_TIMES_FUNC(void)2105 static inline uint64_t BDK_MIO_FUS_READ_TIMES_FUNC(void)
2106 {
2107 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2108 return 0x87e003001570ll;
2109 __bdk_csr_fatal("MIO_FUS_READ_TIMES", 0, 0, 0, 0, 0);
2110 }
2111
2112 #define typedef_BDK_MIO_FUS_READ_TIMES bdk_mio_fus_read_times_t
2113 #define bustype_BDK_MIO_FUS_READ_TIMES BDK_CSR_TYPE_RSL
2114 #define basename_BDK_MIO_FUS_READ_TIMES "MIO_FUS_READ_TIMES"
2115 #define device_bar_BDK_MIO_FUS_READ_TIMES 0x0 /* PF_BAR0 */
2116 #define busnum_BDK_MIO_FUS_READ_TIMES 0
2117 #define arguments_BDK_MIO_FUS_READ_TIMES -1,-1,-1,-1
2118
2119 /**
2120 * Register (RSL) mio_fus_rpr_dat#
2121 *
2122 * INTERNAL: MIO Fuse Repair Memory Register
2123 */
2124 union bdk_mio_fus_rpr_datx
2125 {
2126 uint64_t u;
2127 struct bdk_mio_fus_rpr_datx_s
2128 {
2129 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2130 uint64_t dat : 64; /**< [ 63: 0](R/W) Internal:
2131 Repair memory store (RPR_MEM). Data for read and write. A write to
2132 MIO_FUS_RPR_DAT(1) writes all 128 bits from both registers to RPR_MEM. */
2133 #else /* Word 0 - Little Endian */
2134 uint64_t dat : 64; /**< [ 63: 0](R/W) Internal:
2135 Repair memory store (RPR_MEM). Data for read and write. A write to
2136 MIO_FUS_RPR_DAT(1) writes all 128 bits from both registers to RPR_MEM. */
2137 #endif /* Word 0 - End */
2138 } s;
2139 /* struct bdk_mio_fus_rpr_datx_s cn; */
2140 };
2141 typedef union bdk_mio_fus_rpr_datx bdk_mio_fus_rpr_datx_t;
2142
2143 static inline uint64_t BDK_MIO_FUS_RPR_DATX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_RPR_DATX(unsigned long a)2144 static inline uint64_t BDK_MIO_FUS_RPR_DATX(unsigned long a)
2145 {
2146 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=1))
2147 return 0x87e003001530ll + 8ll * ((a) & 0x1);
2148 __bdk_csr_fatal("MIO_FUS_RPR_DATX", 1, a, 0, 0, 0);
2149 }
2150
2151 #define typedef_BDK_MIO_FUS_RPR_DATX(a) bdk_mio_fus_rpr_datx_t
2152 #define bustype_BDK_MIO_FUS_RPR_DATX(a) BDK_CSR_TYPE_RSL
2153 #define basename_BDK_MIO_FUS_RPR_DATX(a) "MIO_FUS_RPR_DATX"
2154 #define device_bar_BDK_MIO_FUS_RPR_DATX(a) 0x0 /* PF_BAR0 */
2155 #define busnum_BDK_MIO_FUS_RPR_DATX(a) (a)
2156 #define arguments_BDK_MIO_FUS_RPR_DATX(a) (a),-1,-1,-1
2157
2158 /**
2159 * Register (RSL) mio_fus_soft_repair
2160 *
2161 * INTERNAL: MIO Fuse Soft Repair Register
2162 *
2163 * Internal:
2164 * INTERNAL: Aka `Soft Blow'. Upon reset fuse repairs are loaded into REPAIR_MEM as they are
2165 * loaded into the memories. Any new defects are loaded in afterwards, leaving END_PTR at the
2166 * last defect.
2167 */
2168 union bdk_mio_fus_soft_repair
2169 {
2170 uint64_t u;
2171 struct bdk_mio_fus_soft_repair_s
2172 {
2173 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2174 uint64_t reserved_20_63 : 44;
2175 uint64_t rpr_flip_synd : 2; /**< [ 19: 18](R/W/H) Internal:
2176 Flip syndrome bits on RPR_MEM writes. For diagnostic use only. */
2177 uint64_t autoblow : 1; /**< [ 17: 17](R/W/H) Internal:
2178 Set to initiate burning of defect fuses to fuse macro. Clears when fuses are
2179 blown. */
2180 uint64_t too_many : 1; /**< [ 16: 16](RO/H) Internal:
2181 Set if the sum of fuse repairs and memory defects exceeds 48. */
2182 uint64_t numdefects : 8; /**< [ 15: 8](RO/H) Internal:
2183 After reset/BIST indicates the number of memory defects reported. Defects are
2184 stored in REPAIR_MEM from bit address NUMREPAIRS*21 to (NUMREPAIRS*21 + NUMDEFECTS*21 -
2185 1). */
2186 uint64_t numrepairs : 8; /**< [ 7: 0](R/W) Internal:
2187 Indicates the number of soft repairs to load from repair mem to the memories on
2188 a soft/warm reset. Indicates the number of repairs loaded from efuses to repair mem on a
2189 cold reset. */
2190 #else /* Word 0 - Little Endian */
2191 uint64_t numrepairs : 8; /**< [ 7: 0](R/W) Internal:
2192 Indicates the number of soft repairs to load from repair mem to the memories on
2193 a soft/warm reset. Indicates the number of repairs loaded from efuses to repair mem on a
2194 cold reset. */
2195 uint64_t numdefects : 8; /**< [ 15: 8](RO/H) Internal:
2196 After reset/BIST indicates the number of memory defects reported. Defects are
2197 stored in REPAIR_MEM from bit address NUMREPAIRS*21 to (NUMREPAIRS*21 + NUMDEFECTS*21 -
2198 1). */
2199 uint64_t too_many : 1; /**< [ 16: 16](RO/H) Internal:
2200 Set if the sum of fuse repairs and memory defects exceeds 48. */
2201 uint64_t autoblow : 1; /**< [ 17: 17](R/W/H) Internal:
2202 Set to initiate burning of defect fuses to fuse macro. Clears when fuses are
2203 blown. */
2204 uint64_t rpr_flip_synd : 2; /**< [ 19: 18](R/W/H) Internal:
2205 Flip syndrome bits on RPR_MEM writes. For diagnostic use only. */
2206 uint64_t reserved_20_63 : 44;
2207 #endif /* Word 0 - End */
2208 } s;
2209 /* struct bdk_mio_fus_soft_repair_s cn81xx; */
2210 struct bdk_mio_fus_soft_repair_cn88xx
2211 {
2212 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2213 uint64_t reserved_20_63 : 44;
2214 uint64_t rpr_flip_synd : 2; /**< [ 19: 18](R/W/H) Internal:
2215 Flip syndrome bits on RPR_MEM writes. For diagnostic use only. */
2216 uint64_t autoblow : 1; /**< [ 17: 17](R/W/H) Internal:
2217 Set to initiate burning of defect fuses to fuse macro. Clears when fuses are
2218 blown. */
2219 uint64_t too_many : 1; /**< [ 16: 16](RO/H) Internal:
2220 Set if the sum of fuse repairs and memory defects exceeds 195. */
2221 uint64_t numdefects : 8; /**< [ 15: 8](RO/H) Internal:
2222 After reset/BIST indicates the number of memory defects reported. Defects are
2223 stored in REPAIR_MEM from bit address NUMREPAIRS*21 to (NUMREPAIRS*21 + NUMDEFECTS*21 -
2224 1). */
2225 uint64_t numrepairs : 8; /**< [ 7: 0](R/W) Internal:
2226 Indicates the number of soft repairs to load from repair mem to the memories on
2227 a soft/warm reset. Indicates the number of repairs loaded from efuses to repair mem on a
2228 cold reset. */
2229 #else /* Word 0 - Little Endian */
2230 uint64_t numrepairs : 8; /**< [ 7: 0](R/W) Internal:
2231 Indicates the number of soft repairs to load from repair mem to the memories on
2232 a soft/warm reset. Indicates the number of repairs loaded from efuses to repair mem on a
2233 cold reset. */
2234 uint64_t numdefects : 8; /**< [ 15: 8](RO/H) Internal:
2235 After reset/BIST indicates the number of memory defects reported. Defects are
2236 stored in REPAIR_MEM from bit address NUMREPAIRS*21 to (NUMREPAIRS*21 + NUMDEFECTS*21 -
2237 1). */
2238 uint64_t too_many : 1; /**< [ 16: 16](RO/H) Internal:
2239 Set if the sum of fuse repairs and memory defects exceeds 195. */
2240 uint64_t autoblow : 1; /**< [ 17: 17](R/W/H) Internal:
2241 Set to initiate burning of defect fuses to fuse macro. Clears when fuses are
2242 blown. */
2243 uint64_t rpr_flip_synd : 2; /**< [ 19: 18](R/W/H) Internal:
2244 Flip syndrome bits on RPR_MEM writes. For diagnostic use only. */
2245 uint64_t reserved_20_63 : 44;
2246 #endif /* Word 0 - End */
2247 } cn88xx;
2248 /* struct bdk_mio_fus_soft_repair_s cn83xx; */
2249 };
2250 typedef union bdk_mio_fus_soft_repair bdk_mio_fus_soft_repair_t;
2251
2252 #define BDK_MIO_FUS_SOFT_REPAIR BDK_MIO_FUS_SOFT_REPAIR_FUNC()
2253 static inline uint64_t BDK_MIO_FUS_SOFT_REPAIR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_SOFT_REPAIR_FUNC(void)2254 static inline uint64_t BDK_MIO_FUS_SOFT_REPAIR_FUNC(void)
2255 {
2256 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2257 return 0x87e003001540ll;
2258 __bdk_csr_fatal("MIO_FUS_SOFT_REPAIR", 0, 0, 0, 0, 0);
2259 }
2260
2261 #define typedef_BDK_MIO_FUS_SOFT_REPAIR bdk_mio_fus_soft_repair_t
2262 #define bustype_BDK_MIO_FUS_SOFT_REPAIR BDK_CSR_TYPE_RSL
2263 #define basename_BDK_MIO_FUS_SOFT_REPAIR "MIO_FUS_SOFT_REPAIR"
2264 #define device_bar_BDK_MIO_FUS_SOFT_REPAIR 0x0 /* PF_BAR0 */
2265 #define busnum_BDK_MIO_FUS_SOFT_REPAIR 0
2266 #define arguments_BDK_MIO_FUS_SOFT_REPAIR -1,-1,-1,-1
2267
2268 /**
2269 * Register (RSL) mio_fus_tgg
2270 *
2271 * MIO Fuse TGG Register
2272 * This register exists to support Authentik. Authentik code should read this register, then
2273 * clear VAL to prevent other software from observing the value of the TGG fuses.
2274 *
2275 * Internal:
2276 * INTERNAL: It is never possible to read the TGG fuses via MIO_FUS_RCMD. Whenever the fuse
2277 * corresponding to VAL (TGG\<63\>) is blown, it is not possible to blow any of TGG\<62:0\>. The fuse
2278 * corresponding to VAL must be the one and only lock down bit for TGG\<62:0\> - no other fuse
2279 * lockdown bit can prevent blowing TGG\<62:0\>. It must always be possible to blow the fuse
2280 * corresponding to VAL when it is not already blown. If an Authentik part may be converted to a
2281 * non-Authentik part (via some JTAG mechanism or any other mechanism), it must not be possible
2282 * to read the TGG fuse values from the Authentik part by performing this conversion -\> the reset
2283 * value of VAL should be zero in this converted case.
2284 */
2285 union bdk_mio_fus_tgg
2286 {
2287 uint64_t u;
2288 struct bdk_mio_fus_tgg_s
2289 {
2290 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2291 uint64_t val : 1; /**< [ 63: 63](R/W/H) Software can write VAL to 0, but cannot write VAL to a 1. When VAL = 1, DAT reads
2292 the corresponding TGG fuses. When VAL = 0, DAT reads as 0s. The reset value of
2293 this VAL bit is normally its fuse setting (i.e. TGG\<63\>). */
2294 uint64_t dat : 63; /**< [ 62: 0](RO/H) When VAL = 0, DAT always reads as 0x0, regardless of the value of the TGG\<62:0\>
2295 fuses. When VAL = 1, DAT returns the value of the TGG\<62:0\> fuses. */
2296 #else /* Word 0 - Little Endian */
2297 uint64_t dat : 63; /**< [ 62: 0](RO/H) When VAL = 0, DAT always reads as 0x0, regardless of the value of the TGG\<62:0\>
2298 fuses. When VAL = 1, DAT returns the value of the TGG\<62:0\> fuses. */
2299 uint64_t val : 1; /**< [ 63: 63](R/W/H) Software can write VAL to 0, but cannot write VAL to a 1. When VAL = 1, DAT reads
2300 the corresponding TGG fuses. When VAL = 0, DAT reads as 0s. The reset value of
2301 this VAL bit is normally its fuse setting (i.e. TGG\<63\>). */
2302 #endif /* Word 0 - End */
2303 } s;
2304 /* struct bdk_mio_fus_tgg_s cn; */
2305 };
2306 typedef union bdk_mio_fus_tgg bdk_mio_fus_tgg_t;
2307
2308 #define BDK_MIO_FUS_TGG BDK_MIO_FUS_TGG_FUNC()
2309 static inline uint64_t BDK_MIO_FUS_TGG_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_TGG_FUNC(void)2310 static inline uint64_t BDK_MIO_FUS_TGG_FUNC(void)
2311 {
2312 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2313 return 0x87e003001430ll;
2314 __bdk_csr_fatal("MIO_FUS_TGG", 0, 0, 0, 0, 0);
2315 }
2316
2317 #define typedef_BDK_MIO_FUS_TGG bdk_mio_fus_tgg_t
2318 #define bustype_BDK_MIO_FUS_TGG BDK_CSR_TYPE_RSL
2319 #define basename_BDK_MIO_FUS_TGG "MIO_FUS_TGG"
2320 #define device_bar_BDK_MIO_FUS_TGG 0x0 /* PF_BAR0 */
2321 #define busnum_BDK_MIO_FUS_TGG 0
2322 #define arguments_BDK_MIO_FUS_TGG -1,-1,-1,-1
2323
2324 /**
2325 * Register (RSL) mio_fus_wadr
2326 *
2327 * MIO Fuse Write Address Register
2328 */
2329 union bdk_mio_fus_wadr
2330 {
2331 uint64_t u;
2332 struct bdk_mio_fus_wadr_s
2333 {
2334 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2335 uint64_t reserved_6_63 : 58;
2336 uint64_t addr : 6; /**< [ 5: 0](R/W) Indicates which of the banks of 128 fuses to blow. Software
2337 should not change this field while the FUSF_PROG[PROG] bit is set.
2338 It must wait for the hardware to clear it. */
2339 #else /* Word 0 - Little Endian */
2340 uint64_t addr : 6; /**< [ 5: 0](R/W) Indicates which of the banks of 128 fuses to blow. Software
2341 should not change this field while the FUSF_PROG[PROG] bit is set.
2342 It must wait for the hardware to clear it. */
2343 uint64_t reserved_6_63 : 58;
2344 #endif /* Word 0 - End */
2345 } s;
2346 /* struct bdk_mio_fus_wadr_s cn; */
2347 };
2348 typedef union bdk_mio_fus_wadr bdk_mio_fus_wadr_t;
2349
2350 #define BDK_MIO_FUS_WADR BDK_MIO_FUS_WADR_FUNC()
2351 static inline uint64_t BDK_MIO_FUS_WADR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_MIO_FUS_WADR_FUNC(void)2352 static inline uint64_t BDK_MIO_FUS_WADR_FUNC(void)
2353 {
2354 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
2355 return 0x87e003001508ll;
2356 __bdk_csr_fatal("MIO_FUS_WADR", 0, 0, 0, 0, 0);
2357 }
2358
2359 #define typedef_BDK_MIO_FUS_WADR bdk_mio_fus_wadr_t
2360 #define bustype_BDK_MIO_FUS_WADR BDK_CSR_TYPE_RSL
2361 #define basename_BDK_MIO_FUS_WADR "MIO_FUS_WADR"
2362 #define device_bar_BDK_MIO_FUS_WADR 0x0 /* PF_BAR0 */
2363 #define busnum_BDK_MIO_FUS_WADR 0
2364 #define arguments_BDK_MIO_FUS_WADR -1,-1,-1,-1
2365
2366 #endif /* __BDK_CSRS_MIO_FUS_H__ */
2367