1 #ifndef __BDK_CSRS_L2C_CBC_H__
2 #define __BDK_CSRS_L2C_CBC_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
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31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium L2C_CBC.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration l2c_cbc_bar_e
57 *
58 * L2C CBC Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_L2C_CBC_BAR_E_L2C_CBCX_PF_BAR0(a) (0x87e058000000ll + 0x1000000ll * (a))
62 #define BDK_L2C_CBC_BAR_E_L2C_CBCX_PF_BAR0_SIZE 0x800000ull
63 #define BDK_L2C_CBC_BAR_E_L2C_CBCX_PF_BAR4(a) (0x87e058f00000ll + 0x1000000ll * (a))
64 #define BDK_L2C_CBC_BAR_E_L2C_CBCX_PF_BAR4_SIZE 0x100000ull
65
66 /**
67 * Enumeration l2c_cbc_int_vec_e
68 *
69 * L2C CBC MSI-X Vector Enumeration
70 * Enumerates the MSI-X interrupt vectors.
71 */
72 #define BDK_L2C_CBC_INT_VEC_E_INTS (0)
73
74 /**
75 * Register (RSL) l2c_cbc#_int_ena_w1c
76 *
77 * L2C CBC Interrupt Enable Clear Registers
78 * This register clears interrupt enable bits.
79 */
80 union bdk_l2c_cbcx_int_ena_w1c
81 {
82 uint64_t u;
83 struct bdk_l2c_cbcx_int_ena_w1c_s
84 {
85 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
86 uint64_t reserved_9_63 : 55;
87 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
88 Internal:
89 The CBC global sync timeout only, so not an OCI timeout. */
90 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
91 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
92 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
93 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
94 uint64_t reserved_2_3 : 2;
95 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
96 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
97 #else /* Word 0 - Little Endian */
98 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
99 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
100 uint64_t reserved_2_3 : 2;
101 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
102 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
103 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
104 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
105 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
106 Internal:
107 The CBC global sync timeout only, so not an OCI timeout. */
108 uint64_t reserved_9_63 : 55;
109 #endif /* Word 0 - End */
110 } s;
111 struct bdk_l2c_cbcx_int_ena_w1c_cn88xxp1
112 {
113 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
114 uint64_t reserved_9_63 : 55;
115 uint64_t reserved_8 : 1;
116 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
117 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
118 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
119 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
120 uint64_t reserved_2_3 : 2;
121 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
122 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
123 #else /* Word 0 - Little Endian */
124 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
125 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
126 uint64_t reserved_2_3 : 2;
127 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
128 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
129 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
130 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
131 uint64_t reserved_8 : 1;
132 uint64_t reserved_9_63 : 55;
133 #endif /* Word 0 - End */
134 } cn88xxp1;
135 struct bdk_l2c_cbcx_int_ena_w1c_cn81xx
136 {
137 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
138 uint64_t reserved_9_63 : 55;
139 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[GSYNCTO].
140 Internal:
141 The CBC global sync timeout only, so not an OCI timeout. */
142 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
143 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
144 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[MIBDBE]. */
145 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[MIBSBE]. */
146 uint64_t reserved_2_3 : 2;
147 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[RSDDBE]. */
148 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[RSDSBE]. */
149 #else /* Word 0 - Little Endian */
150 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[RSDSBE]. */
151 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[RSDDBE]. */
152 uint64_t reserved_2_3 : 2;
153 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[MIBSBE]. */
154 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[MIBDBE]. */
155 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
156 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
157 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0)_INT_W1C[GSYNCTO].
158 Internal:
159 The CBC global sync timeout only, so not an OCI timeout. */
160 uint64_t reserved_9_63 : 55;
161 #endif /* Word 0 - End */
162 } cn81xx;
163 struct bdk_l2c_cbcx_int_ena_w1c_cn83xx
164 {
165 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
166 uint64_t reserved_9_63 : 55;
167 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
168 Internal:
169 The CBC global sync timeout only, so not an OCI timeout. */
170 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
171 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
172 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
173 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
174 uint64_t reserved_2_3 : 2;
175 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
176 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
177 #else /* Word 0 - Little Endian */
178 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
179 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
180 uint64_t reserved_2_3 : 2;
181 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
182 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
183 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
184 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
185 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
186 Internal:
187 The CBC global sync timeout only, so not an OCI timeout. */
188 uint64_t reserved_9_63 : 55;
189 #endif /* Word 0 - End */
190 } cn83xx;
191 struct bdk_l2c_cbcx_int_ena_w1c_cn88xxp2
192 {
193 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
194 uint64_t reserved_9_63 : 55;
195 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[GSYNCTO].
196 Internal:
197 The CBC global sync timeout only, so not an OCI timeout. */
198 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
199 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
200 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
201 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
202 uint64_t reserved_2_3 : 2;
203 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
204 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
205 #else /* Word 0 - Little Endian */
206 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
207 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
208 uint64_t reserved_2_3 : 2;
209 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
210 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
211 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
212 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
213 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Reads or clears enable for L2C_CBC(0..3)_INT_W1C[GSYNCTO].
214 Internal:
215 The CBC global sync timeout only, so not an OCI timeout. */
216 uint64_t reserved_9_63 : 55;
217 #endif /* Word 0 - End */
218 } cn88xxp2;
219 };
220 typedef union bdk_l2c_cbcx_int_ena_w1c bdk_l2c_cbcx_int_ena_w1c_t;
221
222 static inline uint64_t BDK_L2C_CBCX_INT_ENA_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_INT_ENA_W1C(unsigned long a)223 static inline uint64_t BDK_L2C_CBCX_INT_ENA_W1C(unsigned long a)
224 {
225 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
226 return 0x87e058060020ll + 0x1000000ll * ((a) & 0x0);
227 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
228 return 0x87e058060020ll + 0x1000000ll * ((a) & 0x1);
229 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
230 return 0x87e058060020ll + 0x1000000ll * ((a) & 0x3);
231 __bdk_csr_fatal("L2C_CBCX_INT_ENA_W1C", 1, a, 0, 0, 0);
232 }
233
234 #define typedef_BDK_L2C_CBCX_INT_ENA_W1C(a) bdk_l2c_cbcx_int_ena_w1c_t
235 #define bustype_BDK_L2C_CBCX_INT_ENA_W1C(a) BDK_CSR_TYPE_RSL
236 #define basename_BDK_L2C_CBCX_INT_ENA_W1C(a) "L2C_CBCX_INT_ENA_W1C"
237 #define device_bar_BDK_L2C_CBCX_INT_ENA_W1C(a) 0x0 /* PF_BAR0 */
238 #define busnum_BDK_L2C_CBCX_INT_ENA_W1C(a) (a)
239 #define arguments_BDK_L2C_CBCX_INT_ENA_W1C(a) (a),-1,-1,-1
240
241 /**
242 * Register (RSL) l2c_cbc#_int_ena_w1s
243 *
244 * L2C CBC Interrupt Enable Set Registers
245 * This register sets interrupt enable bits.
246 */
247 union bdk_l2c_cbcx_int_ena_w1s
248 {
249 uint64_t u;
250 struct bdk_l2c_cbcx_int_ena_w1s_s
251 {
252 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
253 uint64_t reserved_9_63 : 55;
254 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
255 Internal:
256 The CBC global sync timeout only, so not an OCI timeout. */
257 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
258 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
259 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
260 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
261 uint64_t reserved_2_3 : 2;
262 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
263 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
264 #else /* Word 0 - Little Endian */
265 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
266 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
267 uint64_t reserved_2_3 : 2;
268 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
269 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
270 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
271 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
272 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
273 Internal:
274 The CBC global sync timeout only, so not an OCI timeout. */
275 uint64_t reserved_9_63 : 55;
276 #endif /* Word 0 - End */
277 } s;
278 struct bdk_l2c_cbcx_int_ena_w1s_cn88xxp1
279 {
280 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
281 uint64_t reserved_9_63 : 55;
282 uint64_t reserved_8 : 1;
283 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
284 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
285 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
286 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
287 uint64_t reserved_2_3 : 2;
288 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
289 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
290 #else /* Word 0 - Little Endian */
291 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
292 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
293 uint64_t reserved_2_3 : 2;
294 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
295 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
296 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
297 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
298 uint64_t reserved_8 : 1;
299 uint64_t reserved_9_63 : 55;
300 #endif /* Word 0 - End */
301 } cn88xxp1;
302 struct bdk_l2c_cbcx_int_ena_w1s_cn81xx
303 {
304 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
305 uint64_t reserved_9_63 : 55;
306 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[GSYNCTO].
307 Internal:
308 The CBC global sync timeout only, so not an OCI timeout. */
309 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
310 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
311 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[MIBDBE]. */
312 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[MIBSBE]. */
313 uint64_t reserved_2_3 : 2;
314 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[RSDDBE]. */
315 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[RSDSBE]. */
316 #else /* Word 0 - Little Endian */
317 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[RSDSBE]. */
318 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[RSDDBE]. */
319 uint64_t reserved_2_3 : 2;
320 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[MIBSBE]. */
321 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[MIBDBE]. */
322 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
323 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
324 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0)_INT_W1C[GSYNCTO].
325 Internal:
326 The CBC global sync timeout only, so not an OCI timeout. */
327 uint64_t reserved_9_63 : 55;
328 #endif /* Word 0 - End */
329 } cn81xx;
330 struct bdk_l2c_cbcx_int_ena_w1s_cn83xx
331 {
332 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
333 uint64_t reserved_9_63 : 55;
334 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
335 Internal:
336 The CBC global sync timeout only, so not an OCI timeout. */
337 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
338 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
339 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
340 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
341 uint64_t reserved_2_3 : 2;
342 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
343 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
344 #else /* Word 0 - Little Endian */
345 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
346 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
347 uint64_t reserved_2_3 : 2;
348 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
349 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
350 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
351 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
352 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..1)_INT_W1C[GSYNCTO].
353 Internal:
354 The CBC global sync timeout only, so not an OCI timeout. */
355 uint64_t reserved_9_63 : 55;
356 #endif /* Word 0 - End */
357 } cn83xx;
358 struct bdk_l2c_cbcx_int_ena_w1s_cn88xxp2
359 {
360 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
361 uint64_t reserved_9_63 : 55;
362 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[GSYNCTO].
363 Internal:
364 The CBC global sync timeout only, so not an OCI timeout. */
365 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
366 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
367 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
368 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
369 uint64_t reserved_2_3 : 2;
370 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
371 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
372 #else /* Word 0 - Little Endian */
373 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
374 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
375 uint64_t reserved_2_3 : 2;
376 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
377 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
378 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
379 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
380 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets enable for L2C_CBC(0..3)_INT_W1C[GSYNCTO].
381 Internal:
382 The CBC global sync timeout only, so not an OCI timeout. */
383 uint64_t reserved_9_63 : 55;
384 #endif /* Word 0 - End */
385 } cn88xxp2;
386 };
387 typedef union bdk_l2c_cbcx_int_ena_w1s bdk_l2c_cbcx_int_ena_w1s_t;
388
389 static inline uint64_t BDK_L2C_CBCX_INT_ENA_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_INT_ENA_W1S(unsigned long a)390 static inline uint64_t BDK_L2C_CBCX_INT_ENA_W1S(unsigned long a)
391 {
392 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
393 return 0x87e058060028ll + 0x1000000ll * ((a) & 0x0);
394 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
395 return 0x87e058060028ll + 0x1000000ll * ((a) & 0x1);
396 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
397 return 0x87e058060028ll + 0x1000000ll * ((a) & 0x3);
398 __bdk_csr_fatal("L2C_CBCX_INT_ENA_W1S", 1, a, 0, 0, 0);
399 }
400
401 #define typedef_BDK_L2C_CBCX_INT_ENA_W1S(a) bdk_l2c_cbcx_int_ena_w1s_t
402 #define bustype_BDK_L2C_CBCX_INT_ENA_W1S(a) BDK_CSR_TYPE_RSL
403 #define basename_BDK_L2C_CBCX_INT_ENA_W1S(a) "L2C_CBCX_INT_ENA_W1S"
404 #define device_bar_BDK_L2C_CBCX_INT_ENA_W1S(a) 0x0 /* PF_BAR0 */
405 #define busnum_BDK_L2C_CBCX_INT_ENA_W1S(a) (a)
406 #define arguments_BDK_L2C_CBCX_INT_ENA_W1S(a) (a),-1,-1,-1
407
408 /**
409 * Register (RSL) l2c_cbc#_int_w1c
410 *
411 * L2C CBC Interrupt Registers
412 * This register is for CBC-based interrupts.
413 */
414 union bdk_l2c_cbcx_int_w1c
415 {
416 uint64_t u;
417 struct bdk_l2c_cbcx_int_w1c_s
418 {
419 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
420 uint64_t reserved_9_63 : 55;
421 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Global sync timeout. Should never assert, for diagnostic use only.
422 Internal:
423 The CBC global sync timeout only, so not an OCI timeout. */
424 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Illegal I/O write operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
425 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
426 to IOBST, IOBSTP, IOBADDR, IASET, IACLR, IAADD, IASWP, IACAS, and LMTST XMC
427 commands.
428 During normal hardware operation, an indication of a software failure and may be
429 considered fatal. */
430 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Illegal I/O read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
431 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
432 to IOBLD, IASET, IACLR, IAADD, IASWP, and IACAS XMC commands.
433 During normal hardware operation, an indication of a software failure and may be
434 considered fatal. */
435 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) MIB double-bit error occurred. See L2C_CBC()_MIBERR for logged information.
436 An indication of a hardware failure and may be considered fatal. */
437 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) MIB single-bit error occurred. See L2C_CBC()_MIBERR for logged
438 information. Hardware corrected the failure. Software may choose to count these
439 single-bit errors. */
440 uint64_t reserved_2_3 : 2;
441 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) RSD double-bit error occurred. See L2C_CBC()_RSDERR for logged information.
442 An indication of a hardware failure and may be considered fatal. */
443 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) RSD single-bit error occurred. See L2C_CBC()_RSDERR for logged
444 information. Hardware automatically corrected the error. Software may choose to
445 count the number of these single-bit errors. */
446 #else /* Word 0 - Little Endian */
447 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) RSD single-bit error occurred. See L2C_CBC()_RSDERR for logged
448 information. Hardware automatically corrected the error. Software may choose to
449 count the number of these single-bit errors. */
450 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) RSD double-bit error occurred. See L2C_CBC()_RSDERR for logged information.
451 An indication of a hardware failure and may be considered fatal. */
452 uint64_t reserved_2_3 : 2;
453 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) MIB single-bit error occurred. See L2C_CBC()_MIBERR for logged
454 information. Hardware corrected the failure. Software may choose to count these
455 single-bit errors. */
456 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) MIB double-bit error occurred. See L2C_CBC()_MIBERR for logged information.
457 An indication of a hardware failure and may be considered fatal. */
458 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Illegal I/O read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
459 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
460 to IOBLD, IASET, IACLR, IAADD, IASWP, and IACAS XMC commands.
461 During normal hardware operation, an indication of a software failure and may be
462 considered fatal. */
463 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Illegal I/O write operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
464 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
465 to IOBST, IOBSTP, IOBADDR, IASET, IACLR, IAADD, IASWP, IACAS, and LMTST XMC
466 commands.
467 During normal hardware operation, an indication of a software failure and may be
468 considered fatal. */
469 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1C/H) Global sync timeout. Should never assert, for diagnostic use only.
470 Internal:
471 The CBC global sync timeout only, so not an OCI timeout. */
472 uint64_t reserved_9_63 : 55;
473 #endif /* Word 0 - End */
474 } s;
475 struct bdk_l2c_cbcx_int_w1c_cn88xxp1
476 {
477 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
478 uint64_t reserved_9_63 : 55;
479 uint64_t reserved_8 : 1;
480 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Illegal I/O write operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
481 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
482 to IOBST, IOBSTP, IOBADDR, IASET, IACLR, IAADD, IASWP, IACAS, and LMTST XMC
483 commands.
484 During normal hardware operation, an indication of a software failure and may be
485 considered fatal. */
486 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Illegal I/O read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
487 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
488 to IOBLD, IASET, IACLR, IAADD, IASWP, and IACAS XMC commands.
489 During normal hardware operation, an indication of a software failure and may be
490 considered fatal. */
491 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) MIB double-bit error occurred. See L2C_CBC()_MIBERR for logged information.
492 An indication of a hardware failure and may be considered fatal. */
493 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) MIB single-bit error occurred. See L2C_CBC()_MIBERR for logged
494 information. Hardware corrected the failure. Software may choose to count these
495 single-bit errors. */
496 uint64_t reserved_2_3 : 2;
497 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) RSD double-bit error occurred. See L2C_CBC()_RSDERR for logged information.
498 An indication of a hardware failure and may be considered fatal. */
499 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) RSD single-bit error occurred. See L2C_CBC()_RSDERR for logged
500 information. Hardware automatically corrected the error. Software may choose to
501 count the number of these single-bit errors. */
502 #else /* Word 0 - Little Endian */
503 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1C/H) RSD single-bit error occurred. See L2C_CBC()_RSDERR for logged
504 information. Hardware automatically corrected the error. Software may choose to
505 count the number of these single-bit errors. */
506 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1C/H) RSD double-bit error occurred. See L2C_CBC()_RSDERR for logged information.
507 An indication of a hardware failure and may be considered fatal. */
508 uint64_t reserved_2_3 : 2;
509 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1C/H) MIB single-bit error occurred. See L2C_CBC()_MIBERR for logged
510 information. Hardware corrected the failure. Software may choose to count these
511 single-bit errors. */
512 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1C/H) MIB double-bit error occurred. See L2C_CBC()_MIBERR for logged information.
513 An indication of a hardware failure and may be considered fatal. */
514 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1C/H) Illegal I/O read operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
515 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
516 to IOBLD, IASET, IACLR, IAADD, IASWP, and IACAS XMC commands.
517 During normal hardware operation, an indication of a software failure and may be
518 considered fatal. */
519 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1C/H) Illegal I/O write operation to a remote node with L2C_OCI_CTL[ENAOCI][node]
520 clear. See L2C_CBC()_IODISOCIERR for logged information. This interrupt applies
521 to IOBST, IOBSTP, IOBADDR, IASET, IACLR, IAADD, IASWP, IACAS, and LMTST XMC
522 commands.
523 During normal hardware operation, an indication of a software failure and may be
524 considered fatal. */
525 uint64_t reserved_8 : 1;
526 uint64_t reserved_9_63 : 55;
527 #endif /* Word 0 - End */
528 } cn88xxp1;
529 /* struct bdk_l2c_cbcx_int_w1c_s cn81xx; */
530 /* struct bdk_l2c_cbcx_int_w1c_s cn83xx; */
531 /* struct bdk_l2c_cbcx_int_w1c_s cn88xxp2; */
532 };
533 typedef union bdk_l2c_cbcx_int_w1c bdk_l2c_cbcx_int_w1c_t;
534
535 static inline uint64_t BDK_L2C_CBCX_INT_W1C(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_INT_W1C(unsigned long a)536 static inline uint64_t BDK_L2C_CBCX_INT_W1C(unsigned long a)
537 {
538 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
539 return 0x87e058060000ll + 0x1000000ll * ((a) & 0x0);
540 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
541 return 0x87e058060000ll + 0x1000000ll * ((a) & 0x1);
542 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
543 return 0x87e058060000ll + 0x1000000ll * ((a) & 0x3);
544 __bdk_csr_fatal("L2C_CBCX_INT_W1C", 1, a, 0, 0, 0);
545 }
546
547 #define typedef_BDK_L2C_CBCX_INT_W1C(a) bdk_l2c_cbcx_int_w1c_t
548 #define bustype_BDK_L2C_CBCX_INT_W1C(a) BDK_CSR_TYPE_RSL
549 #define basename_BDK_L2C_CBCX_INT_W1C(a) "L2C_CBCX_INT_W1C"
550 #define device_bar_BDK_L2C_CBCX_INT_W1C(a) 0x0 /* PF_BAR0 */
551 #define busnum_BDK_L2C_CBCX_INT_W1C(a) (a)
552 #define arguments_BDK_L2C_CBCX_INT_W1C(a) (a),-1,-1,-1
553
554 /**
555 * Register (RSL) l2c_cbc#_int_w1s
556 *
557 * L2C CBC Interrupt Set Registers
558 * This register sets interrupt bits.
559 */
560 union bdk_l2c_cbcx_int_w1s
561 {
562 uint64_t u;
563 struct bdk_l2c_cbcx_int_w1s_s
564 {
565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
566 uint64_t reserved_9_63 : 55;
567 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[GSYNCTO].
568 Internal:
569 The CBC global sync timeout only, so not an OCI timeout. */
570 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
571 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
572 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
573 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
574 uint64_t reserved_2_3 : 2;
575 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
576 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
577 #else /* Word 0 - Little Endian */
578 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
579 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
580 uint64_t reserved_2_3 : 2;
581 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
582 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
583 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
584 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
585 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[GSYNCTO].
586 Internal:
587 The CBC global sync timeout only, so not an OCI timeout. */
588 uint64_t reserved_9_63 : 55;
589 #endif /* Word 0 - End */
590 } s;
591 struct bdk_l2c_cbcx_int_w1s_cn88xxp1
592 {
593 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
594 uint64_t reserved_9_63 : 55;
595 uint64_t reserved_8 : 1;
596 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
597 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
598 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
599 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
600 uint64_t reserved_2_3 : 2;
601 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
602 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
603 #else /* Word 0 - Little Endian */
604 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
605 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
606 uint64_t reserved_2_3 : 2;
607 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
608 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
609 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
610 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
611 uint64_t reserved_8 : 1;
612 uint64_t reserved_9_63 : 55;
613 #endif /* Word 0 - End */
614 } cn88xxp1;
615 struct bdk_l2c_cbcx_int_w1s_cn81xx
616 {
617 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
618 uint64_t reserved_9_63 : 55;
619 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[GSYNCTO].
620 Internal:
621 The CBC global sync timeout only, so not an OCI timeout. */
622 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
623 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
624 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[MIBDBE]. */
625 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[MIBSBE]. */
626 uint64_t reserved_2_3 : 2;
627 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[RSDDBE]. */
628 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[RSDSBE]. */
629 #else /* Word 0 - Little Endian */
630 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[RSDSBE]. */
631 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[RSDDBE]. */
632 uint64_t reserved_2_3 : 2;
633 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[MIBSBE]. */
634 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[MIBDBE]. */
635 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[IORDDISOCI]. */
636 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[IOWRDISOCI]. */
637 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0)_INT_W1C[GSYNCTO].
638 Internal:
639 The CBC global sync timeout only, so not an OCI timeout. */
640 uint64_t reserved_9_63 : 55;
641 #endif /* Word 0 - End */
642 } cn81xx;
643 struct bdk_l2c_cbcx_int_w1s_cn83xx
644 {
645 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
646 uint64_t reserved_9_63 : 55;
647 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[GSYNCTO].
648 Internal:
649 The CBC global sync timeout only, so not an OCI timeout. */
650 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
651 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
652 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
653 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
654 uint64_t reserved_2_3 : 2;
655 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
656 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
657 #else /* Word 0 - Little Endian */
658 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[RSDSBE]. */
659 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[RSDDBE]. */
660 uint64_t reserved_2_3 : 2;
661 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[MIBSBE]. */
662 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[MIBDBE]. */
663 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[IORDDISOCI]. */
664 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[IOWRDISOCI]. */
665 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..1)_INT_W1C[GSYNCTO].
666 Internal:
667 The CBC global sync timeout only, so not an OCI timeout. */
668 uint64_t reserved_9_63 : 55;
669 #endif /* Word 0 - End */
670 } cn83xx;
671 struct bdk_l2c_cbcx_int_w1s_cn88xxp2
672 {
673 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
674 uint64_t reserved_9_63 : 55;
675 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[GSYNCTO].
676 Internal:
677 The CBC global sync timeout only, so not an OCI timeout. */
678 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
679 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
680 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
681 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
682 uint64_t reserved_2_3 : 2;
683 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
684 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
685 #else /* Word 0 - Little Endian */
686 uint64_t rsdsbe : 1; /**< [ 0: 0](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDSBE]. */
687 uint64_t rsddbe : 1; /**< [ 1: 1](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[RSDDBE]. */
688 uint64_t reserved_2_3 : 2;
689 uint64_t mibsbe : 1; /**< [ 4: 4](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBSBE]. */
690 uint64_t mibdbe : 1; /**< [ 5: 5](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[MIBDBE]. */
691 uint64_t iorddisoci : 1; /**< [ 6: 6](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IORDDISOCI]. */
692 uint64_t iowrdisoci : 1; /**< [ 7: 7](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[IOWRDISOCI]. */
693 uint64_t gsyncto : 1; /**< [ 8: 8](R/W1S/H) Reads or sets L2C_CBC(0..3)_INT_W1C[GSYNCTO].
694 Internal:
695 The CBC global sync timeout only, so not an OCI timeout. */
696 uint64_t reserved_9_63 : 55;
697 #endif /* Word 0 - End */
698 } cn88xxp2;
699 };
700 typedef union bdk_l2c_cbcx_int_w1s bdk_l2c_cbcx_int_w1s_t;
701
702 static inline uint64_t BDK_L2C_CBCX_INT_W1S(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_INT_W1S(unsigned long a)703 static inline uint64_t BDK_L2C_CBCX_INT_W1S(unsigned long a)
704 {
705 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
706 return 0x87e058060008ll + 0x1000000ll * ((a) & 0x0);
707 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
708 return 0x87e058060008ll + 0x1000000ll * ((a) & 0x1);
709 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
710 return 0x87e058060008ll + 0x1000000ll * ((a) & 0x3);
711 __bdk_csr_fatal("L2C_CBCX_INT_W1S", 1, a, 0, 0, 0);
712 }
713
714 #define typedef_BDK_L2C_CBCX_INT_W1S(a) bdk_l2c_cbcx_int_w1s_t
715 #define bustype_BDK_L2C_CBCX_INT_W1S(a) BDK_CSR_TYPE_RSL
716 #define basename_BDK_L2C_CBCX_INT_W1S(a) "L2C_CBCX_INT_W1S"
717 #define device_bar_BDK_L2C_CBCX_INT_W1S(a) 0x0 /* PF_BAR0 */
718 #define busnum_BDK_L2C_CBCX_INT_W1S(a) (a)
719 #define arguments_BDK_L2C_CBCX_INT_W1S(a) (a),-1,-1,-1
720
721 /**
722 * Register (RSL) l2c_cbc#_inv#_pfc
723 *
724 * L2C CBC IOC Performance Counter Registers
725 */
726 union bdk_l2c_cbcx_invx_pfc
727 {
728 uint64_t u;
729 struct bdk_l2c_cbcx_invx_pfc_s
730 {
731 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
732 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
733 #else /* Word 0 - Little Endian */
734 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
735 #endif /* Word 0 - End */
736 } s;
737 /* struct bdk_l2c_cbcx_invx_pfc_s cn; */
738 };
739 typedef union bdk_l2c_cbcx_invx_pfc bdk_l2c_cbcx_invx_pfc_t;
740
741 static inline uint64_t BDK_L2C_CBCX_INVX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_INVX_PFC(unsigned long a,unsigned long b)742 static inline uint64_t BDK_L2C_CBCX_INVX_PFC(unsigned long a, unsigned long b)
743 {
744 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
745 return 0x87e058000020ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x0);
746 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=1)))
747 return 0x87e058000020ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x1);
748 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=1)))
749 return 0x87e058000020ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x1);
750 __bdk_csr_fatal("L2C_CBCX_INVX_PFC", 2, a, b, 0, 0);
751 }
752
753 #define typedef_BDK_L2C_CBCX_INVX_PFC(a,b) bdk_l2c_cbcx_invx_pfc_t
754 #define bustype_BDK_L2C_CBCX_INVX_PFC(a,b) BDK_CSR_TYPE_RSL
755 #define basename_BDK_L2C_CBCX_INVX_PFC(a,b) "L2C_CBCX_INVX_PFC"
756 #define device_bar_BDK_L2C_CBCX_INVX_PFC(a,b) 0x0 /* PF_BAR0 */
757 #define busnum_BDK_L2C_CBCX_INVX_PFC(a,b) (a)
758 #define arguments_BDK_L2C_CBCX_INVX_PFC(a,b) (a),(b),-1,-1
759
760 /**
761 * Register (RSL) l2c_cbc#_ioc#_pfc
762 *
763 * L2C CBC IOC Performance Counter Register
764 */
765 union bdk_l2c_cbcx_iocx_pfc
766 {
767 uint64_t u;
768 struct bdk_l2c_cbcx_iocx_pfc_s
769 {
770 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
771 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
772 #else /* Word 0 - Little Endian */
773 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
774 #endif /* Word 0 - End */
775 } s;
776 /* struct bdk_l2c_cbcx_iocx_pfc_s cn; */
777 };
778 typedef union bdk_l2c_cbcx_iocx_pfc bdk_l2c_cbcx_iocx_pfc_t;
779
780 static inline uint64_t BDK_L2C_CBCX_IOCX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_IOCX_PFC(unsigned long a,unsigned long b)781 static inline uint64_t BDK_L2C_CBCX_IOCX_PFC(unsigned long a, unsigned long b)
782 {
783 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
784 return 0x87e058000028ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x0);
785 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
786 return 0x87e058000028ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x0);
787 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b==0)))
788 return 0x87e058000028ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x0);
789 __bdk_csr_fatal("L2C_CBCX_IOCX_PFC", 2, a, b, 0, 0);
790 }
791
792 #define typedef_BDK_L2C_CBCX_IOCX_PFC(a,b) bdk_l2c_cbcx_iocx_pfc_t
793 #define bustype_BDK_L2C_CBCX_IOCX_PFC(a,b) BDK_CSR_TYPE_RSL
794 #define basename_BDK_L2C_CBCX_IOCX_PFC(a,b) "L2C_CBCX_IOCX_PFC"
795 #define device_bar_BDK_L2C_CBCX_IOCX_PFC(a,b) 0x0 /* PF_BAR0 */
796 #define busnum_BDK_L2C_CBCX_IOCX_PFC(a,b) (a)
797 #define arguments_BDK_L2C_CBCX_IOCX_PFC(a,b) (a),(b),-1,-1
798
799 /**
800 * Register (RSL) l2c_cbc#_ior#_pfc
801 *
802 * L2C CBC IOR Performance Counter Register
803 */
804 union bdk_l2c_cbcx_iorx_pfc
805 {
806 uint64_t u;
807 struct bdk_l2c_cbcx_iorx_pfc_s
808 {
809 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
810 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
811 #else /* Word 0 - Little Endian */
812 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
813 #endif /* Word 0 - End */
814 } s;
815 /* struct bdk_l2c_cbcx_iorx_pfc_s cn; */
816 };
817 typedef union bdk_l2c_cbcx_iorx_pfc bdk_l2c_cbcx_iorx_pfc_t;
818
819 static inline uint64_t BDK_L2C_CBCX_IORX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_IORX_PFC(unsigned long a,unsigned long b)820 static inline uint64_t BDK_L2C_CBCX_IORX_PFC(unsigned long a, unsigned long b)
821 {
822 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
823 return 0x87e058000030ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x0);
824 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
825 return 0x87e058000030ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x0);
826 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b==0)))
827 return 0x87e058000030ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x0);
828 __bdk_csr_fatal("L2C_CBCX_IORX_PFC", 2, a, b, 0, 0);
829 }
830
831 #define typedef_BDK_L2C_CBCX_IORX_PFC(a,b) bdk_l2c_cbcx_iorx_pfc_t
832 #define bustype_BDK_L2C_CBCX_IORX_PFC(a,b) BDK_CSR_TYPE_RSL
833 #define basename_BDK_L2C_CBCX_IORX_PFC(a,b) "L2C_CBCX_IORX_PFC"
834 #define device_bar_BDK_L2C_CBCX_IORX_PFC(a,b) 0x0 /* PF_BAR0 */
835 #define busnum_BDK_L2C_CBCX_IORX_PFC(a,b) (a)
836 #define arguments_BDK_L2C_CBCX_IORX_PFC(a,b) (a),(b),-1,-1
837
838 /**
839 * Register (RSL) l2c_cbc#_msix_pba#
840 *
841 * L2C CBC MSI-X Pending Bit Array Registers
842 * This register is the MSI-X PBA table; the bit number is indexed by the L2C_CBC_INT_VEC_E
843 * enumeration.
844 */
845 union bdk_l2c_cbcx_msix_pbax
846 {
847 uint64_t u;
848 struct bdk_l2c_cbcx_msix_pbax_s
849 {
850 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
851 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated L2C_CBC()_MSIX_VEC()_CTL, enumerated by
852 L2C_CBC_INT_VEC_E. Bits
853 that have no associated L2C_CBC_INT_VEC_E are 0. */
854 #else /* Word 0 - Little Endian */
855 uint64_t pend : 64; /**< [ 63: 0](RO) Pending message for the associated L2C_CBC()_MSIX_VEC()_CTL, enumerated by
856 L2C_CBC_INT_VEC_E. Bits
857 that have no associated L2C_CBC_INT_VEC_E are 0. */
858 #endif /* Word 0 - End */
859 } s;
860 /* struct bdk_l2c_cbcx_msix_pbax_s cn; */
861 };
862 typedef union bdk_l2c_cbcx_msix_pbax bdk_l2c_cbcx_msix_pbax_t;
863
864 static inline uint64_t BDK_L2C_CBCX_MSIX_PBAX(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_MSIX_PBAX(unsigned long a,unsigned long b)865 static inline uint64_t BDK_L2C_CBCX_MSIX_PBAX(unsigned long a, unsigned long b)
866 {
867 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
868 return 0x87e058ff0000ll + 0x1000000ll * ((a) & 0x0) + 8ll * ((b) & 0x0);
869 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
870 return 0x87e058ff0000ll + 0x1000000ll * ((a) & 0x1) + 8ll * ((b) & 0x0);
871 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b==0)))
872 return 0x87e058ff0000ll + 0x1000000ll * ((a) & 0x3) + 8ll * ((b) & 0x0);
873 __bdk_csr_fatal("L2C_CBCX_MSIX_PBAX", 2, a, b, 0, 0);
874 }
875
876 #define typedef_BDK_L2C_CBCX_MSIX_PBAX(a,b) bdk_l2c_cbcx_msix_pbax_t
877 #define bustype_BDK_L2C_CBCX_MSIX_PBAX(a,b) BDK_CSR_TYPE_RSL
878 #define basename_BDK_L2C_CBCX_MSIX_PBAX(a,b) "L2C_CBCX_MSIX_PBAX"
879 #define device_bar_BDK_L2C_CBCX_MSIX_PBAX(a,b) 0x4 /* PF_BAR4 */
880 #define busnum_BDK_L2C_CBCX_MSIX_PBAX(a,b) (a)
881 #define arguments_BDK_L2C_CBCX_MSIX_PBAX(a,b) (a),(b),-1,-1
882
883 /**
884 * Register (RSL) l2c_cbc#_msix_vec#_addr
885 *
886 * L2C CBC MSI-X Vector-Table Address Register
887 * This register is the MSI-X vector table, indexed by the L2C_CBC_INT_VEC_E enumeration.
888 */
889 union bdk_l2c_cbcx_msix_vecx_addr
890 {
891 uint64_t u;
892 struct bdk_l2c_cbcx_msix_vecx_addr_s
893 {
894 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
895 uint64_t reserved_49_63 : 15;
896 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
897 uint64_t reserved_1 : 1;
898 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
899 0 = This vector may be read or written by either secure or nonsecure states.
900 1 = This vector's L2C_CBC()_MSIX_VEC()_ADDR, L2C_CBC()_MSIX_VEC()_CTL, and corresponding
901 bit of L2C_CBC()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
902 by the nonsecure world.
903
904 If PCCPF_L2C_CBC_VSEC_SCTL[MSIX_SEC] (for documentation, see
905 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
906 set, all vectors are secure and function as if [SECVEC] was set. */
907 #else /* Word 0 - Little Endian */
908 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
909 0 = This vector may be read or written by either secure or nonsecure states.
910 1 = This vector's L2C_CBC()_MSIX_VEC()_ADDR, L2C_CBC()_MSIX_VEC()_CTL, and corresponding
911 bit of L2C_CBC()_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
912 by the nonsecure world.
913
914 If PCCPF_L2C_CBC_VSEC_SCTL[MSIX_SEC] (for documentation, see
915 PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
916 set, all vectors are secure and function as if [SECVEC] was set. */
917 uint64_t reserved_1 : 1;
918 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
919 uint64_t reserved_49_63 : 15;
920 #endif /* Word 0 - End */
921 } s;
922 /* struct bdk_l2c_cbcx_msix_vecx_addr_s cn; */
923 };
924 typedef union bdk_l2c_cbcx_msix_vecx_addr bdk_l2c_cbcx_msix_vecx_addr_t;
925
926 static inline uint64_t BDK_L2C_CBCX_MSIX_VECX_ADDR(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_MSIX_VECX_ADDR(unsigned long a,unsigned long b)927 static inline uint64_t BDK_L2C_CBCX_MSIX_VECX_ADDR(unsigned long a, unsigned long b)
928 {
929 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
930 return 0x87e058f00000ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
931 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
932 return 0x87e058f00000ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
933 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b==0)))
934 return 0x87e058f00000ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
935 __bdk_csr_fatal("L2C_CBCX_MSIX_VECX_ADDR", 2, a, b, 0, 0);
936 }
937
938 #define typedef_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) bdk_l2c_cbcx_msix_vecx_addr_t
939 #define bustype_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) BDK_CSR_TYPE_RSL
940 #define basename_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) "L2C_CBCX_MSIX_VECX_ADDR"
941 #define device_bar_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) 0x4 /* PF_BAR4 */
942 #define busnum_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) (a)
943 #define arguments_BDK_L2C_CBCX_MSIX_VECX_ADDR(a,b) (a),(b),-1,-1
944
945 /**
946 * Register (RSL) l2c_cbc#_msix_vec#_ctl
947 *
948 * L2C CBC MSI-X Vector-Table Control and Data Register
949 * This register is the MSI-X vector table, indexed by the L2C_CBC_INT_VEC_E enumeration.
950 */
951 union bdk_l2c_cbcx_msix_vecx_ctl
952 {
953 uint64_t u;
954 struct bdk_l2c_cbcx_msix_vecx_ctl_s
955 {
956 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
957 uint64_t reserved_33_63 : 31;
958 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
959 uint64_t reserved_20_31 : 12;
960 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
961 #else /* Word 0 - Little Endian */
962 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
963 uint64_t reserved_20_31 : 12;
964 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts are sent to this vector. */
965 uint64_t reserved_33_63 : 31;
966 #endif /* Word 0 - End */
967 } s;
968 /* struct bdk_l2c_cbcx_msix_vecx_ctl_s cn; */
969 };
970 typedef union bdk_l2c_cbcx_msix_vecx_ctl bdk_l2c_cbcx_msix_vecx_ctl_t;
971
972 static inline uint64_t BDK_L2C_CBCX_MSIX_VECX_CTL(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_MSIX_VECX_CTL(unsigned long a,unsigned long b)973 static inline uint64_t BDK_L2C_CBCX_MSIX_VECX_CTL(unsigned long a, unsigned long b)
974 {
975 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b==0)))
976 return 0x87e058f00008ll + 0x1000000ll * ((a) & 0x0) + 0x10ll * ((b) & 0x0);
977 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b==0)))
978 return 0x87e058f00008ll + 0x1000000ll * ((a) & 0x1) + 0x10ll * ((b) & 0x0);
979 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b==0)))
980 return 0x87e058f00008ll + 0x1000000ll * ((a) & 0x3) + 0x10ll * ((b) & 0x0);
981 __bdk_csr_fatal("L2C_CBCX_MSIX_VECX_CTL", 2, a, b, 0, 0);
982 }
983
984 #define typedef_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) bdk_l2c_cbcx_msix_vecx_ctl_t
985 #define bustype_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) BDK_CSR_TYPE_RSL
986 #define basename_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) "L2C_CBCX_MSIX_VECX_CTL"
987 #define device_bar_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) 0x4 /* PF_BAR4 */
988 #define busnum_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) (a)
989 #define arguments_BDK_L2C_CBCX_MSIX_VECX_CTL(a,b) (a),(b),-1,-1
990
991 /**
992 * Register (RSL) l2c_cbc#_rsc#_pfc
993 *
994 * L2C CBC COMMIT Bus Performance Counter Registers
995 */
996 union bdk_l2c_cbcx_rscx_pfc
997 {
998 uint64_t u;
999 struct bdk_l2c_cbcx_rscx_pfc_s
1000 {
1001 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1002 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1003 #else /* Word 0 - Little Endian */
1004 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1005 #endif /* Word 0 - End */
1006 } s;
1007 /* struct bdk_l2c_cbcx_rscx_pfc_s cn; */
1008 };
1009 typedef union bdk_l2c_cbcx_rscx_pfc bdk_l2c_cbcx_rscx_pfc_t;
1010
1011 static inline uint64_t BDK_L2C_CBCX_RSCX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_RSCX_PFC(unsigned long a,unsigned long b)1012 static inline uint64_t BDK_L2C_CBCX_RSCX_PFC(unsigned long a, unsigned long b)
1013 {
1014 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=1)))
1015 return 0x87e058000010ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x1);
1016 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=2)))
1017 return 0x87e058000010ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x3);
1018 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=2)))
1019 return 0x87e058000010ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x3);
1020 __bdk_csr_fatal("L2C_CBCX_RSCX_PFC", 2, a, b, 0, 0);
1021 }
1022
1023 #define typedef_BDK_L2C_CBCX_RSCX_PFC(a,b) bdk_l2c_cbcx_rscx_pfc_t
1024 #define bustype_BDK_L2C_CBCX_RSCX_PFC(a,b) BDK_CSR_TYPE_RSL
1025 #define basename_BDK_L2C_CBCX_RSCX_PFC(a,b) "L2C_CBCX_RSCX_PFC"
1026 #define device_bar_BDK_L2C_CBCX_RSCX_PFC(a,b) 0x0 /* PF_BAR0 */
1027 #define busnum_BDK_L2C_CBCX_RSCX_PFC(a,b) (a)
1028 #define arguments_BDK_L2C_CBCX_RSCX_PFC(a,b) (a),(b),-1,-1
1029
1030 /**
1031 * Register (RSL) l2c_cbc#_rsd#_pfc
1032 *
1033 * L2C CBC FILL Bus Performance Counter Registers
1034 */
1035 union bdk_l2c_cbcx_rsdx_pfc
1036 {
1037 uint64_t u;
1038 struct bdk_l2c_cbcx_rsdx_pfc_s
1039 {
1040 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1041 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1042 #else /* Word 0 - Little Endian */
1043 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1044 #endif /* Word 0 - End */
1045 } s;
1046 /* struct bdk_l2c_cbcx_rsdx_pfc_s cn; */
1047 };
1048 typedef union bdk_l2c_cbcx_rsdx_pfc bdk_l2c_cbcx_rsdx_pfc_t;
1049
1050 static inline uint64_t BDK_L2C_CBCX_RSDX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_RSDX_PFC(unsigned long a,unsigned long b)1051 static inline uint64_t BDK_L2C_CBCX_RSDX_PFC(unsigned long a, unsigned long b)
1052 {
1053 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=1)))
1054 return 0x87e058000018ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x1);
1055 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=2)))
1056 return 0x87e058000018ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x3);
1057 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=2)))
1058 return 0x87e058000018ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x3);
1059 __bdk_csr_fatal("L2C_CBCX_RSDX_PFC", 2, a, b, 0, 0);
1060 }
1061
1062 #define typedef_BDK_L2C_CBCX_RSDX_PFC(a,b) bdk_l2c_cbcx_rsdx_pfc_t
1063 #define bustype_BDK_L2C_CBCX_RSDX_PFC(a,b) BDK_CSR_TYPE_RSL
1064 #define basename_BDK_L2C_CBCX_RSDX_PFC(a,b) "L2C_CBCX_RSDX_PFC"
1065 #define device_bar_BDK_L2C_CBCX_RSDX_PFC(a,b) 0x0 /* PF_BAR0 */
1066 #define busnum_BDK_L2C_CBCX_RSDX_PFC(a,b) (a)
1067 #define arguments_BDK_L2C_CBCX_RSDX_PFC(a,b) (a),(b),-1,-1
1068
1069 /**
1070 * Register (RSL) l2c_cbc#_scratch
1071 *
1072 * INTERNAL: L2C CBC General Purpose Scratch Register
1073 *
1074 * These registers are only reset by hardware during chip cold reset. The values of the CSR
1075 * fields in these registers do not change during chip warm or soft resets.
1076 */
1077 union bdk_l2c_cbcx_scratch
1078 {
1079 uint64_t u;
1080 struct bdk_l2c_cbcx_scratch_s
1081 {
1082 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1083 uint64_t reserved_8_63 : 56;
1084 uint64_t scratch : 7; /**< [ 7: 1](R/W) General purpose scratch register. */
1085 uint64_t invdly : 1; /**< [ 0: 0](R/W) Delays all invalidates for 9 cycles after a broadcast invalidate. */
1086 #else /* Word 0 - Little Endian */
1087 uint64_t invdly : 1; /**< [ 0: 0](R/W) Delays all invalidates for 9 cycles after a broadcast invalidate. */
1088 uint64_t scratch : 7; /**< [ 7: 1](R/W) General purpose scratch register. */
1089 uint64_t reserved_8_63 : 56;
1090 #endif /* Word 0 - End */
1091 } s;
1092 /* struct bdk_l2c_cbcx_scratch_s cn; */
1093 };
1094 typedef union bdk_l2c_cbcx_scratch bdk_l2c_cbcx_scratch_t;
1095
1096 static inline uint64_t BDK_L2C_CBCX_SCRATCH(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_SCRATCH(unsigned long a)1097 static inline uint64_t BDK_L2C_CBCX_SCRATCH(unsigned long a)
1098 {
1099 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1100 return 0x87e0580d0000ll + 0x1000000ll * ((a) & 0x0);
1101 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1102 return 0x87e0580d0000ll + 0x1000000ll * ((a) & 0x1);
1103 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
1104 return 0x87e0580d0000ll + 0x1000000ll * ((a) & 0x3);
1105 __bdk_csr_fatal("L2C_CBCX_SCRATCH", 1, a, 0, 0, 0);
1106 }
1107
1108 #define typedef_BDK_L2C_CBCX_SCRATCH(a) bdk_l2c_cbcx_scratch_t
1109 #define bustype_BDK_L2C_CBCX_SCRATCH(a) BDK_CSR_TYPE_RSL
1110 #define basename_BDK_L2C_CBCX_SCRATCH(a) "L2C_CBCX_SCRATCH"
1111 #define device_bar_BDK_L2C_CBCX_SCRATCH(a) 0x0 /* PF_BAR0 */
1112 #define busnum_BDK_L2C_CBCX_SCRATCH(a) (a)
1113 #define arguments_BDK_L2C_CBCX_SCRATCH(a) (a),-1,-1,-1
1114
1115 /**
1116 * Register (RSL) l2c_cbc#_xmc#_pfc
1117 *
1118 * L2C CBC ADD bus Performance Counter Registers
1119 */
1120 union bdk_l2c_cbcx_xmcx_pfc
1121 {
1122 uint64_t u;
1123 struct bdk_l2c_cbcx_xmcx_pfc_s
1124 {
1125 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1126 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1127 #else /* Word 0 - Little Endian */
1128 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1129 #endif /* Word 0 - End */
1130 } s;
1131 /* struct bdk_l2c_cbcx_xmcx_pfc_s cn; */
1132 };
1133 typedef union bdk_l2c_cbcx_xmcx_pfc bdk_l2c_cbcx_xmcx_pfc_t;
1134
1135 static inline uint64_t BDK_L2C_CBCX_XMCX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_XMCX_PFC(unsigned long a,unsigned long b)1136 static inline uint64_t BDK_L2C_CBCX_XMCX_PFC(unsigned long a, unsigned long b)
1137 {
1138 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=1)))
1139 return 0x87e058000000ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x1);
1140 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=2)))
1141 return 0x87e058000000ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x3);
1142 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=2)))
1143 return 0x87e058000000ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x3);
1144 __bdk_csr_fatal("L2C_CBCX_XMCX_PFC", 2, a, b, 0, 0);
1145 }
1146
1147 #define typedef_BDK_L2C_CBCX_XMCX_PFC(a,b) bdk_l2c_cbcx_xmcx_pfc_t
1148 #define bustype_BDK_L2C_CBCX_XMCX_PFC(a,b) BDK_CSR_TYPE_RSL
1149 #define basename_BDK_L2C_CBCX_XMCX_PFC(a,b) "L2C_CBCX_XMCX_PFC"
1150 #define device_bar_BDK_L2C_CBCX_XMCX_PFC(a,b) 0x0 /* PF_BAR0 */
1151 #define busnum_BDK_L2C_CBCX_XMCX_PFC(a,b) (a)
1152 #define arguments_BDK_L2C_CBCX_XMCX_PFC(a,b) (a),(b),-1,-1
1153
1154 /**
1155 * Register (RSL) l2c_cbc#_xmc_cmd
1156 *
1157 * L2C CBC ADD Bus Command Register
1158 * Note the following:
1159 *
1160 * The ADD bus command chosen must not be a IOB-destined command or operation is UNDEFINED.
1161 *
1162 * The ADD bus command will have SID forced to IOB, DID forced to L2C, no virtualization checks
1163 * performed (always pass), and xmdmsk forced to 0. Note that this implies that commands that
1164 * REQUIRE a STORE cycle (STP, STC, SAA, FAA, FAS) should not be used or the results are
1165 * unpredictable. The sid = IOB means that the way partitioning used for the command is
1166 * L2C_WPAR_IOB(). L2C_QOS_PP() are not used for these commands.
1167 *
1168 * Any FILL responses generated by the ADD bus command are ignored. Generated STINs, however,
1169 * will correctly invalidate the required cores.
1170 *
1171 * A write that arrives while [INUSE] is set will block until [INUSE] clears. This
1172 * gives software two options when needing to issue a stream of write operations to L2C_XMC_CMD:
1173 * polling on [INUSE], or allowing hardware to handle the interlock -- at the expense of
1174 * locking up the RSL bus for potentially tens of cycles at a time while waiting for an available
1175 * LFB/VAB entry. Note that when [INUSE] clears, the only ordering it implies is that
1176 * software can send another ADD bus command. Subsequent commands may complete out of order
1177 * relative to earlier commands.
1178 *
1179 * The address written to L2C_XMC_CMD is a physical address. L2C performs index
1180 * aliasing (if enabled) on the written address and uses that for the command. This
1181 * index-aliased address is what is returned on a read of L2C_XMC_CMD.
1182 */
1183 union bdk_l2c_cbcx_xmc_cmd
1184 {
1185 uint64_t u;
1186 struct bdk_l2c_cbcx_xmc_cmd_s
1187 {
1188 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1189 uint64_t inuse : 1; /**< [ 63: 63](RO/H) Set to 1 by hardware upon receiving a write; cleared when command has issued (not
1190 necessarily completed, but ordered relative to other traffic) and hardware can accept
1191 another command. */
1192 uint64_t cmd : 7; /**< [ 62: 56](R/W) Command to use for simulated ADD bus request. A new request can be accepted. */
1193 uint64_t reserved_49_55 : 7;
1194 uint64_t nonsec : 1; /**< [ 48: 48](R/W) Nonsecure bit to use for simulated ADD bus request. */
1195 uint64_t reserved_47 : 1;
1196 uint64_t qos : 3; /**< [ 46: 44](R/W) QOS level to use for simulated ADD bus request. */
1197 uint64_t reserved_42_43 : 2;
1198 uint64_t node : 2; /**< [ 41: 40](R/W) CCPI node to use for simulated ADD bus request. */
1199 uint64_t addr : 40; /**< [ 39: 0](R/W) Address to use for simulated ADD bus request. (The address written to
1200 L2C_CBC()_XMC_CMD is a physical address. L2C performs index aliasing (if
1201 enabled) on the written address and uses that for the command. This
1202 index-aliased address is what is returned on a read of L2C_CBC()_XMC_CMD.) */
1203 #else /* Word 0 - Little Endian */
1204 uint64_t addr : 40; /**< [ 39: 0](R/W) Address to use for simulated ADD bus request. (The address written to
1205 L2C_CBC()_XMC_CMD is a physical address. L2C performs index aliasing (if
1206 enabled) on the written address and uses that for the command. This
1207 index-aliased address is what is returned on a read of L2C_CBC()_XMC_CMD.) */
1208 uint64_t node : 2; /**< [ 41: 40](R/W) CCPI node to use for simulated ADD bus request. */
1209 uint64_t reserved_42_43 : 2;
1210 uint64_t qos : 3; /**< [ 46: 44](R/W) QOS level to use for simulated ADD bus request. */
1211 uint64_t reserved_47 : 1;
1212 uint64_t nonsec : 1; /**< [ 48: 48](R/W) Nonsecure bit to use for simulated ADD bus request. */
1213 uint64_t reserved_49_55 : 7;
1214 uint64_t cmd : 7; /**< [ 62: 56](R/W) Command to use for simulated ADD bus request. A new request can be accepted. */
1215 uint64_t inuse : 1; /**< [ 63: 63](RO/H) Set to 1 by hardware upon receiving a write; cleared when command has issued (not
1216 necessarily completed, but ordered relative to other traffic) and hardware can accept
1217 another command. */
1218 #endif /* Word 0 - End */
1219 } s;
1220 /* struct bdk_l2c_cbcx_xmc_cmd_s cn; */
1221 };
1222 typedef union bdk_l2c_cbcx_xmc_cmd bdk_l2c_cbcx_xmc_cmd_t;
1223
1224 static inline uint64_t BDK_L2C_CBCX_XMC_CMD(unsigned long a) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_XMC_CMD(unsigned long a)1225 static inline uint64_t BDK_L2C_CBCX_XMC_CMD(unsigned long a)
1226 {
1227 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && (a==0))
1228 return 0x87e0580c0000ll + 0x1000000ll * ((a) & 0x0);
1229 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && (a<=1))
1230 return 0x87e0580c0000ll + 0x1000000ll * ((a) & 0x1);
1231 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && (a<=3))
1232 return 0x87e0580c0000ll + 0x1000000ll * ((a) & 0x3);
1233 __bdk_csr_fatal("L2C_CBCX_XMC_CMD", 1, a, 0, 0, 0);
1234 }
1235
1236 #define typedef_BDK_L2C_CBCX_XMC_CMD(a) bdk_l2c_cbcx_xmc_cmd_t
1237 #define bustype_BDK_L2C_CBCX_XMC_CMD(a) BDK_CSR_TYPE_RSL
1238 #define basename_BDK_L2C_CBCX_XMC_CMD(a) "L2C_CBCX_XMC_CMD"
1239 #define device_bar_BDK_L2C_CBCX_XMC_CMD(a) 0x0 /* PF_BAR0 */
1240 #define busnum_BDK_L2C_CBCX_XMC_CMD(a) (a)
1241 #define arguments_BDK_L2C_CBCX_XMC_CMD(a) (a),-1,-1,-1
1242
1243 /**
1244 * Register (RSL) l2c_cbc#_xmd#_pfc
1245 *
1246 * L2C CBC STORE bus Performance Counter Registers
1247 */
1248 union bdk_l2c_cbcx_xmdx_pfc
1249 {
1250 uint64_t u;
1251 struct bdk_l2c_cbcx_xmdx_pfc_s
1252 {
1253 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1254 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1255 #else /* Word 0 - Little Endian */
1256 uint64_t count : 64; /**< [ 63: 0](R/W/H) Current counter value. */
1257 #endif /* Word 0 - End */
1258 } s;
1259 /* struct bdk_l2c_cbcx_xmdx_pfc_s cn; */
1260 };
1261 typedef union bdk_l2c_cbcx_xmdx_pfc bdk_l2c_cbcx_xmdx_pfc_t;
1262
1263 static inline uint64_t BDK_L2C_CBCX_XMDX_PFC(unsigned long a, unsigned long b) __attribute__ ((pure, always_inline));
BDK_L2C_CBCX_XMDX_PFC(unsigned long a,unsigned long b)1264 static inline uint64_t BDK_L2C_CBCX_XMDX_PFC(unsigned long a, unsigned long b)
1265 {
1266 if (CAVIUM_IS_MODEL(CAVIUM_CN81XX) && ((a==0) && (b<=1)))
1267 return 0x87e058000008ll + 0x1000000ll * ((a) & 0x0) + 0x40ll * ((b) & 0x1);
1268 if (CAVIUM_IS_MODEL(CAVIUM_CN83XX) && ((a<=1) && (b<=2)))
1269 return 0x87e058000008ll + 0x1000000ll * ((a) & 0x1) + 0x40ll * ((b) & 0x3);
1270 if (CAVIUM_IS_MODEL(CAVIUM_CN88XX) && ((a<=3) && (b<=2)))
1271 return 0x87e058000008ll + 0x1000000ll * ((a) & 0x3) + 0x40ll * ((b) & 0x3);
1272 __bdk_csr_fatal("L2C_CBCX_XMDX_PFC", 2, a, b, 0, 0);
1273 }
1274
1275 #define typedef_BDK_L2C_CBCX_XMDX_PFC(a,b) bdk_l2c_cbcx_xmdx_pfc_t
1276 #define bustype_BDK_L2C_CBCX_XMDX_PFC(a,b) BDK_CSR_TYPE_RSL
1277 #define basename_BDK_L2C_CBCX_XMDX_PFC(a,b) "L2C_CBCX_XMDX_PFC"
1278 #define device_bar_BDK_L2C_CBCX_XMDX_PFC(a,b) 0x0 /* PF_BAR0 */
1279 #define busnum_BDK_L2C_CBCX_XMDX_PFC(a,b) (a)
1280 #define arguments_BDK_L2C_CBCX_XMDX_PFC(a,b) (a),(b),-1,-1
1281
1282 #endif /* __BDK_CSRS_L2C_CBC_H__ */
1283