1 #ifndef __BDK_CSRS_GTI_H__
2 #define __BDK_CSRS_GTI_H__
3 /* This file is auto-generated. Do not edit */
4
5 /***********************license start***************
6 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights
7 * reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are
12 * met:
13 *
14 * * Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 *
17 * * Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials provided
20 * with the distribution.
21
22 * * Neither the name of Cavium Inc. nor the names of
23 * its contributors may be used to endorse or promote products
24 * derived from this software without specific prior written
25 * permission.
26
27 * This Software, including technical data, may be subject to U.S. export control
28 * laws, including the U.S. Export Administration Act and its associated
29 * regulations, and may be subject to export or import regulations in other
30 * countries.
31
32 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
33 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
34 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
35 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
36 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
37 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
38 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
39 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
40 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
41 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
42 ***********************license end**************************************/
43
44
45 /**
46 * @file
47 *
48 * Configuration and status register (CSR) address and type definitions for
49 * Cavium GTI.
50 *
51 * This file is auto generated. Do not edit.
52 *
53 */
54
55 /**
56 * Enumeration gti_bar_e
57 *
58 * GTI Base Address Register Enumeration
59 * Enumerates the base address registers.
60 */
61 #define BDK_GTI_BAR_E_GTI_PF_BAR0_CN8 (0x844000000000ll)
62 #define BDK_GTI_BAR_E_GTI_PF_BAR0_CN8_SIZE 0x800000ull
63 #define BDK_GTI_BAR_E_GTI_PF_BAR0_CN9 (0x844000000000ll)
64 #define BDK_GTI_BAR_E_GTI_PF_BAR0_CN9_SIZE 0x100000ull
65 #define BDK_GTI_BAR_E_GTI_PF_BAR4 (0x84400f000000ll)
66 #define BDK_GTI_BAR_E_GTI_PF_BAR4_SIZE 0x100000ull
67
68 /**
69 * Enumeration gti_int_vec_e
70 *
71 * GTI MSI-X Vector Enumeration
72 * Enumerates the MSI-X interrupt vectors.
73 */
74 #define BDK_GTI_INT_VEC_E_CORE_WDOGX_DEL3T(a) (0xa + (a))
75 #define BDK_GTI_INT_VEC_E_CORE_WDOGX_INT_CN8(a) (0x3a + (a))
76 #define BDK_GTI_INT_VEC_E_CORE_WDOGX_INT_CN9(a) (0x40 + (a))
77 #define BDK_GTI_INT_VEC_E_ERROR (8)
78 #define BDK_GTI_INT_VEC_E_MAILBOX_RX (7)
79 #define BDK_GTI_INT_VEC_E_SECURE_WATCHDOG (4)
80 #define BDK_GTI_INT_VEC_E_SECURE_WATCHDOG_CLEAR (5)
81 #define BDK_GTI_INT_VEC_E_SPARE (9)
82 #define BDK_GTI_INT_VEC_E_TX_TIMESTAMP (6)
83 #define BDK_GTI_INT_VEC_E_WAKE (0)
84 #define BDK_GTI_INT_VEC_E_WAKE_CLEAR (1)
85 #define BDK_GTI_INT_VEC_E_WATCHDOG (2)
86 #define BDK_GTI_INT_VEC_E_WATCHDOG_CLEAR (3)
87
88 /**
89 * Register (NCB) gti_bp_test
90 *
91 * INTERNAL: GTI Backpressure Test Register
92 */
93 union bdk_gti_bp_test
94 {
95 uint64_t u;
96 struct bdk_gti_bp_test_s
97 {
98 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
99 uint64_t enable : 2; /**< [ 63: 62](R/W) Enable test mode. For diagnostic use only.
100 Internal:
101 Once a bit is set, random backpressure is generated
102 at the corresponding point to allow for more frequent backpressure.
103 \<63\> = Limit the NCBO request FIFO, backpressure doing CSR access to GTI registers
104 \<62\> = Limit the NCBI response FIFO, backpressure doing response for NCBO requests */
105 uint64_t reserved_24_61 : 38;
106 uint64_t bp_cfg : 4; /**< [ 23: 20](R/W) Backpressure weight. For diagnostic use only.
107 Internal:
108 There are 2 backpressure configuration bits per enable, with the two bits
109 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
110 0x3=25% of the time.
111 \<23:22\> = Config 1.
112 \<21:20\> = Config 0. */
113 uint64_t reserved_12_19 : 8;
114 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
115 #else /* Word 0 - Little Endian */
116 uint64_t lfsr_freq : 12; /**< [ 11: 0](R/W) Test LFSR update frequency in coprocessor-clocks minus one. */
117 uint64_t reserved_12_19 : 8;
118 uint64_t bp_cfg : 4; /**< [ 23: 20](R/W) Backpressure weight. For diagnostic use only.
119 Internal:
120 There are 2 backpressure configuration bits per enable, with the two bits
121 defined as 0x0=100% of the time, 0x1=75% of the time, 0x2=50% of the time,
122 0x3=25% of the time.
123 \<23:22\> = Config 1.
124 \<21:20\> = Config 0. */
125 uint64_t reserved_24_61 : 38;
126 uint64_t enable : 2; /**< [ 63: 62](R/W) Enable test mode. For diagnostic use only.
127 Internal:
128 Once a bit is set, random backpressure is generated
129 at the corresponding point to allow for more frequent backpressure.
130 \<63\> = Limit the NCBO request FIFO, backpressure doing CSR access to GTI registers
131 \<62\> = Limit the NCBI response FIFO, backpressure doing response for NCBO requests */
132 #endif /* Word 0 - End */
133 } s;
134 /* struct bdk_gti_bp_test_s cn; */
135 };
136 typedef union bdk_gti_bp_test bdk_gti_bp_test_t;
137
138 #define BDK_GTI_BP_TEST BDK_GTI_BP_TEST_FUNC()
139 static inline uint64_t BDK_GTI_BP_TEST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BP_TEST_FUNC(void)140 static inline uint64_t BDK_GTI_BP_TEST_FUNC(void)
141 {
142 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
143 return 0x8440000e0008ll;
144 __bdk_csr_fatal("GTI_BP_TEST", 0, 0, 0, 0, 0);
145 }
146
147 #define typedef_BDK_GTI_BP_TEST bdk_gti_bp_test_t
148 #define bustype_BDK_GTI_BP_TEST BDK_CSR_TYPE_NCB
149 #define basename_BDK_GTI_BP_TEST "GTI_BP_TEST"
150 #define device_bar_BDK_GTI_BP_TEST 0x0 /* PF_BAR0 */
151 #define busnum_BDK_GTI_BP_TEST 0
152 #define arguments_BDK_GTI_BP_TEST -1,-1,-1,-1
153
154 /**
155 * Register (NCB32b) gti_bz_cidr0
156 *
157 * GTI Base Component Identification Register 0
158 */
159 union bdk_gti_bz_cidr0
160 {
161 uint32_t u;
162 struct bdk_gti_bz_cidr0_s
163 {
164 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
165 uint32_t reserved_8_31 : 24;
166 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
167 #else /* Word 0 - Little Endian */
168 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
169 uint32_t reserved_8_31 : 24;
170 #endif /* Word 0 - End */
171 } s;
172 /* struct bdk_gti_bz_cidr0_s cn; */
173 };
174 typedef union bdk_gti_bz_cidr0 bdk_gti_bz_cidr0_t;
175
176 #define BDK_GTI_BZ_CIDR0 BDK_GTI_BZ_CIDR0_FUNC()
177 static inline uint64_t BDK_GTI_BZ_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CIDR0_FUNC(void)178 static inline uint64_t BDK_GTI_BZ_CIDR0_FUNC(void)
179 {
180 return 0x844000030ff0ll;
181 }
182
183 #define typedef_BDK_GTI_BZ_CIDR0 bdk_gti_bz_cidr0_t
184 #define bustype_BDK_GTI_BZ_CIDR0 BDK_CSR_TYPE_NCB32b
185 #define basename_BDK_GTI_BZ_CIDR0 "GTI_BZ_CIDR0"
186 #define device_bar_BDK_GTI_BZ_CIDR0 0x0 /* PF_BAR0 */
187 #define busnum_BDK_GTI_BZ_CIDR0 0
188 #define arguments_BDK_GTI_BZ_CIDR0 -1,-1,-1,-1
189
190 /**
191 * Register (NCB32b) gti_bz_cidr1
192 *
193 * GTI Base Component Identification Register 1
194 */
195 union bdk_gti_bz_cidr1
196 {
197 uint32_t u;
198 struct bdk_gti_bz_cidr1_s
199 {
200 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
201 uint32_t reserved_8_31 : 24;
202 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
203 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
204 #else /* Word 0 - Little Endian */
205 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
206 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
207 uint32_t reserved_8_31 : 24;
208 #endif /* Word 0 - End */
209 } s;
210 /* struct bdk_gti_bz_cidr1_s cn; */
211 };
212 typedef union bdk_gti_bz_cidr1 bdk_gti_bz_cidr1_t;
213
214 #define BDK_GTI_BZ_CIDR1 BDK_GTI_BZ_CIDR1_FUNC()
215 static inline uint64_t BDK_GTI_BZ_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CIDR1_FUNC(void)216 static inline uint64_t BDK_GTI_BZ_CIDR1_FUNC(void)
217 {
218 return 0x844000030ff4ll;
219 }
220
221 #define typedef_BDK_GTI_BZ_CIDR1 bdk_gti_bz_cidr1_t
222 #define bustype_BDK_GTI_BZ_CIDR1 BDK_CSR_TYPE_NCB32b
223 #define basename_BDK_GTI_BZ_CIDR1 "GTI_BZ_CIDR1"
224 #define device_bar_BDK_GTI_BZ_CIDR1 0x0 /* PF_BAR0 */
225 #define busnum_BDK_GTI_BZ_CIDR1 0
226 #define arguments_BDK_GTI_BZ_CIDR1 -1,-1,-1,-1
227
228 /**
229 * Register (NCB32b) gti_bz_cidr2
230 *
231 * GTI Base Component Identification Register 2
232 */
233 union bdk_gti_bz_cidr2
234 {
235 uint32_t u;
236 struct bdk_gti_bz_cidr2_s
237 {
238 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
239 uint32_t reserved_8_31 : 24;
240 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
241 #else /* Word 0 - Little Endian */
242 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
243 uint32_t reserved_8_31 : 24;
244 #endif /* Word 0 - End */
245 } s;
246 /* struct bdk_gti_bz_cidr2_s cn; */
247 };
248 typedef union bdk_gti_bz_cidr2 bdk_gti_bz_cidr2_t;
249
250 #define BDK_GTI_BZ_CIDR2 BDK_GTI_BZ_CIDR2_FUNC()
251 static inline uint64_t BDK_GTI_BZ_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CIDR2_FUNC(void)252 static inline uint64_t BDK_GTI_BZ_CIDR2_FUNC(void)
253 {
254 return 0x844000030ff8ll;
255 }
256
257 #define typedef_BDK_GTI_BZ_CIDR2 bdk_gti_bz_cidr2_t
258 #define bustype_BDK_GTI_BZ_CIDR2 BDK_CSR_TYPE_NCB32b
259 #define basename_BDK_GTI_BZ_CIDR2 "GTI_BZ_CIDR2"
260 #define device_bar_BDK_GTI_BZ_CIDR2 0x0 /* PF_BAR0 */
261 #define busnum_BDK_GTI_BZ_CIDR2 0
262 #define arguments_BDK_GTI_BZ_CIDR2 -1,-1,-1,-1
263
264 /**
265 * Register (NCB32b) gti_bz_cidr3
266 *
267 * GTI Base Component Identification Register 3
268 */
269 union bdk_gti_bz_cidr3
270 {
271 uint32_t u;
272 struct bdk_gti_bz_cidr3_s
273 {
274 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
275 uint32_t reserved_8_31 : 24;
276 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
277 #else /* Word 0 - Little Endian */
278 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
279 uint32_t reserved_8_31 : 24;
280 #endif /* Word 0 - End */
281 } s;
282 /* struct bdk_gti_bz_cidr3_s cn; */
283 };
284 typedef union bdk_gti_bz_cidr3 bdk_gti_bz_cidr3_t;
285
286 #define BDK_GTI_BZ_CIDR3 BDK_GTI_BZ_CIDR3_FUNC()
287 static inline uint64_t BDK_GTI_BZ_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CIDR3_FUNC(void)288 static inline uint64_t BDK_GTI_BZ_CIDR3_FUNC(void)
289 {
290 return 0x844000030ffcll;
291 }
292
293 #define typedef_BDK_GTI_BZ_CIDR3 bdk_gti_bz_cidr3_t
294 #define bustype_BDK_GTI_BZ_CIDR3 BDK_CSR_TYPE_NCB32b
295 #define basename_BDK_GTI_BZ_CIDR3 "GTI_BZ_CIDR3"
296 #define device_bar_BDK_GTI_BZ_CIDR3 0x0 /* PF_BAR0 */
297 #define busnum_BDK_GTI_BZ_CIDR3 0
298 #define arguments_BDK_GTI_BZ_CIDR3 -1,-1,-1,-1
299
300 /**
301 * Register (NCB32b) gti_bz_cntp_ctl
302 *
303 * GTI Base Physical Timer Control Register
304 */
305 union bdk_gti_bz_cntp_ctl
306 {
307 uint32_t u;
308 struct bdk_gti_bz_cntp_ctl_s
309 {
310 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
311 uint32_t reserved_3_31 : 29;
312 uint32_t istatus : 1; /**< [ 2: 2](RO/H) Status. */
313 uint32_t imask : 1; /**< [ 1: 1](R/W) Mask. */
314 uint32_t enable : 1; /**< [ 0: 0](R/W) Enable. */
315 #else /* Word 0 - Little Endian */
316 uint32_t enable : 1; /**< [ 0: 0](R/W) Enable. */
317 uint32_t imask : 1; /**< [ 1: 1](R/W) Mask. */
318 uint32_t istatus : 1; /**< [ 2: 2](RO/H) Status. */
319 uint32_t reserved_3_31 : 29;
320 #endif /* Word 0 - End */
321 } s;
322 /* struct bdk_gti_bz_cntp_ctl_s cn; */
323 };
324 typedef union bdk_gti_bz_cntp_ctl bdk_gti_bz_cntp_ctl_t;
325
326 #define BDK_GTI_BZ_CNTP_CTL BDK_GTI_BZ_CNTP_CTL_FUNC()
327 static inline uint64_t BDK_GTI_BZ_CNTP_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CNTP_CTL_FUNC(void)328 static inline uint64_t BDK_GTI_BZ_CNTP_CTL_FUNC(void)
329 {
330 return 0x84400003002cll;
331 }
332
333 #define typedef_BDK_GTI_BZ_CNTP_CTL bdk_gti_bz_cntp_ctl_t
334 #define bustype_BDK_GTI_BZ_CNTP_CTL BDK_CSR_TYPE_NCB32b
335 #define basename_BDK_GTI_BZ_CNTP_CTL "GTI_BZ_CNTP_CTL"
336 #define device_bar_BDK_GTI_BZ_CNTP_CTL 0x0 /* PF_BAR0 */
337 #define busnum_BDK_GTI_BZ_CNTP_CTL 0
338 #define arguments_BDK_GTI_BZ_CNTP_CTL -1,-1,-1,-1
339
340 /**
341 * Register (NCB) gti_bz_cntp_cval
342 *
343 * GTI Base Physical Timer Compare Value Register
344 */
345 union bdk_gti_bz_cntp_cval
346 {
347 uint64_t u;
348 struct bdk_gti_bz_cntp_cval_s
349 {
350 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
351 uint64_t data : 64; /**< [ 63: 0](R/W/H) Physical timer compare value. */
352 #else /* Word 0 - Little Endian */
353 uint64_t data : 64; /**< [ 63: 0](R/W/H) Physical timer compare value. */
354 #endif /* Word 0 - End */
355 } s;
356 /* struct bdk_gti_bz_cntp_cval_s cn; */
357 };
358 typedef union bdk_gti_bz_cntp_cval bdk_gti_bz_cntp_cval_t;
359
360 #define BDK_GTI_BZ_CNTP_CVAL BDK_GTI_BZ_CNTP_CVAL_FUNC()
361 static inline uint64_t BDK_GTI_BZ_CNTP_CVAL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CNTP_CVAL_FUNC(void)362 static inline uint64_t BDK_GTI_BZ_CNTP_CVAL_FUNC(void)
363 {
364 return 0x844000030020ll;
365 }
366
367 #define typedef_BDK_GTI_BZ_CNTP_CVAL bdk_gti_bz_cntp_cval_t
368 #define bustype_BDK_GTI_BZ_CNTP_CVAL BDK_CSR_TYPE_NCB
369 #define basename_BDK_GTI_BZ_CNTP_CVAL "GTI_BZ_CNTP_CVAL"
370 #define device_bar_BDK_GTI_BZ_CNTP_CVAL 0x0 /* PF_BAR0 */
371 #define busnum_BDK_GTI_BZ_CNTP_CVAL 0
372 #define arguments_BDK_GTI_BZ_CNTP_CVAL -1,-1,-1,-1
373
374 /**
375 * Register (NCB32b) gti_bz_cntp_tval
376 *
377 * GTI Base Physical Timer Timer Value Register
378 */
379 union bdk_gti_bz_cntp_tval
380 {
381 uint32_t u;
382 struct bdk_gti_bz_cntp_tval_s
383 {
384 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
385 uint32_t timervalue : 32; /**< [ 31: 0](R/W/H) Physical timer timer value. */
386 #else /* Word 0 - Little Endian */
387 uint32_t timervalue : 32; /**< [ 31: 0](R/W/H) Physical timer timer value. */
388 #endif /* Word 0 - End */
389 } s;
390 /* struct bdk_gti_bz_cntp_tval_s cn; */
391 };
392 typedef union bdk_gti_bz_cntp_tval bdk_gti_bz_cntp_tval_t;
393
394 #define BDK_GTI_BZ_CNTP_TVAL BDK_GTI_BZ_CNTP_TVAL_FUNC()
395 static inline uint64_t BDK_GTI_BZ_CNTP_TVAL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_CNTP_TVAL_FUNC(void)396 static inline uint64_t BDK_GTI_BZ_CNTP_TVAL_FUNC(void)
397 {
398 return 0x844000030028ll;
399 }
400
401 #define typedef_BDK_GTI_BZ_CNTP_TVAL bdk_gti_bz_cntp_tval_t
402 #define bustype_BDK_GTI_BZ_CNTP_TVAL BDK_CSR_TYPE_NCB32b
403 #define basename_BDK_GTI_BZ_CNTP_TVAL "GTI_BZ_CNTP_TVAL"
404 #define device_bar_BDK_GTI_BZ_CNTP_TVAL 0x0 /* PF_BAR0 */
405 #define busnum_BDK_GTI_BZ_CNTP_TVAL 0
406 #define arguments_BDK_GTI_BZ_CNTP_TVAL -1,-1,-1,-1
407
408 /**
409 * Register (NCB32b) gti_bz_pidr0
410 *
411 * GTI Base Peripheral Identification Register 0
412 */
413 union bdk_gti_bz_pidr0
414 {
415 uint32_t u;
416 struct bdk_gti_bz_pidr0_s
417 {
418 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
419 uint32_t reserved_8_31 : 24;
420 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_BZ. */
421 #else /* Word 0 - Little Endian */
422 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_BZ. */
423 uint32_t reserved_8_31 : 24;
424 #endif /* Word 0 - End */
425 } s;
426 /* struct bdk_gti_bz_pidr0_s cn; */
427 };
428 typedef union bdk_gti_bz_pidr0 bdk_gti_bz_pidr0_t;
429
430 #define BDK_GTI_BZ_PIDR0 BDK_GTI_BZ_PIDR0_FUNC()
431 static inline uint64_t BDK_GTI_BZ_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR0_FUNC(void)432 static inline uint64_t BDK_GTI_BZ_PIDR0_FUNC(void)
433 {
434 return 0x844000030fe0ll;
435 }
436
437 #define typedef_BDK_GTI_BZ_PIDR0 bdk_gti_bz_pidr0_t
438 #define bustype_BDK_GTI_BZ_PIDR0 BDK_CSR_TYPE_NCB32b
439 #define basename_BDK_GTI_BZ_PIDR0 "GTI_BZ_PIDR0"
440 #define device_bar_BDK_GTI_BZ_PIDR0 0x0 /* PF_BAR0 */
441 #define busnum_BDK_GTI_BZ_PIDR0 0
442 #define arguments_BDK_GTI_BZ_PIDR0 -1,-1,-1,-1
443
444 /**
445 * Register (NCB32b) gti_bz_pidr1
446 *
447 * GTI Base Peripheral Identification Register 1
448 */
449 union bdk_gti_bz_pidr1
450 {
451 uint32_t u;
452 struct bdk_gti_bz_pidr1_s
453 {
454 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
455 uint32_t reserved_8_31 : 24;
456 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
457 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
458 #else /* Word 0 - Little Endian */
459 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
460 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
461 uint32_t reserved_8_31 : 24;
462 #endif /* Word 0 - End */
463 } s;
464 /* struct bdk_gti_bz_pidr1_s cn; */
465 };
466 typedef union bdk_gti_bz_pidr1 bdk_gti_bz_pidr1_t;
467
468 #define BDK_GTI_BZ_PIDR1 BDK_GTI_BZ_PIDR1_FUNC()
469 static inline uint64_t BDK_GTI_BZ_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR1_FUNC(void)470 static inline uint64_t BDK_GTI_BZ_PIDR1_FUNC(void)
471 {
472 return 0x844000030fe4ll;
473 }
474
475 #define typedef_BDK_GTI_BZ_PIDR1 bdk_gti_bz_pidr1_t
476 #define bustype_BDK_GTI_BZ_PIDR1 BDK_CSR_TYPE_NCB32b
477 #define basename_BDK_GTI_BZ_PIDR1 "GTI_BZ_PIDR1"
478 #define device_bar_BDK_GTI_BZ_PIDR1 0x0 /* PF_BAR0 */
479 #define busnum_BDK_GTI_BZ_PIDR1 0
480 #define arguments_BDK_GTI_BZ_PIDR1 -1,-1,-1,-1
481
482 /**
483 * Register (NCB32b) gti_bz_pidr2
484 *
485 * GTI Base Peripheral Identification Register 2
486 */
487 union bdk_gti_bz_pidr2
488 {
489 uint32_t u;
490 struct bdk_gti_bz_pidr2_s
491 {
492 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
493 uint32_t reserved_8_31 : 24;
494 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
495 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
496 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
497 #else /* Word 0 - Little Endian */
498 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
499 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
500 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
501 uint32_t reserved_8_31 : 24;
502 #endif /* Word 0 - End */
503 } s;
504 /* struct bdk_gti_bz_pidr2_s cn; */
505 };
506 typedef union bdk_gti_bz_pidr2 bdk_gti_bz_pidr2_t;
507
508 #define BDK_GTI_BZ_PIDR2 BDK_GTI_BZ_PIDR2_FUNC()
509 static inline uint64_t BDK_GTI_BZ_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR2_FUNC(void)510 static inline uint64_t BDK_GTI_BZ_PIDR2_FUNC(void)
511 {
512 return 0x844000030fe8ll;
513 }
514
515 #define typedef_BDK_GTI_BZ_PIDR2 bdk_gti_bz_pidr2_t
516 #define bustype_BDK_GTI_BZ_PIDR2 BDK_CSR_TYPE_NCB32b
517 #define basename_BDK_GTI_BZ_PIDR2 "GTI_BZ_PIDR2"
518 #define device_bar_BDK_GTI_BZ_PIDR2 0x0 /* PF_BAR0 */
519 #define busnum_BDK_GTI_BZ_PIDR2 0
520 #define arguments_BDK_GTI_BZ_PIDR2 -1,-1,-1,-1
521
522 /**
523 * Register (NCB32b) gti_bz_pidr3
524 *
525 * GTI Base Peripheral Identification Register 3
526 */
527 union bdk_gti_bz_pidr3
528 {
529 uint32_t u;
530 struct bdk_gti_bz_pidr3_s
531 {
532 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
533 uint32_t reserved_8_31 : 24;
534 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
535 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
536 product, major and minor pass numbers. */
537 #else /* Word 0 - Little Endian */
538 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
539 product, major and minor pass numbers. */
540 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
541 uint32_t reserved_8_31 : 24;
542 #endif /* Word 0 - End */
543 } s;
544 /* struct bdk_gti_bz_pidr3_s cn; */
545 };
546 typedef union bdk_gti_bz_pidr3 bdk_gti_bz_pidr3_t;
547
548 #define BDK_GTI_BZ_PIDR3 BDK_GTI_BZ_PIDR3_FUNC()
549 static inline uint64_t BDK_GTI_BZ_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR3_FUNC(void)550 static inline uint64_t BDK_GTI_BZ_PIDR3_FUNC(void)
551 {
552 return 0x844000030fecll;
553 }
554
555 #define typedef_BDK_GTI_BZ_PIDR3 bdk_gti_bz_pidr3_t
556 #define bustype_BDK_GTI_BZ_PIDR3 BDK_CSR_TYPE_NCB32b
557 #define basename_BDK_GTI_BZ_PIDR3 "GTI_BZ_PIDR3"
558 #define device_bar_BDK_GTI_BZ_PIDR3 0x0 /* PF_BAR0 */
559 #define busnum_BDK_GTI_BZ_PIDR3 0
560 #define arguments_BDK_GTI_BZ_PIDR3 -1,-1,-1,-1
561
562 /**
563 * Register (NCB32b) gti_bz_pidr4
564 *
565 * GTI Base Peripheral Identification Register 4
566 */
567 union bdk_gti_bz_pidr4
568 {
569 uint32_t u;
570 struct bdk_gti_bz_pidr4_s
571 {
572 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
573 uint32_t reserved_8_31 : 24;
574 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
575 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
576 #else /* Word 0 - Little Endian */
577 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
578 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
579 uint32_t reserved_8_31 : 24;
580 #endif /* Word 0 - End */
581 } s;
582 /* struct bdk_gti_bz_pidr4_s cn; */
583 };
584 typedef union bdk_gti_bz_pidr4 bdk_gti_bz_pidr4_t;
585
586 #define BDK_GTI_BZ_PIDR4 BDK_GTI_BZ_PIDR4_FUNC()
587 static inline uint64_t BDK_GTI_BZ_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR4_FUNC(void)588 static inline uint64_t BDK_GTI_BZ_PIDR4_FUNC(void)
589 {
590 return 0x844000030fd0ll;
591 }
592
593 #define typedef_BDK_GTI_BZ_PIDR4 bdk_gti_bz_pidr4_t
594 #define bustype_BDK_GTI_BZ_PIDR4 BDK_CSR_TYPE_NCB32b
595 #define basename_BDK_GTI_BZ_PIDR4 "GTI_BZ_PIDR4"
596 #define device_bar_BDK_GTI_BZ_PIDR4 0x0 /* PF_BAR0 */
597 #define busnum_BDK_GTI_BZ_PIDR4 0
598 #define arguments_BDK_GTI_BZ_PIDR4 -1,-1,-1,-1
599
600 /**
601 * Register (NCB32b) gti_bz_pidr5
602 *
603 * GTI Base Peripheral Identification Register 5
604 */
605 union bdk_gti_bz_pidr5
606 {
607 uint32_t u;
608 struct bdk_gti_bz_pidr5_s
609 {
610 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
611 uint32_t reserved_0_31 : 32;
612 #else /* Word 0 - Little Endian */
613 uint32_t reserved_0_31 : 32;
614 #endif /* Word 0 - End */
615 } s;
616 /* struct bdk_gti_bz_pidr5_s cn; */
617 };
618 typedef union bdk_gti_bz_pidr5 bdk_gti_bz_pidr5_t;
619
620 #define BDK_GTI_BZ_PIDR5 BDK_GTI_BZ_PIDR5_FUNC()
621 static inline uint64_t BDK_GTI_BZ_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR5_FUNC(void)622 static inline uint64_t BDK_GTI_BZ_PIDR5_FUNC(void)
623 {
624 return 0x844000030fd4ll;
625 }
626
627 #define typedef_BDK_GTI_BZ_PIDR5 bdk_gti_bz_pidr5_t
628 #define bustype_BDK_GTI_BZ_PIDR5 BDK_CSR_TYPE_NCB32b
629 #define basename_BDK_GTI_BZ_PIDR5 "GTI_BZ_PIDR5"
630 #define device_bar_BDK_GTI_BZ_PIDR5 0x0 /* PF_BAR0 */
631 #define busnum_BDK_GTI_BZ_PIDR5 0
632 #define arguments_BDK_GTI_BZ_PIDR5 -1,-1,-1,-1
633
634 /**
635 * Register (NCB32b) gti_bz_pidr6
636 *
637 * GTI Base Peripheral Identification Register 6
638 */
639 union bdk_gti_bz_pidr6
640 {
641 uint32_t u;
642 struct bdk_gti_bz_pidr6_s
643 {
644 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
645 uint32_t reserved_0_31 : 32;
646 #else /* Word 0 - Little Endian */
647 uint32_t reserved_0_31 : 32;
648 #endif /* Word 0 - End */
649 } s;
650 /* struct bdk_gti_bz_pidr6_s cn; */
651 };
652 typedef union bdk_gti_bz_pidr6 bdk_gti_bz_pidr6_t;
653
654 #define BDK_GTI_BZ_PIDR6 BDK_GTI_BZ_PIDR6_FUNC()
655 static inline uint64_t BDK_GTI_BZ_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR6_FUNC(void)656 static inline uint64_t BDK_GTI_BZ_PIDR6_FUNC(void)
657 {
658 return 0x844000030fd8ll;
659 }
660
661 #define typedef_BDK_GTI_BZ_PIDR6 bdk_gti_bz_pidr6_t
662 #define bustype_BDK_GTI_BZ_PIDR6 BDK_CSR_TYPE_NCB32b
663 #define basename_BDK_GTI_BZ_PIDR6 "GTI_BZ_PIDR6"
664 #define device_bar_BDK_GTI_BZ_PIDR6 0x0 /* PF_BAR0 */
665 #define busnum_BDK_GTI_BZ_PIDR6 0
666 #define arguments_BDK_GTI_BZ_PIDR6 -1,-1,-1,-1
667
668 /**
669 * Register (NCB32b) gti_bz_pidr7
670 *
671 * GTI Base Peripheral Identification Register 7
672 */
673 union bdk_gti_bz_pidr7
674 {
675 uint32_t u;
676 struct bdk_gti_bz_pidr7_s
677 {
678 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
679 uint32_t reserved_0_31 : 32;
680 #else /* Word 0 - Little Endian */
681 uint32_t reserved_0_31 : 32;
682 #endif /* Word 0 - End */
683 } s;
684 /* struct bdk_gti_bz_pidr7_s cn; */
685 };
686 typedef union bdk_gti_bz_pidr7 bdk_gti_bz_pidr7_t;
687
688 #define BDK_GTI_BZ_PIDR7 BDK_GTI_BZ_PIDR7_FUNC()
689 static inline uint64_t BDK_GTI_BZ_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_BZ_PIDR7_FUNC(void)690 static inline uint64_t BDK_GTI_BZ_PIDR7_FUNC(void)
691 {
692 return 0x844000030fdcll;
693 }
694
695 #define typedef_BDK_GTI_BZ_PIDR7 bdk_gti_bz_pidr7_t
696 #define bustype_BDK_GTI_BZ_PIDR7 BDK_CSR_TYPE_NCB32b
697 #define basename_BDK_GTI_BZ_PIDR7 "GTI_BZ_PIDR7"
698 #define device_bar_BDK_GTI_BZ_PIDR7 0x0 /* PF_BAR0 */
699 #define busnum_BDK_GTI_BZ_PIDR7 0
700 #define arguments_BDK_GTI_BZ_PIDR7 -1,-1,-1,-1
701
702 /**
703 * Register (NCB32b) gti_cc_cidr0
704 *
705 * GTI Counter Control Component Identification Secure Register 0
706 */
707 union bdk_gti_cc_cidr0
708 {
709 uint32_t u;
710 struct bdk_gti_cc_cidr0_s
711 {
712 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
713 uint32_t reserved_8_31 : 24;
714 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
715 #else /* Word 0 - Little Endian */
716 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
717 uint32_t reserved_8_31 : 24;
718 #endif /* Word 0 - End */
719 } s;
720 /* struct bdk_gti_cc_cidr0_s cn; */
721 };
722 typedef union bdk_gti_cc_cidr0 bdk_gti_cc_cidr0_t;
723
724 #define BDK_GTI_CC_CIDR0 BDK_GTI_CC_CIDR0_FUNC()
725 static inline uint64_t BDK_GTI_CC_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CIDR0_FUNC(void)726 static inline uint64_t BDK_GTI_CC_CIDR0_FUNC(void)
727 {
728 return 0x844000000ff0ll;
729 }
730
731 #define typedef_BDK_GTI_CC_CIDR0 bdk_gti_cc_cidr0_t
732 #define bustype_BDK_GTI_CC_CIDR0 BDK_CSR_TYPE_NCB32b
733 #define basename_BDK_GTI_CC_CIDR0 "GTI_CC_CIDR0"
734 #define device_bar_BDK_GTI_CC_CIDR0 0x0 /* PF_BAR0 */
735 #define busnum_BDK_GTI_CC_CIDR0 0
736 #define arguments_BDK_GTI_CC_CIDR0 -1,-1,-1,-1
737
738 /**
739 * Register (NCB32b) gti_cc_cidr1
740 *
741 * GTI Counter Control Component Identification Secure Register 1
742 */
743 union bdk_gti_cc_cidr1
744 {
745 uint32_t u;
746 struct bdk_gti_cc_cidr1_s
747 {
748 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
749 uint32_t reserved_8_31 : 24;
750 uint32_t cclass : 4; /**< [ 7: 4](SRO) Component class. */
751 uint32_t preamble : 4; /**< [ 3: 0](SRO) Preamble identification value. */
752 #else /* Word 0 - Little Endian */
753 uint32_t preamble : 4; /**< [ 3: 0](SRO) Preamble identification value. */
754 uint32_t cclass : 4; /**< [ 7: 4](SRO) Component class. */
755 uint32_t reserved_8_31 : 24;
756 #endif /* Word 0 - End */
757 } s;
758 /* struct bdk_gti_cc_cidr1_s cn; */
759 };
760 typedef union bdk_gti_cc_cidr1 bdk_gti_cc_cidr1_t;
761
762 #define BDK_GTI_CC_CIDR1 BDK_GTI_CC_CIDR1_FUNC()
763 static inline uint64_t BDK_GTI_CC_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CIDR1_FUNC(void)764 static inline uint64_t BDK_GTI_CC_CIDR1_FUNC(void)
765 {
766 return 0x844000000ff4ll;
767 }
768
769 #define typedef_BDK_GTI_CC_CIDR1 bdk_gti_cc_cidr1_t
770 #define bustype_BDK_GTI_CC_CIDR1 BDK_CSR_TYPE_NCB32b
771 #define basename_BDK_GTI_CC_CIDR1 "GTI_CC_CIDR1"
772 #define device_bar_BDK_GTI_CC_CIDR1 0x0 /* PF_BAR0 */
773 #define busnum_BDK_GTI_CC_CIDR1 0
774 #define arguments_BDK_GTI_CC_CIDR1 -1,-1,-1,-1
775
776 /**
777 * Register (NCB32b) gti_cc_cidr2
778 *
779 * GTI Counter Control Component Identification Secure Register 2
780 */
781 union bdk_gti_cc_cidr2
782 {
783 uint32_t u;
784 struct bdk_gti_cc_cidr2_s
785 {
786 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
787 uint32_t reserved_8_31 : 24;
788 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
789 #else /* Word 0 - Little Endian */
790 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
791 uint32_t reserved_8_31 : 24;
792 #endif /* Word 0 - End */
793 } s;
794 /* struct bdk_gti_cc_cidr2_s cn; */
795 };
796 typedef union bdk_gti_cc_cidr2 bdk_gti_cc_cidr2_t;
797
798 #define BDK_GTI_CC_CIDR2 BDK_GTI_CC_CIDR2_FUNC()
799 static inline uint64_t BDK_GTI_CC_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CIDR2_FUNC(void)800 static inline uint64_t BDK_GTI_CC_CIDR2_FUNC(void)
801 {
802 return 0x844000000ff8ll;
803 }
804
805 #define typedef_BDK_GTI_CC_CIDR2 bdk_gti_cc_cidr2_t
806 #define bustype_BDK_GTI_CC_CIDR2 BDK_CSR_TYPE_NCB32b
807 #define basename_BDK_GTI_CC_CIDR2 "GTI_CC_CIDR2"
808 #define device_bar_BDK_GTI_CC_CIDR2 0x0 /* PF_BAR0 */
809 #define busnum_BDK_GTI_CC_CIDR2 0
810 #define arguments_BDK_GTI_CC_CIDR2 -1,-1,-1,-1
811
812 /**
813 * Register (NCB32b) gti_cc_cidr3
814 *
815 * GTI Counter Control Component Identification Secure Register 3
816 */
817 union bdk_gti_cc_cidr3
818 {
819 uint32_t u;
820 struct bdk_gti_cc_cidr3_s
821 {
822 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
823 uint32_t reserved_8_31 : 24;
824 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
825 #else /* Word 0 - Little Endian */
826 uint32_t preamble : 8; /**< [ 7: 0](SRO) Preamble identification value. */
827 uint32_t reserved_8_31 : 24;
828 #endif /* Word 0 - End */
829 } s;
830 /* struct bdk_gti_cc_cidr3_s cn; */
831 };
832 typedef union bdk_gti_cc_cidr3 bdk_gti_cc_cidr3_t;
833
834 #define BDK_GTI_CC_CIDR3 BDK_GTI_CC_CIDR3_FUNC()
835 static inline uint64_t BDK_GTI_CC_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CIDR3_FUNC(void)836 static inline uint64_t BDK_GTI_CC_CIDR3_FUNC(void)
837 {
838 return 0x844000000ffcll;
839 }
840
841 #define typedef_BDK_GTI_CC_CIDR3 bdk_gti_cc_cidr3_t
842 #define bustype_BDK_GTI_CC_CIDR3 BDK_CSR_TYPE_NCB32b
843 #define basename_BDK_GTI_CC_CIDR3 "GTI_CC_CIDR3"
844 #define device_bar_BDK_GTI_CC_CIDR3 0x0 /* PF_BAR0 */
845 #define busnum_BDK_GTI_CC_CIDR3 0
846 #define arguments_BDK_GTI_CC_CIDR3 -1,-1,-1,-1
847
848 /**
849 * Register (NCB) gti_cc_cntadd
850 *
851 * GTI Counter Control Atomic Add Secure Register
852 * Implementation defined register.
853 */
854 union bdk_gti_cc_cntadd
855 {
856 uint64_t u;
857 struct bdk_gti_cc_cntadd_s
858 {
859 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
860 uint64_t cntadd : 64; /**< [ 63: 0](SWO) The value written to [CNTADD] is atomically added to GTI_CC_CNTCV. */
861 #else /* Word 0 - Little Endian */
862 uint64_t cntadd : 64; /**< [ 63: 0](SWO) The value written to [CNTADD] is atomically added to GTI_CC_CNTCV. */
863 #endif /* Word 0 - End */
864 } s;
865 /* struct bdk_gti_cc_cntadd_s cn; */
866 };
867 typedef union bdk_gti_cc_cntadd bdk_gti_cc_cntadd_t;
868
869 #define BDK_GTI_CC_CNTADD BDK_GTI_CC_CNTADD_FUNC()
870 static inline uint64_t BDK_GTI_CC_CNTADD_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTADD_FUNC(void)871 static inline uint64_t BDK_GTI_CC_CNTADD_FUNC(void)
872 {
873 return 0x8440000000c8ll;
874 }
875
876 #define typedef_BDK_GTI_CC_CNTADD bdk_gti_cc_cntadd_t
877 #define bustype_BDK_GTI_CC_CNTADD BDK_CSR_TYPE_NCB
878 #define basename_BDK_GTI_CC_CNTADD "GTI_CC_CNTADD"
879 #define device_bar_BDK_GTI_CC_CNTADD 0x0 /* PF_BAR0 */
880 #define busnum_BDK_GTI_CC_CNTADD 0
881 #define arguments_BDK_GTI_CC_CNTADD -1,-1,-1,-1
882
883 /**
884 * Register (NCB32b) gti_cc_cntcr
885 *
886 * GTI Counter Control Secure Register
887 */
888 union bdk_gti_cc_cntcr
889 {
890 uint32_t u;
891 struct bdk_gti_cc_cntcr_s
892 {
893 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
894 uint32_t reserved_9_31 : 23;
895 uint32_t fcreq : 1; /**< [ 8: 8](SR/W) Frequency change request. Indicates the number of the entry in the frequency
896 table to select. Selecting an unimplemented entry, or an entry that contains
897 0x0, has no effect on the counter.
898
899 For CNXXXX, which implements a single frequency table entry, must be 0x0. */
900 uint32_t reserved_2_7 : 6;
901 uint32_t hdbg : 1; /**< [ 1: 1](SR/W) System counter halt-on-debug enable.
902 0 = System counter ignores halt-on-debug.
903 1 = Asserted halt-on-debug signal halts system counter update. */
904 uint32_t en : 1; /**< [ 0: 0](SR/W) Enables the system counter. */
905 #else /* Word 0 - Little Endian */
906 uint32_t en : 1; /**< [ 0: 0](SR/W) Enables the system counter. */
907 uint32_t hdbg : 1; /**< [ 1: 1](SR/W) System counter halt-on-debug enable.
908 0 = System counter ignores halt-on-debug.
909 1 = Asserted halt-on-debug signal halts system counter update. */
910 uint32_t reserved_2_7 : 6;
911 uint32_t fcreq : 1; /**< [ 8: 8](SR/W) Frequency change request. Indicates the number of the entry in the frequency
912 table to select. Selecting an unimplemented entry, or an entry that contains
913 0x0, has no effect on the counter.
914
915 For CNXXXX, which implements a single frequency table entry, must be 0x0. */
916 uint32_t reserved_9_31 : 23;
917 #endif /* Word 0 - End */
918 } s;
919 /* struct bdk_gti_cc_cntcr_s cn; */
920 };
921 typedef union bdk_gti_cc_cntcr bdk_gti_cc_cntcr_t;
922
923 #define BDK_GTI_CC_CNTCR BDK_GTI_CC_CNTCR_FUNC()
924 static inline uint64_t BDK_GTI_CC_CNTCR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTCR_FUNC(void)925 static inline uint64_t BDK_GTI_CC_CNTCR_FUNC(void)
926 {
927 return 0x844000000000ll;
928 }
929
930 #define typedef_BDK_GTI_CC_CNTCR bdk_gti_cc_cntcr_t
931 #define bustype_BDK_GTI_CC_CNTCR BDK_CSR_TYPE_NCB32b
932 #define basename_BDK_GTI_CC_CNTCR "GTI_CC_CNTCR"
933 #define device_bar_BDK_GTI_CC_CNTCR 0x0 /* PF_BAR0 */
934 #define busnum_BDK_GTI_CC_CNTCR 0
935 #define arguments_BDK_GTI_CC_CNTCR -1,-1,-1,-1
936
937 /**
938 * Register (NCB) gti_cc_cntcv
939 *
940 * GTI Counter Control Count Value Secure Register
941 */
942 union bdk_gti_cc_cntcv
943 {
944 uint64_t u;
945 struct bdk_gti_cc_cntcv_s
946 {
947 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
948 uint64_t cnt : 64; /**< [ 63: 0](SR/W/H) System counter count value. The counter is also read-only accessible by the
949 nonsecure world with GTI_RD_CNTCV. */
950 #else /* Word 0 - Little Endian */
951 uint64_t cnt : 64; /**< [ 63: 0](SR/W/H) System counter count value. The counter is also read-only accessible by the
952 nonsecure world with GTI_RD_CNTCV. */
953 #endif /* Word 0 - End */
954 } s;
955 /* struct bdk_gti_cc_cntcv_s cn; */
956 };
957 typedef union bdk_gti_cc_cntcv bdk_gti_cc_cntcv_t;
958
959 #define BDK_GTI_CC_CNTCV BDK_GTI_CC_CNTCV_FUNC()
960 static inline uint64_t BDK_GTI_CC_CNTCV_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTCV_FUNC(void)961 static inline uint64_t BDK_GTI_CC_CNTCV_FUNC(void)
962 {
963 return 0x844000000008ll;
964 }
965
966 #define typedef_BDK_GTI_CC_CNTCV bdk_gti_cc_cntcv_t
967 #define bustype_BDK_GTI_CC_CNTCV BDK_CSR_TYPE_NCB
968 #define basename_BDK_GTI_CC_CNTCV "GTI_CC_CNTCV"
969 #define device_bar_BDK_GTI_CC_CNTCV 0x0 /* PF_BAR0 */
970 #define busnum_BDK_GTI_CC_CNTCV 0
971 #define arguments_BDK_GTI_CC_CNTCV -1,-1,-1,-1
972
973 /**
974 * Register (NCB32b) gti_cc_cntfid0
975 *
976 * GTI Counter Control Frequency Mode Table Secure Register 0
977 */
978 union bdk_gti_cc_cntfid0
979 {
980 uint32_t u;
981 struct bdk_gti_cc_cntfid0_s
982 {
983 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
984 uint32_t data : 32; /**< [ 31: 0](SR/W) Generic timer frequency mode table, index 0.
985 Programmed by boot software with the system counter clock frequency in Hertz.
986 See also GTI_CTL_CNTFRQ. */
987 #else /* Word 0 - Little Endian */
988 uint32_t data : 32; /**< [ 31: 0](SR/W) Generic timer frequency mode table, index 0.
989 Programmed by boot software with the system counter clock frequency in Hertz.
990 See also GTI_CTL_CNTFRQ. */
991 #endif /* Word 0 - End */
992 } s;
993 /* struct bdk_gti_cc_cntfid0_s cn; */
994 };
995 typedef union bdk_gti_cc_cntfid0 bdk_gti_cc_cntfid0_t;
996
997 #define BDK_GTI_CC_CNTFID0 BDK_GTI_CC_CNTFID0_FUNC()
998 static inline uint64_t BDK_GTI_CC_CNTFID0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTFID0_FUNC(void)999 static inline uint64_t BDK_GTI_CC_CNTFID0_FUNC(void)
1000 {
1001 return 0x844000000020ll;
1002 }
1003
1004 #define typedef_BDK_GTI_CC_CNTFID0 bdk_gti_cc_cntfid0_t
1005 #define bustype_BDK_GTI_CC_CNTFID0 BDK_CSR_TYPE_NCB32b
1006 #define basename_BDK_GTI_CC_CNTFID0 "GTI_CC_CNTFID0"
1007 #define device_bar_BDK_GTI_CC_CNTFID0 0x0 /* PF_BAR0 */
1008 #define busnum_BDK_GTI_CC_CNTFID0 0
1009 #define arguments_BDK_GTI_CC_CNTFID0 -1,-1,-1,-1
1010
1011 /**
1012 * Register (NCB32b) gti_cc_cntfid1
1013 *
1014 * GTI Counter Control Frequency Mode Table Secure Register 1
1015 */
1016 union bdk_gti_cc_cntfid1
1017 {
1018 uint32_t u;
1019 struct bdk_gti_cc_cntfid1_s
1020 {
1021 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1022 uint32_t constant : 32; /**< [ 31: 0](SRO) Generic timer frequency mode table, index 1. Zero to mark the end of the table. */
1023 #else /* Word 0 - Little Endian */
1024 uint32_t constant : 32; /**< [ 31: 0](SRO) Generic timer frequency mode table, index 1. Zero to mark the end of the table. */
1025 #endif /* Word 0 - End */
1026 } s;
1027 /* struct bdk_gti_cc_cntfid1_s cn; */
1028 };
1029 typedef union bdk_gti_cc_cntfid1 bdk_gti_cc_cntfid1_t;
1030
1031 #define BDK_GTI_CC_CNTFID1 BDK_GTI_CC_CNTFID1_FUNC()
1032 static inline uint64_t BDK_GTI_CC_CNTFID1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTFID1_FUNC(void)1033 static inline uint64_t BDK_GTI_CC_CNTFID1_FUNC(void)
1034 {
1035 return 0x844000000024ll;
1036 }
1037
1038 #define typedef_BDK_GTI_CC_CNTFID1 bdk_gti_cc_cntfid1_t
1039 #define bustype_BDK_GTI_CC_CNTFID1 BDK_CSR_TYPE_NCB32b
1040 #define basename_BDK_GTI_CC_CNTFID1 "GTI_CC_CNTFID1"
1041 #define device_bar_BDK_GTI_CC_CNTFID1 0x0 /* PF_BAR0 */
1042 #define busnum_BDK_GTI_CC_CNTFID1 0
1043 #define arguments_BDK_GTI_CC_CNTFID1 -1,-1,-1,-1
1044
1045 /**
1046 * Register (NCB) gti_cc_cntmb
1047 *
1048 * INTERNAL: GTI Counter Control Mailbox Secure Register
1049 *
1050 * Implementation defined register.
1051 */
1052 union bdk_gti_cc_cntmb
1053 {
1054 uint64_t u;
1055 struct bdk_gti_cc_cntmb_s
1056 {
1057 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1058 uint64_t mbox : 64; /**< [ 63: 0](SR/W) When written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1059
1060 For CCPI-enabled chips only.
1061
1062 Mailboxes are used as follows:
1063
1064 * An AP on node A does a store to node B's GTI_CC_CNTMB.
1065
1066 * As the store flies over CCPI/OCX on chip A, OCI signals GTI to capture a
1067 transmit timestamp. GTI on chip A saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1068 the GTI_CC_CNTMB_INT[TXTS] interrupt.
1069
1070 * As the store flies over CCPI/OCX on chip B, OCI signals GTI to capture a
1071 receive timestamp. GTI on chip B saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1072 the GTI_CC_CNTMB_INT[MBRX] interrupt.
1073
1074 * GTI on chip B writes GTI_CC_CNTMB with the mailbox value.
1075
1076 Note that if a CRC error occurs on the link during the store, the store will get
1077 retried by CCPI resulting in multiple transmit timestamp captures and
1078 TX_TIMESTAMP interrupts. */
1079 #else /* Word 0 - Little Endian */
1080 uint64_t mbox : 64; /**< [ 63: 0](SR/W) When written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1081
1082 For CCPI-enabled chips only.
1083
1084 Mailboxes are used as follows:
1085
1086 * An AP on node A does a store to node B's GTI_CC_CNTMB.
1087
1088 * As the store flies over CCPI/OCX on chip A, OCI signals GTI to capture a
1089 transmit timestamp. GTI on chip A saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1090 the GTI_CC_CNTMB_INT[TXTS] interrupt.
1091
1092 * As the store flies over CCPI/OCX on chip B, OCI signals GTI to capture a
1093 receive timestamp. GTI on chip B saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1094 the GTI_CC_CNTMB_INT[MBRX] interrupt.
1095
1096 * GTI on chip B writes GTI_CC_CNTMB with the mailbox value.
1097
1098 Note that if a CRC error occurs on the link during the store, the store will get
1099 retried by CCPI resulting in multiple transmit timestamp captures and
1100 TX_TIMESTAMP interrupts. */
1101 #endif /* Word 0 - End */
1102 } s;
1103 struct bdk_gti_cc_cntmb_cn9
1104 {
1105 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1106 uint64_t mbox : 64; /**< [ 63: 0](RAZ) Reserved; for backwards compatibility. */
1107 #else /* Word 0 - Little Endian */
1108 uint64_t mbox : 64; /**< [ 63: 0](RAZ) Reserved; for backwards compatibility. */
1109 #endif /* Word 0 - End */
1110 } cn9;
1111 struct bdk_gti_cc_cntmb_cn81xx
1112 {
1113 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1114 uint64_t mbox : 64; /**< [ 63: 0](SR/W) Reserved.
1115 Internal:
1116 When written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1117
1118 For CCPI-enabled chips only.
1119
1120 Mailboxes are used as follows:
1121
1122 * An AP on node A does a store to node B's GTI_CC_CNTMB.
1123
1124 * As the store flies over CCPI/OCX on chip A, OCI signals GTI to capture a
1125 transmit timestamp. GTI on chip A saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1126 the GTI_CC_CNTMB_INT[TXTS] interrupt.
1127
1128 * As the store flies over CCPI/OCX on chip B, OCI signals GTI to capture a
1129 receive timestamp. GTI on chip B saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1130 the GTI_CC_CNTMB_INT[MBRX] interrupt.
1131
1132 * GTI on chip B writes GTI_CC_CNTMB with the mailbox value.
1133
1134 Note that if a CRC error occurs on the link during the store, the store will get
1135 retried by CCPI resulting in multiple transmit timestamp captures and
1136 TX_TIMESTAMP interrupts. */
1137 #else /* Word 0 - Little Endian */
1138 uint64_t mbox : 64; /**< [ 63: 0](SR/W) Reserved.
1139 Internal:
1140 When written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1141
1142 For CCPI-enabled chips only.
1143
1144 Mailboxes are used as follows:
1145
1146 * An AP on node A does a store to node B's GTI_CC_CNTMB.
1147
1148 * As the store flies over CCPI/OCX on chip A, OCI signals GTI to capture a
1149 transmit timestamp. GTI on chip A saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1150 the GTI_CC_CNTMB_INT[TXTS] interrupt.
1151
1152 * As the store flies over CCPI/OCX on chip B, OCI signals GTI to capture a
1153 receive timestamp. GTI on chip B saves GTI_CC_CNTCV in GTI_CC_CNTMBTS, and sets
1154 the GTI_CC_CNTMB_INT[MBRX] interrupt.
1155
1156 * GTI on chip B writes GTI_CC_CNTMB with the mailbox value.
1157
1158 Note that if a CRC error occurs on the link during the store, the store will get
1159 retried by CCPI resulting in multiple transmit timestamp captures and
1160 TX_TIMESTAMP interrupts. */
1161 #endif /* Word 0 - End */
1162 } cn81xx;
1163 /* struct bdk_gti_cc_cntmb_s cn88xx; */
1164 /* struct bdk_gti_cc_cntmb_cn81xx cn83xx; */
1165 };
1166 typedef union bdk_gti_cc_cntmb bdk_gti_cc_cntmb_t;
1167
1168 #define BDK_GTI_CC_CNTMB BDK_GTI_CC_CNTMB_FUNC()
1169 static inline uint64_t BDK_GTI_CC_CNTMB_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMB_FUNC(void)1170 static inline uint64_t BDK_GTI_CC_CNTMB_FUNC(void)
1171 {
1172 return 0x8440000000d0ll;
1173 }
1174
1175 #define typedef_BDK_GTI_CC_CNTMB bdk_gti_cc_cntmb_t
1176 #define bustype_BDK_GTI_CC_CNTMB BDK_CSR_TYPE_NCB
1177 #define basename_BDK_GTI_CC_CNTMB "GTI_CC_CNTMB"
1178 #define device_bar_BDK_GTI_CC_CNTMB 0x0 /* PF_BAR0 */
1179 #define busnum_BDK_GTI_CC_CNTMB 0
1180 #define arguments_BDK_GTI_CC_CNTMB -1,-1,-1,-1
1181
1182 /**
1183 * Register (NCB) gti_cc_cntmb_int
1184 *
1185 * INTERNAL: GTI Counter Control Mailbox Interrupt Register
1186 *
1187 * Implementation defined register.
1188 */
1189 union bdk_gti_cc_cntmb_int
1190 {
1191 uint64_t u;
1192 struct bdk_gti_cc_cntmb_int_s
1193 {
1194 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1195 uint64_t reserved_2_63 : 62;
1196 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1C/H) Mailbox receive interrupt. Set whenever CTI_CC_CNTMB is written. See
1197 GTI_CC_CNTMB. */
1198 uint64_t txts : 1; /**< [ 0: 0](SR/W1C/H) Transmit timestamp interrupt. Set whenever a transmit timestamp is captured in
1199 GTI_CC_CNTMBTS. See GTI_CC_CNTMB. */
1200 #else /* Word 0 - Little Endian */
1201 uint64_t txts : 1; /**< [ 0: 0](SR/W1C/H) Transmit timestamp interrupt. Set whenever a transmit timestamp is captured in
1202 GTI_CC_CNTMBTS. See GTI_CC_CNTMB. */
1203 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1C/H) Mailbox receive interrupt. Set whenever CTI_CC_CNTMB is written. See
1204 GTI_CC_CNTMB. */
1205 uint64_t reserved_2_63 : 62;
1206 #endif /* Word 0 - End */
1207 } s;
1208 /* struct bdk_gti_cc_cntmb_int_s cn8; */
1209 struct bdk_gti_cc_cntmb_int_cn9
1210 {
1211 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1212 uint64_t reserved_2_63 : 62;
1213 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1214 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1215 #else /* Word 0 - Little Endian */
1216 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1217 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1218 uint64_t reserved_2_63 : 62;
1219 #endif /* Word 0 - End */
1220 } cn9;
1221 };
1222 typedef union bdk_gti_cc_cntmb_int bdk_gti_cc_cntmb_int_t;
1223
1224 #define BDK_GTI_CC_CNTMB_INT BDK_GTI_CC_CNTMB_INT_FUNC()
1225 static inline uint64_t BDK_GTI_CC_CNTMB_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMB_INT_FUNC(void)1226 static inline uint64_t BDK_GTI_CC_CNTMB_INT_FUNC(void)
1227 {
1228 return 0x8440000000e0ll;
1229 }
1230
1231 #define typedef_BDK_GTI_CC_CNTMB_INT bdk_gti_cc_cntmb_int_t
1232 #define bustype_BDK_GTI_CC_CNTMB_INT BDK_CSR_TYPE_NCB
1233 #define basename_BDK_GTI_CC_CNTMB_INT "GTI_CC_CNTMB_INT"
1234 #define device_bar_BDK_GTI_CC_CNTMB_INT 0x0 /* PF_BAR0 */
1235 #define busnum_BDK_GTI_CC_CNTMB_INT 0
1236 #define arguments_BDK_GTI_CC_CNTMB_INT -1,-1,-1,-1
1237
1238 /**
1239 * Register (NCB) gti_cc_cntmb_int_ena_clr
1240 *
1241 * INTERNAL: GTI Counter Control Mailbox Interrupt Enable Clear Register
1242 */
1243 union bdk_gti_cc_cntmb_int_ena_clr
1244 {
1245 uint64_t u;
1246 struct bdk_gti_cc_cntmb_int_ena_clr_s
1247 {
1248 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1249 uint64_t reserved_2_63 : 62;
1250 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1C/H) Reads or clears enable for GTI_CC_CNTMB_INT[MBRX]. */
1251 uint64_t txts : 1; /**< [ 0: 0](SR/W1C/H) Reads or clears enable for GTI_CC_CNTMB_INT[TXTS]. */
1252 #else /* Word 0 - Little Endian */
1253 uint64_t txts : 1; /**< [ 0: 0](SR/W1C/H) Reads or clears enable for GTI_CC_CNTMB_INT[TXTS]. */
1254 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1C/H) Reads or clears enable for GTI_CC_CNTMB_INT[MBRX]. */
1255 uint64_t reserved_2_63 : 62;
1256 #endif /* Word 0 - End */
1257 } s;
1258 /* struct bdk_gti_cc_cntmb_int_ena_clr_s cn8; */
1259 struct bdk_gti_cc_cntmb_int_ena_clr_cn9
1260 {
1261 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1262 uint64_t reserved_2_63 : 62;
1263 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1264 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1265 #else /* Word 0 - Little Endian */
1266 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1267 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1268 uint64_t reserved_2_63 : 62;
1269 #endif /* Word 0 - End */
1270 } cn9;
1271 };
1272 typedef union bdk_gti_cc_cntmb_int_ena_clr bdk_gti_cc_cntmb_int_ena_clr_t;
1273
1274 #define BDK_GTI_CC_CNTMB_INT_ENA_CLR BDK_GTI_CC_CNTMB_INT_ENA_CLR_FUNC()
1275 static inline uint64_t BDK_GTI_CC_CNTMB_INT_ENA_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMB_INT_ENA_CLR_FUNC(void)1276 static inline uint64_t BDK_GTI_CC_CNTMB_INT_ENA_CLR_FUNC(void)
1277 {
1278 return 0x8440000000f0ll;
1279 }
1280
1281 #define typedef_BDK_GTI_CC_CNTMB_INT_ENA_CLR bdk_gti_cc_cntmb_int_ena_clr_t
1282 #define bustype_BDK_GTI_CC_CNTMB_INT_ENA_CLR BDK_CSR_TYPE_NCB
1283 #define basename_BDK_GTI_CC_CNTMB_INT_ENA_CLR "GTI_CC_CNTMB_INT_ENA_CLR"
1284 #define device_bar_BDK_GTI_CC_CNTMB_INT_ENA_CLR 0x0 /* PF_BAR0 */
1285 #define busnum_BDK_GTI_CC_CNTMB_INT_ENA_CLR 0
1286 #define arguments_BDK_GTI_CC_CNTMB_INT_ENA_CLR -1,-1,-1,-1
1287
1288 /**
1289 * Register (NCB) gti_cc_cntmb_int_ena_set
1290 *
1291 * INTERNAL: GTI Counter Control Mailbox Interrupt Enable Set Register
1292 */
1293 union bdk_gti_cc_cntmb_int_ena_set
1294 {
1295 uint64_t u;
1296 struct bdk_gti_cc_cntmb_int_ena_set_s
1297 {
1298 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1299 uint64_t reserved_2_63 : 62;
1300 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1S/H) Reads or sets enable for GTI_CC_CNTMB_INT[MBRX]. */
1301 uint64_t txts : 1; /**< [ 0: 0](SR/W1S/H) Reads or sets enable for GTI_CC_CNTMB_INT[TXTS]. */
1302 #else /* Word 0 - Little Endian */
1303 uint64_t txts : 1; /**< [ 0: 0](SR/W1S/H) Reads or sets enable for GTI_CC_CNTMB_INT[TXTS]. */
1304 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1S/H) Reads or sets enable for GTI_CC_CNTMB_INT[MBRX]. */
1305 uint64_t reserved_2_63 : 62;
1306 #endif /* Word 0 - End */
1307 } s;
1308 /* struct bdk_gti_cc_cntmb_int_ena_set_s cn8; */
1309 struct bdk_gti_cc_cntmb_int_ena_set_cn9
1310 {
1311 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1312 uint64_t reserved_2_63 : 62;
1313 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1314 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1315 #else /* Word 0 - Little Endian */
1316 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1317 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1318 uint64_t reserved_2_63 : 62;
1319 #endif /* Word 0 - End */
1320 } cn9;
1321 };
1322 typedef union bdk_gti_cc_cntmb_int_ena_set bdk_gti_cc_cntmb_int_ena_set_t;
1323
1324 #define BDK_GTI_CC_CNTMB_INT_ENA_SET BDK_GTI_CC_CNTMB_INT_ENA_SET_FUNC()
1325 static inline uint64_t BDK_GTI_CC_CNTMB_INT_ENA_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMB_INT_ENA_SET_FUNC(void)1326 static inline uint64_t BDK_GTI_CC_CNTMB_INT_ENA_SET_FUNC(void)
1327 {
1328 return 0x8440000000f8ll;
1329 }
1330
1331 #define typedef_BDK_GTI_CC_CNTMB_INT_ENA_SET bdk_gti_cc_cntmb_int_ena_set_t
1332 #define bustype_BDK_GTI_CC_CNTMB_INT_ENA_SET BDK_CSR_TYPE_NCB
1333 #define basename_BDK_GTI_CC_CNTMB_INT_ENA_SET "GTI_CC_CNTMB_INT_ENA_SET"
1334 #define device_bar_BDK_GTI_CC_CNTMB_INT_ENA_SET 0x0 /* PF_BAR0 */
1335 #define busnum_BDK_GTI_CC_CNTMB_INT_ENA_SET 0
1336 #define arguments_BDK_GTI_CC_CNTMB_INT_ENA_SET -1,-1,-1,-1
1337
1338 /**
1339 * Register (NCB) gti_cc_cntmb_int_set
1340 *
1341 * INTERNAL: GTI Counter Control Mailbox Interrupt Set Register
1342 */
1343 union bdk_gti_cc_cntmb_int_set
1344 {
1345 uint64_t u;
1346 struct bdk_gti_cc_cntmb_int_set_s
1347 {
1348 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1349 uint64_t reserved_2_63 : 62;
1350 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1S/H) Reads or sets GTI_CC_CNTMB_INT[MBRX]. */
1351 uint64_t txts : 1; /**< [ 0: 0](SR/W1S/H) Reads or sets GTI_CC_CNTMB_INT[TXTS]. */
1352 #else /* Word 0 - Little Endian */
1353 uint64_t txts : 1; /**< [ 0: 0](SR/W1S/H) Reads or sets GTI_CC_CNTMB_INT[TXTS]. */
1354 uint64_t mbrx : 1; /**< [ 1: 1](SR/W1S/H) Reads or sets GTI_CC_CNTMB_INT[MBRX]. */
1355 uint64_t reserved_2_63 : 62;
1356 #endif /* Word 0 - End */
1357 } s;
1358 /* struct bdk_gti_cc_cntmb_int_set_s cn8; */
1359 struct bdk_gti_cc_cntmb_int_set_cn9
1360 {
1361 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1362 uint64_t reserved_2_63 : 62;
1363 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1364 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1365 #else /* Word 0 - Little Endian */
1366 uint64_t txts : 1; /**< [ 0: 0](RAZ) Reserved; for backwards compatibility. */
1367 uint64_t mbrx : 1; /**< [ 1: 1](RAZ) Reserved; for backwards compatibility. */
1368 uint64_t reserved_2_63 : 62;
1369 #endif /* Word 0 - End */
1370 } cn9;
1371 };
1372 typedef union bdk_gti_cc_cntmb_int_set bdk_gti_cc_cntmb_int_set_t;
1373
1374 #define BDK_GTI_CC_CNTMB_INT_SET BDK_GTI_CC_CNTMB_INT_SET_FUNC()
1375 static inline uint64_t BDK_GTI_CC_CNTMB_INT_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMB_INT_SET_FUNC(void)1376 static inline uint64_t BDK_GTI_CC_CNTMB_INT_SET_FUNC(void)
1377 {
1378 return 0x8440000000e8ll;
1379 }
1380
1381 #define typedef_BDK_GTI_CC_CNTMB_INT_SET bdk_gti_cc_cntmb_int_set_t
1382 #define bustype_BDK_GTI_CC_CNTMB_INT_SET BDK_CSR_TYPE_NCB
1383 #define basename_BDK_GTI_CC_CNTMB_INT_SET "GTI_CC_CNTMB_INT_SET"
1384 #define device_bar_BDK_GTI_CC_CNTMB_INT_SET 0x0 /* PF_BAR0 */
1385 #define busnum_BDK_GTI_CC_CNTMB_INT_SET 0
1386 #define arguments_BDK_GTI_CC_CNTMB_INT_SET -1,-1,-1,-1
1387
1388 /**
1389 * Register (NCB) gti_cc_cntmbts
1390 *
1391 * INTERNAL: GTI Counter Control Mailbox Time Stamp Secure Register
1392 *
1393 * Implementation defined register.
1394 */
1395 union bdk_gti_cc_cntmbts
1396 {
1397 uint64_t u;
1398 struct bdk_gti_cc_cntmbts_s
1399 {
1400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1401 uint64_t timestamp : 64; /**< [ 63: 0](SRO/H) Mailbox time stamp. When GTI_CC_CNTMB is written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1402 See GTI_CC_CNTMB.
1403
1404 For CCPI-enabled chips only. */
1405 #else /* Word 0 - Little Endian */
1406 uint64_t timestamp : 64; /**< [ 63: 0](SRO/H) Mailbox time stamp. When GTI_CC_CNTMB is written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1407 See GTI_CC_CNTMB.
1408
1409 For CCPI-enabled chips only. */
1410 #endif /* Word 0 - End */
1411 } s;
1412 struct bdk_gti_cc_cntmbts_cn9
1413 {
1414 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1415 uint64_t timestamp : 64; /**< [ 63: 0](RAZ) Reserved; for backwards compatibility. */
1416 #else /* Word 0 - Little Endian */
1417 uint64_t timestamp : 64; /**< [ 63: 0](RAZ) Reserved; for backwards compatibility. */
1418 #endif /* Word 0 - End */
1419 } cn9;
1420 struct bdk_gti_cc_cntmbts_cn81xx
1421 {
1422 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1423 uint64_t timestamp : 64; /**< [ 63: 0](SRO/H) Reserved.
1424 Internal:
1425 Mailbox time stamp. When GTI_CC_CNTMB is written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1426 See GTI_CC_CNTMB.
1427
1428 For CCPI-enabled chips only. */
1429 #else /* Word 0 - Little Endian */
1430 uint64_t timestamp : 64; /**< [ 63: 0](SRO/H) Reserved.
1431 Internal:
1432 Mailbox time stamp. When GTI_CC_CNTMB is written, GTI_CC_CNTCV is saved in GTI_CC_CNTMBTS.
1433 See GTI_CC_CNTMB.
1434
1435 For CCPI-enabled chips only. */
1436 #endif /* Word 0 - End */
1437 } cn81xx;
1438 /* struct bdk_gti_cc_cntmbts_s cn88xx; */
1439 /* struct bdk_gti_cc_cntmbts_cn81xx cn83xx; */
1440 };
1441 typedef union bdk_gti_cc_cntmbts bdk_gti_cc_cntmbts_t;
1442
1443 #define BDK_GTI_CC_CNTMBTS BDK_GTI_CC_CNTMBTS_FUNC()
1444 static inline uint64_t BDK_GTI_CC_CNTMBTS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTMBTS_FUNC(void)1445 static inline uint64_t BDK_GTI_CC_CNTMBTS_FUNC(void)
1446 {
1447 return 0x8440000000d8ll;
1448 }
1449
1450 #define typedef_BDK_GTI_CC_CNTMBTS bdk_gti_cc_cntmbts_t
1451 #define bustype_BDK_GTI_CC_CNTMBTS BDK_CSR_TYPE_NCB
1452 #define basename_BDK_GTI_CC_CNTMBTS "GTI_CC_CNTMBTS"
1453 #define device_bar_BDK_GTI_CC_CNTMBTS 0x0 /* PF_BAR0 */
1454 #define busnum_BDK_GTI_CC_CNTMBTS 0
1455 #define arguments_BDK_GTI_CC_CNTMBTS -1,-1,-1,-1
1456
1457 /**
1458 * Register (NCB32b) gti_cc_cntracc
1459 *
1460 * GTI Counter Control Count Rate Accumulator Secure Register
1461 * Implementation defined register.
1462 */
1463 union bdk_gti_cc_cntracc
1464 {
1465 uint32_t u;
1466 struct bdk_gti_cc_cntracc_s
1467 {
1468 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1469 uint32_t cntracc : 32; /**< [ 31: 0](SRO/H) Fractional bits of the system counter, GTI_RD_CNTCV. */
1470 #else /* Word 0 - Little Endian */
1471 uint32_t cntracc : 32; /**< [ 31: 0](SRO/H) Fractional bits of the system counter, GTI_RD_CNTCV. */
1472 #endif /* Word 0 - End */
1473 } s;
1474 /* struct bdk_gti_cc_cntracc_s cn; */
1475 };
1476 typedef union bdk_gti_cc_cntracc bdk_gti_cc_cntracc_t;
1477
1478 #define BDK_GTI_CC_CNTRACC BDK_GTI_CC_CNTRACC_FUNC()
1479 static inline uint64_t BDK_GTI_CC_CNTRACC_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTRACC_FUNC(void)1480 static inline uint64_t BDK_GTI_CC_CNTRACC_FUNC(void)
1481 {
1482 return 0x8440000000c4ll;
1483 }
1484
1485 #define typedef_BDK_GTI_CC_CNTRACC bdk_gti_cc_cntracc_t
1486 #define bustype_BDK_GTI_CC_CNTRACC BDK_CSR_TYPE_NCB32b
1487 #define basename_BDK_GTI_CC_CNTRACC "GTI_CC_CNTRACC"
1488 #define device_bar_BDK_GTI_CC_CNTRACC 0x0 /* PF_BAR0 */
1489 #define busnum_BDK_GTI_CC_CNTRACC 0
1490 #define arguments_BDK_GTI_CC_CNTRACC -1,-1,-1,-1
1491
1492 /**
1493 * Register (NCB32b) gti_cc_cntrate
1494 *
1495 * GTI Counter Control Count Rate Secure Register
1496 * Implementation defined register.
1497 */
1498 union bdk_gti_cc_cntrate
1499 {
1500 uint32_t u;
1501 struct bdk_gti_cc_cntrate_s
1502 {
1503 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1504 uint32_t cntrate : 32; /**< [ 31: 0](SR/W) Sets the system counter count rate. A 32-bit fraction that is added to
1505 GTI_CC_CNTRACC every source clock. */
1506 #else /* Word 0 - Little Endian */
1507 uint32_t cntrate : 32; /**< [ 31: 0](SR/W) Sets the system counter count rate. A 32-bit fraction that is added to
1508 GTI_CC_CNTRACC every source clock. */
1509 #endif /* Word 0 - End */
1510 } s;
1511 /* struct bdk_gti_cc_cntrate_s cn; */
1512 };
1513 typedef union bdk_gti_cc_cntrate bdk_gti_cc_cntrate_t;
1514
1515 #define BDK_GTI_CC_CNTRATE BDK_GTI_CC_CNTRATE_FUNC()
1516 static inline uint64_t BDK_GTI_CC_CNTRATE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTRATE_FUNC(void)1517 static inline uint64_t BDK_GTI_CC_CNTRATE_FUNC(void)
1518 {
1519 return 0x8440000000c0ll;
1520 }
1521
1522 #define typedef_BDK_GTI_CC_CNTRATE bdk_gti_cc_cntrate_t
1523 #define bustype_BDK_GTI_CC_CNTRATE BDK_CSR_TYPE_NCB32b
1524 #define basename_BDK_GTI_CC_CNTRATE "GTI_CC_CNTRATE"
1525 #define device_bar_BDK_GTI_CC_CNTRATE 0x0 /* PF_BAR0 */
1526 #define busnum_BDK_GTI_CC_CNTRATE 0
1527 #define arguments_BDK_GTI_CC_CNTRATE -1,-1,-1,-1
1528
1529 /**
1530 * Register (NCB32b) gti_cc_cntsr
1531 *
1532 * GTI Counter Control Status Secure Register
1533 */
1534 union bdk_gti_cc_cntsr
1535 {
1536 uint32_t u;
1537 struct bdk_gti_cc_cntsr_s
1538 {
1539 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1540 uint32_t reserved_9_31 : 23;
1541 uint32_t fcack : 1; /**< [ 8: 8](SRO/H) Frequency change acknowledge. Indicates the currently selected entry in the frequency
1542 table.
1543
1544 For CNXXXX, which implements a single frequency table entry, always 0x0. */
1545 uint32_t reserved_2_7 : 6;
1546 uint32_t dbgh : 1; /**< [ 1: 1](SRO/H) Indicates whether the counter is halted because the halt-on-debug signal is asserted.
1547 0 = Counter is not halted.
1548 1 = Counter is halted. */
1549 uint32_t reserved_0 : 1;
1550 #else /* Word 0 - Little Endian */
1551 uint32_t reserved_0 : 1;
1552 uint32_t dbgh : 1; /**< [ 1: 1](SRO/H) Indicates whether the counter is halted because the halt-on-debug signal is asserted.
1553 0 = Counter is not halted.
1554 1 = Counter is halted. */
1555 uint32_t reserved_2_7 : 6;
1556 uint32_t fcack : 1; /**< [ 8: 8](SRO/H) Frequency change acknowledge. Indicates the currently selected entry in the frequency
1557 table.
1558
1559 For CNXXXX, which implements a single frequency table entry, always 0x0. */
1560 uint32_t reserved_9_31 : 23;
1561 #endif /* Word 0 - End */
1562 } s;
1563 /* struct bdk_gti_cc_cntsr_s cn; */
1564 };
1565 typedef union bdk_gti_cc_cntsr bdk_gti_cc_cntsr_t;
1566
1567 #define BDK_GTI_CC_CNTSR BDK_GTI_CC_CNTSR_FUNC()
1568 static inline uint64_t BDK_GTI_CC_CNTSR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_CNTSR_FUNC(void)1569 static inline uint64_t BDK_GTI_CC_CNTSR_FUNC(void)
1570 {
1571 return 0x844000000004ll;
1572 }
1573
1574 #define typedef_BDK_GTI_CC_CNTSR bdk_gti_cc_cntsr_t
1575 #define bustype_BDK_GTI_CC_CNTSR BDK_CSR_TYPE_NCB32b
1576 #define basename_BDK_GTI_CC_CNTSR "GTI_CC_CNTSR"
1577 #define device_bar_BDK_GTI_CC_CNTSR 0x0 /* PF_BAR0 */
1578 #define busnum_BDK_GTI_CC_CNTSR 0
1579 #define arguments_BDK_GTI_CC_CNTSR -1,-1,-1,-1
1580
1581 /**
1582 * Register (NCB) gti_cc_imp_ctl
1583 *
1584 * GTI Counter Control Implementation Control Register
1585 * Implementation defined register.
1586 */
1587 union bdk_gti_cc_imp_ctl
1588 {
1589 uint64_t u;
1590 struct bdk_gti_cc_imp_ctl_s
1591 {
1592 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1593 uint64_t reserved_1_63 : 63;
1594 uint64_t clk_src : 1; /**< [ 0: 0](SR/W) Count source clock for GTI_CC_CNTRATE.
1595 0 = Coprocessor clock.
1596 1 = PTP PPS clock. See MIO_PTP_CLOCK_CFG[PPS]. */
1597 #else /* Word 0 - Little Endian */
1598 uint64_t clk_src : 1; /**< [ 0: 0](SR/W) Count source clock for GTI_CC_CNTRATE.
1599 0 = Coprocessor clock.
1600 1 = PTP PPS clock. See MIO_PTP_CLOCK_CFG[PPS]. */
1601 uint64_t reserved_1_63 : 63;
1602 #endif /* Word 0 - End */
1603 } s;
1604 /* struct bdk_gti_cc_imp_ctl_s cn; */
1605 };
1606 typedef union bdk_gti_cc_imp_ctl bdk_gti_cc_imp_ctl_t;
1607
1608 #define BDK_GTI_CC_IMP_CTL BDK_GTI_CC_IMP_CTL_FUNC()
1609 static inline uint64_t BDK_GTI_CC_IMP_CTL_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_IMP_CTL_FUNC(void)1610 static inline uint64_t BDK_GTI_CC_IMP_CTL_FUNC(void)
1611 {
1612 return 0x844000000100ll;
1613 }
1614
1615 #define typedef_BDK_GTI_CC_IMP_CTL bdk_gti_cc_imp_ctl_t
1616 #define bustype_BDK_GTI_CC_IMP_CTL BDK_CSR_TYPE_NCB
1617 #define basename_BDK_GTI_CC_IMP_CTL "GTI_CC_IMP_CTL"
1618 #define device_bar_BDK_GTI_CC_IMP_CTL 0x0 /* PF_BAR0 */
1619 #define busnum_BDK_GTI_CC_IMP_CTL 0
1620 #define arguments_BDK_GTI_CC_IMP_CTL -1,-1,-1,-1
1621
1622 /**
1623 * Register (NCB32b) gti_cc_pidr0
1624 *
1625 * GTI Counter Control Peripheral Identification Secure Register 0
1626 */
1627 union bdk_gti_cc_pidr0
1628 {
1629 uint32_t u;
1630 struct bdk_gti_cc_pidr0_s
1631 {
1632 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1633 uint32_t reserved_8_31 : 24;
1634 uint32_t partnum0 : 8; /**< [ 7: 0](SRO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_CC. */
1635 #else /* Word 0 - Little Endian */
1636 uint32_t partnum0 : 8; /**< [ 7: 0](SRO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_CC. */
1637 uint32_t reserved_8_31 : 24;
1638 #endif /* Word 0 - End */
1639 } s;
1640 /* struct bdk_gti_cc_pidr0_s cn; */
1641 };
1642 typedef union bdk_gti_cc_pidr0 bdk_gti_cc_pidr0_t;
1643
1644 #define BDK_GTI_CC_PIDR0 BDK_GTI_CC_PIDR0_FUNC()
1645 static inline uint64_t BDK_GTI_CC_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR0_FUNC(void)1646 static inline uint64_t BDK_GTI_CC_PIDR0_FUNC(void)
1647 {
1648 return 0x844000000fe0ll;
1649 }
1650
1651 #define typedef_BDK_GTI_CC_PIDR0 bdk_gti_cc_pidr0_t
1652 #define bustype_BDK_GTI_CC_PIDR0 BDK_CSR_TYPE_NCB32b
1653 #define basename_BDK_GTI_CC_PIDR0 "GTI_CC_PIDR0"
1654 #define device_bar_BDK_GTI_CC_PIDR0 0x0 /* PF_BAR0 */
1655 #define busnum_BDK_GTI_CC_PIDR0 0
1656 #define arguments_BDK_GTI_CC_PIDR0 -1,-1,-1,-1
1657
1658 /**
1659 * Register (NCB32b) gti_cc_pidr1
1660 *
1661 * GTI Counter Control Peripheral Identification Secure Register 1
1662 */
1663 union bdk_gti_cc_pidr1
1664 {
1665 uint32_t u;
1666 struct bdk_gti_cc_pidr1_s
1667 {
1668 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1669 uint32_t reserved_8_31 : 24;
1670 uint32_t idcode : 4; /**< [ 7: 4](SRO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
1671 uint32_t partnum1 : 4; /**< [ 3: 0](SRO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
1672 #else /* Word 0 - Little Endian */
1673 uint32_t partnum1 : 4; /**< [ 3: 0](SRO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
1674 uint32_t idcode : 4; /**< [ 7: 4](SRO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
1675 uint32_t reserved_8_31 : 24;
1676 #endif /* Word 0 - End */
1677 } s;
1678 /* struct bdk_gti_cc_pidr1_s cn; */
1679 };
1680 typedef union bdk_gti_cc_pidr1 bdk_gti_cc_pidr1_t;
1681
1682 #define BDK_GTI_CC_PIDR1 BDK_GTI_CC_PIDR1_FUNC()
1683 static inline uint64_t BDK_GTI_CC_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR1_FUNC(void)1684 static inline uint64_t BDK_GTI_CC_PIDR1_FUNC(void)
1685 {
1686 return 0x844000000fe4ll;
1687 }
1688
1689 #define typedef_BDK_GTI_CC_PIDR1 bdk_gti_cc_pidr1_t
1690 #define bustype_BDK_GTI_CC_PIDR1 BDK_CSR_TYPE_NCB32b
1691 #define basename_BDK_GTI_CC_PIDR1 "GTI_CC_PIDR1"
1692 #define device_bar_BDK_GTI_CC_PIDR1 0x0 /* PF_BAR0 */
1693 #define busnum_BDK_GTI_CC_PIDR1 0
1694 #define arguments_BDK_GTI_CC_PIDR1 -1,-1,-1,-1
1695
1696 /**
1697 * Register (NCB32b) gti_cc_pidr2
1698 *
1699 * GTI Counter Control Peripheral Identification Secure Register 2
1700 */
1701 union bdk_gti_cc_pidr2
1702 {
1703 uint32_t u;
1704 struct bdk_gti_cc_pidr2_s
1705 {
1706 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1707 uint32_t reserved_8_31 : 24;
1708 uint32_t revision : 4; /**< [ 7: 4](SRO) Architectural revision, as assigned by ARM. */
1709 uint32_t jedec : 1; /**< [ 3: 3](SRO) JEDEC assigned. */
1710 uint32_t idcode : 3; /**< [ 2: 0](SRO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
1711 #else /* Word 0 - Little Endian */
1712 uint32_t idcode : 3; /**< [ 2: 0](SRO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
1713 uint32_t jedec : 1; /**< [ 3: 3](SRO) JEDEC assigned. */
1714 uint32_t revision : 4; /**< [ 7: 4](SRO) Architectural revision, as assigned by ARM. */
1715 uint32_t reserved_8_31 : 24;
1716 #endif /* Word 0 - End */
1717 } s;
1718 /* struct bdk_gti_cc_pidr2_s cn; */
1719 };
1720 typedef union bdk_gti_cc_pidr2 bdk_gti_cc_pidr2_t;
1721
1722 #define BDK_GTI_CC_PIDR2 BDK_GTI_CC_PIDR2_FUNC()
1723 static inline uint64_t BDK_GTI_CC_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR2_FUNC(void)1724 static inline uint64_t BDK_GTI_CC_PIDR2_FUNC(void)
1725 {
1726 return 0x844000000fe8ll;
1727 }
1728
1729 #define typedef_BDK_GTI_CC_PIDR2 bdk_gti_cc_pidr2_t
1730 #define bustype_BDK_GTI_CC_PIDR2 BDK_CSR_TYPE_NCB32b
1731 #define basename_BDK_GTI_CC_PIDR2 "GTI_CC_PIDR2"
1732 #define device_bar_BDK_GTI_CC_PIDR2 0x0 /* PF_BAR0 */
1733 #define busnum_BDK_GTI_CC_PIDR2 0
1734 #define arguments_BDK_GTI_CC_PIDR2 -1,-1,-1,-1
1735
1736 /**
1737 * Register (NCB32b) gti_cc_pidr3
1738 *
1739 * GTI Counter Control Peripheral Identification Secure Register 3
1740 */
1741 union bdk_gti_cc_pidr3
1742 {
1743 uint32_t u;
1744 struct bdk_gti_cc_pidr3_s
1745 {
1746 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1747 uint32_t reserved_8_31 : 24;
1748 uint32_t revand : 4; /**< [ 7: 4](SRO) Manufacturer revision number. For CNXXXX always 0x0. */
1749 uint32_t cust : 4; /**< [ 3: 0](SRO) Customer modified. 0x1 = Overall product information should be consulted for
1750 product, major and minor pass numbers. */
1751 #else /* Word 0 - Little Endian */
1752 uint32_t cust : 4; /**< [ 3: 0](SRO) Customer modified. 0x1 = Overall product information should be consulted for
1753 product, major and minor pass numbers. */
1754 uint32_t revand : 4; /**< [ 7: 4](SRO) Manufacturer revision number. For CNXXXX always 0x0. */
1755 uint32_t reserved_8_31 : 24;
1756 #endif /* Word 0 - End */
1757 } s;
1758 /* struct bdk_gti_cc_pidr3_s cn; */
1759 };
1760 typedef union bdk_gti_cc_pidr3 bdk_gti_cc_pidr3_t;
1761
1762 #define BDK_GTI_CC_PIDR3 BDK_GTI_CC_PIDR3_FUNC()
1763 static inline uint64_t BDK_GTI_CC_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR3_FUNC(void)1764 static inline uint64_t BDK_GTI_CC_PIDR3_FUNC(void)
1765 {
1766 return 0x844000000fecll;
1767 }
1768
1769 #define typedef_BDK_GTI_CC_PIDR3 bdk_gti_cc_pidr3_t
1770 #define bustype_BDK_GTI_CC_PIDR3 BDK_CSR_TYPE_NCB32b
1771 #define basename_BDK_GTI_CC_PIDR3 "GTI_CC_PIDR3"
1772 #define device_bar_BDK_GTI_CC_PIDR3 0x0 /* PF_BAR0 */
1773 #define busnum_BDK_GTI_CC_PIDR3 0
1774 #define arguments_BDK_GTI_CC_PIDR3 -1,-1,-1,-1
1775
1776 /**
1777 * Register (NCB32b) gti_cc_pidr4
1778 *
1779 * GTI Counter Control Peripheral Identification Secure Register 4
1780 */
1781 union bdk_gti_cc_pidr4
1782 {
1783 uint32_t u;
1784 struct bdk_gti_cc_pidr4_s
1785 {
1786 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1787 uint32_t reserved_8_31 : 24;
1788 uint32_t pagecnt : 4; /**< [ 7: 4](SRO) Number of log-2 4 KB blocks occupied. */
1789 uint32_t jepcont : 4; /**< [ 3: 0](SRO) JEP106 continuation code. Indicates Cavium. */
1790 #else /* Word 0 - Little Endian */
1791 uint32_t jepcont : 4; /**< [ 3: 0](SRO) JEP106 continuation code. Indicates Cavium. */
1792 uint32_t pagecnt : 4; /**< [ 7: 4](SRO) Number of log-2 4 KB blocks occupied. */
1793 uint32_t reserved_8_31 : 24;
1794 #endif /* Word 0 - End */
1795 } s;
1796 /* struct bdk_gti_cc_pidr4_s cn; */
1797 };
1798 typedef union bdk_gti_cc_pidr4 bdk_gti_cc_pidr4_t;
1799
1800 #define BDK_GTI_CC_PIDR4 BDK_GTI_CC_PIDR4_FUNC()
1801 static inline uint64_t BDK_GTI_CC_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR4_FUNC(void)1802 static inline uint64_t BDK_GTI_CC_PIDR4_FUNC(void)
1803 {
1804 return 0x844000000fd0ll;
1805 }
1806
1807 #define typedef_BDK_GTI_CC_PIDR4 bdk_gti_cc_pidr4_t
1808 #define bustype_BDK_GTI_CC_PIDR4 BDK_CSR_TYPE_NCB32b
1809 #define basename_BDK_GTI_CC_PIDR4 "GTI_CC_PIDR4"
1810 #define device_bar_BDK_GTI_CC_PIDR4 0x0 /* PF_BAR0 */
1811 #define busnum_BDK_GTI_CC_PIDR4 0
1812 #define arguments_BDK_GTI_CC_PIDR4 -1,-1,-1,-1
1813
1814 /**
1815 * Register (NCB32b) gti_cc_pidr5
1816 *
1817 * GTI Counter Control Peripheral Identification Secure Register 5
1818 */
1819 union bdk_gti_cc_pidr5
1820 {
1821 uint32_t u;
1822 struct bdk_gti_cc_pidr5_s
1823 {
1824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1825 uint32_t reserved_0_31 : 32;
1826 #else /* Word 0 - Little Endian */
1827 uint32_t reserved_0_31 : 32;
1828 #endif /* Word 0 - End */
1829 } s;
1830 /* struct bdk_gti_cc_pidr5_s cn; */
1831 };
1832 typedef union bdk_gti_cc_pidr5 bdk_gti_cc_pidr5_t;
1833
1834 #define BDK_GTI_CC_PIDR5 BDK_GTI_CC_PIDR5_FUNC()
1835 static inline uint64_t BDK_GTI_CC_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR5_FUNC(void)1836 static inline uint64_t BDK_GTI_CC_PIDR5_FUNC(void)
1837 {
1838 return 0x844000000fd4ll;
1839 }
1840
1841 #define typedef_BDK_GTI_CC_PIDR5 bdk_gti_cc_pidr5_t
1842 #define bustype_BDK_GTI_CC_PIDR5 BDK_CSR_TYPE_NCB32b
1843 #define basename_BDK_GTI_CC_PIDR5 "GTI_CC_PIDR5"
1844 #define device_bar_BDK_GTI_CC_PIDR5 0x0 /* PF_BAR0 */
1845 #define busnum_BDK_GTI_CC_PIDR5 0
1846 #define arguments_BDK_GTI_CC_PIDR5 -1,-1,-1,-1
1847
1848 /**
1849 * Register (NCB32b) gti_cc_pidr6
1850 *
1851 * GTI Counter Control Peripheral Identification Secure Register 6
1852 */
1853 union bdk_gti_cc_pidr6
1854 {
1855 uint32_t u;
1856 struct bdk_gti_cc_pidr6_s
1857 {
1858 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1859 uint32_t reserved_0_31 : 32;
1860 #else /* Word 0 - Little Endian */
1861 uint32_t reserved_0_31 : 32;
1862 #endif /* Word 0 - End */
1863 } s;
1864 /* struct bdk_gti_cc_pidr6_s cn; */
1865 };
1866 typedef union bdk_gti_cc_pidr6 bdk_gti_cc_pidr6_t;
1867
1868 #define BDK_GTI_CC_PIDR6 BDK_GTI_CC_PIDR6_FUNC()
1869 static inline uint64_t BDK_GTI_CC_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR6_FUNC(void)1870 static inline uint64_t BDK_GTI_CC_PIDR6_FUNC(void)
1871 {
1872 return 0x844000000fd8ll;
1873 }
1874
1875 #define typedef_BDK_GTI_CC_PIDR6 bdk_gti_cc_pidr6_t
1876 #define bustype_BDK_GTI_CC_PIDR6 BDK_CSR_TYPE_NCB32b
1877 #define basename_BDK_GTI_CC_PIDR6 "GTI_CC_PIDR6"
1878 #define device_bar_BDK_GTI_CC_PIDR6 0x0 /* PF_BAR0 */
1879 #define busnum_BDK_GTI_CC_PIDR6 0
1880 #define arguments_BDK_GTI_CC_PIDR6 -1,-1,-1,-1
1881
1882 /**
1883 * Register (NCB32b) gti_cc_pidr7
1884 *
1885 * GTI Counter Control Peripheral Identification Secure Register 7
1886 */
1887 union bdk_gti_cc_pidr7
1888 {
1889 uint32_t u;
1890 struct bdk_gti_cc_pidr7_s
1891 {
1892 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1893 uint32_t reserved_0_31 : 32;
1894 #else /* Word 0 - Little Endian */
1895 uint32_t reserved_0_31 : 32;
1896 #endif /* Word 0 - End */
1897 } s;
1898 /* struct bdk_gti_cc_pidr7_s cn; */
1899 };
1900 typedef union bdk_gti_cc_pidr7 bdk_gti_cc_pidr7_t;
1901
1902 #define BDK_GTI_CC_PIDR7 BDK_GTI_CC_PIDR7_FUNC()
1903 static inline uint64_t BDK_GTI_CC_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CC_PIDR7_FUNC(void)1904 static inline uint64_t BDK_GTI_CC_PIDR7_FUNC(void)
1905 {
1906 return 0x844000000fdcll;
1907 }
1908
1909 #define typedef_BDK_GTI_CC_PIDR7 bdk_gti_cc_pidr7_t
1910 #define bustype_BDK_GTI_CC_PIDR7 BDK_CSR_TYPE_NCB32b
1911 #define basename_BDK_GTI_CC_PIDR7 "GTI_CC_PIDR7"
1912 #define device_bar_BDK_GTI_CC_PIDR7 0x0 /* PF_BAR0 */
1913 #define busnum_BDK_GTI_CC_PIDR7 0
1914 #define arguments_BDK_GTI_CC_PIDR7 -1,-1,-1,-1
1915
1916 /**
1917 * Register (NCB32b) gti_const
1918 *
1919 * GTI Constants Register
1920 */
1921 union bdk_gti_const
1922 {
1923 uint32_t u;
1924 struct bdk_gti_const_s
1925 {
1926 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1927 uint32_t reserved_0_31 : 32;
1928 #else /* Word 0 - Little Endian */
1929 uint32_t reserved_0_31 : 32;
1930 #endif /* Word 0 - End */
1931 } s;
1932 /* struct bdk_gti_const_s cn; */
1933 };
1934 typedef union bdk_gti_const bdk_gti_const_t;
1935
1936 #define BDK_GTI_CONST BDK_GTI_CONST_FUNC()
1937 static inline uint64_t BDK_GTI_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CONST_FUNC(void)1938 static inline uint64_t BDK_GTI_CONST_FUNC(void)
1939 {
1940 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
1941 return 0x8440000e0004ll;
1942 __bdk_csr_fatal("GTI_CONST", 0, 0, 0, 0, 0);
1943 }
1944
1945 #define typedef_BDK_GTI_CONST bdk_gti_const_t
1946 #define bustype_BDK_GTI_CONST BDK_CSR_TYPE_NCB32b
1947 #define basename_BDK_GTI_CONST "GTI_CONST"
1948 #define device_bar_BDK_GTI_CONST 0x0 /* PF_BAR0 */
1949 #define busnum_BDK_GTI_CONST 0
1950 #define arguments_BDK_GTI_CONST -1,-1,-1,-1
1951
1952 /**
1953 * Register (NCB32b) gti_ctl_cidr0
1954 *
1955 * GTI Control Component Identification Register 0
1956 */
1957 union bdk_gti_ctl_cidr0
1958 {
1959 uint32_t u;
1960 struct bdk_gti_ctl_cidr0_s
1961 {
1962 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1963 uint32_t reserved_8_31 : 24;
1964 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1965 #else /* Word 0 - Little Endian */
1966 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
1967 uint32_t reserved_8_31 : 24;
1968 #endif /* Word 0 - End */
1969 } s;
1970 /* struct bdk_gti_ctl_cidr0_s cn; */
1971 };
1972 typedef union bdk_gti_ctl_cidr0 bdk_gti_ctl_cidr0_t;
1973
1974 #define BDK_GTI_CTL_CIDR0 BDK_GTI_CTL_CIDR0_FUNC()
1975 static inline uint64_t BDK_GTI_CTL_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CIDR0_FUNC(void)1976 static inline uint64_t BDK_GTI_CTL_CIDR0_FUNC(void)
1977 {
1978 return 0x844000020ff0ll;
1979 }
1980
1981 #define typedef_BDK_GTI_CTL_CIDR0 bdk_gti_ctl_cidr0_t
1982 #define bustype_BDK_GTI_CTL_CIDR0 BDK_CSR_TYPE_NCB32b
1983 #define basename_BDK_GTI_CTL_CIDR0 "GTI_CTL_CIDR0"
1984 #define device_bar_BDK_GTI_CTL_CIDR0 0x0 /* PF_BAR0 */
1985 #define busnum_BDK_GTI_CTL_CIDR0 0
1986 #define arguments_BDK_GTI_CTL_CIDR0 -1,-1,-1,-1
1987
1988 /**
1989 * Register (NCB32b) gti_ctl_cidr1
1990 *
1991 * GTI Control Component Identification Register 1
1992 */
1993 union bdk_gti_ctl_cidr1
1994 {
1995 uint32_t u;
1996 struct bdk_gti_ctl_cidr1_s
1997 {
1998 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
1999 uint32_t reserved_8_31 : 24;
2000 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
2001 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
2002 #else /* Word 0 - Little Endian */
2003 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
2004 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
2005 uint32_t reserved_8_31 : 24;
2006 #endif /* Word 0 - End */
2007 } s;
2008 /* struct bdk_gti_ctl_cidr1_s cn; */
2009 };
2010 typedef union bdk_gti_ctl_cidr1 bdk_gti_ctl_cidr1_t;
2011
2012 #define BDK_GTI_CTL_CIDR1 BDK_GTI_CTL_CIDR1_FUNC()
2013 static inline uint64_t BDK_GTI_CTL_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CIDR1_FUNC(void)2014 static inline uint64_t BDK_GTI_CTL_CIDR1_FUNC(void)
2015 {
2016 return 0x844000020ff4ll;
2017 }
2018
2019 #define typedef_BDK_GTI_CTL_CIDR1 bdk_gti_ctl_cidr1_t
2020 #define bustype_BDK_GTI_CTL_CIDR1 BDK_CSR_TYPE_NCB32b
2021 #define basename_BDK_GTI_CTL_CIDR1 "GTI_CTL_CIDR1"
2022 #define device_bar_BDK_GTI_CTL_CIDR1 0x0 /* PF_BAR0 */
2023 #define busnum_BDK_GTI_CTL_CIDR1 0
2024 #define arguments_BDK_GTI_CTL_CIDR1 -1,-1,-1,-1
2025
2026 /**
2027 * Register (NCB32b) gti_ctl_cidr2
2028 *
2029 * GTI Control Component Identification Register 2
2030 */
2031 union bdk_gti_ctl_cidr2
2032 {
2033 uint32_t u;
2034 struct bdk_gti_ctl_cidr2_s
2035 {
2036 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2037 uint32_t reserved_8_31 : 24;
2038 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
2039 #else /* Word 0 - Little Endian */
2040 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
2041 uint32_t reserved_8_31 : 24;
2042 #endif /* Word 0 - End */
2043 } s;
2044 /* struct bdk_gti_ctl_cidr2_s cn; */
2045 };
2046 typedef union bdk_gti_ctl_cidr2 bdk_gti_ctl_cidr2_t;
2047
2048 #define BDK_GTI_CTL_CIDR2 BDK_GTI_CTL_CIDR2_FUNC()
2049 static inline uint64_t BDK_GTI_CTL_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CIDR2_FUNC(void)2050 static inline uint64_t BDK_GTI_CTL_CIDR2_FUNC(void)
2051 {
2052 return 0x844000020ff8ll;
2053 }
2054
2055 #define typedef_BDK_GTI_CTL_CIDR2 bdk_gti_ctl_cidr2_t
2056 #define bustype_BDK_GTI_CTL_CIDR2 BDK_CSR_TYPE_NCB32b
2057 #define basename_BDK_GTI_CTL_CIDR2 "GTI_CTL_CIDR2"
2058 #define device_bar_BDK_GTI_CTL_CIDR2 0x0 /* PF_BAR0 */
2059 #define busnum_BDK_GTI_CTL_CIDR2 0
2060 #define arguments_BDK_GTI_CTL_CIDR2 -1,-1,-1,-1
2061
2062 /**
2063 * Register (NCB32b) gti_ctl_cidr3
2064 *
2065 * GTI Control Component Identification Register 3
2066 */
2067 union bdk_gti_ctl_cidr3
2068 {
2069 uint32_t u;
2070 struct bdk_gti_ctl_cidr3_s
2071 {
2072 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2073 uint32_t reserved_8_31 : 24;
2074 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
2075 #else /* Word 0 - Little Endian */
2076 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
2077 uint32_t reserved_8_31 : 24;
2078 #endif /* Word 0 - End */
2079 } s;
2080 /* struct bdk_gti_ctl_cidr3_s cn; */
2081 };
2082 typedef union bdk_gti_ctl_cidr3 bdk_gti_ctl_cidr3_t;
2083
2084 #define BDK_GTI_CTL_CIDR3 BDK_GTI_CTL_CIDR3_FUNC()
2085 static inline uint64_t BDK_GTI_CTL_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CIDR3_FUNC(void)2086 static inline uint64_t BDK_GTI_CTL_CIDR3_FUNC(void)
2087 {
2088 return 0x844000020ffcll;
2089 }
2090
2091 #define typedef_BDK_GTI_CTL_CIDR3 bdk_gti_ctl_cidr3_t
2092 #define bustype_BDK_GTI_CTL_CIDR3 BDK_CSR_TYPE_NCB32b
2093 #define basename_BDK_GTI_CTL_CIDR3 "GTI_CTL_CIDR3"
2094 #define device_bar_BDK_GTI_CTL_CIDR3 0x0 /* PF_BAR0 */
2095 #define busnum_BDK_GTI_CTL_CIDR3 0
2096 #define arguments_BDK_GTI_CTL_CIDR3 -1,-1,-1,-1
2097
2098 /**
2099 * Register (NCB32b) gti_ctl_cntacr0
2100 *
2101 * GTI Control Access Control 0 Register
2102 */
2103 union bdk_gti_ctl_cntacr0
2104 {
2105 uint32_t u;
2106 struct bdk_gti_ctl_cntacr0_s
2107 {
2108 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2109 uint32_t constant : 32; /**< [ 31: 0](RO) Access control 0. */
2110 #else /* Word 0 - Little Endian */
2111 uint32_t constant : 32; /**< [ 31: 0](RO) Access control 0. */
2112 #endif /* Word 0 - End */
2113 } s;
2114 /* struct bdk_gti_ctl_cntacr0_s cn; */
2115 };
2116 typedef union bdk_gti_ctl_cntacr0 bdk_gti_ctl_cntacr0_t;
2117
2118 #define BDK_GTI_CTL_CNTACR0 BDK_GTI_CTL_CNTACR0_FUNC()
2119 static inline uint64_t BDK_GTI_CTL_CNTACR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CNTACR0_FUNC(void)2120 static inline uint64_t BDK_GTI_CTL_CNTACR0_FUNC(void)
2121 {
2122 return 0x844000020040ll;
2123 }
2124
2125 #define typedef_BDK_GTI_CTL_CNTACR0 bdk_gti_ctl_cntacr0_t
2126 #define bustype_BDK_GTI_CTL_CNTACR0 BDK_CSR_TYPE_NCB32b
2127 #define basename_BDK_GTI_CTL_CNTACR0 "GTI_CTL_CNTACR0"
2128 #define device_bar_BDK_GTI_CTL_CNTACR0 0x0 /* PF_BAR0 */
2129 #define busnum_BDK_GTI_CTL_CNTACR0 0
2130 #define arguments_BDK_GTI_CTL_CNTACR0 -1,-1,-1,-1
2131
2132 /**
2133 * Register (NCB32b) gti_ctl_cntfrq
2134 *
2135 * GTI Control Counter Frequency Secure Register
2136 */
2137 union bdk_gti_ctl_cntfrq
2138 {
2139 uint32_t u;
2140 struct bdk_gti_ctl_cntfrq_s
2141 {
2142 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2143 uint32_t data : 32; /**< [ 31: 0](SR/W) Programmed by boot software with the system counter clock frequency in Hertz.
2144 See also GTI_CC_CNTFID0. */
2145 #else /* Word 0 - Little Endian */
2146 uint32_t data : 32; /**< [ 31: 0](SR/W) Programmed by boot software with the system counter clock frequency in Hertz.
2147 See also GTI_CC_CNTFID0. */
2148 #endif /* Word 0 - End */
2149 } s;
2150 /* struct bdk_gti_ctl_cntfrq_s cn; */
2151 };
2152 typedef union bdk_gti_ctl_cntfrq bdk_gti_ctl_cntfrq_t;
2153
2154 #define BDK_GTI_CTL_CNTFRQ BDK_GTI_CTL_CNTFRQ_FUNC()
2155 static inline uint64_t BDK_GTI_CTL_CNTFRQ_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CNTFRQ_FUNC(void)2156 static inline uint64_t BDK_GTI_CTL_CNTFRQ_FUNC(void)
2157 {
2158 return 0x844000020000ll;
2159 }
2160
2161 #define typedef_BDK_GTI_CTL_CNTFRQ bdk_gti_ctl_cntfrq_t
2162 #define bustype_BDK_GTI_CTL_CNTFRQ BDK_CSR_TYPE_NCB32b
2163 #define basename_BDK_GTI_CTL_CNTFRQ "GTI_CTL_CNTFRQ"
2164 #define device_bar_BDK_GTI_CTL_CNTFRQ 0x0 /* PF_BAR0 */
2165 #define busnum_BDK_GTI_CTL_CNTFRQ 0
2166 #define arguments_BDK_GTI_CTL_CNTFRQ -1,-1,-1,-1
2167
2168 /**
2169 * Register (NCB32b) gti_ctl_cntnsar
2170 *
2171 * GTI Control Counter Nonsecure Access Secure Register
2172 */
2173 union bdk_gti_ctl_cntnsar
2174 {
2175 uint32_t u;
2176 struct bdk_gti_ctl_cntnsar_s
2177 {
2178 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2179 uint32_t constant : 32; /**< [ 31: 0](SRO) Counter nonsecure access. */
2180 #else /* Word 0 - Little Endian */
2181 uint32_t constant : 32; /**< [ 31: 0](SRO) Counter nonsecure access. */
2182 #endif /* Word 0 - End */
2183 } s;
2184 /* struct bdk_gti_ctl_cntnsar_s cn; */
2185 };
2186 typedef union bdk_gti_ctl_cntnsar bdk_gti_ctl_cntnsar_t;
2187
2188 #define BDK_GTI_CTL_CNTNSAR BDK_GTI_CTL_CNTNSAR_FUNC()
2189 static inline uint64_t BDK_GTI_CTL_CNTNSAR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CNTNSAR_FUNC(void)2190 static inline uint64_t BDK_GTI_CTL_CNTNSAR_FUNC(void)
2191 {
2192 return 0x844000020004ll;
2193 }
2194
2195 #define typedef_BDK_GTI_CTL_CNTNSAR bdk_gti_ctl_cntnsar_t
2196 #define bustype_BDK_GTI_CTL_CNTNSAR BDK_CSR_TYPE_NCB32b
2197 #define basename_BDK_GTI_CTL_CNTNSAR "GTI_CTL_CNTNSAR"
2198 #define device_bar_BDK_GTI_CTL_CNTNSAR 0x0 /* PF_BAR0 */
2199 #define busnum_BDK_GTI_CTL_CNTNSAR 0
2200 #define arguments_BDK_GTI_CTL_CNTNSAR -1,-1,-1,-1
2201
2202 /**
2203 * Register (NCB32b) gti_ctl_cnttidr
2204 *
2205 * GTI Control Counter Timer ID Register
2206 */
2207 union bdk_gti_ctl_cnttidr
2208 {
2209 uint32_t u;
2210 struct bdk_gti_ctl_cnttidr_s
2211 {
2212 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2213 uint32_t constant : 32; /**< [ 31: 0](RO) Counter timer ID. */
2214 #else /* Word 0 - Little Endian */
2215 uint32_t constant : 32; /**< [ 31: 0](RO) Counter timer ID. */
2216 #endif /* Word 0 - End */
2217 } s;
2218 /* struct bdk_gti_ctl_cnttidr_s cn; */
2219 };
2220 typedef union bdk_gti_ctl_cnttidr bdk_gti_ctl_cnttidr_t;
2221
2222 #define BDK_GTI_CTL_CNTTIDR BDK_GTI_CTL_CNTTIDR_FUNC()
2223 static inline uint64_t BDK_GTI_CTL_CNTTIDR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_CNTTIDR_FUNC(void)2224 static inline uint64_t BDK_GTI_CTL_CNTTIDR_FUNC(void)
2225 {
2226 return 0x844000020008ll;
2227 }
2228
2229 #define typedef_BDK_GTI_CTL_CNTTIDR bdk_gti_ctl_cnttidr_t
2230 #define bustype_BDK_GTI_CTL_CNTTIDR BDK_CSR_TYPE_NCB32b
2231 #define basename_BDK_GTI_CTL_CNTTIDR "GTI_CTL_CNTTIDR"
2232 #define device_bar_BDK_GTI_CTL_CNTTIDR 0x0 /* PF_BAR0 */
2233 #define busnum_BDK_GTI_CTL_CNTTIDR 0
2234 #define arguments_BDK_GTI_CTL_CNTTIDR -1,-1,-1,-1
2235
2236 /**
2237 * Register (NCB32b) gti_ctl_pidr0
2238 *
2239 * GTI Control Peripheral Identification Register 0
2240 */
2241 union bdk_gti_ctl_pidr0
2242 {
2243 uint32_t u;
2244 struct bdk_gti_ctl_pidr0_s
2245 {
2246 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2247 uint32_t reserved_8_31 : 24;
2248 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_CTL. */
2249 #else /* Word 0 - Little Endian */
2250 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_CTL. */
2251 uint32_t reserved_8_31 : 24;
2252 #endif /* Word 0 - End */
2253 } s;
2254 /* struct bdk_gti_ctl_pidr0_s cn; */
2255 };
2256 typedef union bdk_gti_ctl_pidr0 bdk_gti_ctl_pidr0_t;
2257
2258 #define BDK_GTI_CTL_PIDR0 BDK_GTI_CTL_PIDR0_FUNC()
2259 static inline uint64_t BDK_GTI_CTL_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR0_FUNC(void)2260 static inline uint64_t BDK_GTI_CTL_PIDR0_FUNC(void)
2261 {
2262 return 0x844000020fe0ll;
2263 }
2264
2265 #define typedef_BDK_GTI_CTL_PIDR0 bdk_gti_ctl_pidr0_t
2266 #define bustype_BDK_GTI_CTL_PIDR0 BDK_CSR_TYPE_NCB32b
2267 #define basename_BDK_GTI_CTL_PIDR0 "GTI_CTL_PIDR0"
2268 #define device_bar_BDK_GTI_CTL_PIDR0 0x0 /* PF_BAR0 */
2269 #define busnum_BDK_GTI_CTL_PIDR0 0
2270 #define arguments_BDK_GTI_CTL_PIDR0 -1,-1,-1,-1
2271
2272 /**
2273 * Register (NCB32b) gti_ctl_pidr1
2274 *
2275 * GTI Control Peripheral Identification Register 1
2276 */
2277 union bdk_gti_ctl_pidr1
2278 {
2279 uint32_t u;
2280 struct bdk_gti_ctl_pidr1_s
2281 {
2282 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2283 uint32_t reserved_8_31 : 24;
2284 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
2285 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
2286 #else /* Word 0 - Little Endian */
2287 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
2288 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
2289 uint32_t reserved_8_31 : 24;
2290 #endif /* Word 0 - End */
2291 } s;
2292 /* struct bdk_gti_ctl_pidr1_s cn; */
2293 };
2294 typedef union bdk_gti_ctl_pidr1 bdk_gti_ctl_pidr1_t;
2295
2296 #define BDK_GTI_CTL_PIDR1 BDK_GTI_CTL_PIDR1_FUNC()
2297 static inline uint64_t BDK_GTI_CTL_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR1_FUNC(void)2298 static inline uint64_t BDK_GTI_CTL_PIDR1_FUNC(void)
2299 {
2300 return 0x844000020fe4ll;
2301 }
2302
2303 #define typedef_BDK_GTI_CTL_PIDR1 bdk_gti_ctl_pidr1_t
2304 #define bustype_BDK_GTI_CTL_PIDR1 BDK_CSR_TYPE_NCB32b
2305 #define basename_BDK_GTI_CTL_PIDR1 "GTI_CTL_PIDR1"
2306 #define device_bar_BDK_GTI_CTL_PIDR1 0x0 /* PF_BAR0 */
2307 #define busnum_BDK_GTI_CTL_PIDR1 0
2308 #define arguments_BDK_GTI_CTL_PIDR1 -1,-1,-1,-1
2309
2310 /**
2311 * Register (NCB32b) gti_ctl_pidr2
2312 *
2313 * GTI Control Peripheral Identification Register 2
2314 */
2315 union bdk_gti_ctl_pidr2
2316 {
2317 uint32_t u;
2318 struct bdk_gti_ctl_pidr2_s
2319 {
2320 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2321 uint32_t reserved_8_31 : 24;
2322 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
2323 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
2324 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
2325 #else /* Word 0 - Little Endian */
2326 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
2327 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
2328 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
2329 uint32_t reserved_8_31 : 24;
2330 #endif /* Word 0 - End */
2331 } s;
2332 /* struct bdk_gti_ctl_pidr2_s cn; */
2333 };
2334 typedef union bdk_gti_ctl_pidr2 bdk_gti_ctl_pidr2_t;
2335
2336 #define BDK_GTI_CTL_PIDR2 BDK_GTI_CTL_PIDR2_FUNC()
2337 static inline uint64_t BDK_GTI_CTL_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR2_FUNC(void)2338 static inline uint64_t BDK_GTI_CTL_PIDR2_FUNC(void)
2339 {
2340 return 0x844000020fe8ll;
2341 }
2342
2343 #define typedef_BDK_GTI_CTL_PIDR2 bdk_gti_ctl_pidr2_t
2344 #define bustype_BDK_GTI_CTL_PIDR2 BDK_CSR_TYPE_NCB32b
2345 #define basename_BDK_GTI_CTL_PIDR2 "GTI_CTL_PIDR2"
2346 #define device_bar_BDK_GTI_CTL_PIDR2 0x0 /* PF_BAR0 */
2347 #define busnum_BDK_GTI_CTL_PIDR2 0
2348 #define arguments_BDK_GTI_CTL_PIDR2 -1,-1,-1,-1
2349
2350 /**
2351 * Register (NCB32b) gti_ctl_pidr3
2352 *
2353 * GTI Control Peripheral Identification Register 3
2354 */
2355 union bdk_gti_ctl_pidr3
2356 {
2357 uint32_t u;
2358 struct bdk_gti_ctl_pidr3_s
2359 {
2360 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2361 uint32_t reserved_8_31 : 24;
2362 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
2363 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
2364 product, major and minor pass numbers. */
2365 #else /* Word 0 - Little Endian */
2366 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
2367 product, major and minor pass numbers. */
2368 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
2369 uint32_t reserved_8_31 : 24;
2370 #endif /* Word 0 - End */
2371 } s;
2372 /* struct bdk_gti_ctl_pidr3_s cn; */
2373 };
2374 typedef union bdk_gti_ctl_pidr3 bdk_gti_ctl_pidr3_t;
2375
2376 #define BDK_GTI_CTL_PIDR3 BDK_GTI_CTL_PIDR3_FUNC()
2377 static inline uint64_t BDK_GTI_CTL_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR3_FUNC(void)2378 static inline uint64_t BDK_GTI_CTL_PIDR3_FUNC(void)
2379 {
2380 return 0x844000020fecll;
2381 }
2382
2383 #define typedef_BDK_GTI_CTL_PIDR3 bdk_gti_ctl_pidr3_t
2384 #define bustype_BDK_GTI_CTL_PIDR3 BDK_CSR_TYPE_NCB32b
2385 #define basename_BDK_GTI_CTL_PIDR3 "GTI_CTL_PIDR3"
2386 #define device_bar_BDK_GTI_CTL_PIDR3 0x0 /* PF_BAR0 */
2387 #define busnum_BDK_GTI_CTL_PIDR3 0
2388 #define arguments_BDK_GTI_CTL_PIDR3 -1,-1,-1,-1
2389
2390 /**
2391 * Register (NCB32b) gti_ctl_pidr4
2392 *
2393 * GTI Control Peripheral Identification Register 4
2394 */
2395 union bdk_gti_ctl_pidr4
2396 {
2397 uint32_t u;
2398 struct bdk_gti_ctl_pidr4_s
2399 {
2400 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2401 uint32_t reserved_8_31 : 24;
2402 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
2403 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
2404 #else /* Word 0 - Little Endian */
2405 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
2406 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
2407 uint32_t reserved_8_31 : 24;
2408 #endif /* Word 0 - End */
2409 } s;
2410 /* struct bdk_gti_ctl_pidr4_s cn; */
2411 };
2412 typedef union bdk_gti_ctl_pidr4 bdk_gti_ctl_pidr4_t;
2413
2414 #define BDK_GTI_CTL_PIDR4 BDK_GTI_CTL_PIDR4_FUNC()
2415 static inline uint64_t BDK_GTI_CTL_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR4_FUNC(void)2416 static inline uint64_t BDK_GTI_CTL_PIDR4_FUNC(void)
2417 {
2418 return 0x844000020fd0ll;
2419 }
2420
2421 #define typedef_BDK_GTI_CTL_PIDR4 bdk_gti_ctl_pidr4_t
2422 #define bustype_BDK_GTI_CTL_PIDR4 BDK_CSR_TYPE_NCB32b
2423 #define basename_BDK_GTI_CTL_PIDR4 "GTI_CTL_PIDR4"
2424 #define device_bar_BDK_GTI_CTL_PIDR4 0x0 /* PF_BAR0 */
2425 #define busnum_BDK_GTI_CTL_PIDR4 0
2426 #define arguments_BDK_GTI_CTL_PIDR4 -1,-1,-1,-1
2427
2428 /**
2429 * Register (NCB32b) gti_ctl_pidr5
2430 *
2431 * GTI Control Peripheral Identification Register 5
2432 */
2433 union bdk_gti_ctl_pidr5
2434 {
2435 uint32_t u;
2436 struct bdk_gti_ctl_pidr5_s
2437 {
2438 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2439 uint32_t reserved_0_31 : 32;
2440 #else /* Word 0 - Little Endian */
2441 uint32_t reserved_0_31 : 32;
2442 #endif /* Word 0 - End */
2443 } s;
2444 /* struct bdk_gti_ctl_pidr5_s cn; */
2445 };
2446 typedef union bdk_gti_ctl_pidr5 bdk_gti_ctl_pidr5_t;
2447
2448 #define BDK_GTI_CTL_PIDR5 BDK_GTI_CTL_PIDR5_FUNC()
2449 static inline uint64_t BDK_GTI_CTL_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR5_FUNC(void)2450 static inline uint64_t BDK_GTI_CTL_PIDR5_FUNC(void)
2451 {
2452 return 0x844000020fd4ll;
2453 }
2454
2455 #define typedef_BDK_GTI_CTL_PIDR5 bdk_gti_ctl_pidr5_t
2456 #define bustype_BDK_GTI_CTL_PIDR5 BDK_CSR_TYPE_NCB32b
2457 #define basename_BDK_GTI_CTL_PIDR5 "GTI_CTL_PIDR5"
2458 #define device_bar_BDK_GTI_CTL_PIDR5 0x0 /* PF_BAR0 */
2459 #define busnum_BDK_GTI_CTL_PIDR5 0
2460 #define arguments_BDK_GTI_CTL_PIDR5 -1,-1,-1,-1
2461
2462 /**
2463 * Register (NCB32b) gti_ctl_pidr6
2464 *
2465 * GTI Control Peripheral Identification Register 6
2466 */
2467 union bdk_gti_ctl_pidr6
2468 {
2469 uint32_t u;
2470 struct bdk_gti_ctl_pidr6_s
2471 {
2472 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2473 uint32_t reserved_0_31 : 32;
2474 #else /* Word 0 - Little Endian */
2475 uint32_t reserved_0_31 : 32;
2476 #endif /* Word 0 - End */
2477 } s;
2478 /* struct bdk_gti_ctl_pidr6_s cn; */
2479 };
2480 typedef union bdk_gti_ctl_pidr6 bdk_gti_ctl_pidr6_t;
2481
2482 #define BDK_GTI_CTL_PIDR6 BDK_GTI_CTL_PIDR6_FUNC()
2483 static inline uint64_t BDK_GTI_CTL_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR6_FUNC(void)2484 static inline uint64_t BDK_GTI_CTL_PIDR6_FUNC(void)
2485 {
2486 return 0x844000020fd8ll;
2487 }
2488
2489 #define typedef_BDK_GTI_CTL_PIDR6 bdk_gti_ctl_pidr6_t
2490 #define bustype_BDK_GTI_CTL_PIDR6 BDK_CSR_TYPE_NCB32b
2491 #define basename_BDK_GTI_CTL_PIDR6 "GTI_CTL_PIDR6"
2492 #define device_bar_BDK_GTI_CTL_PIDR6 0x0 /* PF_BAR0 */
2493 #define busnum_BDK_GTI_CTL_PIDR6 0
2494 #define arguments_BDK_GTI_CTL_PIDR6 -1,-1,-1,-1
2495
2496 /**
2497 * Register (NCB32b) gti_ctl_pidr7
2498 *
2499 * GTI Control Peripheral Identification Register 7
2500 */
2501 union bdk_gti_ctl_pidr7
2502 {
2503 uint32_t u;
2504 struct bdk_gti_ctl_pidr7_s
2505 {
2506 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2507 uint32_t reserved_0_31 : 32;
2508 #else /* Word 0 - Little Endian */
2509 uint32_t reserved_0_31 : 32;
2510 #endif /* Word 0 - End */
2511 } s;
2512 /* struct bdk_gti_ctl_pidr7_s cn; */
2513 };
2514 typedef union bdk_gti_ctl_pidr7 bdk_gti_ctl_pidr7_t;
2515
2516 #define BDK_GTI_CTL_PIDR7 BDK_GTI_CTL_PIDR7_FUNC()
2517 static inline uint64_t BDK_GTI_CTL_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CTL_PIDR7_FUNC(void)2518 static inline uint64_t BDK_GTI_CTL_PIDR7_FUNC(void)
2519 {
2520 return 0x844000020fdcll;
2521 }
2522
2523 #define typedef_BDK_GTI_CTL_PIDR7 bdk_gti_ctl_pidr7_t
2524 #define bustype_BDK_GTI_CTL_PIDR7 BDK_CSR_TYPE_NCB32b
2525 #define basename_BDK_GTI_CTL_PIDR7 "GTI_CTL_PIDR7"
2526 #define device_bar_BDK_GTI_CTL_PIDR7 0x0 /* PF_BAR0 */
2527 #define busnum_BDK_GTI_CTL_PIDR7 0
2528 #define arguments_BDK_GTI_CTL_PIDR7 -1,-1,-1,-1
2529
2530 /**
2531 * Register (NCB) gti_cwd_del3t
2532 *
2533 * GTI Per-core Watchdog DEL3T Interrupt Register
2534 * Generic timer per-core watchdog DEL3T interrupts.
2535 */
2536 union bdk_gti_cwd_del3t
2537 {
2538 uint64_t u;
2539 struct bdk_gti_cwd_del3t_s
2540 {
2541 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2542 uint64_t reserved_54_63 : 10;
2543 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Per-core watchdog DEL3T interrupt. */
2544 #else /* Word 0 - Little Endian */
2545 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Per-core watchdog DEL3T interrupt. */
2546 uint64_t reserved_54_63 : 10;
2547 #endif /* Word 0 - End */
2548 } s;
2549 struct bdk_gti_cwd_del3t_cn8
2550 {
2551 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2552 uint64_t reserved_48_63 : 16;
2553 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Per-core watchdog DEL3T interrupt. */
2554 #else /* Word 0 - Little Endian */
2555 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Per-core watchdog DEL3T interrupt. */
2556 uint64_t reserved_48_63 : 16;
2557 #endif /* Word 0 - End */
2558 } cn8;
2559 /* struct bdk_gti_cwd_del3t_s cn9; */
2560 };
2561 typedef union bdk_gti_cwd_del3t bdk_gti_cwd_del3t_t;
2562
2563 #define BDK_GTI_CWD_DEL3T BDK_GTI_CWD_DEL3T_FUNC()
2564 static inline uint64_t BDK_GTI_CWD_DEL3T_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_DEL3T_FUNC(void)2565 static inline uint64_t BDK_GTI_CWD_DEL3T_FUNC(void)
2566 {
2567 return 0x844000040220ll;
2568 }
2569
2570 #define typedef_BDK_GTI_CWD_DEL3T bdk_gti_cwd_del3t_t
2571 #define bustype_BDK_GTI_CWD_DEL3T BDK_CSR_TYPE_NCB
2572 #define basename_BDK_GTI_CWD_DEL3T "GTI_CWD_DEL3T"
2573 #define device_bar_BDK_GTI_CWD_DEL3T 0x0 /* PF_BAR0 */
2574 #define busnum_BDK_GTI_CWD_DEL3T 0
2575 #define arguments_BDK_GTI_CWD_DEL3T -1,-1,-1,-1
2576
2577 /**
2578 * Register (NCB) gti_cwd_del3t_ena_clr
2579 *
2580 * GTI Per-core Watchdog Interrupt Enable Clear Register
2581 * This register clears interrupt enable bits.
2582 */
2583 union bdk_gti_cwd_del3t_ena_clr
2584 {
2585 uint64_t u;
2586 struct bdk_gti_cwd_del3t_ena_clr_s
2587 {
2588 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2589 uint64_t reserved_54_63 : 10;
2590 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Reads or clears enable for GTI_CWD_DEL3T[CORE]. */
2591 #else /* Word 0 - Little Endian */
2592 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Reads or clears enable for GTI_CWD_DEL3T[CORE]. */
2593 uint64_t reserved_54_63 : 10;
2594 #endif /* Word 0 - End */
2595 } s;
2596 struct bdk_gti_cwd_del3t_ena_clr_cn8
2597 {
2598 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2599 uint64_t reserved_48_63 : 16;
2600 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GTI_CWD_DEL3T[CORE]. */
2601 #else /* Word 0 - Little Endian */
2602 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GTI_CWD_DEL3T[CORE]. */
2603 uint64_t reserved_48_63 : 16;
2604 #endif /* Word 0 - End */
2605 } cn8;
2606 /* struct bdk_gti_cwd_del3t_ena_clr_s cn9; */
2607 };
2608 typedef union bdk_gti_cwd_del3t_ena_clr bdk_gti_cwd_del3t_ena_clr_t;
2609
2610 #define BDK_GTI_CWD_DEL3T_ENA_CLR BDK_GTI_CWD_DEL3T_ENA_CLR_FUNC()
2611 static inline uint64_t BDK_GTI_CWD_DEL3T_ENA_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_DEL3T_ENA_CLR_FUNC(void)2612 static inline uint64_t BDK_GTI_CWD_DEL3T_ENA_CLR_FUNC(void)
2613 {
2614 return 0x844000040230ll;
2615 }
2616
2617 #define typedef_BDK_GTI_CWD_DEL3T_ENA_CLR bdk_gti_cwd_del3t_ena_clr_t
2618 #define bustype_BDK_GTI_CWD_DEL3T_ENA_CLR BDK_CSR_TYPE_NCB
2619 #define basename_BDK_GTI_CWD_DEL3T_ENA_CLR "GTI_CWD_DEL3T_ENA_CLR"
2620 #define device_bar_BDK_GTI_CWD_DEL3T_ENA_CLR 0x0 /* PF_BAR0 */
2621 #define busnum_BDK_GTI_CWD_DEL3T_ENA_CLR 0
2622 #define arguments_BDK_GTI_CWD_DEL3T_ENA_CLR -1,-1,-1,-1
2623
2624 /**
2625 * Register (NCB) gti_cwd_del3t_ena_set
2626 *
2627 * GTI Per-core Watchdog DEL3T Interrupt Enable Set Register
2628 * This register sets interrupt enable bits.
2629 */
2630 union bdk_gti_cwd_del3t_ena_set
2631 {
2632 uint64_t u;
2633 struct bdk_gti_cwd_del3t_ena_set_s
2634 {
2635 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2636 uint64_t reserved_54_63 : 10;
2637 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets enable for GTI_CWD_DEL3T[CORE]. */
2638 #else /* Word 0 - Little Endian */
2639 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets enable for GTI_CWD_DEL3T[CORE]. */
2640 uint64_t reserved_54_63 : 10;
2641 #endif /* Word 0 - End */
2642 } s;
2643 struct bdk_gti_cwd_del3t_ena_set_cn8
2644 {
2645 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2646 uint64_t reserved_48_63 : 16;
2647 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GTI_CWD_DEL3T[CORE]. */
2648 #else /* Word 0 - Little Endian */
2649 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GTI_CWD_DEL3T[CORE]. */
2650 uint64_t reserved_48_63 : 16;
2651 #endif /* Word 0 - End */
2652 } cn8;
2653 /* struct bdk_gti_cwd_del3t_ena_set_s cn9; */
2654 };
2655 typedef union bdk_gti_cwd_del3t_ena_set bdk_gti_cwd_del3t_ena_set_t;
2656
2657 #define BDK_GTI_CWD_DEL3T_ENA_SET BDK_GTI_CWD_DEL3T_ENA_SET_FUNC()
2658 static inline uint64_t BDK_GTI_CWD_DEL3T_ENA_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_DEL3T_ENA_SET_FUNC(void)2659 static inline uint64_t BDK_GTI_CWD_DEL3T_ENA_SET_FUNC(void)
2660 {
2661 return 0x844000040238ll;
2662 }
2663
2664 #define typedef_BDK_GTI_CWD_DEL3T_ENA_SET bdk_gti_cwd_del3t_ena_set_t
2665 #define bustype_BDK_GTI_CWD_DEL3T_ENA_SET BDK_CSR_TYPE_NCB
2666 #define basename_BDK_GTI_CWD_DEL3T_ENA_SET "GTI_CWD_DEL3T_ENA_SET"
2667 #define device_bar_BDK_GTI_CWD_DEL3T_ENA_SET 0x0 /* PF_BAR0 */
2668 #define busnum_BDK_GTI_CWD_DEL3T_ENA_SET 0
2669 #define arguments_BDK_GTI_CWD_DEL3T_ENA_SET -1,-1,-1,-1
2670
2671 /**
2672 * Register (NCB) gti_cwd_del3t_set
2673 *
2674 * GTI Per-core Watchdog DEL3T Interrupt Set Register
2675 * This register sets interrupt bits.
2676 */
2677 union bdk_gti_cwd_del3t_set
2678 {
2679 uint64_t u;
2680 struct bdk_gti_cwd_del3t_set_s
2681 {
2682 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2683 uint64_t reserved_54_63 : 10;
2684 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets GTI_CWD_DEL3T[CORE]. */
2685 #else /* Word 0 - Little Endian */
2686 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets GTI_CWD_DEL3T[CORE]. */
2687 uint64_t reserved_54_63 : 10;
2688 #endif /* Word 0 - End */
2689 } s;
2690 struct bdk_gti_cwd_del3t_set_cn8
2691 {
2692 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2693 uint64_t reserved_48_63 : 16;
2694 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GTI_CWD_DEL3T[CORE]. */
2695 #else /* Word 0 - Little Endian */
2696 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GTI_CWD_DEL3T[CORE]. */
2697 uint64_t reserved_48_63 : 16;
2698 #endif /* Word 0 - End */
2699 } cn8;
2700 /* struct bdk_gti_cwd_del3t_set_s cn9; */
2701 };
2702 typedef union bdk_gti_cwd_del3t_set bdk_gti_cwd_del3t_set_t;
2703
2704 #define BDK_GTI_CWD_DEL3T_SET BDK_GTI_CWD_DEL3T_SET_FUNC()
2705 static inline uint64_t BDK_GTI_CWD_DEL3T_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_DEL3T_SET_FUNC(void)2706 static inline uint64_t BDK_GTI_CWD_DEL3T_SET_FUNC(void)
2707 {
2708 return 0x844000040228ll;
2709 }
2710
2711 #define typedef_BDK_GTI_CWD_DEL3T_SET bdk_gti_cwd_del3t_set_t
2712 #define bustype_BDK_GTI_CWD_DEL3T_SET BDK_CSR_TYPE_NCB
2713 #define basename_BDK_GTI_CWD_DEL3T_SET "GTI_CWD_DEL3T_SET"
2714 #define device_bar_BDK_GTI_CWD_DEL3T_SET 0x0 /* PF_BAR0 */
2715 #define busnum_BDK_GTI_CWD_DEL3T_SET 0
2716 #define arguments_BDK_GTI_CWD_DEL3T_SET -1,-1,-1,-1
2717
2718 /**
2719 * Register (NCB) gti_cwd_int
2720 *
2721 * GTI Per-core Watchdog Interrupt Register
2722 * Generic timer per-core watchdog interrupts.
2723 */
2724 union bdk_gti_cwd_int
2725 {
2726 uint64_t u;
2727 struct bdk_gti_cwd_int_s
2728 {
2729 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2730 uint64_t reserved_54_63 : 10;
2731 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Per-core watchdog interrupt. */
2732 #else /* Word 0 - Little Endian */
2733 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Per-core watchdog interrupt. */
2734 uint64_t reserved_54_63 : 10;
2735 #endif /* Word 0 - End */
2736 } s;
2737 struct bdk_gti_cwd_int_cn8
2738 {
2739 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2740 uint64_t reserved_48_63 : 16;
2741 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Per-core watchdog interrupt. */
2742 #else /* Word 0 - Little Endian */
2743 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Per-core watchdog interrupt. */
2744 uint64_t reserved_48_63 : 16;
2745 #endif /* Word 0 - End */
2746 } cn8;
2747 /* struct bdk_gti_cwd_int_s cn9; */
2748 };
2749 typedef union bdk_gti_cwd_int bdk_gti_cwd_int_t;
2750
2751 #define BDK_GTI_CWD_INT BDK_GTI_CWD_INT_FUNC()
2752 static inline uint64_t BDK_GTI_CWD_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_INT_FUNC(void)2753 static inline uint64_t BDK_GTI_CWD_INT_FUNC(void)
2754 {
2755 return 0x844000040200ll;
2756 }
2757
2758 #define typedef_BDK_GTI_CWD_INT bdk_gti_cwd_int_t
2759 #define bustype_BDK_GTI_CWD_INT BDK_CSR_TYPE_NCB
2760 #define basename_BDK_GTI_CWD_INT "GTI_CWD_INT"
2761 #define device_bar_BDK_GTI_CWD_INT 0x0 /* PF_BAR0 */
2762 #define busnum_BDK_GTI_CWD_INT 0
2763 #define arguments_BDK_GTI_CWD_INT -1,-1,-1,-1
2764
2765 /**
2766 * Register (NCB) gti_cwd_int_ena_clr
2767 *
2768 * GTI Per-core Watchdog Interrupt Enable Clear Register
2769 * This register clears interrupt enable bits.
2770 */
2771 union bdk_gti_cwd_int_ena_clr
2772 {
2773 uint64_t u;
2774 struct bdk_gti_cwd_int_ena_clr_s
2775 {
2776 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2777 uint64_t reserved_54_63 : 10;
2778 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Reads or clears enable for GTI_CWD_INT[CORE]. */
2779 #else /* Word 0 - Little Endian */
2780 uint64_t core : 54; /**< [ 53: 0](R/W1C/H) Reads or clears enable for GTI_CWD_INT[CORE]. */
2781 uint64_t reserved_54_63 : 10;
2782 #endif /* Word 0 - End */
2783 } s;
2784 struct bdk_gti_cwd_int_ena_clr_cn8
2785 {
2786 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2787 uint64_t reserved_48_63 : 16;
2788 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GTI_CWD_INT[CORE]. */
2789 #else /* Word 0 - Little Endian */
2790 uint64_t core : 48; /**< [ 47: 0](R/W1C/H) Reads or clears enable for GTI_CWD_INT[CORE]. */
2791 uint64_t reserved_48_63 : 16;
2792 #endif /* Word 0 - End */
2793 } cn8;
2794 /* struct bdk_gti_cwd_int_ena_clr_s cn9; */
2795 };
2796 typedef union bdk_gti_cwd_int_ena_clr bdk_gti_cwd_int_ena_clr_t;
2797
2798 #define BDK_GTI_CWD_INT_ENA_CLR BDK_GTI_CWD_INT_ENA_CLR_FUNC()
2799 static inline uint64_t BDK_GTI_CWD_INT_ENA_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_INT_ENA_CLR_FUNC(void)2800 static inline uint64_t BDK_GTI_CWD_INT_ENA_CLR_FUNC(void)
2801 {
2802 return 0x844000040210ll;
2803 }
2804
2805 #define typedef_BDK_GTI_CWD_INT_ENA_CLR bdk_gti_cwd_int_ena_clr_t
2806 #define bustype_BDK_GTI_CWD_INT_ENA_CLR BDK_CSR_TYPE_NCB
2807 #define basename_BDK_GTI_CWD_INT_ENA_CLR "GTI_CWD_INT_ENA_CLR"
2808 #define device_bar_BDK_GTI_CWD_INT_ENA_CLR 0x0 /* PF_BAR0 */
2809 #define busnum_BDK_GTI_CWD_INT_ENA_CLR 0
2810 #define arguments_BDK_GTI_CWD_INT_ENA_CLR -1,-1,-1,-1
2811
2812 /**
2813 * Register (NCB) gti_cwd_int_ena_set
2814 *
2815 * GTI Per-core Watchdog Interrupt Enable Set Register
2816 * This register sets interrupt enable bits.
2817 */
2818 union bdk_gti_cwd_int_ena_set
2819 {
2820 uint64_t u;
2821 struct bdk_gti_cwd_int_ena_set_s
2822 {
2823 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2824 uint64_t reserved_54_63 : 10;
2825 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets enable for GTI_CWD_INT[CORE]. */
2826 #else /* Word 0 - Little Endian */
2827 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets enable for GTI_CWD_INT[CORE]. */
2828 uint64_t reserved_54_63 : 10;
2829 #endif /* Word 0 - End */
2830 } s;
2831 struct bdk_gti_cwd_int_ena_set_cn8
2832 {
2833 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2834 uint64_t reserved_48_63 : 16;
2835 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GTI_CWD_INT[CORE]. */
2836 #else /* Word 0 - Little Endian */
2837 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets enable for GTI_CWD_INT[CORE]. */
2838 uint64_t reserved_48_63 : 16;
2839 #endif /* Word 0 - End */
2840 } cn8;
2841 /* struct bdk_gti_cwd_int_ena_set_s cn9; */
2842 };
2843 typedef union bdk_gti_cwd_int_ena_set bdk_gti_cwd_int_ena_set_t;
2844
2845 #define BDK_GTI_CWD_INT_ENA_SET BDK_GTI_CWD_INT_ENA_SET_FUNC()
2846 static inline uint64_t BDK_GTI_CWD_INT_ENA_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_INT_ENA_SET_FUNC(void)2847 static inline uint64_t BDK_GTI_CWD_INT_ENA_SET_FUNC(void)
2848 {
2849 return 0x844000040218ll;
2850 }
2851
2852 #define typedef_BDK_GTI_CWD_INT_ENA_SET bdk_gti_cwd_int_ena_set_t
2853 #define bustype_BDK_GTI_CWD_INT_ENA_SET BDK_CSR_TYPE_NCB
2854 #define basename_BDK_GTI_CWD_INT_ENA_SET "GTI_CWD_INT_ENA_SET"
2855 #define device_bar_BDK_GTI_CWD_INT_ENA_SET 0x0 /* PF_BAR0 */
2856 #define busnum_BDK_GTI_CWD_INT_ENA_SET 0
2857 #define arguments_BDK_GTI_CWD_INT_ENA_SET -1,-1,-1,-1
2858
2859 /**
2860 * Register (NCB) gti_cwd_int_set
2861 *
2862 * GTI Per-core Watchdog Interrupt Set Register
2863 * This register sets interrupt bits.
2864 */
2865 union bdk_gti_cwd_int_set
2866 {
2867 uint64_t u;
2868 struct bdk_gti_cwd_int_set_s
2869 {
2870 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2871 uint64_t reserved_54_63 : 10;
2872 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets GTI_CWD_INT[CORE]. */
2873 #else /* Word 0 - Little Endian */
2874 uint64_t core : 54; /**< [ 53: 0](R/W1S/H) Reads or sets GTI_CWD_INT[CORE]. */
2875 uint64_t reserved_54_63 : 10;
2876 #endif /* Word 0 - End */
2877 } s;
2878 struct bdk_gti_cwd_int_set_cn8
2879 {
2880 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2881 uint64_t reserved_48_63 : 16;
2882 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GTI_CWD_INT[CORE]. */
2883 #else /* Word 0 - Little Endian */
2884 uint64_t core : 48; /**< [ 47: 0](R/W1S/H) Reads or sets GTI_CWD_INT[CORE]. */
2885 uint64_t reserved_48_63 : 16;
2886 #endif /* Word 0 - End */
2887 } cn8;
2888 /* struct bdk_gti_cwd_int_set_s cn9; */
2889 };
2890 typedef union bdk_gti_cwd_int_set bdk_gti_cwd_int_set_t;
2891
2892 #define BDK_GTI_CWD_INT_SET BDK_GTI_CWD_INT_SET_FUNC()
2893 static inline uint64_t BDK_GTI_CWD_INT_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_INT_SET_FUNC(void)2894 static inline uint64_t BDK_GTI_CWD_INT_SET_FUNC(void)
2895 {
2896 return 0x844000040208ll;
2897 }
2898
2899 #define typedef_BDK_GTI_CWD_INT_SET bdk_gti_cwd_int_set_t
2900 #define bustype_BDK_GTI_CWD_INT_SET BDK_CSR_TYPE_NCB
2901 #define basename_BDK_GTI_CWD_INT_SET "GTI_CWD_INT_SET"
2902 #define device_bar_BDK_GTI_CWD_INT_SET 0x0 /* PF_BAR0 */
2903 #define busnum_BDK_GTI_CWD_INT_SET 0
2904 #define arguments_BDK_GTI_CWD_INT_SET -1,-1,-1,-1
2905
2906 /**
2907 * Register (NCB) gti_cwd_poke#
2908 *
2909 * GTI Per-core Watchdog Poke Registers
2910 * Per-core watchdog poke. Writing any value to this register does the following:
2911 * * Clears any pending interrupt generated by the associated watchdog.
2912 * * Resets GTI_CWD_WDOG()[STATE] to 0x0.
2913 * * Sets GTI_CWD_WDOG()[CNT] to (GTI_CWD_WDOG()[LEN] \<\< 8).
2914 *
2915 * Reading this register returns the associated GTI_CWD_WDOG() register.
2916 */
2917 union bdk_gti_cwd_pokex
2918 {
2919 uint64_t u;
2920 struct bdk_gti_cwd_pokex_s
2921 {
2922 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2923 uint64_t zero : 18; /**< [ 63: 46](WO) Reserved. */
2924 uint64_t gstop : 1; /**< [ 45: 45](RO/H) Global-stop enable. */
2925 uint64_t dstop : 1; /**< [ 44: 44](RO/H) Debug-stop enable. */
2926 uint64_t cnt : 24; /**< [ 43: 20](RO/H) Number of 1024-cycle intervals until next watchdog expiration. Set on write to
2927 associated GTI_CWD_POKE(). */
2928 uint64_t len : 16; /**< [ 19: 4](RO/H) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
2929 decremented every 1024 cycles. */
2930 uint64_t state : 2; /**< [ 3: 2](RO/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
2931 write to associated GTI_CWD_POKE(). */
2932 uint64_t mode : 2; /**< [ 1: 0](RO/H) Watchdog mode:
2933 0x0 = Off.
2934 0x1 = Interrupt only.
2935 0x2 = Interrupt + DEL3T.
2936 0x3 = Interrupt + DEL3T + soft reset. */
2937 #else /* Word 0 - Little Endian */
2938 uint64_t mode : 2; /**< [ 1: 0](RO/H) Watchdog mode:
2939 0x0 = Off.
2940 0x1 = Interrupt only.
2941 0x2 = Interrupt + DEL3T.
2942 0x3 = Interrupt + DEL3T + soft reset. */
2943 uint64_t state : 2; /**< [ 3: 2](RO/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
2944 write to associated GTI_CWD_POKE(). */
2945 uint64_t len : 16; /**< [ 19: 4](RO/H) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
2946 decremented every 1024 cycles. */
2947 uint64_t cnt : 24; /**< [ 43: 20](RO/H) Number of 1024-cycle intervals until next watchdog expiration. Set on write to
2948 associated GTI_CWD_POKE(). */
2949 uint64_t dstop : 1; /**< [ 44: 44](RO/H) Debug-stop enable. */
2950 uint64_t gstop : 1; /**< [ 45: 45](RO/H) Global-stop enable. */
2951 uint64_t zero : 18; /**< [ 63: 46](WO) Reserved. */
2952 #endif /* Word 0 - End */
2953 } s;
2954 /* struct bdk_gti_cwd_pokex_s cn; */
2955 };
2956 typedef union bdk_gti_cwd_pokex bdk_gti_cwd_pokex_t;
2957
2958 static inline uint64_t BDK_GTI_CWD_POKEX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_POKEX(unsigned long a)2959 static inline uint64_t BDK_GTI_CWD_POKEX(unsigned long a)
2960 {
2961 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=47))
2962 return 0x844000050000ll + 8ll * ((a) & 0x3f);
2963 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=53))
2964 return 0x844000050000ll + 8ll * ((a) & 0x3f);
2965 __bdk_csr_fatal("GTI_CWD_POKEX", 1, a, 0, 0, 0);
2966 }
2967
2968 #define typedef_BDK_GTI_CWD_POKEX(a) bdk_gti_cwd_pokex_t
2969 #define bustype_BDK_GTI_CWD_POKEX(a) BDK_CSR_TYPE_NCB
2970 #define basename_BDK_GTI_CWD_POKEX(a) "GTI_CWD_POKEX"
2971 #define device_bar_BDK_GTI_CWD_POKEX(a) 0x0 /* PF_BAR0 */
2972 #define busnum_BDK_GTI_CWD_POKEX(a) (a)
2973 #define arguments_BDK_GTI_CWD_POKEX(a) (a),-1,-1,-1
2974
2975 /**
2976 * Register (NCB) gti_cwd_wdog#
2977 *
2978 * GTI Per-core Watchdog Registers
2979 */
2980 union bdk_gti_cwd_wdogx
2981 {
2982 uint64_t u;
2983 struct bdk_gti_cwd_wdogx_s
2984 {
2985 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
2986 uint64_t reserved_46_63 : 18;
2987 uint64_t gstop : 1; /**< [ 45: 45](R/W) Global-stop enable. */
2988 uint64_t dstop : 1; /**< [ 44: 44](R/W) Debug-stop enable. */
2989 uint64_t cnt : 24; /**< [ 43: 20](R/W/H) Number of 1024-cycle intervals until next watchdog expiration. Set on write to
2990 associated GTI_CWD_POKE().
2991
2992 Typically on each write to CTI_CMD_WDOG(), [CNT] should be set to [LEN] * 256. */
2993 uint64_t len : 16; /**< [ 19: 4](R/W) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
2994 decremented every 1024 cycles. */
2995 uint64_t state : 2; /**< [ 3: 2](R/W/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
2996 write to associated GTI_CWD_POKE(). */
2997 uint64_t mode : 2; /**< [ 1: 0](R/W) Watchdog mode:
2998 0x0 = Off.
2999 0x1 = Interrupt only.
3000 0x2 = Interrupt + DEL3T.
3001 0x3 = Interrupt + DEL3T + soft reset. */
3002 #else /* Word 0 - Little Endian */
3003 uint64_t mode : 2; /**< [ 1: 0](R/W) Watchdog mode:
3004 0x0 = Off.
3005 0x1 = Interrupt only.
3006 0x2 = Interrupt + DEL3T.
3007 0x3 = Interrupt + DEL3T + soft reset. */
3008 uint64_t state : 2; /**< [ 3: 2](R/W/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
3009 write to associated GTI_CWD_POKE(). */
3010 uint64_t len : 16; /**< [ 19: 4](R/W) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
3011 decremented every 1024 cycles. */
3012 uint64_t cnt : 24; /**< [ 43: 20](R/W/H) Number of 1024-cycle intervals until next watchdog expiration. Set on write to
3013 associated GTI_CWD_POKE().
3014
3015 Typically on each write to CTI_CMD_WDOG(), [CNT] should be set to [LEN] * 256. */
3016 uint64_t dstop : 1; /**< [ 44: 44](R/W) Debug-stop enable. */
3017 uint64_t gstop : 1; /**< [ 45: 45](R/W) Global-stop enable. */
3018 uint64_t reserved_46_63 : 18;
3019 #endif /* Word 0 - End */
3020 } s;
3021 /* struct bdk_gti_cwd_wdogx_s cn8; */
3022 struct bdk_gti_cwd_wdogx_cn9
3023 {
3024 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3025 uint64_t reserved_46_63 : 18;
3026 uint64_t gstop : 1; /**< [ 45: 45](R/W) Global-stop enable. */
3027 uint64_t dstop : 1; /**< [ 44: 44](R/W) Debug-stop enable. */
3028 uint64_t cnt : 24; /**< [ 43: 20](R/W/H) Number of one microsecond intervals until next watchdog expiration.
3029 Set on write to associated GTI_CWD_POKE().
3030 Typically on each write to GTI_CWD_WDOG(), [CNT] should be set to [LEN] * 256. */
3031 uint64_t len : 16; /**< [ 19: 4](R/W) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
3032 decremented every one microsecond. */
3033 uint64_t state : 2; /**< [ 3: 2](R/W/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
3034 write to associated GTI_CWD_POKE(). */
3035 uint64_t mode : 2; /**< [ 1: 0](R/W) Watchdog mode:
3036 0x0 = Off.
3037 0x1 = Interrupt only.
3038 0x2 = Interrupt + DEL3T.
3039 0x3 = Interrupt + DEL3T + soft reset. */
3040 #else /* Word 0 - Little Endian */
3041 uint64_t mode : 2; /**< [ 1: 0](R/W) Watchdog mode:
3042 0x0 = Off.
3043 0x1 = Interrupt only.
3044 0x2 = Interrupt + DEL3T.
3045 0x3 = Interrupt + DEL3T + soft reset. */
3046 uint64_t state : 2; /**< [ 3: 2](R/W/H) Watchdog state. The number of watchdog time expirations since last core poke. Cleared on
3047 write to associated GTI_CWD_POKE(). */
3048 uint64_t len : 16; /**< [ 19: 4](R/W) Watchdog time-expiration length. The most-significant 16 bits of a 24-bit value to be
3049 decremented every one microsecond. */
3050 uint64_t cnt : 24; /**< [ 43: 20](R/W/H) Number of one microsecond intervals until next watchdog expiration.
3051 Set on write to associated GTI_CWD_POKE().
3052 Typically on each write to GTI_CWD_WDOG(), [CNT] should be set to [LEN] * 256. */
3053 uint64_t dstop : 1; /**< [ 44: 44](R/W) Debug-stop enable. */
3054 uint64_t gstop : 1; /**< [ 45: 45](R/W) Global-stop enable. */
3055 uint64_t reserved_46_63 : 18;
3056 #endif /* Word 0 - End */
3057 } cn9;
3058 };
3059 typedef union bdk_gti_cwd_wdogx bdk_gti_cwd_wdogx_t;
3060
3061 static inline uint64_t BDK_GTI_CWD_WDOGX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_CWD_WDOGX(unsigned long a)3062 static inline uint64_t BDK_GTI_CWD_WDOGX(unsigned long a)
3063 {
3064 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=47))
3065 return 0x844000040000ll + 8ll * ((a) & 0x3f);
3066 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=53))
3067 return 0x844000040000ll + 8ll * ((a) & 0x3f);
3068 __bdk_csr_fatal("GTI_CWD_WDOGX", 1, a, 0, 0, 0);
3069 }
3070
3071 #define typedef_BDK_GTI_CWD_WDOGX(a) bdk_gti_cwd_wdogx_t
3072 #define bustype_BDK_GTI_CWD_WDOGX(a) BDK_CSR_TYPE_NCB
3073 #define basename_BDK_GTI_CWD_WDOGX(a) "GTI_CWD_WDOGX"
3074 #define device_bar_BDK_GTI_CWD_WDOGX(a) 0x0 /* PF_BAR0 */
3075 #define busnum_BDK_GTI_CWD_WDOGX(a) (a)
3076 #define arguments_BDK_GTI_CWD_WDOGX(a) (a),-1,-1,-1
3077
3078 /**
3079 * Register (NCB) gti_err_bist_status
3080 *
3081 * GTI BIST Status Register
3082 */
3083 union bdk_gti_err_bist_status
3084 {
3085 uint64_t u;
3086 struct bdk_gti_err_bist_status_s
3087 {
3088 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3089 uint64_t reserved_2_63 : 62;
3090 uint64_t ram : 2; /**< [ 1: 0](RO/H) BIST status. */
3091 #else /* Word 0 - Little Endian */
3092 uint64_t ram : 2; /**< [ 1: 0](RO/H) BIST status. */
3093 uint64_t reserved_2_63 : 62;
3094 #endif /* Word 0 - End */
3095 } s;
3096 /* struct bdk_gti_err_bist_status_s cn; */
3097 };
3098 typedef union bdk_gti_err_bist_status bdk_gti_err_bist_status_t;
3099
3100 #define BDK_GTI_ERR_BIST_STATUS BDK_GTI_ERR_BIST_STATUS_FUNC()
3101 static inline uint64_t BDK_GTI_ERR_BIST_STATUS_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_BIST_STATUS_FUNC(void)3102 static inline uint64_t BDK_GTI_ERR_BIST_STATUS_FUNC(void)
3103 {
3104 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
3105 return 0x8440000f0030ll;
3106 __bdk_csr_fatal("GTI_ERR_BIST_STATUS", 0, 0, 0, 0, 0);
3107 }
3108
3109 #define typedef_BDK_GTI_ERR_BIST_STATUS bdk_gti_err_bist_status_t
3110 #define bustype_BDK_GTI_ERR_BIST_STATUS BDK_CSR_TYPE_NCB
3111 #define basename_BDK_GTI_ERR_BIST_STATUS "GTI_ERR_BIST_STATUS"
3112 #define device_bar_BDK_GTI_ERR_BIST_STATUS 0x0 /* PF_BAR0 */
3113 #define busnum_BDK_GTI_ERR_BIST_STATUS 0
3114 #define arguments_BDK_GTI_ERR_BIST_STATUS -1,-1,-1,-1
3115
3116 /**
3117 * Register (NCB) gti_err_ecc_disable
3118 *
3119 * GTI ECC Disable Register
3120 */
3121 union bdk_gti_err_ecc_disable
3122 {
3123 uint64_t u;
3124 struct bdk_gti_err_ecc_disable_s
3125 {
3126 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3127 uint64_t reserved_2_63 : 62;
3128 uint64_t ram : 2; /**< [ 1: 0](R/W) Each bit disables correction of respective RAM. */
3129 #else /* Word 0 - Little Endian */
3130 uint64_t ram : 2; /**< [ 1: 0](R/W) Each bit disables correction of respective RAM. */
3131 uint64_t reserved_2_63 : 62;
3132 #endif /* Word 0 - End */
3133 } s;
3134 /* struct bdk_gti_err_ecc_disable_s cn; */
3135 };
3136 typedef union bdk_gti_err_ecc_disable bdk_gti_err_ecc_disable_t;
3137
3138 #define BDK_GTI_ERR_ECC_DISABLE BDK_GTI_ERR_ECC_DISABLE_FUNC()
3139 static inline uint64_t BDK_GTI_ERR_ECC_DISABLE_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_ECC_DISABLE_FUNC(void)3140 static inline uint64_t BDK_GTI_ERR_ECC_DISABLE_FUNC(void)
3141 {
3142 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
3143 return 0x8440000f0020ll;
3144 __bdk_csr_fatal("GTI_ERR_ECC_DISABLE", 0, 0, 0, 0, 0);
3145 }
3146
3147 #define typedef_BDK_GTI_ERR_ECC_DISABLE bdk_gti_err_ecc_disable_t
3148 #define bustype_BDK_GTI_ERR_ECC_DISABLE BDK_CSR_TYPE_NCB
3149 #define basename_BDK_GTI_ERR_ECC_DISABLE "GTI_ERR_ECC_DISABLE"
3150 #define device_bar_BDK_GTI_ERR_ECC_DISABLE 0x0 /* PF_BAR0 */
3151 #define busnum_BDK_GTI_ERR_ECC_DISABLE 0
3152 #define arguments_BDK_GTI_ERR_ECC_DISABLE -1,-1,-1,-1
3153
3154 /**
3155 * Register (NCB) gti_err_ecc_flip
3156 *
3157 * GTI ECC Flip Register
3158 */
3159 union bdk_gti_err_ecc_flip
3160 {
3161 uint64_t u;
3162 struct bdk_gti_err_ecc_flip_s
3163 {
3164 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3165 uint64_t reserved_34_63 : 30;
3166 uint64_t ramx : 2; /**< [ 33: 32](R/W) Each bit flips a second bit of syndrome in the respective RAM. */
3167 uint64_t reserved_2_31 : 30;
3168 uint64_t ram : 2; /**< [ 1: 0](R/W) Each bit flips the first bit of syndrome in the respective RAM. */
3169 #else /* Word 0 - Little Endian */
3170 uint64_t ram : 2; /**< [ 1: 0](R/W) Each bit flips the first bit of syndrome in the respective RAM. */
3171 uint64_t reserved_2_31 : 30;
3172 uint64_t ramx : 2; /**< [ 33: 32](R/W) Each bit flips a second bit of syndrome in the respective RAM. */
3173 uint64_t reserved_34_63 : 30;
3174 #endif /* Word 0 - End */
3175 } s;
3176 /* struct bdk_gti_err_ecc_flip_s cn; */
3177 };
3178 typedef union bdk_gti_err_ecc_flip bdk_gti_err_ecc_flip_t;
3179
3180 #define BDK_GTI_ERR_ECC_FLIP BDK_GTI_ERR_ECC_FLIP_FUNC()
3181 static inline uint64_t BDK_GTI_ERR_ECC_FLIP_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_ECC_FLIP_FUNC(void)3182 static inline uint64_t BDK_GTI_ERR_ECC_FLIP_FUNC(void)
3183 {
3184 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX))
3185 return 0x8440000f0028ll;
3186 __bdk_csr_fatal("GTI_ERR_ECC_FLIP", 0, 0, 0, 0, 0);
3187 }
3188
3189 #define typedef_BDK_GTI_ERR_ECC_FLIP bdk_gti_err_ecc_flip_t
3190 #define bustype_BDK_GTI_ERR_ECC_FLIP BDK_CSR_TYPE_NCB
3191 #define basename_BDK_GTI_ERR_ECC_FLIP "GTI_ERR_ECC_FLIP"
3192 #define device_bar_BDK_GTI_ERR_ECC_FLIP 0x0 /* PF_BAR0 */
3193 #define busnum_BDK_GTI_ERR_ECC_FLIP 0
3194 #define arguments_BDK_GTI_ERR_ECC_FLIP -1,-1,-1,-1
3195
3196 /**
3197 * Register (NCB) gti_err_int
3198 *
3199 * INTERNAL: GTI Error Interrupt Register
3200 */
3201 union bdk_gti_err_int
3202 {
3203 uint64_t u;
3204 struct bdk_gti_err_int_s
3205 {
3206 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3207 uint64_t reserved_34_63 : 30;
3208 uint64_t dbe : 2; /**< [ 33: 32](R/W1C/H) Double bit error. */
3209 uint64_t reserved_2_31 : 30;
3210 uint64_t sbe : 2; /**< [ 1: 0](R/W1C/H) Single bit error. */
3211 #else /* Word 0 - Little Endian */
3212 uint64_t sbe : 2; /**< [ 1: 0](R/W1C/H) Single bit error. */
3213 uint64_t reserved_2_31 : 30;
3214 uint64_t dbe : 2; /**< [ 33: 32](R/W1C/H) Double bit error. */
3215 uint64_t reserved_34_63 : 30;
3216 #endif /* Word 0 - End */
3217 } s;
3218 /* struct bdk_gti_err_int_s cn8; */
3219 struct bdk_gti_err_int_cn9
3220 {
3221 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3222 uint64_t reserved_34_63 : 30;
3223 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3224 uint64_t reserved_2_31 : 30;
3225 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3226 #else /* Word 0 - Little Endian */
3227 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3228 uint64_t reserved_2_31 : 30;
3229 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3230 uint64_t reserved_34_63 : 30;
3231 #endif /* Word 0 - End */
3232 } cn9;
3233 };
3234 typedef union bdk_gti_err_int bdk_gti_err_int_t;
3235
3236 #define BDK_GTI_ERR_INT BDK_GTI_ERR_INT_FUNC()
3237 static inline uint64_t BDK_GTI_ERR_INT_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_INT_FUNC(void)3238 static inline uint64_t BDK_GTI_ERR_INT_FUNC(void)
3239 {
3240 return 0x8440000f0000ll;
3241 }
3242
3243 #define typedef_BDK_GTI_ERR_INT bdk_gti_err_int_t
3244 #define bustype_BDK_GTI_ERR_INT BDK_CSR_TYPE_NCB
3245 #define basename_BDK_GTI_ERR_INT "GTI_ERR_INT"
3246 #define device_bar_BDK_GTI_ERR_INT 0x0 /* PF_BAR0 */
3247 #define busnum_BDK_GTI_ERR_INT 0
3248 #define arguments_BDK_GTI_ERR_INT -1,-1,-1,-1
3249
3250 /**
3251 * Register (NCB) gti_err_int_ena_clr
3252 *
3253 * INTERNAL: GTI Error Interrupt Enable Clear Register
3254 */
3255 union bdk_gti_err_int_ena_clr
3256 {
3257 uint64_t u;
3258 struct bdk_gti_err_int_ena_clr_s
3259 {
3260 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3261 uint64_t reserved_34_63 : 30;
3262 uint64_t dbe : 2; /**< [ 33: 32](R/W1C/H) Reads or clears enable for GTI_ERR_INT[DBE]. */
3263 uint64_t reserved_2_31 : 30;
3264 uint64_t sbe : 2; /**< [ 1: 0](R/W1C/H) Reads or clears enable for GTI_ERR_INT[SBE]. */
3265 #else /* Word 0 - Little Endian */
3266 uint64_t sbe : 2; /**< [ 1: 0](R/W1C/H) Reads or clears enable for GTI_ERR_INT[SBE]. */
3267 uint64_t reserved_2_31 : 30;
3268 uint64_t dbe : 2; /**< [ 33: 32](R/W1C/H) Reads or clears enable for GTI_ERR_INT[DBE]. */
3269 uint64_t reserved_34_63 : 30;
3270 #endif /* Word 0 - End */
3271 } s;
3272 /* struct bdk_gti_err_int_ena_clr_s cn8; */
3273 struct bdk_gti_err_int_ena_clr_cn9
3274 {
3275 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3276 uint64_t reserved_34_63 : 30;
3277 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3278 uint64_t reserved_2_31 : 30;
3279 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3280 #else /* Word 0 - Little Endian */
3281 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3282 uint64_t reserved_2_31 : 30;
3283 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3284 uint64_t reserved_34_63 : 30;
3285 #endif /* Word 0 - End */
3286 } cn9;
3287 };
3288 typedef union bdk_gti_err_int_ena_clr bdk_gti_err_int_ena_clr_t;
3289
3290 #define BDK_GTI_ERR_INT_ENA_CLR BDK_GTI_ERR_INT_ENA_CLR_FUNC()
3291 static inline uint64_t BDK_GTI_ERR_INT_ENA_CLR_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_INT_ENA_CLR_FUNC(void)3292 static inline uint64_t BDK_GTI_ERR_INT_ENA_CLR_FUNC(void)
3293 {
3294 return 0x8440000f0010ll;
3295 }
3296
3297 #define typedef_BDK_GTI_ERR_INT_ENA_CLR bdk_gti_err_int_ena_clr_t
3298 #define bustype_BDK_GTI_ERR_INT_ENA_CLR BDK_CSR_TYPE_NCB
3299 #define basename_BDK_GTI_ERR_INT_ENA_CLR "GTI_ERR_INT_ENA_CLR"
3300 #define device_bar_BDK_GTI_ERR_INT_ENA_CLR 0x0 /* PF_BAR0 */
3301 #define busnum_BDK_GTI_ERR_INT_ENA_CLR 0
3302 #define arguments_BDK_GTI_ERR_INT_ENA_CLR -1,-1,-1,-1
3303
3304 /**
3305 * Register (NCB) gti_err_int_ena_set
3306 *
3307 * INTERNAL: GTI Error Interrupt Enable Set Register
3308 */
3309 union bdk_gti_err_int_ena_set
3310 {
3311 uint64_t u;
3312 struct bdk_gti_err_int_ena_set_s
3313 {
3314 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3315 uint64_t reserved_34_63 : 30;
3316 uint64_t dbe : 2; /**< [ 33: 32](R/W1S/H) Reads or sets enable for GTI_ERR_INT[DBE]. */
3317 uint64_t reserved_2_31 : 30;
3318 uint64_t sbe : 2; /**< [ 1: 0](R/W1S/H) Reads or sets enable for GTI_ERR_INT[SBE]. */
3319 #else /* Word 0 - Little Endian */
3320 uint64_t sbe : 2; /**< [ 1: 0](R/W1S/H) Reads or sets enable for GTI_ERR_INT[SBE]. */
3321 uint64_t reserved_2_31 : 30;
3322 uint64_t dbe : 2; /**< [ 33: 32](R/W1S/H) Reads or sets enable for GTI_ERR_INT[DBE]. */
3323 uint64_t reserved_34_63 : 30;
3324 #endif /* Word 0 - End */
3325 } s;
3326 /* struct bdk_gti_err_int_ena_set_s cn8; */
3327 struct bdk_gti_err_int_ena_set_cn9
3328 {
3329 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3330 uint64_t reserved_34_63 : 30;
3331 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3332 uint64_t reserved_2_31 : 30;
3333 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3334 #else /* Word 0 - Little Endian */
3335 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3336 uint64_t reserved_2_31 : 30;
3337 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3338 uint64_t reserved_34_63 : 30;
3339 #endif /* Word 0 - End */
3340 } cn9;
3341 };
3342 typedef union bdk_gti_err_int_ena_set bdk_gti_err_int_ena_set_t;
3343
3344 #define BDK_GTI_ERR_INT_ENA_SET BDK_GTI_ERR_INT_ENA_SET_FUNC()
3345 static inline uint64_t BDK_GTI_ERR_INT_ENA_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_INT_ENA_SET_FUNC(void)3346 static inline uint64_t BDK_GTI_ERR_INT_ENA_SET_FUNC(void)
3347 {
3348 return 0x8440000f0018ll;
3349 }
3350
3351 #define typedef_BDK_GTI_ERR_INT_ENA_SET bdk_gti_err_int_ena_set_t
3352 #define bustype_BDK_GTI_ERR_INT_ENA_SET BDK_CSR_TYPE_NCB
3353 #define basename_BDK_GTI_ERR_INT_ENA_SET "GTI_ERR_INT_ENA_SET"
3354 #define device_bar_BDK_GTI_ERR_INT_ENA_SET 0x0 /* PF_BAR0 */
3355 #define busnum_BDK_GTI_ERR_INT_ENA_SET 0
3356 #define arguments_BDK_GTI_ERR_INT_ENA_SET -1,-1,-1,-1
3357
3358 /**
3359 * Register (NCB) gti_err_int_set
3360 *
3361 * INTERNAL: GTI Error Interrupt Set Register
3362 */
3363 union bdk_gti_err_int_set
3364 {
3365 uint64_t u;
3366 struct bdk_gti_err_int_set_s
3367 {
3368 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3369 uint64_t reserved_34_63 : 30;
3370 uint64_t dbe : 2; /**< [ 33: 32](R/W1S/H) Reads or sets GTI_ERR_INT[DBE]. */
3371 uint64_t reserved_2_31 : 30;
3372 uint64_t sbe : 2; /**< [ 1: 0](R/W1S/H) Reads or sets GTI_ERR_INT[SBE]. */
3373 #else /* Word 0 - Little Endian */
3374 uint64_t sbe : 2; /**< [ 1: 0](R/W1S/H) Reads or sets GTI_ERR_INT[SBE]. */
3375 uint64_t reserved_2_31 : 30;
3376 uint64_t dbe : 2; /**< [ 33: 32](R/W1S/H) Reads or sets GTI_ERR_INT[DBE]. */
3377 uint64_t reserved_34_63 : 30;
3378 #endif /* Word 0 - End */
3379 } s;
3380 /* struct bdk_gti_err_int_set_s cn8; */
3381 struct bdk_gti_err_int_set_cn9
3382 {
3383 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3384 uint64_t reserved_34_63 : 30;
3385 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3386 uint64_t reserved_2_31 : 30;
3387 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3388 #else /* Word 0 - Little Endian */
3389 uint64_t sbe : 2; /**< [ 1: 0](RAZ) Reserved; for backwards compatibility. */
3390 uint64_t reserved_2_31 : 30;
3391 uint64_t dbe : 2; /**< [ 33: 32](RAZ) Reserved; for backwards compatibility. */
3392 uint64_t reserved_34_63 : 30;
3393 #endif /* Word 0 - End */
3394 } cn9;
3395 };
3396 typedef union bdk_gti_err_int_set bdk_gti_err_int_set_t;
3397
3398 #define BDK_GTI_ERR_INT_SET BDK_GTI_ERR_INT_SET_FUNC()
3399 static inline uint64_t BDK_GTI_ERR_INT_SET_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_ERR_INT_SET_FUNC(void)3400 static inline uint64_t BDK_GTI_ERR_INT_SET_FUNC(void)
3401 {
3402 return 0x8440000f0008ll;
3403 }
3404
3405 #define typedef_BDK_GTI_ERR_INT_SET bdk_gti_err_int_set_t
3406 #define bustype_BDK_GTI_ERR_INT_SET BDK_CSR_TYPE_NCB
3407 #define basename_BDK_GTI_ERR_INT_SET "GTI_ERR_INT_SET"
3408 #define device_bar_BDK_GTI_ERR_INT_SET 0x0 /* PF_BAR0 */
3409 #define busnum_BDK_GTI_ERR_INT_SET 0
3410 #define arguments_BDK_GTI_ERR_INT_SET -1,-1,-1,-1
3411
3412 /**
3413 * Register (NCB32b) gti_force_clken
3414 *
3415 * GTI Force Clock Enable Register
3416 */
3417 union bdk_gti_force_clken
3418 {
3419 uint32_t u;
3420 struct bdk_gti_force_clken_s
3421 {
3422 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3423 uint32_t reserved_1_31 : 31;
3424 uint32_t clken : 1; /**< [ 0: 0](R/W) Force the conditional clocking within GTI to be always on. For diagnostic use only. */
3425 #else /* Word 0 - Little Endian */
3426 uint32_t clken : 1; /**< [ 0: 0](R/W) Force the conditional clocking within GTI to be always on. For diagnostic use only. */
3427 uint32_t reserved_1_31 : 31;
3428 #endif /* Word 0 - End */
3429 } s;
3430 /* struct bdk_gti_force_clken_s cn; */
3431 };
3432 typedef union bdk_gti_force_clken bdk_gti_force_clken_t;
3433
3434 #define BDK_GTI_FORCE_CLKEN BDK_GTI_FORCE_CLKEN_FUNC()
3435 static inline uint64_t BDK_GTI_FORCE_CLKEN_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_FORCE_CLKEN_FUNC(void)3436 static inline uint64_t BDK_GTI_FORCE_CLKEN_FUNC(void)
3437 {
3438 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3439 return 0x8440000e0000ll;
3440 __bdk_csr_fatal("GTI_FORCE_CLKEN", 0, 0, 0, 0, 0);
3441 }
3442
3443 #define typedef_BDK_GTI_FORCE_CLKEN bdk_gti_force_clken_t
3444 #define bustype_BDK_GTI_FORCE_CLKEN BDK_CSR_TYPE_NCB32b
3445 #define basename_BDK_GTI_FORCE_CLKEN "GTI_FORCE_CLKEN"
3446 #define device_bar_BDK_GTI_FORCE_CLKEN 0x0 /* PF_BAR0 */
3447 #define busnum_BDK_GTI_FORCE_CLKEN 0
3448 #define arguments_BDK_GTI_FORCE_CLKEN -1,-1,-1,-1
3449
3450 /**
3451 * Register (NCB32b) gti_imp_const
3452 *
3453 * GTI Implementation Constant Register
3454 */
3455 union bdk_gti_imp_const
3456 {
3457 uint32_t u;
3458 struct bdk_gti_imp_const_s
3459 {
3460 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3461 uint32_t reserved_8_31 : 24;
3462 uint32_t wdogs : 8; /**< [ 7: 0](RO) The number of watchdog timers implemented. */
3463 #else /* Word 0 - Little Endian */
3464 uint32_t wdogs : 8; /**< [ 7: 0](RO) The number of watchdog timers implemented. */
3465 uint32_t reserved_8_31 : 24;
3466 #endif /* Word 0 - End */
3467 } s;
3468 /* struct bdk_gti_imp_const_s cn; */
3469 };
3470 typedef union bdk_gti_imp_const bdk_gti_imp_const_t;
3471
3472 #define BDK_GTI_IMP_CONST BDK_GTI_IMP_CONST_FUNC()
3473 static inline uint64_t BDK_GTI_IMP_CONST_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_IMP_CONST_FUNC(void)3474 static inline uint64_t BDK_GTI_IMP_CONST_FUNC(void)
3475 {
3476 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
3477 return 0x8440000e0010ll;
3478 __bdk_csr_fatal("GTI_IMP_CONST", 0, 0, 0, 0, 0);
3479 }
3480
3481 #define typedef_BDK_GTI_IMP_CONST bdk_gti_imp_const_t
3482 #define bustype_BDK_GTI_IMP_CONST BDK_CSR_TYPE_NCB32b
3483 #define basename_BDK_GTI_IMP_CONST "GTI_IMP_CONST"
3484 #define device_bar_BDK_GTI_IMP_CONST 0x0 /* PF_BAR0 */
3485 #define busnum_BDK_GTI_IMP_CONST 0
3486 #define arguments_BDK_GTI_IMP_CONST -1,-1,-1,-1
3487
3488 /**
3489 * Register (NCB) gti_msix_pba#
3490 *
3491 * GTI MSI-X Pending Bit Array Registers
3492 * This register is the MSI-X PBA table, the bit number is indexed by the GTI_INT_VEC_E enumeration.
3493 */
3494 union bdk_gti_msix_pbax
3495 {
3496 uint64_t u;
3497 struct bdk_gti_msix_pbax_s
3498 {
3499 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3500 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for each interrupt, enumerated by GTI_INT_VEC_E.
3501 Bits that have no associated GTI_INT_VEC_E are zero. */
3502 #else /* Word 0 - Little Endian */
3503 uint64_t pend : 64; /**< [ 63: 0](RO/H) Pending message for each interrupt, enumerated by GTI_INT_VEC_E.
3504 Bits that have no associated GTI_INT_VEC_E are zero. */
3505 #endif /* Word 0 - End */
3506 } s;
3507 /* struct bdk_gti_msix_pbax_s cn; */
3508 };
3509 typedef union bdk_gti_msix_pbax bdk_gti_msix_pbax_t;
3510
3511 static inline uint64_t BDK_GTI_MSIX_PBAX(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_MSIX_PBAX(unsigned long a)3512 static inline uint64_t BDK_GTI_MSIX_PBAX(unsigned long a)
3513 {
3514 if (a<=1)
3515 return 0x84400f0f0000ll + 8ll * ((a) & 0x1);
3516 __bdk_csr_fatal("GTI_MSIX_PBAX", 1, a, 0, 0, 0);
3517 }
3518
3519 #define typedef_BDK_GTI_MSIX_PBAX(a) bdk_gti_msix_pbax_t
3520 #define bustype_BDK_GTI_MSIX_PBAX(a) BDK_CSR_TYPE_NCB
3521 #define basename_BDK_GTI_MSIX_PBAX(a) "GTI_MSIX_PBAX"
3522 #define device_bar_BDK_GTI_MSIX_PBAX(a) 0x4 /* PF_BAR4 */
3523 #define busnum_BDK_GTI_MSIX_PBAX(a) (a)
3524 #define arguments_BDK_GTI_MSIX_PBAX(a) (a),-1,-1,-1
3525
3526 /**
3527 * Register (NCB) gti_msix_vec#_addr
3528 *
3529 * GTI MSI-X Vector Table Address Registers
3530 * This register is the MSI-X vector table, indexed by the GTI_INT_VEC_E enumeration.
3531 */
3532 union bdk_gti_msix_vecx_addr
3533 {
3534 uint64_t u;
3535 struct bdk_gti_msix_vecx_addr_s
3536 {
3537 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3538 uint64_t reserved_53_63 : 11;
3539 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3540 uint64_t reserved_1 : 1;
3541 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3542 0 = This vector may be read or written by either secure or nonsecure states.
3543 1 = This vector's GTI_MSIX_VEC()_ADDR, GTI_MSIX_VEC()_CTL, and corresponding
3544 bit of GTI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3545 by the nonsecure world.
3546
3547 If PCCPF_GTI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3548 set, all vectors are secure and function as if [SECVEC] was set. */
3549 #else /* Word 0 - Little Endian */
3550 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3551 0 = This vector may be read or written by either secure or nonsecure states.
3552 1 = This vector's GTI_MSIX_VEC()_ADDR, GTI_MSIX_VEC()_CTL, and corresponding
3553 bit of GTI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3554 by the nonsecure world.
3555
3556 If PCCPF_GTI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3557 set, all vectors are secure and function as if [SECVEC] was set. */
3558 uint64_t reserved_1 : 1;
3559 uint64_t addr : 51; /**< [ 52: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3560 uint64_t reserved_53_63 : 11;
3561 #endif /* Word 0 - End */
3562 } s;
3563 struct bdk_gti_msix_vecx_addr_cn8
3564 {
3565 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3566 uint64_t reserved_49_63 : 15;
3567 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3568 uint64_t reserved_1 : 1;
3569 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3570 0 = This vector may be read or written by either secure or nonsecure states.
3571 1 = This vector's GTI_MSIX_VEC()_ADDR, GTI_MSIX_VEC()_CTL, and corresponding
3572 bit of GTI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3573 by the nonsecure world.
3574
3575 If PCCPF_GTI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3576 set, all vectors are secure and function as if [SECVEC] was set. */
3577 #else /* Word 0 - Little Endian */
3578 uint64_t secvec : 1; /**< [ 0: 0](SR/W) Secure vector.
3579 0 = This vector may be read or written by either secure or nonsecure states.
3580 1 = This vector's GTI_MSIX_VEC()_ADDR, GTI_MSIX_VEC()_CTL, and corresponding
3581 bit of GTI_MSIX_PBA() are RAZ/WI and does not cause a fault when accessed
3582 by the nonsecure world.
3583
3584 If PCCPF_GTI_VSEC_SCTL[MSIX_SEC] (for documentation, see PCCPF_XXX_VSEC_SCTL[MSIX_SEC]) is
3585 set, all vectors are secure and function as if [SECVEC] was set. */
3586 uint64_t reserved_1 : 1;
3587 uint64_t addr : 47; /**< [ 48: 2](R/W) IOVA to use for MSI-X delivery of this vector. */
3588 uint64_t reserved_49_63 : 15;
3589 #endif /* Word 0 - End */
3590 } cn8;
3591 /* struct bdk_gti_msix_vecx_addr_s cn9; */
3592 };
3593 typedef union bdk_gti_msix_vecx_addr bdk_gti_msix_vecx_addr_t;
3594
3595 static inline uint64_t BDK_GTI_MSIX_VECX_ADDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_MSIX_VECX_ADDR(unsigned long a)3596 static inline uint64_t BDK_GTI_MSIX_VECX_ADDR(unsigned long a)
3597 {
3598 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=105))
3599 return 0x84400f000000ll + 0x10ll * ((a) & 0x7f);
3600 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=117))
3601 return 0x84400f000000ll + 0x10ll * ((a) & 0x7f);
3602 __bdk_csr_fatal("GTI_MSIX_VECX_ADDR", 1, a, 0, 0, 0);
3603 }
3604
3605 #define typedef_BDK_GTI_MSIX_VECX_ADDR(a) bdk_gti_msix_vecx_addr_t
3606 #define bustype_BDK_GTI_MSIX_VECX_ADDR(a) BDK_CSR_TYPE_NCB
3607 #define basename_BDK_GTI_MSIX_VECX_ADDR(a) "GTI_MSIX_VECX_ADDR"
3608 #define device_bar_BDK_GTI_MSIX_VECX_ADDR(a) 0x4 /* PF_BAR4 */
3609 #define busnum_BDK_GTI_MSIX_VECX_ADDR(a) (a)
3610 #define arguments_BDK_GTI_MSIX_VECX_ADDR(a) (a),-1,-1,-1
3611
3612 /**
3613 * Register (NCB) gti_msix_vec#_ctl
3614 *
3615 * GTI MSI-X Vector Table Control and Data Registers
3616 * This register is the MSI-X vector table, indexed by the GTI_INT_VEC_E enumeration.
3617 */
3618 union bdk_gti_msix_vecx_ctl
3619 {
3620 uint64_t u;
3621 struct bdk_gti_msix_vecx_ctl_s
3622 {
3623 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3624 uint64_t reserved_33_63 : 31;
3625 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
3626 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
3627 #else /* Word 0 - Little Endian */
3628 uint64_t data : 32; /**< [ 31: 0](R/W) Data to use for MSI-X delivery of this vector. */
3629 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
3630 uint64_t reserved_33_63 : 31;
3631 #endif /* Word 0 - End */
3632 } s;
3633 struct bdk_gti_msix_vecx_ctl_cn8
3634 {
3635 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3636 uint64_t reserved_33_63 : 31;
3637 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
3638 uint64_t reserved_20_31 : 12;
3639 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
3640 #else /* Word 0 - Little Endian */
3641 uint64_t data : 20; /**< [ 19: 0](R/W) Data to use for MSI-X delivery of this vector. */
3642 uint64_t reserved_20_31 : 12;
3643 uint64_t mask : 1; /**< [ 32: 32](R/W) When set, no MSI-X interrupts will be sent to this vector. */
3644 uint64_t reserved_33_63 : 31;
3645 #endif /* Word 0 - End */
3646 } cn8;
3647 /* struct bdk_gti_msix_vecx_ctl_s cn9; */
3648 };
3649 typedef union bdk_gti_msix_vecx_ctl bdk_gti_msix_vecx_ctl_t;
3650
3651 static inline uint64_t BDK_GTI_MSIX_VECX_CTL(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_MSIX_VECX_CTL(unsigned long a)3652 static inline uint64_t BDK_GTI_MSIX_VECX_CTL(unsigned long a)
3653 {
3654 if (CAVIUM_IS_MODEL(CAVIUM_CN8XXX) && (a<=105))
3655 return 0x84400f000008ll + 0x10ll * ((a) & 0x7f);
3656 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX) && (a<=117))
3657 return 0x84400f000008ll + 0x10ll * ((a) & 0x7f);
3658 __bdk_csr_fatal("GTI_MSIX_VECX_CTL", 1, a, 0, 0, 0);
3659 }
3660
3661 #define typedef_BDK_GTI_MSIX_VECX_CTL(a) bdk_gti_msix_vecx_ctl_t
3662 #define bustype_BDK_GTI_MSIX_VECX_CTL(a) BDK_CSR_TYPE_NCB
3663 #define basename_BDK_GTI_MSIX_VECX_CTL(a) "GTI_MSIX_VECX_CTL"
3664 #define device_bar_BDK_GTI_MSIX_VECX_CTL(a) 0x4 /* PF_BAR4 */
3665 #define busnum_BDK_GTI_MSIX_VECX_CTL(a) (a)
3666 #define arguments_BDK_GTI_MSIX_VECX_CTL(a) (a),-1,-1,-1
3667
3668 /**
3669 * Register (NCB32b) gti_rd_cidr0
3670 *
3671 * GTI Counter Read Component Identification Register 0
3672 */
3673 union bdk_gti_rd_cidr0
3674 {
3675 uint32_t u;
3676 struct bdk_gti_rd_cidr0_s
3677 {
3678 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3679 uint32_t reserved_8_31 : 24;
3680 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3681 #else /* Word 0 - Little Endian */
3682 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3683 uint32_t reserved_8_31 : 24;
3684 #endif /* Word 0 - End */
3685 } s;
3686 /* struct bdk_gti_rd_cidr0_s cn; */
3687 };
3688 typedef union bdk_gti_rd_cidr0 bdk_gti_rd_cidr0_t;
3689
3690 #define BDK_GTI_RD_CIDR0 BDK_GTI_RD_CIDR0_FUNC()
3691 static inline uint64_t BDK_GTI_RD_CIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_CIDR0_FUNC(void)3692 static inline uint64_t BDK_GTI_RD_CIDR0_FUNC(void)
3693 {
3694 return 0x844000010ff0ll;
3695 }
3696
3697 #define typedef_BDK_GTI_RD_CIDR0 bdk_gti_rd_cidr0_t
3698 #define bustype_BDK_GTI_RD_CIDR0 BDK_CSR_TYPE_NCB32b
3699 #define basename_BDK_GTI_RD_CIDR0 "GTI_RD_CIDR0"
3700 #define device_bar_BDK_GTI_RD_CIDR0 0x0 /* PF_BAR0 */
3701 #define busnum_BDK_GTI_RD_CIDR0 0
3702 #define arguments_BDK_GTI_RD_CIDR0 -1,-1,-1,-1
3703
3704 /**
3705 * Register (NCB32b) gti_rd_cidr1
3706 *
3707 * GTI Counter Read Component Identification Register 1
3708 */
3709 union bdk_gti_rd_cidr1
3710 {
3711 uint32_t u;
3712 struct bdk_gti_rd_cidr1_s
3713 {
3714 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3715 uint32_t reserved_8_31 : 24;
3716 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
3717 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
3718 #else /* Word 0 - Little Endian */
3719 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
3720 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
3721 uint32_t reserved_8_31 : 24;
3722 #endif /* Word 0 - End */
3723 } s;
3724 /* struct bdk_gti_rd_cidr1_s cn; */
3725 };
3726 typedef union bdk_gti_rd_cidr1 bdk_gti_rd_cidr1_t;
3727
3728 #define BDK_GTI_RD_CIDR1 BDK_GTI_RD_CIDR1_FUNC()
3729 static inline uint64_t BDK_GTI_RD_CIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_CIDR1_FUNC(void)3730 static inline uint64_t BDK_GTI_RD_CIDR1_FUNC(void)
3731 {
3732 return 0x844000010ff4ll;
3733 }
3734
3735 #define typedef_BDK_GTI_RD_CIDR1 bdk_gti_rd_cidr1_t
3736 #define bustype_BDK_GTI_RD_CIDR1 BDK_CSR_TYPE_NCB32b
3737 #define basename_BDK_GTI_RD_CIDR1 "GTI_RD_CIDR1"
3738 #define device_bar_BDK_GTI_RD_CIDR1 0x0 /* PF_BAR0 */
3739 #define busnum_BDK_GTI_RD_CIDR1 0
3740 #define arguments_BDK_GTI_RD_CIDR1 -1,-1,-1,-1
3741
3742 /**
3743 * Register (NCB32b) gti_rd_cidr2
3744 *
3745 * GTI Counter Read Component Identification Register 2
3746 */
3747 union bdk_gti_rd_cidr2
3748 {
3749 uint32_t u;
3750 struct bdk_gti_rd_cidr2_s
3751 {
3752 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3753 uint32_t reserved_8_31 : 24;
3754 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3755 #else /* Word 0 - Little Endian */
3756 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
3757 uint32_t reserved_8_31 : 24;
3758 #endif /* Word 0 - End */
3759 } s;
3760 /* struct bdk_gti_rd_cidr2_s cn; */
3761 };
3762 typedef union bdk_gti_rd_cidr2 bdk_gti_rd_cidr2_t;
3763
3764 #define BDK_GTI_RD_CIDR2 BDK_GTI_RD_CIDR2_FUNC()
3765 static inline uint64_t BDK_GTI_RD_CIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_CIDR2_FUNC(void)3766 static inline uint64_t BDK_GTI_RD_CIDR2_FUNC(void)
3767 {
3768 return 0x844000010ff8ll;
3769 }
3770
3771 #define typedef_BDK_GTI_RD_CIDR2 bdk_gti_rd_cidr2_t
3772 #define bustype_BDK_GTI_RD_CIDR2 BDK_CSR_TYPE_NCB32b
3773 #define basename_BDK_GTI_RD_CIDR2 "GTI_RD_CIDR2"
3774 #define device_bar_BDK_GTI_RD_CIDR2 0x0 /* PF_BAR0 */
3775 #define busnum_BDK_GTI_RD_CIDR2 0
3776 #define arguments_BDK_GTI_RD_CIDR2 -1,-1,-1,-1
3777
3778 /**
3779 * Register (NCB32b) gti_rd_cidr3
3780 *
3781 * GTI Counter Read Component Identification Register 3
3782 */
3783 union bdk_gti_rd_cidr3
3784 {
3785 uint32_t u;
3786 struct bdk_gti_rd_cidr3_s
3787 {
3788 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3789 uint32_t reserved_8_31 : 24;
3790 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
3791 #else /* Word 0 - Little Endian */
3792 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
3793 uint32_t reserved_8_31 : 24;
3794 #endif /* Word 0 - End */
3795 } s;
3796 /* struct bdk_gti_rd_cidr3_s cn; */
3797 };
3798 typedef union bdk_gti_rd_cidr3 bdk_gti_rd_cidr3_t;
3799
3800 #define BDK_GTI_RD_CIDR3 BDK_GTI_RD_CIDR3_FUNC()
3801 static inline uint64_t BDK_GTI_RD_CIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_CIDR3_FUNC(void)3802 static inline uint64_t BDK_GTI_RD_CIDR3_FUNC(void)
3803 {
3804 return 0x844000010ffcll;
3805 }
3806
3807 #define typedef_BDK_GTI_RD_CIDR3 bdk_gti_rd_cidr3_t
3808 #define bustype_BDK_GTI_RD_CIDR3 BDK_CSR_TYPE_NCB32b
3809 #define basename_BDK_GTI_RD_CIDR3 "GTI_RD_CIDR3"
3810 #define device_bar_BDK_GTI_RD_CIDR3 0x0 /* PF_BAR0 */
3811 #define busnum_BDK_GTI_RD_CIDR3 0
3812 #define arguments_BDK_GTI_RD_CIDR3 -1,-1,-1,-1
3813
3814 /**
3815 * Register (NCB) gti_rd_cntcv
3816 *
3817 * GTI Counter Read Value Register
3818 */
3819 union bdk_gti_rd_cntcv
3820 {
3821 uint64_t u;
3822 struct bdk_gti_rd_cntcv_s
3823 {
3824 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3825 uint64_t cnt : 64; /**< [ 63: 0](RO/H) System counter count value. The counter is writable with GTI_CC_CNTCV. */
3826 #else /* Word 0 - Little Endian */
3827 uint64_t cnt : 64; /**< [ 63: 0](RO/H) System counter count value. The counter is writable with GTI_CC_CNTCV. */
3828 #endif /* Word 0 - End */
3829 } s;
3830 /* struct bdk_gti_rd_cntcv_s cn; */
3831 };
3832 typedef union bdk_gti_rd_cntcv bdk_gti_rd_cntcv_t;
3833
3834 #define BDK_GTI_RD_CNTCV BDK_GTI_RD_CNTCV_FUNC()
3835 static inline uint64_t BDK_GTI_RD_CNTCV_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_CNTCV_FUNC(void)3836 static inline uint64_t BDK_GTI_RD_CNTCV_FUNC(void)
3837 {
3838 return 0x844000010000ll;
3839 }
3840
3841 #define typedef_BDK_GTI_RD_CNTCV bdk_gti_rd_cntcv_t
3842 #define bustype_BDK_GTI_RD_CNTCV BDK_CSR_TYPE_NCB
3843 #define basename_BDK_GTI_RD_CNTCV "GTI_RD_CNTCV"
3844 #define device_bar_BDK_GTI_RD_CNTCV 0x0 /* PF_BAR0 */
3845 #define busnum_BDK_GTI_RD_CNTCV 0
3846 #define arguments_BDK_GTI_RD_CNTCV -1,-1,-1,-1
3847
3848 /**
3849 * Register (NCB32b) gti_rd_pidr0
3850 *
3851 * GTI Counter Read Peripheral Identification Register 0
3852 */
3853 union bdk_gti_rd_pidr0
3854 {
3855 uint32_t u;
3856 struct bdk_gti_rd_pidr0_s
3857 {
3858 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3859 uint32_t reserved_8_31 : 24;
3860 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_RD. */
3861 #else /* Word 0 - Little Endian */
3862 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_RD. */
3863 uint32_t reserved_8_31 : 24;
3864 #endif /* Word 0 - End */
3865 } s;
3866 /* struct bdk_gti_rd_pidr0_s cn; */
3867 };
3868 typedef union bdk_gti_rd_pidr0 bdk_gti_rd_pidr0_t;
3869
3870 #define BDK_GTI_RD_PIDR0 BDK_GTI_RD_PIDR0_FUNC()
3871 static inline uint64_t BDK_GTI_RD_PIDR0_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR0_FUNC(void)3872 static inline uint64_t BDK_GTI_RD_PIDR0_FUNC(void)
3873 {
3874 return 0x844000010fe0ll;
3875 }
3876
3877 #define typedef_BDK_GTI_RD_PIDR0 bdk_gti_rd_pidr0_t
3878 #define bustype_BDK_GTI_RD_PIDR0 BDK_CSR_TYPE_NCB32b
3879 #define basename_BDK_GTI_RD_PIDR0 "GTI_RD_PIDR0"
3880 #define device_bar_BDK_GTI_RD_PIDR0 0x0 /* PF_BAR0 */
3881 #define busnum_BDK_GTI_RD_PIDR0 0
3882 #define arguments_BDK_GTI_RD_PIDR0 -1,-1,-1,-1
3883
3884 /**
3885 * Register (NCB32b) gti_rd_pidr1
3886 *
3887 * GTI Counter Read Peripheral Identification Register 1
3888 */
3889 union bdk_gti_rd_pidr1
3890 {
3891 uint32_t u;
3892 struct bdk_gti_rd_pidr1_s
3893 {
3894 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3895 uint32_t reserved_8_31 : 24;
3896 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
3897 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
3898 #else /* Word 0 - Little Endian */
3899 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
3900 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
3901 uint32_t reserved_8_31 : 24;
3902 #endif /* Word 0 - End */
3903 } s;
3904 /* struct bdk_gti_rd_pidr1_s cn; */
3905 };
3906 typedef union bdk_gti_rd_pidr1 bdk_gti_rd_pidr1_t;
3907
3908 #define BDK_GTI_RD_PIDR1 BDK_GTI_RD_PIDR1_FUNC()
3909 static inline uint64_t BDK_GTI_RD_PIDR1_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR1_FUNC(void)3910 static inline uint64_t BDK_GTI_RD_PIDR1_FUNC(void)
3911 {
3912 return 0x844000010fe4ll;
3913 }
3914
3915 #define typedef_BDK_GTI_RD_PIDR1 bdk_gti_rd_pidr1_t
3916 #define bustype_BDK_GTI_RD_PIDR1 BDK_CSR_TYPE_NCB32b
3917 #define basename_BDK_GTI_RD_PIDR1 "GTI_RD_PIDR1"
3918 #define device_bar_BDK_GTI_RD_PIDR1 0x0 /* PF_BAR0 */
3919 #define busnum_BDK_GTI_RD_PIDR1 0
3920 #define arguments_BDK_GTI_RD_PIDR1 -1,-1,-1,-1
3921
3922 /**
3923 * Register (NCB32b) gti_rd_pidr2
3924 *
3925 * GTI Counter Read Peripheral Identification Register 2
3926 */
3927 union bdk_gti_rd_pidr2
3928 {
3929 uint32_t u;
3930 struct bdk_gti_rd_pidr2_s
3931 {
3932 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3933 uint32_t reserved_8_31 : 24;
3934 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
3935 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
3936 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
3937 #else /* Word 0 - Little Endian */
3938 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
3939 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
3940 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
3941 uint32_t reserved_8_31 : 24;
3942 #endif /* Word 0 - End */
3943 } s;
3944 /* struct bdk_gti_rd_pidr2_s cn; */
3945 };
3946 typedef union bdk_gti_rd_pidr2 bdk_gti_rd_pidr2_t;
3947
3948 #define BDK_GTI_RD_PIDR2 BDK_GTI_RD_PIDR2_FUNC()
3949 static inline uint64_t BDK_GTI_RD_PIDR2_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR2_FUNC(void)3950 static inline uint64_t BDK_GTI_RD_PIDR2_FUNC(void)
3951 {
3952 return 0x844000010fe8ll;
3953 }
3954
3955 #define typedef_BDK_GTI_RD_PIDR2 bdk_gti_rd_pidr2_t
3956 #define bustype_BDK_GTI_RD_PIDR2 BDK_CSR_TYPE_NCB32b
3957 #define basename_BDK_GTI_RD_PIDR2 "GTI_RD_PIDR2"
3958 #define device_bar_BDK_GTI_RD_PIDR2 0x0 /* PF_BAR0 */
3959 #define busnum_BDK_GTI_RD_PIDR2 0
3960 #define arguments_BDK_GTI_RD_PIDR2 -1,-1,-1,-1
3961
3962 /**
3963 * Register (NCB32b) gti_rd_pidr3
3964 *
3965 * GTI Counter Read Peripheral Identification Register 3
3966 */
3967 union bdk_gti_rd_pidr3
3968 {
3969 uint32_t u;
3970 struct bdk_gti_rd_pidr3_s
3971 {
3972 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
3973 uint32_t reserved_8_31 : 24;
3974 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
3975 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
3976 product, major and minor pass numbers. */
3977 #else /* Word 0 - Little Endian */
3978 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
3979 product, major and minor pass numbers. */
3980 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
3981 uint32_t reserved_8_31 : 24;
3982 #endif /* Word 0 - End */
3983 } s;
3984 /* struct bdk_gti_rd_pidr3_s cn; */
3985 };
3986 typedef union bdk_gti_rd_pidr3 bdk_gti_rd_pidr3_t;
3987
3988 #define BDK_GTI_RD_PIDR3 BDK_GTI_RD_PIDR3_FUNC()
3989 static inline uint64_t BDK_GTI_RD_PIDR3_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR3_FUNC(void)3990 static inline uint64_t BDK_GTI_RD_PIDR3_FUNC(void)
3991 {
3992 return 0x844000010fecll;
3993 }
3994
3995 #define typedef_BDK_GTI_RD_PIDR3 bdk_gti_rd_pidr3_t
3996 #define bustype_BDK_GTI_RD_PIDR3 BDK_CSR_TYPE_NCB32b
3997 #define basename_BDK_GTI_RD_PIDR3 "GTI_RD_PIDR3"
3998 #define device_bar_BDK_GTI_RD_PIDR3 0x0 /* PF_BAR0 */
3999 #define busnum_BDK_GTI_RD_PIDR3 0
4000 #define arguments_BDK_GTI_RD_PIDR3 -1,-1,-1,-1
4001
4002 /**
4003 * Register (NCB32b) gti_rd_pidr4
4004 *
4005 * GTI Counter Read Peripheral Identification Register 4
4006 */
4007 union bdk_gti_rd_pidr4
4008 {
4009 uint32_t u;
4010 struct bdk_gti_rd_pidr4_s
4011 {
4012 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4013 uint32_t reserved_8_31 : 24;
4014 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
4015 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
4016 #else /* Word 0 - Little Endian */
4017 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
4018 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
4019 uint32_t reserved_8_31 : 24;
4020 #endif /* Word 0 - End */
4021 } s;
4022 /* struct bdk_gti_rd_pidr4_s cn; */
4023 };
4024 typedef union bdk_gti_rd_pidr4 bdk_gti_rd_pidr4_t;
4025
4026 #define BDK_GTI_RD_PIDR4 BDK_GTI_RD_PIDR4_FUNC()
4027 static inline uint64_t BDK_GTI_RD_PIDR4_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR4_FUNC(void)4028 static inline uint64_t BDK_GTI_RD_PIDR4_FUNC(void)
4029 {
4030 return 0x844000010fd0ll;
4031 }
4032
4033 #define typedef_BDK_GTI_RD_PIDR4 bdk_gti_rd_pidr4_t
4034 #define bustype_BDK_GTI_RD_PIDR4 BDK_CSR_TYPE_NCB32b
4035 #define basename_BDK_GTI_RD_PIDR4 "GTI_RD_PIDR4"
4036 #define device_bar_BDK_GTI_RD_PIDR4 0x0 /* PF_BAR0 */
4037 #define busnum_BDK_GTI_RD_PIDR4 0
4038 #define arguments_BDK_GTI_RD_PIDR4 -1,-1,-1,-1
4039
4040 /**
4041 * Register (NCB32b) gti_rd_pidr5
4042 *
4043 * GTI Counter Read Peripheral Identification Register 5
4044 */
4045 union bdk_gti_rd_pidr5
4046 {
4047 uint32_t u;
4048 struct bdk_gti_rd_pidr5_s
4049 {
4050 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4051 uint32_t reserved_0_31 : 32;
4052 #else /* Word 0 - Little Endian */
4053 uint32_t reserved_0_31 : 32;
4054 #endif /* Word 0 - End */
4055 } s;
4056 /* struct bdk_gti_rd_pidr5_s cn; */
4057 };
4058 typedef union bdk_gti_rd_pidr5 bdk_gti_rd_pidr5_t;
4059
4060 #define BDK_GTI_RD_PIDR5 BDK_GTI_RD_PIDR5_FUNC()
4061 static inline uint64_t BDK_GTI_RD_PIDR5_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR5_FUNC(void)4062 static inline uint64_t BDK_GTI_RD_PIDR5_FUNC(void)
4063 {
4064 return 0x844000010fd4ll;
4065 }
4066
4067 #define typedef_BDK_GTI_RD_PIDR5 bdk_gti_rd_pidr5_t
4068 #define bustype_BDK_GTI_RD_PIDR5 BDK_CSR_TYPE_NCB32b
4069 #define basename_BDK_GTI_RD_PIDR5 "GTI_RD_PIDR5"
4070 #define device_bar_BDK_GTI_RD_PIDR5 0x0 /* PF_BAR0 */
4071 #define busnum_BDK_GTI_RD_PIDR5 0
4072 #define arguments_BDK_GTI_RD_PIDR5 -1,-1,-1,-1
4073
4074 /**
4075 * Register (NCB32b) gti_rd_pidr6
4076 *
4077 * GTI Counter Read Peripheral Identification Register 6
4078 */
4079 union bdk_gti_rd_pidr6
4080 {
4081 uint32_t u;
4082 struct bdk_gti_rd_pidr6_s
4083 {
4084 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4085 uint32_t reserved_0_31 : 32;
4086 #else /* Word 0 - Little Endian */
4087 uint32_t reserved_0_31 : 32;
4088 #endif /* Word 0 - End */
4089 } s;
4090 /* struct bdk_gti_rd_pidr6_s cn; */
4091 };
4092 typedef union bdk_gti_rd_pidr6 bdk_gti_rd_pidr6_t;
4093
4094 #define BDK_GTI_RD_PIDR6 BDK_GTI_RD_PIDR6_FUNC()
4095 static inline uint64_t BDK_GTI_RD_PIDR6_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR6_FUNC(void)4096 static inline uint64_t BDK_GTI_RD_PIDR6_FUNC(void)
4097 {
4098 return 0x844000010fd8ll;
4099 }
4100
4101 #define typedef_BDK_GTI_RD_PIDR6 bdk_gti_rd_pidr6_t
4102 #define bustype_BDK_GTI_RD_PIDR6 BDK_CSR_TYPE_NCB32b
4103 #define basename_BDK_GTI_RD_PIDR6 "GTI_RD_PIDR6"
4104 #define device_bar_BDK_GTI_RD_PIDR6 0x0 /* PF_BAR0 */
4105 #define busnum_BDK_GTI_RD_PIDR6 0
4106 #define arguments_BDK_GTI_RD_PIDR6 -1,-1,-1,-1
4107
4108 /**
4109 * Register (NCB32b) gti_rd_pidr7
4110 *
4111 * GTI Counter Read Peripheral Identification Register 7
4112 */
4113 union bdk_gti_rd_pidr7
4114 {
4115 uint32_t u;
4116 struct bdk_gti_rd_pidr7_s
4117 {
4118 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4119 uint32_t reserved_0_31 : 32;
4120 #else /* Word 0 - Little Endian */
4121 uint32_t reserved_0_31 : 32;
4122 #endif /* Word 0 - End */
4123 } s;
4124 /* struct bdk_gti_rd_pidr7_s cn; */
4125 };
4126 typedef union bdk_gti_rd_pidr7 bdk_gti_rd_pidr7_t;
4127
4128 #define BDK_GTI_RD_PIDR7 BDK_GTI_RD_PIDR7_FUNC()
4129 static inline uint64_t BDK_GTI_RD_PIDR7_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_RD_PIDR7_FUNC(void)4130 static inline uint64_t BDK_GTI_RD_PIDR7_FUNC(void)
4131 {
4132 return 0x844000010fdcll;
4133 }
4134
4135 #define typedef_BDK_GTI_RD_PIDR7 bdk_gti_rd_pidr7_t
4136 #define bustype_BDK_GTI_RD_PIDR7 BDK_CSR_TYPE_NCB32b
4137 #define basename_BDK_GTI_RD_PIDR7 "GTI_RD_PIDR7"
4138 #define device_bar_BDK_GTI_RD_PIDR7 0x0 /* PF_BAR0 */
4139 #define busnum_BDK_GTI_RD_PIDR7 0
4140 #define arguments_BDK_GTI_RD_PIDR7 -1,-1,-1,-1
4141
4142 /**
4143 * Register (NCB) gti_scratch
4144 *
4145 * INTERNAL: GTI Scratch Register
4146 */
4147 union bdk_gti_scratch
4148 {
4149 uint64_t u;
4150 struct bdk_gti_scratch_s
4151 {
4152 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4153 uint64_t scratch : 64; /**< [ 63: 0](R/W) Scratch register. */
4154 #else /* Word 0 - Little Endian */
4155 uint64_t scratch : 64; /**< [ 63: 0](R/W) Scratch register. */
4156 #endif /* Word 0 - End */
4157 } s;
4158 /* struct bdk_gti_scratch_s cn; */
4159 };
4160 typedef union bdk_gti_scratch bdk_gti_scratch_t;
4161
4162 #define BDK_GTI_SCRATCH BDK_GTI_SCRATCH_FUNC()
4163 static inline uint64_t BDK_GTI_SCRATCH_FUNC(void) __attribute__ ((pure, always_inline));
BDK_GTI_SCRATCH_FUNC(void)4164 static inline uint64_t BDK_GTI_SCRATCH_FUNC(void)
4165 {
4166 if (CAVIUM_IS_MODEL(CAVIUM_CN9XXX))
4167 return 0x8440000e0018ll;
4168 __bdk_csr_fatal("GTI_SCRATCH", 0, 0, 0, 0, 0);
4169 }
4170
4171 #define typedef_BDK_GTI_SCRATCH bdk_gti_scratch_t
4172 #define bustype_BDK_GTI_SCRATCH BDK_CSR_TYPE_NCB
4173 #define basename_BDK_GTI_SCRATCH "GTI_SCRATCH"
4174 #define device_bar_BDK_GTI_SCRATCH 0x0 /* PF_BAR0 */
4175 #define busnum_BDK_GTI_SCRATCH 0
4176 #define arguments_BDK_GTI_SCRATCH -1,-1,-1,-1
4177
4178 /**
4179 * Register (NCB32b) gti_wc#_cidr0
4180 *
4181 * GTI Watchdog Control Component Identification Register 0
4182 */
4183 union bdk_gti_wcx_cidr0
4184 {
4185 uint32_t u;
4186 struct bdk_gti_wcx_cidr0_s
4187 {
4188 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4189 uint32_t reserved_8_31 : 24;
4190 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4191 #else /* Word 0 - Little Endian */
4192 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4193 uint32_t reserved_8_31 : 24;
4194 #endif /* Word 0 - End */
4195 } s;
4196 /* struct bdk_gti_wcx_cidr0_s cn; */
4197 };
4198 typedef union bdk_gti_wcx_cidr0 bdk_gti_wcx_cidr0_t;
4199
4200 static inline uint64_t BDK_GTI_WCX_CIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_CIDR0(unsigned long a)4201 static inline uint64_t BDK_GTI_WCX_CIDR0(unsigned long a)
4202 {
4203 if (a<=1)
4204 return 0x844000080ff0ll + 0x20000ll * ((a) & 0x1);
4205 __bdk_csr_fatal("GTI_WCX_CIDR0", 1, a, 0, 0, 0);
4206 }
4207
4208 #define typedef_BDK_GTI_WCX_CIDR0(a) bdk_gti_wcx_cidr0_t
4209 #define bustype_BDK_GTI_WCX_CIDR0(a) BDK_CSR_TYPE_NCB32b
4210 #define basename_BDK_GTI_WCX_CIDR0(a) "GTI_WCX_CIDR0"
4211 #define device_bar_BDK_GTI_WCX_CIDR0(a) 0x0 /* PF_BAR0 */
4212 #define busnum_BDK_GTI_WCX_CIDR0(a) (a)
4213 #define arguments_BDK_GTI_WCX_CIDR0(a) (a),-1,-1,-1
4214
4215 /**
4216 * Register (NCB32b) gti_wc#_cidr1
4217 *
4218 * GTI Watchdog Control Component Identification Register 1
4219 */
4220 union bdk_gti_wcx_cidr1
4221 {
4222 uint32_t u;
4223 struct bdk_gti_wcx_cidr1_s
4224 {
4225 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4226 uint32_t reserved_8_31 : 24;
4227 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
4228 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
4229 #else /* Word 0 - Little Endian */
4230 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
4231 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
4232 uint32_t reserved_8_31 : 24;
4233 #endif /* Word 0 - End */
4234 } s;
4235 /* struct bdk_gti_wcx_cidr1_s cn; */
4236 };
4237 typedef union bdk_gti_wcx_cidr1 bdk_gti_wcx_cidr1_t;
4238
4239 static inline uint64_t BDK_GTI_WCX_CIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_CIDR1(unsigned long a)4240 static inline uint64_t BDK_GTI_WCX_CIDR1(unsigned long a)
4241 {
4242 if (a<=1)
4243 return 0x844000080ff4ll + 0x20000ll * ((a) & 0x1);
4244 __bdk_csr_fatal("GTI_WCX_CIDR1", 1, a, 0, 0, 0);
4245 }
4246
4247 #define typedef_BDK_GTI_WCX_CIDR1(a) bdk_gti_wcx_cidr1_t
4248 #define bustype_BDK_GTI_WCX_CIDR1(a) BDK_CSR_TYPE_NCB32b
4249 #define basename_BDK_GTI_WCX_CIDR1(a) "GTI_WCX_CIDR1"
4250 #define device_bar_BDK_GTI_WCX_CIDR1(a) 0x0 /* PF_BAR0 */
4251 #define busnum_BDK_GTI_WCX_CIDR1(a) (a)
4252 #define arguments_BDK_GTI_WCX_CIDR1(a) (a),-1,-1,-1
4253
4254 /**
4255 * Register (NCB32b) gti_wc#_cidr2
4256 *
4257 * GTI Watchdog Control Component Identification Register 2
4258 */
4259 union bdk_gti_wcx_cidr2
4260 {
4261 uint32_t u;
4262 struct bdk_gti_wcx_cidr2_s
4263 {
4264 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4265 uint32_t reserved_8_31 : 24;
4266 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4267 #else /* Word 0 - Little Endian */
4268 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4269 uint32_t reserved_8_31 : 24;
4270 #endif /* Word 0 - End */
4271 } s;
4272 /* struct bdk_gti_wcx_cidr2_s cn; */
4273 };
4274 typedef union bdk_gti_wcx_cidr2 bdk_gti_wcx_cidr2_t;
4275
4276 static inline uint64_t BDK_GTI_WCX_CIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_CIDR2(unsigned long a)4277 static inline uint64_t BDK_GTI_WCX_CIDR2(unsigned long a)
4278 {
4279 if (a<=1)
4280 return 0x844000080ff8ll + 0x20000ll * ((a) & 0x1);
4281 __bdk_csr_fatal("GTI_WCX_CIDR2", 1, a, 0, 0, 0);
4282 }
4283
4284 #define typedef_BDK_GTI_WCX_CIDR2(a) bdk_gti_wcx_cidr2_t
4285 #define bustype_BDK_GTI_WCX_CIDR2(a) BDK_CSR_TYPE_NCB32b
4286 #define basename_BDK_GTI_WCX_CIDR2(a) "GTI_WCX_CIDR2"
4287 #define device_bar_BDK_GTI_WCX_CIDR2(a) 0x0 /* PF_BAR0 */
4288 #define busnum_BDK_GTI_WCX_CIDR2(a) (a)
4289 #define arguments_BDK_GTI_WCX_CIDR2(a) (a),-1,-1,-1
4290
4291 /**
4292 * Register (NCB32b) gti_wc#_cidr3
4293 *
4294 * GTI Watchdog Control Component Identification Register 3
4295 */
4296 union bdk_gti_wcx_cidr3
4297 {
4298 uint32_t u;
4299 struct bdk_gti_wcx_cidr3_s
4300 {
4301 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4302 uint32_t reserved_8_31 : 24;
4303 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
4304 #else /* Word 0 - Little Endian */
4305 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
4306 uint32_t reserved_8_31 : 24;
4307 #endif /* Word 0 - End */
4308 } s;
4309 /* struct bdk_gti_wcx_cidr3_s cn; */
4310 };
4311 typedef union bdk_gti_wcx_cidr3 bdk_gti_wcx_cidr3_t;
4312
4313 static inline uint64_t BDK_GTI_WCX_CIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_CIDR3(unsigned long a)4314 static inline uint64_t BDK_GTI_WCX_CIDR3(unsigned long a)
4315 {
4316 if (a<=1)
4317 return 0x844000080ffcll + 0x20000ll * ((a) & 0x1);
4318 __bdk_csr_fatal("GTI_WCX_CIDR3", 1, a, 0, 0, 0);
4319 }
4320
4321 #define typedef_BDK_GTI_WCX_CIDR3(a) bdk_gti_wcx_cidr3_t
4322 #define bustype_BDK_GTI_WCX_CIDR3(a) BDK_CSR_TYPE_NCB32b
4323 #define basename_BDK_GTI_WCX_CIDR3(a) "GTI_WCX_CIDR3"
4324 #define device_bar_BDK_GTI_WCX_CIDR3(a) 0x0 /* PF_BAR0 */
4325 #define busnum_BDK_GTI_WCX_CIDR3(a) (a)
4326 #define arguments_BDK_GTI_WCX_CIDR3(a) (a),-1,-1,-1
4327
4328 /**
4329 * Register (NCB32b) gti_wc#_pidr0
4330 *
4331 * GTI Watchdog Control Peripheral Identification Register 0
4332 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4333 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4334 */
4335 union bdk_gti_wcx_pidr0
4336 {
4337 uint32_t u;
4338 struct bdk_gti_wcx_pidr0_s
4339 {
4340 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4341 uint32_t reserved_8_31 : 24;
4342 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_WC. */
4343 #else /* Word 0 - Little Endian */
4344 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_WC. */
4345 uint32_t reserved_8_31 : 24;
4346 #endif /* Word 0 - End */
4347 } s;
4348 /* struct bdk_gti_wcx_pidr0_s cn; */
4349 };
4350 typedef union bdk_gti_wcx_pidr0 bdk_gti_wcx_pidr0_t;
4351
4352 static inline uint64_t BDK_GTI_WCX_PIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR0(unsigned long a)4353 static inline uint64_t BDK_GTI_WCX_PIDR0(unsigned long a)
4354 {
4355 if (a<=1)
4356 return 0x844000080fe0ll + 0x20000ll * ((a) & 0x1);
4357 __bdk_csr_fatal("GTI_WCX_PIDR0", 1, a, 0, 0, 0);
4358 }
4359
4360 #define typedef_BDK_GTI_WCX_PIDR0(a) bdk_gti_wcx_pidr0_t
4361 #define bustype_BDK_GTI_WCX_PIDR0(a) BDK_CSR_TYPE_NCB32b
4362 #define basename_BDK_GTI_WCX_PIDR0(a) "GTI_WCX_PIDR0"
4363 #define device_bar_BDK_GTI_WCX_PIDR0(a) 0x0 /* PF_BAR0 */
4364 #define busnum_BDK_GTI_WCX_PIDR0(a) (a)
4365 #define arguments_BDK_GTI_WCX_PIDR0(a) (a),-1,-1,-1
4366
4367 /**
4368 * Register (NCB32b) gti_wc#_pidr1
4369 *
4370 * GTI Watchdog Control Peripheral Identification Register 1
4371 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4372 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4373 */
4374 union bdk_gti_wcx_pidr1
4375 {
4376 uint32_t u;
4377 struct bdk_gti_wcx_pidr1_s
4378 {
4379 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4380 uint32_t reserved_8_31 : 24;
4381 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
4382 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
4383 #else /* Word 0 - Little Endian */
4384 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
4385 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
4386 uint32_t reserved_8_31 : 24;
4387 #endif /* Word 0 - End */
4388 } s;
4389 /* struct bdk_gti_wcx_pidr1_s cn; */
4390 };
4391 typedef union bdk_gti_wcx_pidr1 bdk_gti_wcx_pidr1_t;
4392
4393 static inline uint64_t BDK_GTI_WCX_PIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR1(unsigned long a)4394 static inline uint64_t BDK_GTI_WCX_PIDR1(unsigned long a)
4395 {
4396 if (a<=1)
4397 return 0x844000080fe4ll + 0x20000ll * ((a) & 0x1);
4398 __bdk_csr_fatal("GTI_WCX_PIDR1", 1, a, 0, 0, 0);
4399 }
4400
4401 #define typedef_BDK_GTI_WCX_PIDR1(a) bdk_gti_wcx_pidr1_t
4402 #define bustype_BDK_GTI_WCX_PIDR1(a) BDK_CSR_TYPE_NCB32b
4403 #define basename_BDK_GTI_WCX_PIDR1(a) "GTI_WCX_PIDR1"
4404 #define device_bar_BDK_GTI_WCX_PIDR1(a) 0x0 /* PF_BAR0 */
4405 #define busnum_BDK_GTI_WCX_PIDR1(a) (a)
4406 #define arguments_BDK_GTI_WCX_PIDR1(a) (a),-1,-1,-1
4407
4408 /**
4409 * Register (NCB32b) gti_wc#_pidr2
4410 *
4411 * GTI Watchdog Control Peripheral Identification Register 2
4412 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4413 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4414 */
4415 union bdk_gti_wcx_pidr2
4416 {
4417 uint32_t u;
4418 struct bdk_gti_wcx_pidr2_s
4419 {
4420 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4421 uint32_t reserved_8_31 : 24;
4422 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
4423 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
4424 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
4425 #else /* Word 0 - Little Endian */
4426 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
4427 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
4428 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
4429 uint32_t reserved_8_31 : 24;
4430 #endif /* Word 0 - End */
4431 } s;
4432 /* struct bdk_gti_wcx_pidr2_s cn; */
4433 };
4434 typedef union bdk_gti_wcx_pidr2 bdk_gti_wcx_pidr2_t;
4435
4436 static inline uint64_t BDK_GTI_WCX_PIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR2(unsigned long a)4437 static inline uint64_t BDK_GTI_WCX_PIDR2(unsigned long a)
4438 {
4439 if (a<=1)
4440 return 0x844000080fe8ll + 0x20000ll * ((a) & 0x1);
4441 __bdk_csr_fatal("GTI_WCX_PIDR2", 1, a, 0, 0, 0);
4442 }
4443
4444 #define typedef_BDK_GTI_WCX_PIDR2(a) bdk_gti_wcx_pidr2_t
4445 #define bustype_BDK_GTI_WCX_PIDR2(a) BDK_CSR_TYPE_NCB32b
4446 #define basename_BDK_GTI_WCX_PIDR2(a) "GTI_WCX_PIDR2"
4447 #define device_bar_BDK_GTI_WCX_PIDR2(a) 0x0 /* PF_BAR0 */
4448 #define busnum_BDK_GTI_WCX_PIDR2(a) (a)
4449 #define arguments_BDK_GTI_WCX_PIDR2(a) (a),-1,-1,-1
4450
4451 /**
4452 * Register (NCB32b) gti_wc#_pidr3
4453 *
4454 * GTI Watchdog Control Peripheral Identification Register 3
4455 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4456 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4457 */
4458 union bdk_gti_wcx_pidr3
4459 {
4460 uint32_t u;
4461 struct bdk_gti_wcx_pidr3_s
4462 {
4463 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4464 uint32_t reserved_8_31 : 24;
4465 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
4466 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
4467 product, major and minor pass numbers. */
4468 #else /* Word 0 - Little Endian */
4469 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
4470 product, major and minor pass numbers. */
4471 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
4472 uint32_t reserved_8_31 : 24;
4473 #endif /* Word 0 - End */
4474 } s;
4475 /* struct bdk_gti_wcx_pidr3_s cn; */
4476 };
4477 typedef union bdk_gti_wcx_pidr3 bdk_gti_wcx_pidr3_t;
4478
4479 static inline uint64_t BDK_GTI_WCX_PIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR3(unsigned long a)4480 static inline uint64_t BDK_GTI_WCX_PIDR3(unsigned long a)
4481 {
4482 if (a<=1)
4483 return 0x844000080fecll + 0x20000ll * ((a) & 0x1);
4484 __bdk_csr_fatal("GTI_WCX_PIDR3", 1, a, 0, 0, 0);
4485 }
4486
4487 #define typedef_BDK_GTI_WCX_PIDR3(a) bdk_gti_wcx_pidr3_t
4488 #define bustype_BDK_GTI_WCX_PIDR3(a) BDK_CSR_TYPE_NCB32b
4489 #define basename_BDK_GTI_WCX_PIDR3(a) "GTI_WCX_PIDR3"
4490 #define device_bar_BDK_GTI_WCX_PIDR3(a) 0x0 /* PF_BAR0 */
4491 #define busnum_BDK_GTI_WCX_PIDR3(a) (a)
4492 #define arguments_BDK_GTI_WCX_PIDR3(a) (a),-1,-1,-1
4493
4494 /**
4495 * Register (NCB32b) gti_wc#_pidr4
4496 *
4497 * GTI Watchdog Control Peripheral Identification Register 4
4498 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4499 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4500 */
4501 union bdk_gti_wcx_pidr4
4502 {
4503 uint32_t u;
4504 struct bdk_gti_wcx_pidr4_s
4505 {
4506 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4507 uint32_t reserved_8_31 : 24;
4508 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
4509 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
4510 #else /* Word 0 - Little Endian */
4511 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
4512 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
4513 uint32_t reserved_8_31 : 24;
4514 #endif /* Word 0 - End */
4515 } s;
4516 /* struct bdk_gti_wcx_pidr4_s cn; */
4517 };
4518 typedef union bdk_gti_wcx_pidr4 bdk_gti_wcx_pidr4_t;
4519
4520 static inline uint64_t BDK_GTI_WCX_PIDR4(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR4(unsigned long a)4521 static inline uint64_t BDK_GTI_WCX_PIDR4(unsigned long a)
4522 {
4523 if (a<=1)
4524 return 0x844000080fd0ll + 0x20000ll * ((a) & 0x1);
4525 __bdk_csr_fatal("GTI_WCX_PIDR4", 1, a, 0, 0, 0);
4526 }
4527
4528 #define typedef_BDK_GTI_WCX_PIDR4(a) bdk_gti_wcx_pidr4_t
4529 #define bustype_BDK_GTI_WCX_PIDR4(a) BDK_CSR_TYPE_NCB32b
4530 #define basename_BDK_GTI_WCX_PIDR4(a) "GTI_WCX_PIDR4"
4531 #define device_bar_BDK_GTI_WCX_PIDR4(a) 0x0 /* PF_BAR0 */
4532 #define busnum_BDK_GTI_WCX_PIDR4(a) (a)
4533 #define arguments_BDK_GTI_WCX_PIDR4(a) (a),-1,-1,-1
4534
4535 /**
4536 * Register (NCB32b) gti_wc#_pidr5
4537 *
4538 * GTI Watchdog Control Peripheral Identification Register 5
4539 */
4540 union bdk_gti_wcx_pidr5
4541 {
4542 uint32_t u;
4543 struct bdk_gti_wcx_pidr5_s
4544 {
4545 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4546 uint32_t reserved_0_31 : 32;
4547 #else /* Word 0 - Little Endian */
4548 uint32_t reserved_0_31 : 32;
4549 #endif /* Word 0 - End */
4550 } s;
4551 /* struct bdk_gti_wcx_pidr5_s cn; */
4552 };
4553 typedef union bdk_gti_wcx_pidr5 bdk_gti_wcx_pidr5_t;
4554
4555 static inline uint64_t BDK_GTI_WCX_PIDR5(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR5(unsigned long a)4556 static inline uint64_t BDK_GTI_WCX_PIDR5(unsigned long a)
4557 {
4558 if (a<=1)
4559 return 0x844000080fd4ll + 0x20000ll * ((a) & 0x1);
4560 __bdk_csr_fatal("GTI_WCX_PIDR5", 1, a, 0, 0, 0);
4561 }
4562
4563 #define typedef_BDK_GTI_WCX_PIDR5(a) bdk_gti_wcx_pidr5_t
4564 #define bustype_BDK_GTI_WCX_PIDR5(a) BDK_CSR_TYPE_NCB32b
4565 #define basename_BDK_GTI_WCX_PIDR5(a) "GTI_WCX_PIDR5"
4566 #define device_bar_BDK_GTI_WCX_PIDR5(a) 0x0 /* PF_BAR0 */
4567 #define busnum_BDK_GTI_WCX_PIDR5(a) (a)
4568 #define arguments_BDK_GTI_WCX_PIDR5(a) (a),-1,-1,-1
4569
4570 /**
4571 * Register (NCB32b) gti_wc#_pidr6
4572 *
4573 * GTI Watchdog Control Peripheral Identification Register 6
4574 */
4575 union bdk_gti_wcx_pidr6
4576 {
4577 uint32_t u;
4578 struct bdk_gti_wcx_pidr6_s
4579 {
4580 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4581 uint32_t reserved_0_31 : 32;
4582 #else /* Word 0 - Little Endian */
4583 uint32_t reserved_0_31 : 32;
4584 #endif /* Word 0 - End */
4585 } s;
4586 /* struct bdk_gti_wcx_pidr6_s cn; */
4587 };
4588 typedef union bdk_gti_wcx_pidr6 bdk_gti_wcx_pidr6_t;
4589
4590 static inline uint64_t BDK_GTI_WCX_PIDR6(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR6(unsigned long a)4591 static inline uint64_t BDK_GTI_WCX_PIDR6(unsigned long a)
4592 {
4593 if (a<=1)
4594 return 0x844000080fd8ll + 0x20000ll * ((a) & 0x1);
4595 __bdk_csr_fatal("GTI_WCX_PIDR6", 1, a, 0, 0, 0);
4596 }
4597
4598 #define typedef_BDK_GTI_WCX_PIDR6(a) bdk_gti_wcx_pidr6_t
4599 #define bustype_BDK_GTI_WCX_PIDR6(a) BDK_CSR_TYPE_NCB32b
4600 #define basename_BDK_GTI_WCX_PIDR6(a) "GTI_WCX_PIDR6"
4601 #define device_bar_BDK_GTI_WCX_PIDR6(a) 0x0 /* PF_BAR0 */
4602 #define busnum_BDK_GTI_WCX_PIDR6(a) (a)
4603 #define arguments_BDK_GTI_WCX_PIDR6(a) (a),-1,-1,-1
4604
4605 /**
4606 * Register (NCB32b) gti_wc#_pidr7
4607 *
4608 * GTI Watchdog Control Peripheral Identification Register 7
4609 */
4610 union bdk_gti_wcx_pidr7
4611 {
4612 uint32_t u;
4613 struct bdk_gti_wcx_pidr7_s
4614 {
4615 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4616 uint32_t reserved_0_31 : 32;
4617 #else /* Word 0 - Little Endian */
4618 uint32_t reserved_0_31 : 32;
4619 #endif /* Word 0 - End */
4620 } s;
4621 /* struct bdk_gti_wcx_pidr7_s cn; */
4622 };
4623 typedef union bdk_gti_wcx_pidr7 bdk_gti_wcx_pidr7_t;
4624
4625 static inline uint64_t BDK_GTI_WCX_PIDR7(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_PIDR7(unsigned long a)4626 static inline uint64_t BDK_GTI_WCX_PIDR7(unsigned long a)
4627 {
4628 if (a<=1)
4629 return 0x844000080fdcll + 0x20000ll * ((a) & 0x1);
4630 __bdk_csr_fatal("GTI_WCX_PIDR7", 1, a, 0, 0, 0);
4631 }
4632
4633 #define typedef_BDK_GTI_WCX_PIDR7(a) bdk_gti_wcx_pidr7_t
4634 #define bustype_BDK_GTI_WCX_PIDR7(a) BDK_CSR_TYPE_NCB32b
4635 #define basename_BDK_GTI_WCX_PIDR7(a) "GTI_WCX_PIDR7"
4636 #define device_bar_BDK_GTI_WCX_PIDR7(a) 0x0 /* PF_BAR0 */
4637 #define busnum_BDK_GTI_WCX_PIDR7(a) (a)
4638 #define arguments_BDK_GTI_WCX_PIDR7(a) (a),-1,-1,-1
4639
4640 /**
4641 * Register (NCB32b) gti_wc#_w_iidr
4642 *
4643 * GTI Watchdog Control Interface Identification Register
4644 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4645 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4646 */
4647 union bdk_gti_wcx_w_iidr
4648 {
4649 uint32_t u;
4650 struct bdk_gti_wcx_w_iidr_s
4651 {
4652 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4653 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
4654 In CNXXXX, enumerated by PCC_PROD_E. */
4655 uint32_t variant : 4; /**< [ 23: 20](RO) Variant field.
4656 Note in the SBSA this is defined as part of the product identification.
4657 In CNXXXX, the major pass number. */
4658 uint32_t arch : 4; /**< [ 19: 16](RO) Architecture revision. 0x0 = SBSA 1.0 watchdogs. */
4659 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
4660 In CNXXXX, the minor pass number. */
4661 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer: 0x34C = Cavium. */
4662 #else /* Word 0 - Little Endian */
4663 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer: 0x34C = Cavium. */
4664 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
4665 In CNXXXX, the minor pass number. */
4666 uint32_t arch : 4; /**< [ 19: 16](RO) Architecture revision. 0x0 = SBSA 1.0 watchdogs. */
4667 uint32_t variant : 4; /**< [ 23: 20](RO) Variant field.
4668 Note in the SBSA this is defined as part of the product identification.
4669 In CNXXXX, the major pass number. */
4670 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
4671 In CNXXXX, enumerated by PCC_PROD_E. */
4672 #endif /* Word 0 - End */
4673 } s;
4674 /* struct bdk_gti_wcx_w_iidr_s cn; */
4675 };
4676 typedef union bdk_gti_wcx_w_iidr bdk_gti_wcx_w_iidr_t;
4677
4678 static inline uint64_t BDK_GTI_WCX_W_IIDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_W_IIDR(unsigned long a)4679 static inline uint64_t BDK_GTI_WCX_W_IIDR(unsigned long a)
4680 {
4681 if (a<=1)
4682 return 0x844000080fccll + 0x20000ll * ((a) & 0x1);
4683 __bdk_csr_fatal("GTI_WCX_W_IIDR", 1, a, 0, 0, 0);
4684 }
4685
4686 #define typedef_BDK_GTI_WCX_W_IIDR(a) bdk_gti_wcx_w_iidr_t
4687 #define bustype_BDK_GTI_WCX_W_IIDR(a) BDK_CSR_TYPE_NCB32b
4688 #define basename_BDK_GTI_WCX_W_IIDR(a) "GTI_WCX_W_IIDR"
4689 #define device_bar_BDK_GTI_WCX_W_IIDR(a) 0x0 /* PF_BAR0 */
4690 #define busnum_BDK_GTI_WCX_W_IIDR(a) (a)
4691 #define arguments_BDK_GTI_WCX_W_IIDR(a) (a),-1,-1,-1
4692
4693 /**
4694 * Register (NCB32b) gti_wc#_wcs
4695 *
4696 * GTI Watchdog Control and Status Register
4697 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4698 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4699 */
4700 union bdk_gti_wcx_wcs
4701 {
4702 uint32_t u;
4703 struct bdk_gti_wcx_wcs_s
4704 {
4705 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4706 uint32_t reserved_3_31 : 29;
4707 uint32_t ws1 : 1; /**< [ 2: 2](RO/H) WS1 */
4708 uint32_t ws0 : 1; /**< [ 1: 1](RO/H) WS0 */
4709 uint32_t en : 1; /**< [ 0: 0](R/W) Enable. */
4710 #else /* Word 0 - Little Endian */
4711 uint32_t en : 1; /**< [ 0: 0](R/W) Enable. */
4712 uint32_t ws0 : 1; /**< [ 1: 1](RO/H) WS0 */
4713 uint32_t ws1 : 1; /**< [ 2: 2](RO/H) WS1 */
4714 uint32_t reserved_3_31 : 29;
4715 #endif /* Word 0 - End */
4716 } s;
4717 /* struct bdk_gti_wcx_wcs_s cn; */
4718 };
4719 typedef union bdk_gti_wcx_wcs bdk_gti_wcx_wcs_t;
4720
4721 static inline uint64_t BDK_GTI_WCX_WCS(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_WCS(unsigned long a)4722 static inline uint64_t BDK_GTI_WCX_WCS(unsigned long a)
4723 {
4724 if (a<=1)
4725 return 0x844000080000ll + 0x20000ll * ((a) & 0x1);
4726 __bdk_csr_fatal("GTI_WCX_WCS", 1, a, 0, 0, 0);
4727 }
4728
4729 #define typedef_BDK_GTI_WCX_WCS(a) bdk_gti_wcx_wcs_t
4730 #define bustype_BDK_GTI_WCX_WCS(a) BDK_CSR_TYPE_NCB32b
4731 #define basename_BDK_GTI_WCX_WCS(a) "GTI_WCX_WCS"
4732 #define device_bar_BDK_GTI_WCX_WCS(a) 0x0 /* PF_BAR0 */
4733 #define busnum_BDK_GTI_WCX_WCS(a) (a)
4734 #define arguments_BDK_GTI_WCX_WCS(a) (a),-1,-1,-1
4735
4736 /**
4737 * Register (NCB) gti_wc#_wcv
4738 *
4739 * GTI Watchdog Control Compare Value Register
4740 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4741 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4742 */
4743 union bdk_gti_wcx_wcv
4744 {
4745 uint64_t u;
4746 struct bdk_gti_wcx_wcv_s
4747 {
4748 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4749 uint64_t wdcv : 64; /**< [ 63: 0](R/W/H) Watchdog compare value. */
4750 #else /* Word 0 - Little Endian */
4751 uint64_t wdcv : 64; /**< [ 63: 0](R/W/H) Watchdog compare value. */
4752 #endif /* Word 0 - End */
4753 } s;
4754 /* struct bdk_gti_wcx_wcv_s cn; */
4755 };
4756 typedef union bdk_gti_wcx_wcv bdk_gti_wcx_wcv_t;
4757
4758 static inline uint64_t BDK_GTI_WCX_WCV(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_WCV(unsigned long a)4759 static inline uint64_t BDK_GTI_WCX_WCV(unsigned long a)
4760 {
4761 if (a<=1)
4762 return 0x844000080010ll + 0x20000ll * ((a) & 0x1);
4763 __bdk_csr_fatal("GTI_WCX_WCV", 1, a, 0, 0, 0);
4764 }
4765
4766 #define typedef_BDK_GTI_WCX_WCV(a) bdk_gti_wcx_wcv_t
4767 #define bustype_BDK_GTI_WCX_WCV(a) BDK_CSR_TYPE_NCB
4768 #define basename_BDK_GTI_WCX_WCV(a) "GTI_WCX_WCV"
4769 #define device_bar_BDK_GTI_WCX_WCV(a) 0x0 /* PF_BAR0 */
4770 #define busnum_BDK_GTI_WCX_WCV(a) (a)
4771 #define arguments_BDK_GTI_WCX_WCV(a) (a),-1,-1,-1
4772
4773 /**
4774 * Register (NCB32b) gti_wc#_wor
4775 *
4776 * GTI Watchdog Control Offset Register
4777 * GTI_WC(0) accesses the secure watchdog and is accessible only by the
4778 * secure-world. GTI_WC(1) accesses the nonsecure watchdog.
4779 */
4780 union bdk_gti_wcx_wor
4781 {
4782 uint32_t u;
4783 struct bdk_gti_wcx_wor_s
4784 {
4785 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4786 uint32_t offset : 32; /**< [ 31: 0](R/W/H) Watchdog offset. */
4787 #else /* Word 0 - Little Endian */
4788 uint32_t offset : 32; /**< [ 31: 0](R/W/H) Watchdog offset. */
4789 #endif /* Word 0 - End */
4790 } s;
4791 /* struct bdk_gti_wcx_wor_s cn; */
4792 };
4793 typedef union bdk_gti_wcx_wor bdk_gti_wcx_wor_t;
4794
4795 static inline uint64_t BDK_GTI_WCX_WOR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WCX_WOR(unsigned long a)4796 static inline uint64_t BDK_GTI_WCX_WOR(unsigned long a)
4797 {
4798 if (a<=1)
4799 return 0x844000080008ll + 0x20000ll * ((a) & 0x1);
4800 __bdk_csr_fatal("GTI_WCX_WOR", 1, a, 0, 0, 0);
4801 }
4802
4803 #define typedef_BDK_GTI_WCX_WOR(a) bdk_gti_wcx_wor_t
4804 #define bustype_BDK_GTI_WCX_WOR(a) BDK_CSR_TYPE_NCB32b
4805 #define basename_BDK_GTI_WCX_WOR(a) "GTI_WCX_WOR"
4806 #define device_bar_BDK_GTI_WCX_WOR(a) 0x0 /* PF_BAR0 */
4807 #define busnum_BDK_GTI_WCX_WOR(a) (a)
4808 #define arguments_BDK_GTI_WCX_WOR(a) (a),-1,-1,-1
4809
4810 /**
4811 * Register (NCB32b) gti_wr#_cidr0
4812 *
4813 * GTI Watchdog Refresh Component Identification Register 0
4814 */
4815 union bdk_gti_wrx_cidr0
4816 {
4817 uint32_t u;
4818 struct bdk_gti_wrx_cidr0_s
4819 {
4820 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4821 uint32_t reserved_8_31 : 24;
4822 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4823 #else /* Word 0 - Little Endian */
4824 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4825 uint32_t reserved_8_31 : 24;
4826 #endif /* Word 0 - End */
4827 } s;
4828 /* struct bdk_gti_wrx_cidr0_s cn; */
4829 };
4830 typedef union bdk_gti_wrx_cidr0 bdk_gti_wrx_cidr0_t;
4831
4832 static inline uint64_t BDK_GTI_WRX_CIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_CIDR0(unsigned long a)4833 static inline uint64_t BDK_GTI_WRX_CIDR0(unsigned long a)
4834 {
4835 if (a<=1)
4836 return 0x844000090ff0ll + 0x20000ll * ((a) & 0x1);
4837 __bdk_csr_fatal("GTI_WRX_CIDR0", 1, a, 0, 0, 0);
4838 }
4839
4840 #define typedef_BDK_GTI_WRX_CIDR0(a) bdk_gti_wrx_cidr0_t
4841 #define bustype_BDK_GTI_WRX_CIDR0(a) BDK_CSR_TYPE_NCB32b
4842 #define basename_BDK_GTI_WRX_CIDR0(a) "GTI_WRX_CIDR0"
4843 #define device_bar_BDK_GTI_WRX_CIDR0(a) 0x0 /* PF_BAR0 */
4844 #define busnum_BDK_GTI_WRX_CIDR0(a) (a)
4845 #define arguments_BDK_GTI_WRX_CIDR0(a) (a),-1,-1,-1
4846
4847 /**
4848 * Register (NCB32b) gti_wr#_cidr1
4849 *
4850 * GTI Watchdog Refresh Component Identification Register 1
4851 */
4852 union bdk_gti_wrx_cidr1
4853 {
4854 uint32_t u;
4855 struct bdk_gti_wrx_cidr1_s
4856 {
4857 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4858 uint32_t reserved_8_31 : 24;
4859 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
4860 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
4861 #else /* Word 0 - Little Endian */
4862 uint32_t preamble : 4; /**< [ 3: 0](RO) Preamble identification value. */
4863 uint32_t cclass : 4; /**< [ 7: 4](RO) Component class. */
4864 uint32_t reserved_8_31 : 24;
4865 #endif /* Word 0 - End */
4866 } s;
4867 /* struct bdk_gti_wrx_cidr1_s cn; */
4868 };
4869 typedef union bdk_gti_wrx_cidr1 bdk_gti_wrx_cidr1_t;
4870
4871 static inline uint64_t BDK_GTI_WRX_CIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_CIDR1(unsigned long a)4872 static inline uint64_t BDK_GTI_WRX_CIDR1(unsigned long a)
4873 {
4874 if (a<=1)
4875 return 0x844000090ff4ll + 0x20000ll * ((a) & 0x1);
4876 __bdk_csr_fatal("GTI_WRX_CIDR1", 1, a, 0, 0, 0);
4877 }
4878
4879 #define typedef_BDK_GTI_WRX_CIDR1(a) bdk_gti_wrx_cidr1_t
4880 #define bustype_BDK_GTI_WRX_CIDR1(a) BDK_CSR_TYPE_NCB32b
4881 #define basename_BDK_GTI_WRX_CIDR1(a) "GTI_WRX_CIDR1"
4882 #define device_bar_BDK_GTI_WRX_CIDR1(a) 0x0 /* PF_BAR0 */
4883 #define busnum_BDK_GTI_WRX_CIDR1(a) (a)
4884 #define arguments_BDK_GTI_WRX_CIDR1(a) (a),-1,-1,-1
4885
4886 /**
4887 * Register (NCB32b) gti_wr#_cidr2
4888 *
4889 * GTI Watchdog Refresh Component Identification Register 2
4890 */
4891 union bdk_gti_wrx_cidr2
4892 {
4893 uint32_t u;
4894 struct bdk_gti_wrx_cidr2_s
4895 {
4896 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4897 uint32_t reserved_8_31 : 24;
4898 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4899 #else /* Word 0 - Little Endian */
4900 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value. */
4901 uint32_t reserved_8_31 : 24;
4902 #endif /* Word 0 - End */
4903 } s;
4904 /* struct bdk_gti_wrx_cidr2_s cn; */
4905 };
4906 typedef union bdk_gti_wrx_cidr2 bdk_gti_wrx_cidr2_t;
4907
4908 static inline uint64_t BDK_GTI_WRX_CIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_CIDR2(unsigned long a)4909 static inline uint64_t BDK_GTI_WRX_CIDR2(unsigned long a)
4910 {
4911 if (a<=1)
4912 return 0x844000090ff8ll + 0x20000ll * ((a) & 0x1);
4913 __bdk_csr_fatal("GTI_WRX_CIDR2", 1, a, 0, 0, 0);
4914 }
4915
4916 #define typedef_BDK_GTI_WRX_CIDR2(a) bdk_gti_wrx_cidr2_t
4917 #define bustype_BDK_GTI_WRX_CIDR2(a) BDK_CSR_TYPE_NCB32b
4918 #define basename_BDK_GTI_WRX_CIDR2(a) "GTI_WRX_CIDR2"
4919 #define device_bar_BDK_GTI_WRX_CIDR2(a) 0x0 /* PF_BAR0 */
4920 #define busnum_BDK_GTI_WRX_CIDR2(a) (a)
4921 #define arguments_BDK_GTI_WRX_CIDR2(a) (a),-1,-1,-1
4922
4923 /**
4924 * Register (NCB32b) gti_wr#_cidr3
4925 *
4926 * GTI Watchdog Refresh Component Identification Register 3
4927 */
4928 union bdk_gti_wrx_cidr3
4929 {
4930 uint32_t u;
4931 struct bdk_gti_wrx_cidr3_s
4932 {
4933 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4934 uint32_t reserved_8_31 : 24;
4935 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
4936 #else /* Word 0 - Little Endian */
4937 uint32_t preamble : 8; /**< [ 7: 0](RO) Preamble identification value */
4938 uint32_t reserved_8_31 : 24;
4939 #endif /* Word 0 - End */
4940 } s;
4941 /* struct bdk_gti_wrx_cidr3_s cn; */
4942 };
4943 typedef union bdk_gti_wrx_cidr3 bdk_gti_wrx_cidr3_t;
4944
4945 static inline uint64_t BDK_GTI_WRX_CIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_CIDR3(unsigned long a)4946 static inline uint64_t BDK_GTI_WRX_CIDR3(unsigned long a)
4947 {
4948 if (a<=1)
4949 return 0x844000090ffcll + 0x20000ll * ((a) & 0x1);
4950 __bdk_csr_fatal("GTI_WRX_CIDR3", 1, a, 0, 0, 0);
4951 }
4952
4953 #define typedef_BDK_GTI_WRX_CIDR3(a) bdk_gti_wrx_cidr3_t
4954 #define bustype_BDK_GTI_WRX_CIDR3(a) BDK_CSR_TYPE_NCB32b
4955 #define basename_BDK_GTI_WRX_CIDR3(a) "GTI_WRX_CIDR3"
4956 #define device_bar_BDK_GTI_WRX_CIDR3(a) 0x0 /* PF_BAR0 */
4957 #define busnum_BDK_GTI_WRX_CIDR3(a) (a)
4958 #define arguments_BDK_GTI_WRX_CIDR3(a) (a),-1,-1,-1
4959
4960 /**
4961 * Register (NCB32b) gti_wr#_pidr0
4962 *
4963 * GTI Watchdog Refresh Peripheral Identification Register 0
4964 */
4965 union bdk_gti_wrx_pidr0
4966 {
4967 uint32_t u;
4968 struct bdk_gti_wrx_pidr0_s
4969 {
4970 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
4971 uint32_t reserved_8_31 : 24;
4972 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_WR. */
4973 #else /* Word 0 - Little Endian */
4974 uint32_t partnum0 : 8; /**< [ 7: 0](RO) Part number \<7:0\>. Indicates PCC_PIDR_PARTNUM0_E::GTI_WR. */
4975 uint32_t reserved_8_31 : 24;
4976 #endif /* Word 0 - End */
4977 } s;
4978 /* struct bdk_gti_wrx_pidr0_s cn; */
4979 };
4980 typedef union bdk_gti_wrx_pidr0 bdk_gti_wrx_pidr0_t;
4981
4982 static inline uint64_t BDK_GTI_WRX_PIDR0(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR0(unsigned long a)4983 static inline uint64_t BDK_GTI_WRX_PIDR0(unsigned long a)
4984 {
4985 if (a<=1)
4986 return 0x844000090fe0ll + 0x20000ll * ((a) & 0x1);
4987 __bdk_csr_fatal("GTI_WRX_PIDR0", 1, a, 0, 0, 0);
4988 }
4989
4990 #define typedef_BDK_GTI_WRX_PIDR0(a) bdk_gti_wrx_pidr0_t
4991 #define bustype_BDK_GTI_WRX_PIDR0(a) BDK_CSR_TYPE_NCB32b
4992 #define basename_BDK_GTI_WRX_PIDR0(a) "GTI_WRX_PIDR0"
4993 #define device_bar_BDK_GTI_WRX_PIDR0(a) 0x0 /* PF_BAR0 */
4994 #define busnum_BDK_GTI_WRX_PIDR0(a) (a)
4995 #define arguments_BDK_GTI_WRX_PIDR0(a) (a),-1,-1,-1
4996
4997 /**
4998 * Register (NCB32b) gti_wr#_pidr1
4999 *
5000 * GTI Watchdog Refresh Peripheral Identification Register 1
5001 */
5002 union bdk_gti_wrx_pidr1
5003 {
5004 uint32_t u;
5005 struct bdk_gti_wrx_pidr1_s
5006 {
5007 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5008 uint32_t reserved_8_31 : 24;
5009 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
5010 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
5011 #else /* Word 0 - Little Endian */
5012 uint32_t partnum1 : 4; /**< [ 3: 0](RO) Part number \<11:8\>. Indicates PCC_PIDR_PARTNUM1_E::COMP. */
5013 uint32_t idcode : 4; /**< [ 7: 4](RO) JEP106 identification code \<3:0\>. Cavium code is 0x4C. */
5014 uint32_t reserved_8_31 : 24;
5015 #endif /* Word 0 - End */
5016 } s;
5017 /* struct bdk_gti_wrx_pidr1_s cn; */
5018 };
5019 typedef union bdk_gti_wrx_pidr1 bdk_gti_wrx_pidr1_t;
5020
5021 static inline uint64_t BDK_GTI_WRX_PIDR1(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR1(unsigned long a)5022 static inline uint64_t BDK_GTI_WRX_PIDR1(unsigned long a)
5023 {
5024 if (a<=1)
5025 return 0x844000090fe4ll + 0x20000ll * ((a) & 0x1);
5026 __bdk_csr_fatal("GTI_WRX_PIDR1", 1, a, 0, 0, 0);
5027 }
5028
5029 #define typedef_BDK_GTI_WRX_PIDR1(a) bdk_gti_wrx_pidr1_t
5030 #define bustype_BDK_GTI_WRX_PIDR1(a) BDK_CSR_TYPE_NCB32b
5031 #define basename_BDK_GTI_WRX_PIDR1(a) "GTI_WRX_PIDR1"
5032 #define device_bar_BDK_GTI_WRX_PIDR1(a) 0x0 /* PF_BAR0 */
5033 #define busnum_BDK_GTI_WRX_PIDR1(a) (a)
5034 #define arguments_BDK_GTI_WRX_PIDR1(a) (a),-1,-1,-1
5035
5036 /**
5037 * Register (NCB32b) gti_wr#_pidr2
5038 *
5039 * GTI Watchdog Refresh Peripheral Identification Register 2
5040 */
5041 union bdk_gti_wrx_pidr2
5042 {
5043 uint32_t u;
5044 struct bdk_gti_wrx_pidr2_s
5045 {
5046 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5047 uint32_t reserved_8_31 : 24;
5048 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
5049 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
5050 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
5051 #else /* Word 0 - Little Endian */
5052 uint32_t idcode : 3; /**< [ 2: 0](RO) JEP106 identification code \<6:4\>. Cavium code is 0x4C. */
5053 uint32_t jedec : 1; /**< [ 3: 3](RO) JEDEC assigned. */
5054 uint32_t revision : 4; /**< [ 7: 4](RO) Architectural revision, as assigned by ARM. */
5055 uint32_t reserved_8_31 : 24;
5056 #endif /* Word 0 - End */
5057 } s;
5058 /* struct bdk_gti_wrx_pidr2_s cn; */
5059 };
5060 typedef union bdk_gti_wrx_pidr2 bdk_gti_wrx_pidr2_t;
5061
5062 static inline uint64_t BDK_GTI_WRX_PIDR2(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR2(unsigned long a)5063 static inline uint64_t BDK_GTI_WRX_PIDR2(unsigned long a)
5064 {
5065 if (a<=1)
5066 return 0x844000090fe8ll + 0x20000ll * ((a) & 0x1);
5067 __bdk_csr_fatal("GTI_WRX_PIDR2", 1, a, 0, 0, 0);
5068 }
5069
5070 #define typedef_BDK_GTI_WRX_PIDR2(a) bdk_gti_wrx_pidr2_t
5071 #define bustype_BDK_GTI_WRX_PIDR2(a) BDK_CSR_TYPE_NCB32b
5072 #define basename_BDK_GTI_WRX_PIDR2(a) "GTI_WRX_PIDR2"
5073 #define device_bar_BDK_GTI_WRX_PIDR2(a) 0x0 /* PF_BAR0 */
5074 #define busnum_BDK_GTI_WRX_PIDR2(a) (a)
5075 #define arguments_BDK_GTI_WRX_PIDR2(a) (a),-1,-1,-1
5076
5077 /**
5078 * Register (NCB32b) gti_wr#_pidr3
5079 *
5080 * GTI Watchdog Refresh Peripheral Identification Register 3
5081 */
5082 union bdk_gti_wrx_pidr3
5083 {
5084 uint32_t u;
5085 struct bdk_gti_wrx_pidr3_s
5086 {
5087 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5088 uint32_t reserved_8_31 : 24;
5089 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
5090 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
5091 product, major and minor pass numbers. */
5092 #else /* Word 0 - Little Endian */
5093 uint32_t cust : 4; /**< [ 3: 0](RO) Customer modified. 0x1 = Overall product information should be consulted for
5094 product, major and minor pass numbers. */
5095 uint32_t revand : 4; /**< [ 7: 4](RO) Manufacturer revision number. For CNXXXX always 0x0. */
5096 uint32_t reserved_8_31 : 24;
5097 #endif /* Word 0 - End */
5098 } s;
5099 /* struct bdk_gti_wrx_pidr3_s cn; */
5100 };
5101 typedef union bdk_gti_wrx_pidr3 bdk_gti_wrx_pidr3_t;
5102
5103 static inline uint64_t BDK_GTI_WRX_PIDR3(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR3(unsigned long a)5104 static inline uint64_t BDK_GTI_WRX_PIDR3(unsigned long a)
5105 {
5106 if (a<=1)
5107 return 0x844000090fecll + 0x20000ll * ((a) & 0x1);
5108 __bdk_csr_fatal("GTI_WRX_PIDR3", 1, a, 0, 0, 0);
5109 }
5110
5111 #define typedef_BDK_GTI_WRX_PIDR3(a) bdk_gti_wrx_pidr3_t
5112 #define bustype_BDK_GTI_WRX_PIDR3(a) BDK_CSR_TYPE_NCB32b
5113 #define basename_BDK_GTI_WRX_PIDR3(a) "GTI_WRX_PIDR3"
5114 #define device_bar_BDK_GTI_WRX_PIDR3(a) 0x0 /* PF_BAR0 */
5115 #define busnum_BDK_GTI_WRX_PIDR3(a) (a)
5116 #define arguments_BDK_GTI_WRX_PIDR3(a) (a),-1,-1,-1
5117
5118 /**
5119 * Register (NCB32b) gti_wr#_pidr4
5120 *
5121 * GTI Watchdog Refresh Peripheral Identification Register 4
5122 */
5123 union bdk_gti_wrx_pidr4
5124 {
5125 uint32_t u;
5126 struct bdk_gti_wrx_pidr4_s
5127 {
5128 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5129 uint32_t reserved_8_31 : 24;
5130 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
5131 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
5132 #else /* Word 0 - Little Endian */
5133 uint32_t jepcont : 4; /**< [ 3: 0](RO) JEP106 continuation code. Indicates Cavium. */
5134 uint32_t pagecnt : 4; /**< [ 7: 4](RO) Number of log-2 4 KB blocks occupied. */
5135 uint32_t reserved_8_31 : 24;
5136 #endif /* Word 0 - End */
5137 } s;
5138 /* struct bdk_gti_wrx_pidr4_s cn; */
5139 };
5140 typedef union bdk_gti_wrx_pidr4 bdk_gti_wrx_pidr4_t;
5141
5142 static inline uint64_t BDK_GTI_WRX_PIDR4(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR4(unsigned long a)5143 static inline uint64_t BDK_GTI_WRX_PIDR4(unsigned long a)
5144 {
5145 if (a<=1)
5146 return 0x844000090fd0ll + 0x20000ll * ((a) & 0x1);
5147 __bdk_csr_fatal("GTI_WRX_PIDR4", 1, a, 0, 0, 0);
5148 }
5149
5150 #define typedef_BDK_GTI_WRX_PIDR4(a) bdk_gti_wrx_pidr4_t
5151 #define bustype_BDK_GTI_WRX_PIDR4(a) BDK_CSR_TYPE_NCB32b
5152 #define basename_BDK_GTI_WRX_PIDR4(a) "GTI_WRX_PIDR4"
5153 #define device_bar_BDK_GTI_WRX_PIDR4(a) 0x0 /* PF_BAR0 */
5154 #define busnum_BDK_GTI_WRX_PIDR4(a) (a)
5155 #define arguments_BDK_GTI_WRX_PIDR4(a) (a),-1,-1,-1
5156
5157 /**
5158 * Register (NCB32b) gti_wr#_pidr5
5159 *
5160 * GTI Watchdog Refresh Peripheral Identification Register 5
5161 */
5162 union bdk_gti_wrx_pidr5
5163 {
5164 uint32_t u;
5165 struct bdk_gti_wrx_pidr5_s
5166 {
5167 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5168 uint32_t reserved_0_31 : 32;
5169 #else /* Word 0 - Little Endian */
5170 uint32_t reserved_0_31 : 32;
5171 #endif /* Word 0 - End */
5172 } s;
5173 /* struct bdk_gti_wrx_pidr5_s cn; */
5174 };
5175 typedef union bdk_gti_wrx_pidr5 bdk_gti_wrx_pidr5_t;
5176
5177 static inline uint64_t BDK_GTI_WRX_PIDR5(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR5(unsigned long a)5178 static inline uint64_t BDK_GTI_WRX_PIDR5(unsigned long a)
5179 {
5180 if (a<=1)
5181 return 0x844000090fd4ll + 0x20000ll * ((a) & 0x1);
5182 __bdk_csr_fatal("GTI_WRX_PIDR5", 1, a, 0, 0, 0);
5183 }
5184
5185 #define typedef_BDK_GTI_WRX_PIDR5(a) bdk_gti_wrx_pidr5_t
5186 #define bustype_BDK_GTI_WRX_PIDR5(a) BDK_CSR_TYPE_NCB32b
5187 #define basename_BDK_GTI_WRX_PIDR5(a) "GTI_WRX_PIDR5"
5188 #define device_bar_BDK_GTI_WRX_PIDR5(a) 0x0 /* PF_BAR0 */
5189 #define busnum_BDK_GTI_WRX_PIDR5(a) (a)
5190 #define arguments_BDK_GTI_WRX_PIDR5(a) (a),-1,-1,-1
5191
5192 /**
5193 * Register (NCB32b) gti_wr#_pidr6
5194 *
5195 * GTI Watchdog Refresh Peripheral Identification Register 6
5196 */
5197 union bdk_gti_wrx_pidr6
5198 {
5199 uint32_t u;
5200 struct bdk_gti_wrx_pidr6_s
5201 {
5202 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5203 uint32_t reserved_0_31 : 32;
5204 #else /* Word 0 - Little Endian */
5205 uint32_t reserved_0_31 : 32;
5206 #endif /* Word 0 - End */
5207 } s;
5208 /* struct bdk_gti_wrx_pidr6_s cn; */
5209 };
5210 typedef union bdk_gti_wrx_pidr6 bdk_gti_wrx_pidr6_t;
5211
5212 static inline uint64_t BDK_GTI_WRX_PIDR6(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR6(unsigned long a)5213 static inline uint64_t BDK_GTI_WRX_PIDR6(unsigned long a)
5214 {
5215 if (a<=1)
5216 return 0x844000090fd8ll + 0x20000ll * ((a) & 0x1);
5217 __bdk_csr_fatal("GTI_WRX_PIDR6", 1, a, 0, 0, 0);
5218 }
5219
5220 #define typedef_BDK_GTI_WRX_PIDR6(a) bdk_gti_wrx_pidr6_t
5221 #define bustype_BDK_GTI_WRX_PIDR6(a) BDK_CSR_TYPE_NCB32b
5222 #define basename_BDK_GTI_WRX_PIDR6(a) "GTI_WRX_PIDR6"
5223 #define device_bar_BDK_GTI_WRX_PIDR6(a) 0x0 /* PF_BAR0 */
5224 #define busnum_BDK_GTI_WRX_PIDR6(a) (a)
5225 #define arguments_BDK_GTI_WRX_PIDR6(a) (a),-1,-1,-1
5226
5227 /**
5228 * Register (NCB32b) gti_wr#_pidr7
5229 *
5230 * GTI Watchdog Refresh Peripheral Identification Register 7
5231 */
5232 union bdk_gti_wrx_pidr7
5233 {
5234 uint32_t u;
5235 struct bdk_gti_wrx_pidr7_s
5236 {
5237 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5238 uint32_t reserved_0_31 : 32;
5239 #else /* Word 0 - Little Endian */
5240 uint32_t reserved_0_31 : 32;
5241 #endif /* Word 0 - End */
5242 } s;
5243 /* struct bdk_gti_wrx_pidr7_s cn; */
5244 };
5245 typedef union bdk_gti_wrx_pidr7 bdk_gti_wrx_pidr7_t;
5246
5247 static inline uint64_t BDK_GTI_WRX_PIDR7(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_PIDR7(unsigned long a)5248 static inline uint64_t BDK_GTI_WRX_PIDR7(unsigned long a)
5249 {
5250 if (a<=1)
5251 return 0x844000090fdcll + 0x20000ll * ((a) & 0x1);
5252 __bdk_csr_fatal("GTI_WRX_PIDR7", 1, a, 0, 0, 0);
5253 }
5254
5255 #define typedef_BDK_GTI_WRX_PIDR7(a) bdk_gti_wrx_pidr7_t
5256 #define bustype_BDK_GTI_WRX_PIDR7(a) BDK_CSR_TYPE_NCB32b
5257 #define basename_BDK_GTI_WRX_PIDR7(a) "GTI_WRX_PIDR7"
5258 #define device_bar_BDK_GTI_WRX_PIDR7(a) 0x0 /* PF_BAR0 */
5259 #define busnum_BDK_GTI_WRX_PIDR7(a) (a)
5260 #define arguments_BDK_GTI_WRX_PIDR7(a) (a),-1,-1,-1
5261
5262 /**
5263 * Register (NCB32b) gti_wr#_w_iidr
5264 *
5265 * GTI Watchdog Refresh Interface Identification Register
5266 * GTI_WR(0) accesses the secure watchdog and is accessible only by the
5267 * secure-world. GTI_WR(1) accesses the nonsecure watchdog.
5268 */
5269 union bdk_gti_wrx_w_iidr
5270 {
5271 uint32_t u;
5272 struct bdk_gti_wrx_w_iidr_s
5273 {
5274 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5275 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
5276 In CNXXXX, enumerated by PCC_PROD_E. */
5277 uint32_t variant : 4; /**< [ 23: 20](RO) Variant field.
5278 Note in the SBSA this is defined as part of the product identification.
5279 In CNXXXX, the major pass number. */
5280 uint32_t arch : 4; /**< [ 19: 16](RO) Architecture revision. 0x0 = SBSA 1.0 watchdogs. */
5281 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
5282 In CNXXXX, the minor pass number. */
5283 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer: 0x34C = Cavium. */
5284 #else /* Word 0 - Little Endian */
5285 uint32_t implementer : 12; /**< [ 11: 0](RO) Indicates the implementer: 0x34C = Cavium. */
5286 uint32_t revision : 4; /**< [ 15: 12](RO) Indicates the minor revision of the product.
5287 In CNXXXX, the minor pass number. */
5288 uint32_t arch : 4; /**< [ 19: 16](RO) Architecture revision. 0x0 = SBSA 1.0 watchdogs. */
5289 uint32_t variant : 4; /**< [ 23: 20](RO) Variant field.
5290 Note in the SBSA this is defined as part of the product identification.
5291 In CNXXXX, the major pass number. */
5292 uint32_t productid : 8; /**< [ 31: 24](RO) An implementation defined product number for the device.
5293 In CNXXXX, enumerated by PCC_PROD_E. */
5294 #endif /* Word 0 - End */
5295 } s;
5296 /* struct bdk_gti_wrx_w_iidr_s cn; */
5297 };
5298 typedef union bdk_gti_wrx_w_iidr bdk_gti_wrx_w_iidr_t;
5299
5300 static inline uint64_t BDK_GTI_WRX_W_IIDR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_W_IIDR(unsigned long a)5301 static inline uint64_t BDK_GTI_WRX_W_IIDR(unsigned long a)
5302 {
5303 if (a<=1)
5304 return 0x844000090fccll + 0x20000ll * ((a) & 0x1);
5305 __bdk_csr_fatal("GTI_WRX_W_IIDR", 1, a, 0, 0, 0);
5306 }
5307
5308 #define typedef_BDK_GTI_WRX_W_IIDR(a) bdk_gti_wrx_w_iidr_t
5309 #define bustype_BDK_GTI_WRX_W_IIDR(a) BDK_CSR_TYPE_NCB32b
5310 #define basename_BDK_GTI_WRX_W_IIDR(a) "GTI_WRX_W_IIDR"
5311 #define device_bar_BDK_GTI_WRX_W_IIDR(a) 0x0 /* PF_BAR0 */
5312 #define busnum_BDK_GTI_WRX_W_IIDR(a) (a)
5313 #define arguments_BDK_GTI_WRX_W_IIDR(a) (a),-1,-1,-1
5314
5315 /**
5316 * Register (NCB32b) gti_wr#_wrr
5317 *
5318 * GTI Watchdog Refresh Register
5319 * GTI_WR(0) accesses the secure watchdog and is accessible only by the
5320 * secure-world. GTI_WR(1) accesses the nonsecure watchdog.
5321 */
5322 union bdk_gti_wrx_wrr
5323 {
5324 uint32_t u;
5325 struct bdk_gti_wrx_wrr_s
5326 {
5327 #if __BYTE_ORDER == __BIG_ENDIAN /* Word 0 - Big Endian */
5328 uint32_t zero : 32; /**< [ 31: 0](WO) Watchdog refresh. */
5329 #else /* Word 0 - Little Endian */
5330 uint32_t zero : 32; /**< [ 31: 0](WO) Watchdog refresh. */
5331 #endif /* Word 0 - End */
5332 } s;
5333 /* struct bdk_gti_wrx_wrr_s cn; */
5334 };
5335 typedef union bdk_gti_wrx_wrr bdk_gti_wrx_wrr_t;
5336
5337 static inline uint64_t BDK_GTI_WRX_WRR(unsigned long a) __attribute__ ((pure, always_inline));
BDK_GTI_WRX_WRR(unsigned long a)5338 static inline uint64_t BDK_GTI_WRX_WRR(unsigned long a)
5339 {
5340 if (a<=1)
5341 return 0x844000090000ll + 0x20000ll * ((a) & 0x1);
5342 __bdk_csr_fatal("GTI_WRX_WRR", 1, a, 0, 0, 0);
5343 }
5344
5345 #define typedef_BDK_GTI_WRX_WRR(a) bdk_gti_wrx_wrr_t
5346 #define bustype_BDK_GTI_WRX_WRR(a) BDK_CSR_TYPE_NCB32b
5347 #define basename_BDK_GTI_WRX_WRR(a) "GTI_WRX_WRR"
5348 #define device_bar_BDK_GTI_WRX_WRR(a) 0x0 /* PF_BAR0 */
5349 #define busnum_BDK_GTI_WRX_WRR(a) (a)
5350 #define arguments_BDK_GTI_WRX_WRR(a) (a),-1,-1,-1
5351
5352 #endif /* __BDK_CSRS_GTI_H__ */
5353