1 /***********************license start*********************************** 2 * Copyright (c) 2003-2017 Cavium Inc. ([email protected]). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 * 23 * This Software, including technical data, may be subject to U.S. export 24 * control laws, including the U.S. Export Administration Act and its 25 * associated regulations, and may be subject to export or import 26 * regulations in other countries. 27 * 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT 31 * TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY 32 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT 33 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES 34 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR 35 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, 36 * QUIET POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK 37 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 /** 41 * @file 42 * 43 * This is file defines ASM primitives for the executive. 44 45 * <hr>$Revision: 53373 $<hr> 46 * 47 * @defgroup asm Assembly support 48 * @{ 49 */ 50 51 /* This header file can be included from a .S file. Keep non-preprocessor 52 things under !__ASSEMBLER__. */ 53 #ifndef __ASSEMBLER__ 54 55 /* turn the variable name into a string */ 56 #define __BDK_TMP_STR(x) __BDK_TMP_STR2(x) 57 #define __BDK_TMP_STR2(x) #x 58 #define __BDK_VASTR(...) #__VA_ARGS__ 59 60 #define BDK_MRS_NV(reg, val) asm ("mrs %x[rd]," #reg : [rd] "=r" (val)) 61 #define BDK_MRS(reg, val) asm volatile ("mrs %x[rd]," #reg : [rd] "=r" (val)) 62 #define BDK_MSR(reg, val) asm volatile ("msr " #reg ",%x[rd]" : : [rd] "r" (val)) 63 64 /* other useful stuff */ 65 #define BDK_MB asm volatile ("dmb sy" : : :"memory") /* Full memory barrier, like MIPS SYNC */ 66 #define BDK_WMB asm volatile ("dmb st" : : :"memory") /* Write memory barreir, like MIPS SYNCW */ 67 #define BDK_WFE asm volatile ("wfe" : : :"memory") /* Wait for event */ 68 #define BDK_SEV asm volatile ("sev" : : :"memory") /* Send global event */ 69 #define BDK_DSB asm volatile ("dsb sy" : : :"memory") /* DSB */ 70 71 // normal prefetches that use the pref instruction 72 #define BDK_PREFETCH_PREFX(type, address, offset) asm volatile ("PRFUM " type ", [%[rbase],%[off]]" : : [rbase] "r" (address), [off] "I" (offset)) 73 // a normal prefetch 74 #define BDK_PREFETCH(address, offset) BDK_PREFETCH_PREFX("PLDL1KEEP", address, offset) 75 #define BDK_ICACHE_INVALIDATE { asm volatile ("ic iallu" : : ); } // invalidate entire icache 76 77 #define BDK_SYS_CVMCACHE_WBI_L2 "#0,c11,c1,#2" // L2 Cache Cache Hit Writeback Invalidate 78 #define BDK_SYS_CVMCACHE_WB_L2 "#0,c11,c1,#3" // L2 Cache Hit Writeback 79 #define BDK_SYS_CVMCACHE_LCK_L2 "#0,c11,c1,#4" // L2 Cache Fetch and Lock 80 #define BDK_SYS_CVMCACHE_WBI_L2_INDEXED "#0,c11,c0,#5" // L2 Cache Index Writeback Invalidate 81 #define BDK_SYS_CVMCACHE_LTG_L2_INDEXED "#0,c11,c0,#7" // L2 Cache Index Load Tag 82 #define BDK_SYS_CVMCACHE_INVALL_DC "#0,c11,c0,#2" // L1 Dcache Invalidate 83 #define BDK_CACHE_WBI_L2(address) { asm volatile ("sys " BDK_SYS_CVMCACHE_WBI_L2 ", %0" : : "r" (address)); } // Push to memory, invalidate, and unlock 84 #define BDK_CACHE_WBI_L2_INDEXED(encoded) { asm volatile ("sys " BDK_SYS_CVMCACHE_WBI_L2_INDEXED ", %0" : : "r" (encoded)); } // Push to memory, invalidate, and unlock, index by set/way 85 #define BDK_CACHE_WB_L2(address) { asm volatile ("sys " BDK_SYS_CVMCACHE_WB_L2 ", %0" : : "r" (address)); } // Push to memory, don't invalidate, don't unlock 86 #define BDK_CACHE_LCK_L2(address) { asm volatile ("sys " BDK_SYS_CVMCACHE_LCK_L2 ", %0" : : "r" (address)); } // Lock into L2 87 #define BDK_DCACHE_INVALIDATE { asm volatile ("sys " BDK_SYS_CVMCACHE_INVALL_DC ", xzr"); } // Invalidate the entire Dcache on local core 88 #define BDK_CACHE_LTG_L2_INDEXED(encoded) { asm volatile ("sys " BDK_SYS_CVMCACHE_LTG_L2_INDEXED ", %0" : : "r" (encoded)); } // Load L2 TAG, index by set/way 89 90 #define BDK_STORE_PAIR(ptr, data1, data2) { asm volatile ("stp %x[d1], %x[d2], [%[b]]" : [mem] "+m" (*(__uint128_t*)ptr) : [b] "r" (ptr), [d1] "r" (data1), [d2] "r" (data2)); } 91 92 #endif /* __ASSEMBLER__ */ 93 94 /** @} */ 95