1/*
2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <travis.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Travis must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Travis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24cpu_reset_func_start travis
25	/* ----------------------------------------------------
26	 * Disable speculative loads
27	 * ----------------------------------------------------
28	 */
29	msr	SSBS, xzr
30cpu_reset_func_end travis
31
32func travis_core_pwr_dwn
33#if ENABLE_SME_FOR_NS
34        /* ---------------------------------------------------
35         * Disable SME if enabled and supported
36         * ---------------------------------------------------
37         */
38	mrs     x0, ID_AA64PFR1_EL1
39	ubfx	x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
40		#ID_AA64PFR1_EL1_SME_WIDTH
41        cmp     x0, #SME_NOT_IMPLEMENTED
42	b.eq	1f
43	msr	TRAVIS_SVCRSM, xzr
44	msr	TRAVIS_SVCRZA, xzr
451:
46#endif
47	/* ---------------------------------------------------
48	 * Enable CPU power down bit in power control register
49	 * ---------------------------------------------------
50	 */
51	sysreg_bit_set TRAVIS_IMP_CPUPWRCTLR_EL1, \
52		TRAVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
53	isb
54	ret
55endfunc travis_core_pwr_dwn
56
57errata_report_shim travis
58
59.section .rodata.travis_regs, "aS"
60travis_regs: /* The ASCII list of register names to be reported */
61	.asciz	"cpuectlr_el1", ""
62
63func travis_cpu_reg_dump
64	adr 	x6, travis_regs
65	mrs	x8, TRAVIS_IMP_CPUECTLR_EL1
66	ret
67endfunc travis_cpu_reg_dump
68
69declare_cpu_ops travis, TRAVIS_MIDR, \
70	travis_reset_func, \
71	travis_core_pwr_dwn
72