1/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <nevis.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Nevis must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Nevis supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24cpu_reset_func_start nevis
25	/* ----------------------------------------------------
26	 * Disable speculative loads
27	 * ----------------------------------------------------
28	 */
29	msr	SSBS, xzr
30cpu_reset_func_end nevis
31
32func nevis_core_pwr_dwn
33	/* ---------------------------------------------------
34	 * Enable CPU power down bit in power control register
35	 * ---------------------------------------------------
36	 */
37	sysreg_bit_set NEVIS_IMP_CPUPWRCTLR_EL1, \
38		NEVIS_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
39	isb
40	ret
41endfunc nevis_core_pwr_dwn
42
43errata_report_shim nevis
44
45.section .rodata.nevis_regs, "aS"
46nevis_regs: /* The ASCII list of register names to be reported */
47	.asciz	"cpuectlr_el1", ""
48
49func nevis_cpu_reg_dump
50	adr 	x6, nevis_regs
51	mrs	x8, NEVIS_CPUECTLR_EL1
52	ret
53endfunc nevis_cpu_reg_dump
54
55declare_cpu_ops nevis, NEVIS_MIDR, \
56	nevis_reset_func, \
57	nevis_core_pwr_dwn
58