1/*
2 * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_x4.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex X4 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex X4 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26        wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_runtime_start cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
30	/* dsb before isb of power down sequence */
31	dsb	sy
32workaround_runtime_end cortex_x4, ERRATUM(2740089)
33
34check_erratum_ls cortex_x4, ERRATUM(2740089), CPU_REV(0, 1)
35
36workaround_reset_start cortex_x4, ERRATUM(2763018), ERRATA_X4_2763018
37	sysreg_bit_set	CORTEX_X4_CPUACTLR3_EL1, BIT(47)
38workaround_reset_end cortex_x4, ERRATUM(2763018)
39
40check_erratum_ls cortex_x4, ERRATUM(2763018), CPU_REV(0, 1)
41
42workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
43#if IMAGE_BL31
44	/*
45	 * The Cortex X4 generic vectors are overridden to apply errata
46	 * mitigation on exception entry from lower ELs.
47	 */
48	override_vector_table wa_cve_vbar_cortex_x4
49#endif /* IMAGE_BL31 */
50workaround_reset_end cortex_x4, CVE(2022, 23960)
51
52check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
53
54cpu_reset_func_start cortex_x4
55	/* Disable speculative loads */
56	msr	SSBS, xzr
57cpu_reset_func_end cortex_x4
58
59	/* ----------------------------------------------------
60	 * HW will do the cache maintenance while powering down
61	 * ----------------------------------------------------
62	 */
63func cortex_x4_core_pwr_dwn
64	/* ---------------------------------------------------
65	 * Enable CPU power down bit in power control register
66	 * ---------------------------------------------------
67	 */
68	sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
69
70	apply_erratum cortex_x4, ERRATUM(2740089), ERRATA_X4_2740089
71
72	isb
73	ret
74endfunc cortex_x4_core_pwr_dwn
75
76errata_report_shim cortex_x4
77
78	/* ---------------------------------------------
79	 * This function provides Cortex X4-specific
80	 * register information for crash reporting.
81	 * It needs to return with x6 pointing to
82	 * a list of register names in ascii and
83	 * x8 - x15 having values of registers to be
84	 * reported.
85	 * ---------------------------------------------
86	 */
87.section .rodata.cortex_x4_regs, "aS"
88cortex_x4_regs:  /* The ascii list of register names to be reported */
89	.asciz	"cpuectlr_el1", ""
90
91func cortex_x4_cpu_reg_dump
92	adr	x6, cortex_x4_regs
93	mrs	x8, CORTEX_X4_CPUECTLR_EL1
94	ret
95endfunc cortex_x4_cpu_reg_dump
96
97declare_cpu_ops cortex_x4, CORTEX_X4_MIDR, \
98	cortex_x4_reset_func, \
99	cortex_x4_core_pwr_dwn
100