1/*
2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_x3.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301
30	sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \
31	CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH
32workaround_reset_end cortex_x3, ERRATUM(2070301)
33
34check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
35
36workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
37        sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
38workaround_reset_end cortex_x3, ERRATUM(2266875)
39
40check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
41
42workaround_runtime_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
43	sysreg_bit_set	CORTEX_X3_CPUACTLR2_EL1, BIT(0)
44workaround_runtime_end cortex_x3, ERRATUM(2302506), NO_ISB
45
46check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1)
47
48workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
49	sysreg_bit_set	CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
50workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
51
52check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
53
54workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204
55	/* Set bit 40 in CPUACTLR2_EL1 */
56	sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40)
57workaround_reset_end cortex_x3, ERRATUM(2372204)
58
59check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0)
60
61workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
62	/* Disable retention control for WFI and WFE. */
63	mrs	x0, CORTEX_X3_CPUPWRCTLR_EL1
64	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
65	bfi	x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
66	msr	CORTEX_X3_CPUPWRCTLR_EL1, x0
67workaround_reset_end cortex_x3, ERRATUM(2615812)
68
69check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
70
71workaround_runtime_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945
72	sysreg_bit_set	CORTEX_X3_CPUACTLR6_EL1, BIT(41)
73workaround_runtime_end cortex_x3, ERRATUM(2641945), NO_ISB
74
75check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0)
76
77workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
78	/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
79	sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
80	sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
81workaround_reset_end cortex_x3, ERRATUM(2742421)
82
83check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
84
85workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
86	/* dsb before isb of power down sequence */
87	dsb sy
88workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
89
90check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
91
92workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
93	/* Set CPUACTLR3_EL1 bit 47 */
94	sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
95workaround_reset_end cortex_x3, ERRATUM(2779509)
96
97check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
98
99workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
100#if IMAGE_BL31
101	override_vector_table wa_cve_vbar_cortex_x3
102#endif /* IMAGE_BL31 */
103workaround_reset_end cortex_x3, CVE(2022, 23960)
104
105check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
106
107cpu_reset_func_start cortex_x3
108	/* Disable speculative loads */
109	msr	SSBS, xzr
110cpu_reset_func_end cortex_x3
111
112	/* ----------------------------------------------------
113	 * HW will do the cache maintenance while powering down
114	 * ----------------------------------------------------
115	 */
116func cortex_x3_core_pwr_dwn
117	apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
118	/* ---------------------------------------------------
119	 * Enable CPU power down bit in power control register
120	 * ---------------------------------------------------
121	 */
122	sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
123	apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
124	isb
125	ret
126endfunc cortex_x3_core_pwr_dwn
127
128errata_report_shim cortex_x3
129
130	/* ---------------------------------------------
131	 * This function provides Cortex-X3-
132	 * specific register information for crash
133	 * reporting. It needs to return with x6
134	 * pointing to a list of register names in ascii
135	 * and x8 - x15 having values of registers to be
136	 * reported.
137	 * ---------------------------------------------
138	 */
139.section .rodata.cortex_x3_regs, "aS"
140cortex_x3_regs:  /* The ascii list of register names to be reported */
141	.asciz	"cpuectlr_el1", ""
142
143func cortex_x3_cpu_reg_dump
144	adr	x6, cortex_x3_regs
145	mrs	x8, CORTEX_X3_CPUECTLR_EL1
146	ret
147endfunc cortex_x3_cpu_reg_dump
148
149declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
150	cortex_x3_reset_func, \
151	cortex_x3_core_pwr_dwn
152