1/*
2 * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_gelas.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Gelas must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Gelas supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24cpu_reset_func_start cortex_gelas
25	/* ----------------------------------------------------
26	 * Disable speculative loads
27	 * ----------------------------------------------------
28	 */
29	msr	SSBS, xzr
30cpu_reset_func_end cortex_gelas
31
32	/* ----------------------------------------------------
33	 * HW will do the cache maintenance while powering down
34	 * ----------------------------------------------------
35	 */
36func cortex_gelas_core_pwr_dwn
37#if ENABLE_SME_FOR_NS
38        /* ---------------------------------------------------
39         * Disable SME if enabled and supported
40         * ---------------------------------------------------
41         */
42	mrs     x0, ID_AA64PFR1_EL1
43	ubfx	x0, x0, #ID_AA64PFR1_EL1_SME_SHIFT, \
44		#ID_AA64PFR1_EL1_SME_WIDTH
45        cmp     x0, #SME_NOT_IMPLEMENTED
46	b.eq	1f
47	msr	CORTEX_GELAS_SVCRSM, xzr
48	msr	CORTEX_GELAS_SVCRZA, xzr
491:
50#endif
51	/* ---------------------------------------------------
52	 * Enable CPU power down bit in power control register
53	 * ---------------------------------------------------
54	 */
55	sysreg_bit_set 	CORTEX_GELAS_CPUPWRCTLR_EL1, \
56		CORTEX_GELAS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
57	isb
58	ret
59endfunc cortex_gelas_core_pwr_dwn
60
61errata_report_shim cortex_gelas
62
63	/* ---------------------------------------------
64	 * This function provides Gelas specific
65	 * register information for crash reporting.
66	 * It needs to return with x6 pointing to
67	 * a list of register names in ascii and
68	 * x8 - x15 having values of registers to be
69	 * reported.
70	 * ---------------------------------------------
71	 */
72.section .rodata.cortex_gelas_regs, "aS"
73cortex_gelas_regs: /* The ASCII list of register names to be reported */
74	.asciz	"imp_cpuectlr_el1", ""
75
76func cortex_gelas_cpu_reg_dump
77	adr	x6, cortex_gelas_regs
78	mrs	x8, CORTEX_GELAS_IMP_CPUECTLR_EL1
79	ret
80endfunc cortex_gelas_cpu_reg_dump
81
82declare_cpu_ops cortex_gelas, CORTEX_GELAS_MIDR, \
83	cortex_gelas_reset_func, \
84	cortex_gelas_core_pwr_dwn
85