1/*
2 * Copyright (c) 2023, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_chaberton.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Cortex Chaberton must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24cpu_reset_func_start cortex_chaberton
25	/* Disable speculative loads */
26	msr	SSBS, xzr
27cpu_reset_func_end cortex_chaberton
28
29	/* ----------------------------------------------------
30	 * HW will do the cache maintenance while powering down
31	 * ----------------------------------------------------
32	 */
33func cortex_chaberton_core_pwr_dwn
34	/* ---------------------------------------------------
35	 * Enable CPU power down bit in power control register
36	 * ---------------------------------------------------
37	 */
38	sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
39	isb
40	ret
41endfunc cortex_chaberton_core_pwr_dwn
42
43errata_report_shim cortex_chaberton
44
45	/* ---------------------------------------------
46	 * This function provides Cortex Chaberton specific
47	 * register information for crash reporting.
48	 * It needs to return with x6 pointing to
49	 * a list of register names in ascii and
50	 * x8 - x15 having values of registers to be
51	 * reported.
52	 * ---------------------------------------------
53	 */
54.section .rodata.cortex_chaberton_regs, "aS"
55cortex_chaberton_regs:  /* The ascii list of register names to be reported */
56	.asciz	"cpuectlr_el1", ""
57
58func cortex_chaberton_cpu_reg_dump
59	adr	x6, cortex_chaberton_regs
60	mrs	x8, CORTEX_CHABERTON_CPUECTLR_EL1
61	ret
62endfunc cortex_chaberton_cpu_reg_dump
63
64declare_cpu_ops cortex_chaberton, CORTEX_CHABERTON_MIDR, \
65	cortex_chaberton_reset_func, \
66	cortex_chaberton_core_pwr_dwn
67