1/*
2 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a715.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex-A715 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex-A715 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818
30        sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20)
31workaround_reset_end cortex_a715, ERRATUM(2331818)
32
33check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0)
34
35workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187
36	/* GCR_EL1 is only present with FEAT_MTE2. */
37	mrs x1, ID_AA64PFR1_EL1
38	ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
39	cmp x0, #MTE_IMPLEMENTED_ELX
40	bne #1f
41	sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT
42
431:
44	/* Mitigation upon ERETAA and ERETAB. */
45	mov x0, #2
46	msr CORTEX_A715_CPUPSELR_EL3, x0
47	isb
48	ldr x0, =0xd69f0bff
49	msr CORTEX_A715_CPUPOR_EL3, x0
50	ldr x0, =0xfffffbff
51	msr CORTEX_A715_CPUPMR_EL3, x0
52	mov x1, #0
53	orr x1, x1, #(1<<0)
54	orr x1, x1, #(3<<4)
55	orr x1, x1, #(0xf<<6)
56	orr x1, x1, #(1<<13)
57	orr x1, x1, #(1<<53)
58	msr CORTEX_A715_CPUPCR_EL3, x1
59workaround_reset_end cortex_a715, ERRATUM(2344187)
60
61check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0)
62
63workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290
64/* Erratum 2413290 workaround is required only if SPE is enabled */
65#if ENABLE_SPE_FOR_NS != 0
66	/* Check if Static profiling extension is implemented or present. */
67	mrs x1, id_aa64dfr0_el1
68	ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
69	cbz x0, 1f
70	/* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
71	sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57)
72	sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58)
731:
74#endif
75workaround_reset_end cortex_a715, ERRATUM(2413290)
76
77check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0)
78
79workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947
80        sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33)
81workaround_reset_end cortex_a715, ERRATUM(2420947)
82
83check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0)
84
85workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384
86        sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27)
87workaround_reset_end cortex_a715, ERRATUM(2429384)
88
89check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0)
90
91workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
92	sysreg_bit_set	CORTEX_A715_CPUACTLR2_EL1, BIT(26)
93workaround_reset_end cortex_a715, ERRATUM(2561034)
94
95check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
96
97workaround_reset_start cortex_a715, ERRATUM(2728106), ERRATA_A715_2728106
98	mov x0, #3
99	msr CORTEX_A715_CPUPSELR_EL3, x0
100	isb
101	ldr x0, =0xd503339f
102	msr CORTEX_A715_CPUPOR_EL3, x0
103	ldr x0, =0xfffff3ff
104	msr CORTEX_A715_CPUPMR_EL3, x0
105	mov x0, #1
106	orr x0, x0, #(3<<4)
107	orr x0, x0, #(0xf<<6)
108	orr x0, x0, #(1<<13)
109	orr x0, x0, #(1<<20)
110	orr x0, x0, #(1<<22)
111	orr x0, x0, #(1<<31)
112	orr x0, x0, #(1<<50)
113	msr CORTEX_A715_CPUPCR_EL3, x0
114workaround_reset_end cortex_a715, ERRATUM(2728106)
115
116check_erratum_ls cortex_a715, ERRATUM(2728106), CPU_REV(1, 1)
117
118workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
119#if IMAGE_BL31
120	/*
121	 * The Cortex-A715 generic vectors are overridden to apply errata
122	 * mitigation on exception entry from lower ELs.
123	 */
124	override_vector_table wa_cve_vbar_cortex_a715
125#endif /* IMAGE_BL31 */
126workaround_reset_end cortex_a715, CVE(2022, 23960)
127
128check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
129
130cpu_reset_func_start cortex_a715
131	/* Disable speculative loads */
132	msr	SSBS, xzr
133cpu_reset_func_end cortex_a715
134
135	/* ----------------------------------------------------
136	 * HW will do the cache maintenance while powering down
137	 * ----------------------------------------------------
138	 */
139func cortex_a715_core_pwr_dwn
140	/* ---------------------------------------------------
141	 * Enable CPU power down bit in power control register
142	 * ---------------------------------------------------
143	 */
144	mrs	x0, CORTEX_A715_CPUPWRCTLR_EL1
145	orr	x0, x0, #CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
146	msr	CORTEX_A715_CPUPWRCTLR_EL1, x0
147	isb
148	ret
149endfunc cortex_a715_core_pwr_dwn
150
151errata_report_shim cortex_a715
152
153	/* ---------------------------------------------
154	 * This function provides Cortex-A715 specific
155	 * register information for crash reporting.
156	 * It needs to return with x6 pointing to
157	 * a list of register names in ascii and
158	 * x8 - x15 having values of registers to be
159	 * reported.
160	 * ---------------------------------------------
161	 */
162.section .rodata.cortex_a715_regs, "aS"
163cortex_a715_regs:  /* The ascii list of register names to be reported */
164	.asciz	"cpuectlr_el1", ""
165
166func cortex_a715_cpu_reg_dump
167	adr	x6, cortex_a715_regs
168	mrs	x8, CORTEX_A715_CPUECTLR_EL1
169	ret
170endfunc cortex_a715_cpu_reg_dump
171
172declare_cpu_ops cortex_a715, CORTEX_A715_MIDR, \
173	cortex_a715_reset_func, \
174	cortex_a715_core_pwr_dwn
175