1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J784S4 and J742S2 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/mux/mux.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-ti.h> 11 12#include "k3-serdes.h" 13 14/ { 15 serdes_refclk: clock-serdes { 16 #clock-cells = <0>; 17 compatible = "fixed-clock"; 18 /* To be enabled when serdes_wiz* is functional */ 19 status = "disabled"; 20 }; 21}; 22 23&cbass_main { 24 /* 25 * MSMC is configured by bootloaders and a runtime fixup is done in the 26 * DT for this node 27 */ 28 msmc_ram: sram@70000000 { 29 compatible = "mmio-sram"; 30 reg = <0x00 0x70000000 0x00 0x800000>; 31 #address-cells = <1>; 32 #size-cells = <1>; 33 ranges = <0x00 0x00 0x70000000 0x800000>; 34 35 atf-sram@0 { 36 reg = <0x00 0x20000>; 37 }; 38 39 tifs-sram@1f0000 { 40 reg = <0x1f0000 0x10000>; 41 }; 42 43 l3cache-sram@200000 { 44 reg = <0x200000 0x200000>; 45 }; 46 }; 47 48 scm_conf: bus@100000 { 49 compatible = "simple-bus"; 50 reg = <0x00 0x00100000 0x00 0x1c000>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 ranges = <0x00 0x00 0x00100000 0x1c000>; 54 55 cpsw1_phy_gmii_sel: phy@4034 { 56 compatible = "ti,am654-phy-gmii-sel"; 57 reg = <0x4034 0x4>; 58 #phy-cells = <1>; 59 }; 60 61 cpsw0_phy_gmii_sel: phy@4044 { 62 compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; 63 reg = <0x4044 0x20>; 64 #phy-cells = <1>; 65 ti,qsgmii-main-ports = <7>, <7>; 66 }; 67 68 pcie0_ctrl: pcie0-ctrl@4070 { 69 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 70 reg = <0x4070 0x4>; 71 }; 72 73 pcie1_ctrl: pcie1-ctrl@4074 { 74 compatible = "ti,j784s4-pcie-ctrl", "syscon"; 75 reg = <0x4074 0x4>; 76 }; 77 78 serdes_ln_ctrl: mux-controller@4080 { 79 compatible = "reg-mux"; 80 reg = <0x00004080 0x30>; 81 #mux-control-cells = <1>; 82 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ 83 <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ 84 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ 85 <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ 86 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ 87 <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ 88 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ 89 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ 90 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, 91 <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 92 <J784S4_SERDES0_LANE2_IP3_UNUSED>, 93 <J784S4_SERDES0_LANE3_USB>, 94 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, 95 <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 96 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, 97 <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 98 <J784S4_SERDES2_LANE0_IP2_UNUSED>, 99 <J784S4_SERDES2_LANE1_IP2_UNUSED>, 100 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, 101 <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 102 <J784S4_SERDES4_LANE0_EDP_LANE0>, 103 <J784S4_SERDES4_LANE1_EDP_LANE1>, 104 <J784S4_SERDES4_LANE2_EDP_LANE2>, 105 <J784S4_SERDES4_LANE3_EDP_LANE3>; 106 }; 107 108 usb_serdes_mux: mux-controller@4000 { 109 compatible = "reg-mux"; 110 reg = <0x4000 0x4>; 111 #mux-control-cells = <1>; 112 mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 3 mux */ 113 }; 114 115 ehrpwm_tbclk: clock-controller@4140 { 116 compatible = "ti,am654-ehrpwm-tbclk"; 117 reg = <0x4140 0x18>; 118 #clock-cells = <1>; 119 }; 120 121 audio_refclk1: clock@82e4 { 122 compatible = "ti,am62-audio-refclk"; 123 reg = <0x82e4 0x4>; 124 clocks = <&k3_clks 157 34>; 125 assigned-clocks = <&k3_clks 157 34>; 126 assigned-clock-parents = <&k3_clks 157 63>; 127 #clock-cells = <0>; 128 }; 129 }; 130 131 main_ehrpwm0: pwm@3000000 { 132 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 133 reg = <0x00 0x3000000 0x00 0x100>; 134 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 219 0>; 135 clock-names = "tbclk", "fck"; 136 power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>; 137 #pwm-cells = <3>; 138 status = "disabled"; 139 }; 140 141 main_ehrpwm1: pwm@3010000 { 142 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 143 reg = <0x00 0x3010000 0x00 0x100>; 144 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 220 0>; 145 clock-names = "tbclk", "fck"; 146 power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>; 147 #pwm-cells = <3>; 148 status = "disabled"; 149 }; 150 151 main_ehrpwm2: pwm@3020000 { 152 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 153 reg = <0x00 0x3020000 0x00 0x100>; 154 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 221 0>; 155 clock-names = "tbclk", "fck"; 156 power-domains = <&k3_pds 221 TI_SCI_PD_EXCLUSIVE>; 157 #pwm-cells = <3>; 158 status = "disabled"; 159 }; 160 161 main_ehrpwm3: pwm@3030000 { 162 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 163 reg = <0x00 0x3030000 0x00 0x100>; 164 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 222 0>; 165 clock-names = "tbclk", "fck"; 166 power-domains = <&k3_pds 222 TI_SCI_PD_EXCLUSIVE>; 167 #pwm-cells = <3>; 168 status = "disabled"; 169 }; 170 171 main_ehrpwm4: pwm@3040000 { 172 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 173 reg = <0x00 0x3040000 0x00 0x100>; 174 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 223 0>; 175 clock-names = "tbclk", "fck"; 176 power-domains = <&k3_pds 223 TI_SCI_PD_EXCLUSIVE>; 177 #pwm-cells = <3>; 178 status = "disabled"; 179 }; 180 181 main_ehrpwm5: pwm@3050000 { 182 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 183 reg = <0x00 0x3050000 0x00 0x100>; 184 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 224 0>; 185 clock-names = "tbclk", "fck"; 186 power-domains = <&k3_pds 224 TI_SCI_PD_EXCLUSIVE>; 187 #pwm-cells = <3>; 188 status = "disabled"; 189 }; 190 191 gic500: interrupt-controller@1800000 { 192 compatible = "arm,gic-v3"; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges; 196 #interrupt-cells = <3>; 197 interrupt-controller; 198 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 199 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 200 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 201 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 202 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 203 204 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 206 207 gic_its: msi-controller@1820000 { 208 compatible = "arm,gic-v3-its"; 209 reg = <0x00 0x01820000 0x00 0x10000>; 210 socionext,synquacer-pre-its = <0x1000000 0x400000>; 211 msi-controller; 212 #msi-cells = <1>; 213 }; 214 }; 215 216 main_gpio_intr: interrupt-controller@a00000 { 217 compatible = "ti,sci-intr"; 218 reg = <0x00 0x00a00000 0x00 0x800>; 219 ti,intr-trigger-type = <1>; 220 interrupt-controller; 221 interrupt-parent = <&gic500>; 222 #interrupt-cells = <1>; 223 ti,sci = <&sms>; 224 ti,sci-dev-id = <10>; 225 ti,interrupt-ranges = <8 392 56>; 226 }; 227 228 main_pmx0: pinctrl@11c000 { 229 compatible = "ti,j7200-padconf", "pinctrl-single"; 230 /* Proxy 0 addressing */ 231 reg = <0x00 0x11c000 0x00 0x120>; 232 #pinctrl-cells = <1>; 233 pinctrl-single,register-width = <32>; 234 pinctrl-single,function-mask = <0xffffffff>; 235 }; 236 237 /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */ 238 main_timerio_input: pinctrl@104200 { 239 compatible = "ti,j7200-padconf", "pinctrl-single"; 240 reg = <0x00 0x104200 0x00 0x50>; 241 #pinctrl-cells = <1>; 242 pinctrl-single,register-width = <32>; 243 pinctrl-single,function-mask = <0x00000007>; 244 }; 245 246 /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */ 247 main_timerio_output: pinctrl@104280 { 248 compatible = "ti,j7200-padconf", "pinctrl-single"; 249 reg = <0x00 0x104280 0x00 0x20>; 250 #pinctrl-cells = <1>; 251 pinctrl-single,register-width = <32>; 252 pinctrl-single,function-mask = <0x0000001f>; 253 }; 254 255 main_crypto: crypto@4e00000 { 256 compatible = "ti,j721e-sa2ul"; 257 reg = <0x00 0x4e00000 0x00 0x1200>; 258 power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 259 #address-cells = <2>; 260 #size-cells = <2>; 261 ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 262 263 dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 264 <&main_udmap 0x4a41>; 265 dma-names = "tx", "rx1", "rx2"; 266 267 rng: rng@4e10000 { 268 compatible = "inside-secure,safexcel-eip76"; 269 reg = <0x00 0x4e10000 0x00 0x7d>; 270 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 271 }; 272 }; 273 274 main_timer0: timer@2400000 { 275 compatible = "ti,am654-timer"; 276 reg = <0x00 0x2400000 0x00 0x400>; 277 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&k3_clks 97 2>; 279 clock-names = "fck"; 280 assigned-clocks = <&k3_clks 97 2>; 281 assigned-clock-parents = <&k3_clks 97 3>; 282 power-domains = <&k3_pds 97 TI_SCI_PD_EXCLUSIVE>; 283 ti,timer-pwm; 284 }; 285 286 main_timer1: timer@2410000 { 287 compatible = "ti,am654-timer"; 288 reg = <0x00 0x2410000 0x00 0x400>; 289 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&k3_clks 98 2>; 291 clock-names = "fck"; 292 assigned-clocks = <&k3_clks 98 2>; 293 assigned-clock-parents = <&k3_clks 98 3>; 294 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 295 ti,timer-pwm; 296 }; 297 298 main_timer2: timer@2420000 { 299 compatible = "ti,am654-timer"; 300 reg = <0x00 0x2420000 0x00 0x400>; 301 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&k3_clks 99 2>; 303 clock-names = "fck"; 304 assigned-clocks = <&k3_clks 99 2>; 305 assigned-clock-parents = <&k3_clks 99 3>; 306 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 307 ti,timer-pwm; 308 }; 309 310 main_timer3: timer@2430000 { 311 compatible = "ti,am654-timer"; 312 reg = <0x00 0x2430000 0x00 0x400>; 313 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&k3_clks 100 2>; 315 clock-names = "fck"; 316 assigned-clocks = <&k3_clks 100 2>; 317 assigned-clock-parents = <&k3_clks 100 3>; 318 power-domains = <&k3_pds 100 TI_SCI_PD_EXCLUSIVE>; 319 ti,timer-pwm; 320 }; 321 322 main_timer4: timer@2440000 { 323 compatible = "ti,am654-timer"; 324 reg = <0x00 0x2440000 0x00 0x400>; 325 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&k3_clks 101 2>; 327 clock-names = "fck"; 328 assigned-clocks = <&k3_clks 101 2>; 329 assigned-clock-parents = <&k3_clks 101 3>; 330 power-domains = <&k3_pds 101 TI_SCI_PD_EXCLUSIVE>; 331 ti,timer-pwm; 332 }; 333 334 main_timer5: timer@2450000 { 335 compatible = "ti,am654-timer"; 336 reg = <0x00 0x2450000 0x00 0x400>; 337 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&k3_clks 102 2>; 339 clock-names = "fck"; 340 assigned-clocks = <&k3_clks 102 2>; 341 assigned-clock-parents = <&k3_clks 102 3>; 342 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 343 ti,timer-pwm; 344 }; 345 346 main_timer6: timer@2460000 { 347 compatible = "ti,am654-timer"; 348 reg = <0x00 0x2460000 0x00 0x400>; 349 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&k3_clks 103 2>; 351 clock-names = "fck"; 352 assigned-clocks = <&k3_clks 103 2>; 353 assigned-clock-parents = <&k3_clks 103 3>; 354 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 355 ti,timer-pwm; 356 }; 357 358 main_timer7: timer@2470000 { 359 compatible = "ti,am654-timer"; 360 reg = <0x00 0x2470000 0x00 0x400>; 361 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&k3_clks 104 2>; 363 clock-names = "fck"; 364 assigned-clocks = <&k3_clks 104 2>; 365 assigned-clock-parents = <&k3_clks 104 3>; 366 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 367 ti,timer-pwm; 368 }; 369 370 main_timer8: timer@2480000 { 371 compatible = "ti,am654-timer"; 372 reg = <0x00 0x2480000 0x00 0x400>; 373 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&k3_clks 105 2>; 375 clock-names = "fck"; 376 assigned-clocks = <&k3_clks 105 2>; 377 assigned-clock-parents = <&k3_clks 105 3>; 378 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 379 ti,timer-pwm; 380 }; 381 382 main_timer9: timer@2490000 { 383 compatible = "ti,am654-timer"; 384 reg = <0x00 0x2490000 0x00 0x400>; 385 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&k3_clks 106 2>; 387 clock-names = "fck"; 388 assigned-clocks = <&k3_clks 106 2>; 389 assigned-clock-parents = <&k3_clks 106 3>; 390 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 391 ti,timer-pwm; 392 }; 393 394 main_timer10: timer@24a0000 { 395 compatible = "ti,am654-timer"; 396 reg = <0x00 0x24a0000 0x00 0x400>; 397 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&k3_clks 107 2>; 399 clock-names = "fck"; 400 assigned-clocks = <&k3_clks 107 2>; 401 assigned-clock-parents = <&k3_clks 107 3>; 402 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 403 ti,timer-pwm; 404 }; 405 406 main_timer11: timer@24b0000 { 407 compatible = "ti,am654-timer"; 408 reg = <0x00 0x24b0000 0x00 0x400>; 409 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&k3_clks 108 2>; 411 clock-names = "fck"; 412 assigned-clocks = <&k3_clks 108 2>; 413 assigned-clock-parents = <&k3_clks 108 3>; 414 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; 415 ti,timer-pwm; 416 }; 417 418 main_timer12: timer@24c0000 { 419 compatible = "ti,am654-timer"; 420 reg = <0x00 0x24c0000 0x00 0x400>; 421 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&k3_clks 109 2>; 423 clock-names = "fck"; 424 assigned-clocks = <&k3_clks 109 2>; 425 assigned-clock-parents = <&k3_clks 109 3>; 426 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; 427 ti,timer-pwm; 428 }; 429 430 main_timer13: timer@24d0000 { 431 compatible = "ti,am654-timer"; 432 reg = <0x00 0x24d0000 0x00 0x400>; 433 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 434 clocks = <&k3_clks 110 2>; 435 clock-names = "fck"; 436 assigned-clocks = <&k3_clks 110 2>; 437 assigned-clock-parents = <&k3_clks 110 3>; 438 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 439 ti,timer-pwm; 440 }; 441 442 main_timer14: timer@24e0000 { 443 compatible = "ti,am654-timer"; 444 reg = <0x00 0x24e0000 0x00 0x400>; 445 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&k3_clks 111 2>; 447 clock-names = "fck"; 448 assigned-clocks = <&k3_clks 111 2>; 449 assigned-clock-parents = <&k3_clks 111 3>; 450 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 451 ti,timer-pwm; 452 }; 453 454 main_timer15: timer@24f0000 { 455 compatible = "ti,am654-timer"; 456 reg = <0x00 0x24f0000 0x00 0x400>; 457 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&k3_clks 112 2>; 459 clock-names = "fck"; 460 assigned-clocks = <&k3_clks 112 2>; 461 assigned-clock-parents = <&k3_clks 112 3>; 462 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 463 ti,timer-pwm; 464 }; 465 466 main_timer16: timer@2500000 { 467 compatible = "ti,am654-timer"; 468 reg = <0x00 0x2500000 0x00 0x400>; 469 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&k3_clks 113 2>; 471 clock-names = "fck"; 472 assigned-clocks = <&k3_clks 113 2>; 473 assigned-clock-parents = <&k3_clks 113 3>; 474 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 475 ti,timer-pwm; 476 }; 477 478 main_timer17: timer@2510000 { 479 compatible = "ti,am654-timer"; 480 reg = <0x00 0x2510000 0x00 0x400>; 481 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&k3_clks 114 2>; 483 clock-names = "fck"; 484 assigned-clocks = <&k3_clks 114 2>; 485 assigned-clock-parents = <&k3_clks 114 3>; 486 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 487 ti,timer-pwm; 488 }; 489 490 main_timer18: timer@2520000 { 491 compatible = "ti,am654-timer"; 492 reg = <0x00 0x2520000 0x00 0x400>; 493 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&k3_clks 115 2>; 495 clock-names = "fck"; 496 assigned-clocks = <&k3_clks 115 2>; 497 assigned-clock-parents = <&k3_clks 115 3>; 498 power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; 499 ti,timer-pwm; 500 }; 501 502 main_timer19: timer@2530000 { 503 compatible = "ti,am654-timer"; 504 reg = <0x00 0x2530000 0x00 0x400>; 505 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 506 clocks = <&k3_clks 116 2>; 507 clock-names = "fck"; 508 assigned-clocks = <&k3_clks 116 2>; 509 assigned-clock-parents = <&k3_clks 116 3>; 510 power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; 511 ti,timer-pwm; 512 }; 513 514 main_uart0: serial@2800000 { 515 compatible = "ti,j721e-uart", "ti,am654-uart"; 516 reg = <0x00 0x02800000 0x00 0x200>; 517 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&k3_clks 146 0>; 519 clock-names = "fclk"; 520 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 521 status = "disabled"; 522 }; 523 524 main_uart1: serial@2810000 { 525 compatible = "ti,j721e-uart", "ti,am654-uart"; 526 reg = <0x00 0x02810000 0x00 0x200>; 527 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&k3_clks 388 0>; 529 clock-names = "fclk"; 530 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 531 status = "disabled"; 532 }; 533 534 main_uart2: serial@2820000 { 535 compatible = "ti,j721e-uart", "ti,am654-uart"; 536 reg = <0x00 0x02820000 0x00 0x200>; 537 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&k3_clks 389 0>; 539 clock-names = "fclk"; 540 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 541 status = "disabled"; 542 }; 543 544 main_uart3: serial@2830000 { 545 compatible = "ti,j721e-uart", "ti,am654-uart"; 546 reg = <0x00 0x02830000 0x00 0x200>; 547 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&k3_clks 390 0>; 549 clock-names = "fclk"; 550 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 551 status = "disabled"; 552 }; 553 554 main_uart4: serial@2840000 { 555 compatible = "ti,j721e-uart", "ti,am654-uart"; 556 reg = <0x00 0x02840000 0x00 0x200>; 557 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&k3_clks 391 0>; 559 clock-names = "fclk"; 560 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 561 status = "disabled"; 562 }; 563 564 main_uart5: serial@2850000 { 565 compatible = "ti,j721e-uart", "ti,am654-uart"; 566 reg = <0x00 0x02850000 0x00 0x200>; 567 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&k3_clks 392 0>; 569 clock-names = "fclk"; 570 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 571 status = "disabled"; 572 }; 573 574 main_uart6: serial@2860000 { 575 compatible = "ti,j721e-uart", "ti,am654-uart"; 576 reg = <0x00 0x02860000 0x00 0x200>; 577 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&k3_clks 393 0>; 579 clock-names = "fclk"; 580 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 581 status = "disabled"; 582 }; 583 584 main_uart7: serial@2870000 { 585 compatible = "ti,j721e-uart", "ti,am654-uart"; 586 reg = <0x00 0x02870000 0x00 0x200>; 587 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&k3_clks 394 0>; 589 clock-names = "fclk"; 590 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 591 status = "disabled"; 592 }; 593 594 main_uart8: serial@2880000 { 595 compatible = "ti,j721e-uart", "ti,am654-uart"; 596 reg = <0x00 0x02880000 0x00 0x200>; 597 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&k3_clks 395 0>; 599 clock-names = "fclk"; 600 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 601 status = "disabled"; 602 }; 603 604 main_uart9: serial@2890000 { 605 compatible = "ti,j721e-uart", "ti,am654-uart"; 606 reg = <0x00 0x02890000 0x00 0x200>; 607 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&k3_clks 396 0>; 609 clock-names = "fclk"; 610 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 611 status = "disabled"; 612 }; 613 614 main_gpio0: gpio@600000 { 615 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 616 reg = <0x00 0x00600000 0x00 0x100>; 617 gpio-controller; 618 #gpio-cells = <2>; 619 interrupt-parent = <&main_gpio_intr>; 620 interrupts = <145>, <146>, <147>, <148>, <149>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 ti,ngpio = <66>; 624 ti,davinci-gpio-unbanked = <0>; 625 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 626 clocks = <&k3_clks 163 0>; 627 clock-names = "gpio"; 628 status = "disabled"; 629 }; 630 631 main_gpio2: gpio@610000 { 632 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 633 reg = <0x00 0x00610000 0x00 0x100>; 634 gpio-controller; 635 #gpio-cells = <2>; 636 interrupt-parent = <&main_gpio_intr>; 637 interrupts = <154>, <155>, <156>, <157>, <158>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 ti,ngpio = <66>; 641 ti,davinci-gpio-unbanked = <0>; 642 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 643 clocks = <&k3_clks 164 0>; 644 clock-names = "gpio"; 645 status = "disabled"; 646 }; 647 648 main_gpio4: gpio@620000 { 649 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 650 reg = <0x00 0x00620000 0x00 0x100>; 651 gpio-controller; 652 #gpio-cells = <2>; 653 interrupt-parent = <&main_gpio_intr>; 654 interrupts = <163>, <164>, <165>, <166>, <167>; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 ti,ngpio = <66>; 658 ti,davinci-gpio-unbanked = <0>; 659 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 660 clocks = <&k3_clks 165 0>; 661 clock-names = "gpio"; 662 status = "disabled"; 663 }; 664 665 main_gpio6: gpio@630000 { 666 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 667 reg = <0x00 0x00630000 0x00 0x100>; 668 gpio-controller; 669 #gpio-cells = <2>; 670 interrupt-parent = <&main_gpio_intr>; 671 interrupts = <172>, <173>, <174>, <175>, <176>; 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 ti,ngpio = <66>; 675 ti,davinci-gpio-unbanked = <0>; 676 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 677 clocks = <&k3_clks 166 0>; 678 clock-names = "gpio"; 679 status = "disabled"; 680 }; 681 682 usbss0: usb@4104000 { 683 bootph-all; 684 compatible = "ti,j721e-usb"; 685 reg = <0x00 0x4104000 0x00 0x100>; 686 dma-coherent; 687 power-domains = <&k3_pds 398 TI_SCI_PD_EXCLUSIVE>; 688 clocks = <&k3_clks 398 21>, <&k3_clks 398 2>; 689 clock-names = "ref", "lpm"; 690 assigned-clocks = <&k3_clks 398 21>; /* USB2_REFCLK */ 691 assigned-clock-parents = <&k3_clks 398 22>; /* HFOSC0 */ 692 #address-cells = <2>; 693 #size-cells = <2>; 694 ranges; 695 696 status = "disabled"; /* Needs lane config */ 697 698 usb0: usb@6000000 { 699 bootph-all; 700 compatible = "cdns,usb3"; 701 reg = <0x00 0x6000000 0x00 0x10000>, 702 <0x00 0x6010000 0x00 0x10000>, 703 <0x00 0x6020000 0x00 0x10000>; 704 reg-names = "otg", "xhci", "dev"; 705 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 706 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 707 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */ 708 interrupt-names = "host", 709 "peripheral", 710 "otg"; 711 }; 712 }; 713 714 main_i2c0: i2c@2000000 { 715 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 716 reg = <0x00 0x02000000 0x00 0x100>; 717 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 clocks = <&k3_clks 270 2>; 721 clock-names = "fck"; 722 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 723 status = "disabled"; 724 }; 725 726 main_i2c1: i2c@2010000 { 727 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 728 reg = <0x00 0x02010000 0x00 0x100>; 729 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 clocks = <&k3_clks 271 2>; 733 clock-names = "fck"; 734 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 735 status = "disabled"; 736 }; 737 738 main_i2c2: i2c@2020000 { 739 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 740 reg = <0x00 0x02020000 0x00 0x100>; 741 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 clocks = <&k3_clks 272 2>; 745 clock-names = "fck"; 746 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 747 status = "disabled"; 748 }; 749 750 main_i2c3: i2c@2030000 { 751 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 752 reg = <0x00 0x02030000 0x00 0x100>; 753 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 754 #address-cells = <1>; 755 #size-cells = <0>; 756 clocks = <&k3_clks 273 2>; 757 clock-names = "fck"; 758 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 759 status = "disabled"; 760 }; 761 762 main_i2c4: i2c@2040000 { 763 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 764 reg = <0x00 0x02040000 0x00 0x100>; 765 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 clocks = <&k3_clks 274 2>; 769 clock-names = "fck"; 770 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 771 status = "disabled"; 772 }; 773 774 main_i2c5: i2c@2050000 { 775 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 776 reg = <0x00 0x02050000 0x00 0x100>; 777 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 clocks = <&k3_clks 275 2>; 781 clock-names = "fck"; 782 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 783 status = "disabled"; 784 }; 785 786 main_i2c6: i2c@2060000 { 787 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 788 reg = <0x00 0x02060000 0x00 0x100>; 789 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 clocks = <&k3_clks 276 2>; 793 clock-names = "fck"; 794 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 795 status = "disabled"; 796 }; 797 798 ti_csi2rx0: ticsi2rx@4500000 { 799 compatible = "ti,j721e-csi2rx-shim"; 800 reg = <0x00 0x04500000 0x00 0x00001000>; 801 ranges; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 dmas = <&main_bcdma_csi 0 0x4940 0>; 805 dma-names = "rx0"; 806 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 807 status = "disabled"; 808 809 cdns_csi2rx0: csi-bridge@4504000 { 810 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 811 reg = <0x00 0x04504000 0x00 0x00001000>; 812 clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, 813 <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; 814 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 815 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 816 phys = <&dphy0>; 817 phy-names = "dphy"; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 csi0_port0: port@0 { 824 reg = <0>; 825 status = "disabled"; 826 }; 827 828 csi0_port1: port@1 { 829 reg = <1>; 830 status = "disabled"; 831 }; 832 833 csi0_port2: port@2 { 834 reg = <2>; 835 status = "disabled"; 836 }; 837 838 csi0_port3: port@3 { 839 reg = <3>; 840 status = "disabled"; 841 }; 842 843 csi0_port4: port@4 { 844 reg = <4>; 845 status = "disabled"; 846 }; 847 }; 848 }; 849 }; 850 851 ti_csi2rx1: ticsi2rx@4510000 { 852 compatible = "ti,j721e-csi2rx-shim"; 853 reg = <0x00 0x04510000 0x00 0x1000>; 854 ranges; 855 #address-cells = <2>; 856 #size-cells = <2>; 857 dmas = <&main_bcdma_csi 0 0x4960 0>; 858 dma-names = "rx0"; 859 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 860 status = "disabled"; 861 862 cdns_csi2rx1: csi-bridge@4514000 { 863 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 864 reg = <0x00 0x04514000 0x00 0x00001000>; 865 clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, 866 <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; 867 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 868 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 869 phys = <&dphy1>; 870 phy-names = "dphy"; 871 ports { 872 #address-cells = <1>; 873 #size-cells = <0>; 874 875 csi1_port0: port@0 { 876 reg = <0>; 877 status = "disabled"; 878 }; 879 880 csi1_port1: port@1 { 881 reg = <1>; 882 status = "disabled"; 883 }; 884 885 csi1_port2: port@2 { 886 reg = <2>; 887 status = "disabled"; 888 }; 889 890 csi1_port3: port@3 { 891 reg = <3>; 892 status = "disabled"; 893 }; 894 895 csi1_port4: port@4 { 896 reg = <4>; 897 status = "disabled"; 898 }; 899 }; 900 }; 901 }; 902 903 ti_csi2rx2: ticsi2rx@4520000 { 904 compatible = "ti,j721e-csi2rx-shim"; 905 reg = <0x00 0x04520000 0x00 0x00001000>; 906 ranges; 907 #address-cells = <2>; 908 #size-cells = <2>; 909 dmas = <&main_bcdma_csi 0 0x4980 0>; 910 dma-names = "rx0"; 911 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 912 status = "disabled"; 913 914 cdns_csi2rx2: csi-bridge@4524000 { 915 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 916 reg = <0x00 0x04524000 0x00 0x00001000>; 917 clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, 918 <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; 919 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 920 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 921 phys = <&dphy2>; 922 phy-names = "dphy"; 923 924 ports { 925 #address-cells = <1>; 926 #size-cells = <0>; 927 928 csi2_port0: port@0 { 929 reg = <0>; 930 status = "disabled"; 931 }; 932 933 csi2_port1: port@1 { 934 reg = <1>; 935 status = "disabled"; 936 }; 937 938 csi2_port2: port@2 { 939 reg = <2>; 940 status = "disabled"; 941 }; 942 943 csi2_port3: port@3 { 944 reg = <3>; 945 status = "disabled"; 946 }; 947 948 csi2_port4: port@4 { 949 reg = <4>; 950 status = "disabled"; 951 }; 952 }; 953 }; 954 }; 955 956 dphy0: phy@4580000 { 957 compatible = "cdns,dphy-rx"; 958 reg = <0x00 0x04580000 0x00 0x00001100>; 959 #phy-cells = <0>; 960 power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; 961 status = "disabled"; 962 }; 963 964 dphy1: phy@4590000 { 965 compatible = "cdns,dphy-rx"; 966 reg = <0x00 0x04590000 0x00 0x00001100>; 967 #phy-cells = <0>; 968 power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; 969 status = "disabled"; 970 }; 971 972 dphy2: phy@45a0000 { 973 compatible = "cdns,dphy-rx"; 974 reg = <0x00 0x045a0000 0x00 0x00001100>; 975 #phy-cells = <0>; 976 power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; 977 status = "disabled"; 978 }; 979 980 vpu0: video-codec@4210000 { 981 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 982 reg = <0x00 0x4210000 0x00 0x10000>; 983 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&k3_clks 241 2>; 985 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>; 986 }; 987 988 vpu1: video-codec@4220000 { 989 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 990 reg = <0x00 0x4220000 0x00 0x10000>; 991 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&k3_clks 242 2>; 993 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>; 994 }; 995 996 main_sdhci0: mmc@4f80000 { 997 compatible = "ti,j721e-sdhci-8bit"; 998 reg = <0x00 0x04f80000 0x00 0x1000>, 999 <0x00 0x04f88000 0x00 0x400>; 1000 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1001 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 1002 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 1003 clock-names = "clk_ahb", "clk_xin"; 1004 assigned-clocks = <&k3_clks 140 2>; 1005 assigned-clock-parents = <&k3_clks 140 3>; 1006 bus-width = <8>; 1007 ti,otap-del-sel-legacy = <0x0>; 1008 ti,otap-del-sel-mmc-hs = <0x0>; 1009 ti,otap-del-sel-ddr52 = <0x6>; 1010 ti,otap-del-sel-hs200 = <0x8>; 1011 ti,otap-del-sel-hs400 = <0x5>; 1012 ti,itap-del-sel-legacy = <0x10>; 1013 ti,itap-del-sel-mmc-hs = <0xa>; 1014 ti,strobe-sel = <0x77>; 1015 ti,clkbuf-sel = <0x7>; 1016 ti,trm-icp = <0x8>; 1017 mmc-ddr-1_8v; 1018 mmc-hs200-1_8v; 1019 mmc-hs400-1_8v; 1020 dma-coherent; 1021 status = "disabled"; 1022 }; 1023 1024 main_sdhci1: mmc@4fb0000 { 1025 compatible = "ti,j721e-sdhci-4bit"; 1026 reg = <0x00 0x04fb0000 0x00 0x1000>, 1027 <0x00 0x04fb8000 0x00 0x400>; 1028 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1029 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 1030 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 1031 clock-names = "clk_ahb", "clk_xin"; 1032 assigned-clocks = <&k3_clks 141 4>; 1033 assigned-clock-parents = <&k3_clks 141 5>; 1034 bus-width = <4>; 1035 ti,otap-del-sel-legacy = <0x0>; 1036 ti,otap-del-sel-sd-hs = <0x0>; 1037 ti,otap-del-sel-sdr12 = <0xf>; 1038 ti,otap-del-sel-sdr25 = <0xf>; 1039 ti,otap-del-sel-sdr50 = <0xc>; 1040 ti,otap-del-sel-sdr104 = <0x5>; 1041 ti,otap-del-sel-ddr50 = <0xc>; 1042 ti,itap-del-sel-legacy = <0x0>; 1043 ti,itap-del-sel-sd-hs = <0x0>; 1044 ti,itap-del-sel-sdr12 = <0x0>; 1045 ti,itap-del-sel-sdr25 = <0x0>; 1046 ti,itap-del-sel-ddr50 = <0x2>; 1047 ti,clkbuf-sel = <0x7>; 1048 ti,trm-icp = <0x8>; 1049 dma-coherent; 1050 status = "disabled"; 1051 }; 1052 1053 pcie0_rc: pcie@2900000 { 1054 compatible = "ti,j784s4-pcie-host"; 1055 reg = <0x00 0x02900000 0x00 0x1000>, 1056 <0x00 0x02907000 0x00 0x400>, 1057 <0x00 0x0d000000 0x00 0x00800000>, 1058 <0x00 0x10000000 0x00 0x00001000>; 1059 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1060 interrupt-names = "link_state"; 1061 interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>; 1062 device_type = "pci"; 1063 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>; 1064 max-link-speed = <3>; 1065 num-lanes = <4>; 1066 power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>; 1067 clocks = <&k3_clks 332 0>; 1068 clock-names = "fck"; 1069 #address-cells = <3>; 1070 #size-cells = <2>; 1071 bus-range = <0x0 0xff>; 1072 vendor-id = <0x104c>; 1073 device-id = <0xb012>; 1074 msi-map = <0x0 &gic_its 0x0 0x10000>; 1075 dma-coherent; 1076 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>, 1077 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>; 1078 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1079 status = "disabled"; 1080 }; 1081 1082 pcie1_rc: pcie@2910000 { 1083 compatible = "ti,j784s4-pcie-host"; 1084 reg = <0x00 0x02910000 0x00 0x1000>, 1085 <0x00 0x02917000 0x00 0x400>, 1086 <0x00 0x0d800000 0x00 0x00800000>, 1087 <0x00 0x18000000 0x00 0x00001000>; 1088 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1089 interrupt-names = "link_state"; 1090 interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; 1091 device_type = "pci"; 1092 ti,syscon-pcie-ctrl = <&pcie1_ctrl 0x0>; 1093 max-link-speed = <3>; 1094 num-lanes = <4>; 1095 power-domains = <&k3_pds 333 TI_SCI_PD_EXCLUSIVE>; 1096 clocks = <&k3_clks 333 0>; 1097 clock-names = "fck"; 1098 #address-cells = <3>; 1099 #size-cells = <2>; 1100 bus-range = <0x0 0xff>; 1101 vendor-id = <0x104c>; 1102 device-id = <0xb012>; 1103 msi-map = <0x0 &gic_its 0x10000 0x10000>; 1104 dma-coherent; 1105 ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>, 1106 <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>; 1107 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 1108 status = "disabled"; 1109 }; 1110 1111 serdes_wiz0: wiz@5060000 { 1112 compatible = "ti,j784s4-wiz-10g"; 1113 #address-cells = <1>; 1114 #size-cells = <1>; 1115 power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>; 1116 clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&serdes_refclk>, <&k3_clks 404 5>; 1117 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1118 assigned-clocks = <&k3_clks 404 6>; 1119 assigned-clock-parents = <&k3_clks 404 10>; 1120 num-lanes = <4>; 1121 #reset-cells = <1>; 1122 #clock-cells = <1>; 1123 ranges = <0x5060000 0x00 0x5060000 0x10000>; 1124 status = "disabled"; 1125 1126 serdes0: serdes@5060000 { 1127 compatible = "ti,j721e-serdes-10g"; 1128 reg = <0x05060000 0x010000>; 1129 reg-names = "torrent_phy"; 1130 resets = <&serdes_wiz0 0>; 1131 reset-names = "torrent_reset"; 1132 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1133 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1134 clock-names = "refclk", "phy_en_refclk"; 1135 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1136 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1137 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1138 assigned-clock-parents = <&k3_clks 404 6>, 1139 <&k3_clks 404 6>, 1140 <&k3_clks 404 6>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 #clock-cells = <1>; 1144 status = "disabled"; 1145 }; 1146 }; 1147 1148 serdes_wiz1: wiz@5070000 { 1149 compatible = "ti,j784s4-wiz-10g"; 1150 #address-cells = <1>; 1151 #size-cells = <1>; 1152 power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>; 1153 clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&serdes_refclk>, <&k3_clks 405 5>; 1154 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1155 assigned-clocks = <&k3_clks 405 6>; 1156 assigned-clock-parents = <&k3_clks 405 10>; 1157 num-lanes = <4>; 1158 #reset-cells = <1>; 1159 #clock-cells = <1>; 1160 ranges = <0x05070000 0x00 0x05070000 0x10000>; 1161 status = "disabled"; 1162 1163 serdes1: serdes@5070000 { 1164 compatible = "ti,j721e-serdes-10g"; 1165 reg = <0x05070000 0x010000>; 1166 reg-names = "torrent_phy"; 1167 resets = <&serdes_wiz1 0>; 1168 reset-names = "torrent_reset"; 1169 clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1170 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>; 1171 clock-names = "refclk", "phy_en_refclk"; 1172 assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>, 1173 <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>, 1174 <&serdes_wiz1 TI_WIZ_REFCLK_DIG>; 1175 assigned-clock-parents = <&k3_clks 405 6>, 1176 <&k3_clks 405 6>, 1177 <&k3_clks 405 6>; 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 #clock-cells = <1>; 1181 status = "disabled"; 1182 }; 1183 }; 1184 1185 serdes_wiz4: wiz@5050000 { 1186 compatible = "ti,j784s4-wiz-10g"; 1187 #address-cells = <1>; 1188 #size-cells = <1>; 1189 power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>; 1190 clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&serdes_refclk>, <&k3_clks 407 5>; 1191 clock-names = "fck", "core_ref_clk", "ext_ref_clk", "core_ref1_clk"; 1192 assigned-clocks = <&k3_clks 407 6>; 1193 assigned-clock-parents = <&k3_clks 407 10>; 1194 num-lanes = <4>; 1195 #reset-cells = <1>; 1196 #clock-cells = <1>; 1197 ranges = <0x05050000 0x00 0x05050000 0x10000>, 1198 <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */ 1199 status = "disabled"; 1200 1201 serdes4: serdes@5050000 { 1202 /* 1203 * Note: we also map DPTX PHY registers as the Torrent 1204 * needs to manage those. 1205 */ 1206 compatible = "ti,j721e-serdes-10g"; 1207 reg = <0x05050000 0x010000>, 1208 <0x0a030a00 0x40>; /* DPTX PHY */ 1209 reg-names = "torrent_phy"; 1210 resets = <&serdes_wiz4 0>; 1211 reset-names = "torrent_reset"; 1212 clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1213 <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>; 1214 clock-names = "refclk", "phy_en_refclk"; 1215 assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, 1216 <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, 1217 <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; 1218 assigned-clock-parents = <&k3_clks 407 6>, 1219 <&k3_clks 407 6>, 1220 <&k3_clks 407 6>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 #clock-cells = <1>; 1224 status = "disabled"; 1225 }; 1226 }; 1227 1228 main_navss: bus@30000000 { 1229 bootph-all; 1230 compatible = "simple-bus"; 1231 #address-cells = <2>; 1232 #size-cells = <2>; 1233 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 1234 ti,sci-dev-id = <280>; 1235 dma-coherent; 1236 dma-ranges; 1237 1238 main_navss_intr: interrupt-controller@310e0000 { 1239 compatible = "ti,sci-intr"; 1240 reg = <0x00 0x310e0000 0x00 0x4000>; 1241 ti,intr-trigger-type = <4>; 1242 interrupt-controller; 1243 interrupt-parent = <&gic500>; 1244 #interrupt-cells = <1>; 1245 ti,sci = <&sms>; 1246 ti,sci-dev-id = <283>; 1247 ti,interrupt-ranges = <0 64 64>, 1248 <64 448 64>, 1249 <128 672 64>; 1250 }; 1251 1252 main_udmass_inta: msi-controller@33d00000 { 1253 compatible = "ti,sci-inta"; 1254 reg = <0x00 0x33d00000 0x00 0x100000>; 1255 interrupt-controller; 1256 #interrupt-cells = <0>; 1257 interrupt-parent = <&main_navss_intr>; 1258 msi-controller; 1259 ti,sci = <&sms>; 1260 ti,sci-dev-id = <321>; 1261 ti,interrupt-ranges = <0 0 256>; 1262 ti,unmapped-event-sources = <&main_bcdma_csi>; 1263 }; 1264 1265 secure_proxy_main: mailbox@32c00000 { 1266 bootph-all; 1267 compatible = "ti,am654-secure-proxy"; 1268 #mbox-cells = <1>; 1269 reg-names = "target_data", "rt", "scfg"; 1270 reg = <0x00 0x32c00000 0x00 0x100000>, 1271 <0x00 0x32400000 0x00 0x100000>, 1272 <0x00 0x32800000 0x00 0x100000>; 1273 interrupt-names = "rx_011"; 1274 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1275 }; 1276 1277 hwspinlock: hwlock@30e00000 { 1278 compatible = "ti,am654-hwspinlock"; 1279 reg = <0x00 0x30e00000 0x00 0x1000>; 1280 #hwlock-cells = <1>; 1281 }; 1282 1283 mailbox0_cluster0: mailbox@31f80000 { 1284 compatible = "ti,am654-mailbox"; 1285 reg = <0x00 0x31f80000 0x00 0x200>; 1286 #mbox-cells = <1>; 1287 ti,mbox-num-users = <4>; 1288 ti,mbox-num-fifos = <16>; 1289 interrupt-parent = <&main_navss_intr>; 1290 status = "disabled"; 1291 }; 1292 1293 mailbox0_cluster1: mailbox@31f81000 { 1294 compatible = "ti,am654-mailbox"; 1295 reg = <0x00 0x31f81000 0x00 0x200>; 1296 #mbox-cells = <1>; 1297 ti,mbox-num-users = <4>; 1298 ti,mbox-num-fifos = <16>; 1299 interrupt-parent = <&main_navss_intr>; 1300 status = "disabled"; 1301 }; 1302 1303 mailbox0_cluster2: mailbox@31f82000 { 1304 compatible = "ti,am654-mailbox"; 1305 reg = <0x00 0x31f82000 0x00 0x200>; 1306 #mbox-cells = <1>; 1307 ti,mbox-num-users = <4>; 1308 ti,mbox-num-fifos = <16>; 1309 interrupt-parent = <&main_navss_intr>; 1310 status = "disabled"; 1311 }; 1312 1313 mailbox0_cluster3: mailbox@31f83000 { 1314 compatible = "ti,am654-mailbox"; 1315 reg = <0x00 0x31f83000 0x00 0x200>; 1316 #mbox-cells = <1>; 1317 ti,mbox-num-users = <4>; 1318 ti,mbox-num-fifos = <16>; 1319 interrupt-parent = <&main_navss_intr>; 1320 status = "disabled"; 1321 }; 1322 1323 mailbox0_cluster4: mailbox@31f84000 { 1324 compatible = "ti,am654-mailbox"; 1325 reg = <0x00 0x31f84000 0x00 0x200>; 1326 #mbox-cells = <1>; 1327 ti,mbox-num-users = <4>; 1328 ti,mbox-num-fifos = <16>; 1329 interrupt-parent = <&main_navss_intr>; 1330 status = "disabled"; 1331 }; 1332 1333 mailbox0_cluster5: mailbox@31f85000 { 1334 compatible = "ti,am654-mailbox"; 1335 reg = <0x00 0x31f85000 0x00 0x200>; 1336 #mbox-cells = <1>; 1337 ti,mbox-num-users = <4>; 1338 ti,mbox-num-fifos = <16>; 1339 interrupt-parent = <&main_navss_intr>; 1340 status = "disabled"; 1341 }; 1342 1343 mailbox0_cluster6: mailbox@31f86000 { 1344 compatible = "ti,am654-mailbox"; 1345 reg = <0x00 0x31f86000 0x00 0x200>; 1346 #mbox-cells = <1>; 1347 ti,mbox-num-users = <4>; 1348 ti,mbox-num-fifos = <16>; 1349 interrupt-parent = <&main_navss_intr>; 1350 status = "disabled"; 1351 }; 1352 1353 mailbox0_cluster7: mailbox@31f87000 { 1354 compatible = "ti,am654-mailbox"; 1355 reg = <0x00 0x31f87000 0x00 0x200>; 1356 #mbox-cells = <1>; 1357 ti,mbox-num-users = <4>; 1358 ti,mbox-num-fifos = <16>; 1359 interrupt-parent = <&main_navss_intr>; 1360 status = "disabled"; 1361 }; 1362 1363 mailbox0_cluster8: mailbox@31f88000 { 1364 compatible = "ti,am654-mailbox"; 1365 reg = <0x00 0x31f88000 0x00 0x200>; 1366 #mbox-cells = <1>; 1367 ti,mbox-num-users = <4>; 1368 ti,mbox-num-fifos = <16>; 1369 interrupt-parent = <&main_navss_intr>; 1370 status = "disabled"; 1371 }; 1372 1373 mailbox0_cluster9: mailbox@31f89000 { 1374 compatible = "ti,am654-mailbox"; 1375 reg = <0x00 0x31f89000 0x00 0x200>; 1376 #mbox-cells = <1>; 1377 ti,mbox-num-users = <4>; 1378 ti,mbox-num-fifos = <16>; 1379 interrupt-parent = <&main_navss_intr>; 1380 status = "disabled"; 1381 }; 1382 1383 mailbox0_cluster10: mailbox@31f8a000 { 1384 compatible = "ti,am654-mailbox"; 1385 reg = <0x00 0x31f8a000 0x00 0x200>; 1386 #mbox-cells = <1>; 1387 ti,mbox-num-users = <4>; 1388 ti,mbox-num-fifos = <16>; 1389 interrupt-parent = <&main_navss_intr>; 1390 status = "disabled"; 1391 }; 1392 1393 mailbox0_cluster11: mailbox@31f8b000 { 1394 compatible = "ti,am654-mailbox"; 1395 reg = <0x00 0x31f8b000 0x00 0x200>; 1396 #mbox-cells = <1>; 1397 ti,mbox-num-users = <4>; 1398 ti,mbox-num-fifos = <16>; 1399 interrupt-parent = <&main_navss_intr>; 1400 status = "disabled"; 1401 }; 1402 1403 mailbox1_cluster0: mailbox@31f90000 { 1404 compatible = "ti,am654-mailbox"; 1405 reg = <0x00 0x31f90000 0x00 0x200>; 1406 #mbox-cells = <1>; 1407 ti,mbox-num-users = <4>; 1408 ti,mbox-num-fifos = <16>; 1409 interrupt-parent = <&main_navss_intr>; 1410 status = "disabled"; 1411 }; 1412 1413 mailbox1_cluster1: mailbox@31f91000 { 1414 compatible = "ti,am654-mailbox"; 1415 reg = <0x00 0x31f91000 0x00 0x200>; 1416 #mbox-cells = <1>; 1417 ti,mbox-num-users = <4>; 1418 ti,mbox-num-fifos = <16>; 1419 interrupt-parent = <&main_navss_intr>; 1420 status = "disabled"; 1421 }; 1422 1423 mailbox1_cluster2: mailbox@31f92000 { 1424 compatible = "ti,am654-mailbox"; 1425 reg = <0x00 0x31f92000 0x00 0x200>; 1426 #mbox-cells = <1>; 1427 ti,mbox-num-users = <4>; 1428 ti,mbox-num-fifos = <16>; 1429 interrupt-parent = <&main_navss_intr>; 1430 status = "disabled"; 1431 }; 1432 1433 mailbox1_cluster3: mailbox@31f93000 { 1434 compatible = "ti,am654-mailbox"; 1435 reg = <0x00 0x31f93000 0x00 0x200>; 1436 #mbox-cells = <1>; 1437 ti,mbox-num-users = <4>; 1438 ti,mbox-num-fifos = <16>; 1439 interrupt-parent = <&main_navss_intr>; 1440 status = "disabled"; 1441 }; 1442 1443 mailbox1_cluster4: mailbox@31f94000 { 1444 compatible = "ti,am654-mailbox"; 1445 reg = <0x00 0x31f94000 0x00 0x200>; 1446 #mbox-cells = <1>; 1447 ti,mbox-num-users = <4>; 1448 ti,mbox-num-fifos = <16>; 1449 interrupt-parent = <&main_navss_intr>; 1450 status = "disabled"; 1451 }; 1452 1453 mailbox1_cluster5: mailbox@31f95000 { 1454 compatible = "ti,am654-mailbox"; 1455 reg = <0x00 0x31f95000 0x00 0x200>; 1456 #mbox-cells = <1>; 1457 ti,mbox-num-users = <4>; 1458 ti,mbox-num-fifos = <16>; 1459 interrupt-parent = <&main_navss_intr>; 1460 status = "disabled"; 1461 }; 1462 1463 mailbox1_cluster6: mailbox@31f96000 { 1464 compatible = "ti,am654-mailbox"; 1465 reg = <0x00 0x31f96000 0x00 0x200>; 1466 #mbox-cells = <1>; 1467 ti,mbox-num-users = <4>; 1468 ti,mbox-num-fifos = <16>; 1469 interrupt-parent = <&main_navss_intr>; 1470 status = "disabled"; 1471 }; 1472 1473 mailbox1_cluster7: mailbox@31f97000 { 1474 compatible = "ti,am654-mailbox"; 1475 reg = <0x00 0x31f97000 0x00 0x200>; 1476 #mbox-cells = <1>; 1477 ti,mbox-num-users = <4>; 1478 ti,mbox-num-fifos = <16>; 1479 interrupt-parent = <&main_navss_intr>; 1480 status = "disabled"; 1481 }; 1482 1483 mailbox1_cluster8: mailbox@31f98000 { 1484 compatible = "ti,am654-mailbox"; 1485 reg = <0x00 0x31f98000 0x00 0x200>; 1486 #mbox-cells = <1>; 1487 ti,mbox-num-users = <4>; 1488 ti,mbox-num-fifos = <16>; 1489 interrupt-parent = <&main_navss_intr>; 1490 status = "disabled"; 1491 }; 1492 1493 mailbox1_cluster9: mailbox@31f99000 { 1494 compatible = "ti,am654-mailbox"; 1495 reg = <0x00 0x31f99000 0x00 0x200>; 1496 #mbox-cells = <1>; 1497 ti,mbox-num-users = <4>; 1498 ti,mbox-num-fifos = <16>; 1499 interrupt-parent = <&main_navss_intr>; 1500 status = "disabled"; 1501 }; 1502 1503 mailbox1_cluster10: mailbox@31f9a000 { 1504 compatible = "ti,am654-mailbox"; 1505 reg = <0x00 0x31f9a000 0x00 0x200>; 1506 #mbox-cells = <1>; 1507 ti,mbox-num-users = <4>; 1508 ti,mbox-num-fifos = <16>; 1509 interrupt-parent = <&main_navss_intr>; 1510 status = "disabled"; 1511 }; 1512 1513 mailbox1_cluster11: mailbox@31f9b000 { 1514 compatible = "ti,am654-mailbox"; 1515 reg = <0x00 0x31f9b000 0x00 0x200>; 1516 #mbox-cells = <1>; 1517 ti,mbox-num-users = <4>; 1518 ti,mbox-num-fifos = <16>; 1519 interrupt-parent = <&main_navss_intr>; 1520 status = "disabled"; 1521 }; 1522 1523 main_ringacc: ringacc@3c000000 { 1524 compatible = "ti,am654-navss-ringacc"; 1525 reg = <0x00 0x3c000000 0x00 0x400000>, 1526 <0x00 0x38000000 0x00 0x400000>, 1527 <0x00 0x31120000 0x00 0x100>, 1528 <0x00 0x33000000 0x00 0x40000>, 1529 <0x00 0x31080000 0x00 0x40000>; 1530 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 1531 ti,num-rings = <1024>; 1532 ti,sci-rm-range-gp-rings = <0x1>; 1533 ti,sci = <&sms>; 1534 ti,sci-dev-id = <315>; 1535 msi-parent = <&main_udmass_inta>; 1536 }; 1537 1538 main_udmap: dma-controller@31150000 { 1539 compatible = "ti,j721e-navss-main-udmap"; 1540 reg = <0x00 0x31150000 0x00 0x100>, 1541 <0x00 0x34000000 0x00 0x80000>, 1542 <0x00 0x35000000 0x00 0x200000>, 1543 <0x00 0x30b00000 0x00 0x20000>, 1544 <0x00 0x30c00000 0x00 0x8000>, 1545 <0x00 0x30d00000 0x00 0x4000>; 1546 reg-names = "gcfg", "rchanrt", "tchanrt", 1547 "tchan", "rchan", "rflow"; 1548 msi-parent = <&main_udmass_inta>; 1549 #dma-cells = <1>; 1550 1551 ti,sci = <&sms>; 1552 ti,sci-dev-id = <319>; 1553 ti,ringacc = <&main_ringacc>; 1554 1555 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 1556 <0x0f>, /* TX_HCHAN */ 1557 <0x10>; /* TX_UHCHAN */ 1558 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 1559 <0x0b>, /* RX_HCHAN */ 1560 <0x0c>; /* RX_UHCHAN */ 1561 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 1562 }; 1563 1564 main_bcdma_csi: dma-controller@311a0000 { 1565 compatible = "ti,j721s2-dmss-bcdma-csi"; 1566 reg = <0x00 0x311a0000 0x00 0x100>, 1567 <0x00 0x35d00000 0x00 0x20000>, 1568 <0x00 0x35c00000 0x00 0x10000>, 1569 <0x00 0x35e00000 0x00 0x80000>; 1570 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 1571 msi-parent = <&main_udmass_inta>; 1572 #dma-cells = <3>; 1573 ti,sci = <&sms>; 1574 ti,sci-dev-id = <281>; 1575 ti,sci-rm-range-rchan = <0x21>; 1576 ti,sci-rm-range-tchan = <0x22>; 1577 }; 1578 1579 cpts@310d0000 { 1580 compatible = "ti,j721e-cpts"; 1581 reg = <0x00 0x310d0000 0x00 0x400>; 1582 reg-names = "cpts"; 1583 clocks = <&k3_clks 282 0>; 1584 clock-names = "cpts"; 1585 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 1586 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 1587 interrupts-extended = <&main_navss_intr 391>; 1588 interrupt-names = "cpts"; 1589 ti,cpts-periodic-outputs = <6>; 1590 ti,cpts-ext-ts-inputs = <8>; 1591 }; 1592 }; 1593 1594 main_cpsw0: ethernet@c000000 { 1595 compatible = "ti,j784s4-cpswxg-nuss"; 1596 reg = <0x00 0xc000000 0x00 0x200000>; 1597 reg-names = "cpsw_nuss"; 1598 ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 1599 #address-cells = <2>; 1600 #size-cells = <2>; 1601 dma-coherent; 1602 clocks = <&k3_clks 64 0>; 1603 clock-names = "fck"; 1604 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1605 1606 dmas = <&main_udmap 0xca00>, 1607 <&main_udmap 0xca01>, 1608 <&main_udmap 0xca02>, 1609 <&main_udmap 0xca03>, 1610 <&main_udmap 0xca04>, 1611 <&main_udmap 0xca05>, 1612 <&main_udmap 0xca06>, 1613 <&main_udmap 0xca07>, 1614 <&main_udmap 0x4a00>; 1615 dma-names = "tx0", "tx1", "tx2", "tx3", 1616 "tx4", "tx5", "tx6", "tx7", 1617 "rx"; 1618 1619 status = "disabled"; 1620 1621 ethernet-ports { 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 1625 main_cpsw0_port1: port@1 { 1626 reg = <1>; 1627 label = "port1"; 1628 ti,mac-only; 1629 status = "disabled"; 1630 }; 1631 1632 main_cpsw0_port2: port@2 { 1633 reg = <2>; 1634 label = "port2"; 1635 ti,mac-only; 1636 status = "disabled"; 1637 }; 1638 1639 main_cpsw0_port3: port@3 { 1640 reg = <3>; 1641 label = "port3"; 1642 ti,mac-only; 1643 status = "disabled"; 1644 }; 1645 1646 main_cpsw0_port4: port@4 { 1647 reg = <4>; 1648 label = "port4"; 1649 ti,mac-only; 1650 status = "disabled"; 1651 }; 1652 1653 main_cpsw0_port5: port@5 { 1654 reg = <5>; 1655 label = "port5"; 1656 ti,mac-only; 1657 status = "disabled"; 1658 }; 1659 1660 main_cpsw0_port6: port@6 { 1661 reg = <6>; 1662 label = "port6"; 1663 ti,mac-only; 1664 status = "disabled"; 1665 }; 1666 1667 main_cpsw0_port7: port@7 { 1668 reg = <7>; 1669 label = "port7"; 1670 ti,mac-only; 1671 status = "disabled"; 1672 }; 1673 1674 main_cpsw0_port8: port@8 { 1675 reg = <8>; 1676 label = "port8"; 1677 ti,mac-only; 1678 status = "disabled"; 1679 }; 1680 }; 1681 1682 main_cpsw0_mdio: mdio@f00 { 1683 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1684 reg = <0x00 0xf00 0x00 0x100>; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 clocks = <&k3_clks 64 0>; 1688 clock-names = "fck"; 1689 bus_freq = <1000000>; 1690 status = "disabled"; 1691 }; 1692 1693 cpts@3d000 { 1694 compatible = "ti,am65-cpts"; 1695 reg = <0x00 0x3d000 0x00 0x400>; 1696 clocks = <&k3_clks 64 3>; 1697 clock-names = "cpts"; 1698 interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1699 interrupt-names = "cpts"; 1700 ti,cpts-ext-ts-inputs = <4>; 1701 ti,cpts-periodic-outputs = <2>; 1702 }; 1703 }; 1704 1705 main_cpsw1: ethernet@c200000 { 1706 compatible = "ti,j721e-cpsw-nuss"; 1707 reg = <0x00 0xc200000 0x00 0x200000>; 1708 reg-names = "cpsw_nuss"; 1709 ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; 1710 #address-cells = <2>; 1711 #size-cells = <2>; 1712 dma-coherent; 1713 clocks = <&k3_clks 62 0>; 1714 clock-names = "fck"; 1715 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 1716 1717 dmas = <&main_udmap 0xc640>, 1718 <&main_udmap 0xc641>, 1719 <&main_udmap 0xc642>, 1720 <&main_udmap 0xc643>, 1721 <&main_udmap 0xc644>, 1722 <&main_udmap 0xc645>, 1723 <&main_udmap 0xc646>, 1724 <&main_udmap 0xc647>, 1725 <&main_udmap 0x4640>; 1726 dma-names = "tx0", "tx1", "tx2", "tx3", 1727 "tx4", "tx5", "tx6", "tx7", 1728 "rx"; 1729 1730 status = "disabled"; 1731 1732 ethernet-ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 main_cpsw1_port1: port@1 { 1737 reg = <1>; 1738 label = "port1"; 1739 phys = <&cpsw1_phy_gmii_sel 1>; 1740 ti,mac-only; 1741 status = "disabled"; 1742 }; 1743 }; 1744 1745 main_cpsw1_mdio: mdio@f00 { 1746 compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; 1747 reg = <0x00 0xf00 0x00 0x100>; 1748 #address-cells = <1>; 1749 #size-cells = <0>; 1750 clocks = <&k3_clks 62 0>; 1751 clock-names = "fck"; 1752 bus_freq = <1000000>; 1753 status = "disabled"; 1754 }; 1755 1756 cpts@3d000 { 1757 compatible = "ti,am65-cpts"; 1758 reg = <0x00 0x3d000 0x00 0x400>; 1759 clocks = <&k3_clks 62 3>; 1760 clock-names = "cpts"; 1761 interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1762 interrupt-names = "cpts"; 1763 ti,cpts-ext-ts-inputs = <4>; 1764 ti,cpts-periodic-outputs = <2>; 1765 }; 1766 }; 1767 1768 main_mcan0: can@2701000 { 1769 compatible = "bosch,m_can"; 1770 reg = <0x00 0x02701000 0x00 0x200>, 1771 <0x00 0x02708000 0x00 0x8000>; 1772 reg-names = "m_can", "message_ram"; 1773 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 1774 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 1775 clock-names = "hclk", "cclk"; 1776 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1778 interrupt-names = "int0", "int1"; 1779 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1780 status = "disabled"; 1781 }; 1782 1783 main_mcan1: can@2711000 { 1784 compatible = "bosch,m_can"; 1785 reg = <0x00 0x02711000 0x00 0x200>, 1786 <0x00 0x02718000 0x00 0x8000>; 1787 reg-names = "m_can", "message_ram"; 1788 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 1789 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 1790 clock-names = "hclk", "cclk"; 1791 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1793 interrupt-names = "int0", "int1"; 1794 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1795 status = "disabled"; 1796 }; 1797 1798 main_mcan2: can@2721000 { 1799 compatible = "bosch,m_can"; 1800 reg = <0x00 0x02721000 0x00 0x200>, 1801 <0x00 0x02728000 0x00 0x8000>; 1802 reg-names = "m_can", "message_ram"; 1803 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 1804 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 1805 clock-names = "hclk", "cclk"; 1806 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1808 interrupt-names = "int0", "int1"; 1809 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1810 status = "disabled"; 1811 }; 1812 1813 main_mcan3: can@2731000 { 1814 compatible = "bosch,m_can"; 1815 reg = <0x00 0x02731000 0x00 0x200>, 1816 <0x00 0x02738000 0x00 0x8000>; 1817 reg-names = "m_can", "message_ram"; 1818 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 1819 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 1820 clock-names = "hclk", "cclk"; 1821 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1823 interrupt-names = "int0", "int1"; 1824 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1825 status = "disabled"; 1826 }; 1827 1828 main_mcan4: can@2741000 { 1829 compatible = "bosch,m_can"; 1830 reg = <0x00 0x02741000 0x00 0x200>, 1831 <0x00 0x02748000 0x00 0x8000>; 1832 reg-names = "m_can", "message_ram"; 1833 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 1834 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 1835 clock-names = "hclk", "cclk"; 1836 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1838 interrupt-names = "int0", "int1"; 1839 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1840 status = "disabled"; 1841 }; 1842 1843 main_mcan5: can@2751000 { 1844 compatible = "bosch,m_can"; 1845 reg = <0x00 0x02751000 0x00 0x200>, 1846 <0x00 0x02758000 0x00 0x8000>; 1847 reg-names = "m_can", "message_ram"; 1848 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 1849 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 1850 clock-names = "hclk", "cclk"; 1851 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1853 interrupt-names = "int0", "int1"; 1854 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1855 status = "disabled"; 1856 }; 1857 1858 main_mcan6: can@2761000 { 1859 compatible = "bosch,m_can"; 1860 reg = <0x00 0x02761000 0x00 0x200>, 1861 <0x00 0x02768000 0x00 0x8000>; 1862 reg-names = "m_can", "message_ram"; 1863 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 1864 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 1865 clock-names = "hclk", "cclk"; 1866 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1867 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1868 interrupt-names = "int0", "int1"; 1869 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1870 status = "disabled"; 1871 }; 1872 1873 main_mcan7: can@2771000 { 1874 compatible = "bosch,m_can"; 1875 reg = <0x00 0x02771000 0x00 0x200>, 1876 <0x00 0x02778000 0x00 0x8000>; 1877 reg-names = "m_can", "message_ram"; 1878 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 1879 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 1880 clock-names = "hclk", "cclk"; 1881 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1883 interrupt-names = "int0", "int1"; 1884 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1885 status = "disabled"; 1886 }; 1887 1888 main_mcan8: can@2781000 { 1889 compatible = "bosch,m_can"; 1890 reg = <0x00 0x02781000 0x00 0x200>, 1891 <0x00 0x02788000 0x00 0x8000>; 1892 reg-names = "m_can", "message_ram"; 1893 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 1894 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 1895 clock-names = "hclk", "cclk"; 1896 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 1898 interrupt-names = "int0", "int1"; 1899 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1900 status = "disabled"; 1901 }; 1902 1903 main_mcan9: can@2791000 { 1904 compatible = "bosch,m_can"; 1905 reg = <0x00 0x02791000 0x00 0x200>, 1906 <0x00 0x02798000 0x00 0x8000>; 1907 reg-names = "m_can", "message_ram"; 1908 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 1909 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 1910 clock-names = "hclk", "cclk"; 1911 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 1913 interrupt-names = "int0", "int1"; 1914 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1915 status = "disabled"; 1916 }; 1917 1918 main_mcan10: can@27a1000 { 1919 compatible = "bosch,m_can"; 1920 reg = <0x00 0x027a1000 0x00 0x200>, 1921 <0x00 0x027a8000 0x00 0x8000>; 1922 reg-names = "m_can", "message_ram"; 1923 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 1924 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 1925 clock-names = "hclk", "cclk"; 1926 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1928 interrupt-names = "int0", "int1"; 1929 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1930 status = "disabled"; 1931 }; 1932 1933 main_mcan11: can@27b1000 { 1934 compatible = "bosch,m_can"; 1935 reg = <0x00 0x027b1000 0x00 0x200>, 1936 <0x00 0x027b8000 0x00 0x8000>; 1937 reg-names = "m_can", "message_ram"; 1938 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 1939 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 1940 clock-names = "hclk", "cclk"; 1941 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1943 interrupt-names = "int0", "int1"; 1944 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1945 status = "disabled"; 1946 }; 1947 1948 main_mcan12: can@27c1000 { 1949 compatible = "bosch,m_can"; 1950 reg = <0x00 0x027c1000 0x00 0x200>, 1951 <0x00 0x027c8000 0x00 0x8000>; 1952 reg-names = "m_can", "message_ram"; 1953 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 1954 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 1955 clock-names = "hclk", "cclk"; 1956 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1958 interrupt-names = "int0", "int1"; 1959 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1960 status = "disabled"; 1961 }; 1962 1963 main_mcan13: can@27d1000 { 1964 compatible = "bosch,m_can"; 1965 reg = <0x00 0x027d1000 0x00 0x200>, 1966 <0x00 0x027d8000 0x00 0x8000>; 1967 reg-names = "m_can", "message_ram"; 1968 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 1969 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 1970 clock-names = "hclk", "cclk"; 1971 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "int0", "int1"; 1974 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1975 status = "disabled"; 1976 }; 1977 1978 main_mcan14: can@2681000 { 1979 compatible = "bosch,m_can"; 1980 reg = <0x00 0x02681000 0x00 0x200>, 1981 <0x00 0x02688000 0x00 0x8000>; 1982 reg-names = "m_can", "message_ram"; 1983 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 1984 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 1985 clock-names = "hclk", "cclk"; 1986 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 1988 interrupt-names = "int0", "int1"; 1989 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1990 status = "disabled"; 1991 }; 1992 1993 main_mcan15: can@2691000 { 1994 compatible = "bosch,m_can"; 1995 reg = <0x00 0x02691000 0x00 0x200>, 1996 <0x00 0x02698000 0x00 0x8000>; 1997 reg-names = "m_can", "message_ram"; 1998 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 1999 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 2000 clock-names = "hclk", "cclk"; 2001 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 2003 interrupt-names = "int0", "int1"; 2004 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2005 status = "disabled"; 2006 }; 2007 2008 main_mcan16: can@26a1000 { 2009 compatible = "bosch,m_can"; 2010 reg = <0x00 0x026a1000 0x00 0x200>, 2011 <0x00 0x026a8000 0x00 0x8000>; 2012 reg-names = "m_can", "message_ram"; 2013 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 2014 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 2015 clock-names = "hclk", "cclk"; 2016 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 2017 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2018 interrupt-names = "int0", "int1"; 2019 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2020 status = "disabled"; 2021 }; 2022 2023 main_mcan17: can@26b1000 { 2024 compatible = "bosch,m_can"; 2025 reg = <0x00 0x026b1000 0x00 0x200>, 2026 <0x00 0x026b8000 0x00 0x8000>; 2027 reg-names = "m_can", "message_ram"; 2028 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 2029 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 2030 clock-names = "hclk", "cclk"; 2031 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 2033 interrupt-names = "int0", "int1"; 2034 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 2035 status = "disabled"; 2036 }; 2037 2038 main_spi0: spi@2100000 { 2039 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2040 reg = <0x00 0x02100000 0x00 0x400>; 2041 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 2045 clocks = <&k3_clks 376 0>; 2046 status = "disabled"; 2047 }; 2048 2049 main_spi1: spi@2110000 { 2050 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2051 reg = <0x00 0x02110000 0x00 0x400>; 2052 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2053 #address-cells = <1>; 2054 #size-cells = <0>; 2055 power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 2056 clocks = <&k3_clks 377 0>; 2057 status = "disabled"; 2058 }; 2059 2060 main_spi2: spi@2120000 { 2061 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2062 reg = <0x00 0x02120000 0x00 0x400>; 2063 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 2067 clocks = <&k3_clks 378 0>; 2068 status = "disabled"; 2069 }; 2070 2071 main_spi3: spi@2130000 { 2072 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2073 reg = <0x00 0x02130000 0x00 0x400>; 2074 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2075 #address-cells = <1>; 2076 #size-cells = <0>; 2077 power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 2078 clocks = <&k3_clks 379 0>; 2079 status = "disabled"; 2080 }; 2081 2082 main_spi4: spi@2140000 { 2083 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2084 reg = <0x00 0x02140000 0x00 0x400>; 2085 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2086 #address-cells = <1>; 2087 #size-cells = <0>; 2088 power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 2089 clocks = <&k3_clks 380 0>; 2090 status = "disabled"; 2091 }; 2092 2093 main_spi5: spi@2150000 { 2094 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2095 reg = <0x00 0x02150000 0x00 0x400>; 2096 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2097 #address-cells = <1>; 2098 #size-cells = <0>; 2099 power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 2100 clocks = <&k3_clks 381 0>; 2101 status = "disabled"; 2102 }; 2103 2104 main_spi6: spi@2160000 { 2105 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2106 reg = <0x00 0x02160000 0x00 0x400>; 2107 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2108 #address-cells = <1>; 2109 #size-cells = <0>; 2110 power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 2111 clocks = <&k3_clks 382 0>; 2112 status = "disabled"; 2113 }; 2114 2115 main_spi7: spi@2170000 { 2116 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2117 reg = <0x00 0x02170000 0x00 0x400>; 2118 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2119 #address-cells = <1>; 2120 #size-cells = <0>; 2121 power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 2122 clocks = <&k3_clks 383 0>; 2123 status = "disabled"; 2124 }; 2125 2126 ufs_wrapper: ufs-wrapper@4e80000 { 2127 compatible = "ti,j721e-ufs"; 2128 reg = <0x00 0x4e80000 0x00 0x100>; 2129 power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; 2130 clocks = <&k3_clks 387 3>; 2131 assigned-clocks = <&k3_clks 387 3>; 2132 assigned-clock-parents = <&k3_clks 387 6>; 2133 ranges; 2134 #address-cells = <2>; 2135 #size-cells = <2>; 2136 status = "disabled"; 2137 2138 ufs@4e84000 { 2139 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; 2140 reg = <0x00 0x4e84000 0x00 0x10000>; 2141 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2142 freq-table-hz = <250000000 250000000>, <19200000 19200000>, 2143 <19200000 19200000>; 2144 clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; 2145 clock-names = "core_clk", "phy_clk", "ref_clk"; 2146 dma-coherent; 2147 }; 2148 }; 2149 2150 main_r5fss0: r5fss@5c00000 { 2151 compatible = "ti,j721s2-r5fss"; 2152 ti,cluster-mode = <1>; 2153 #address-cells = <1>; 2154 #size-cells = <1>; 2155 ranges = <0x5c00000 0x00 0x5c00000 0x20000>, 2156 <0x5d00000 0x00 0x5d00000 0x20000>; 2157 power-domains = <&k3_pds 336 TI_SCI_PD_EXCLUSIVE>; 2158 2159 main_r5fss0_core0: r5f@5c00000 { 2160 compatible = "ti,j721s2-r5f"; 2161 reg = <0x5c00000 0x00010000>, 2162 <0x5c10000 0x00010000>; 2163 reg-names = "atcm", "btcm"; 2164 ti,sci = <&sms>; 2165 ti,sci-dev-id = <339>; 2166 ti,sci-proc-ids = <0x06 0xff>; 2167 resets = <&k3_reset 339 1>; 2168 firmware-name = "j784s4-main-r5f0_0-fw"; 2169 ti,atcm-enable = <1>; 2170 ti,btcm-enable = <1>; 2171 ti,loczrama = <1>; 2172 }; 2173 2174 main_r5fss0_core1: r5f@5d00000 { 2175 compatible = "ti,j721s2-r5f"; 2176 reg = <0x5d00000 0x00010000>, 2177 <0x5d10000 0x00010000>; 2178 reg-names = "atcm", "btcm"; 2179 ti,sci = <&sms>; 2180 ti,sci-dev-id = <340>; 2181 ti,sci-proc-ids = <0x07 0xff>; 2182 resets = <&k3_reset 340 1>; 2183 firmware-name = "j784s4-main-r5f0_1-fw"; 2184 ti,atcm-enable = <1>; 2185 ti,btcm-enable = <1>; 2186 ti,loczrama = <1>; 2187 }; 2188 }; 2189 2190 main_r5fss1: r5fss@5e00000 { 2191 compatible = "ti,j721s2-r5fss"; 2192 ti,cluster-mode = <1>; 2193 #address-cells = <1>; 2194 #size-cells = <1>; 2195 ranges = <0x5e00000 0x00 0x5e00000 0x20000>, 2196 <0x5f00000 0x00 0x5f00000 0x20000>; 2197 power-domains = <&k3_pds 337 TI_SCI_PD_EXCLUSIVE>; 2198 2199 main_r5fss1_core0: r5f@5e00000 { 2200 compatible = "ti,j721s2-r5f"; 2201 reg = <0x5e00000 0x00010000>, 2202 <0x5e10000 0x00010000>; 2203 reg-names = "atcm", "btcm"; 2204 ti,sci = <&sms>; 2205 ti,sci-dev-id = <341>; 2206 ti,sci-proc-ids = <0x08 0xff>; 2207 resets = <&k3_reset 341 1>; 2208 firmware-name = "j784s4-main-r5f1_0-fw"; 2209 ti,atcm-enable = <1>; 2210 ti,btcm-enable = <1>; 2211 ti,loczrama = <1>; 2212 }; 2213 2214 main_r5fss1_core1: r5f@5f00000 { 2215 compatible = "ti,j721s2-r5f"; 2216 reg = <0x5f00000 0x00010000>, 2217 <0x5f10000 0x00010000>; 2218 reg-names = "atcm", "btcm"; 2219 ti,sci = <&sms>; 2220 ti,sci-dev-id = <342>; 2221 ti,sci-proc-ids = <0x09 0xff>; 2222 resets = <&k3_reset 342 1>; 2223 firmware-name = "j784s4-main-r5f1_1-fw"; 2224 ti,atcm-enable = <1>; 2225 ti,btcm-enable = <1>; 2226 ti,loczrama = <1>; 2227 }; 2228 }; 2229 2230 main_r5fss2: r5fss@5900000 { 2231 compatible = "ti,j721s2-r5fss"; 2232 ti,cluster-mode = <1>; 2233 #address-cells = <1>; 2234 #size-cells = <1>; 2235 ranges = <0x5900000 0x00 0x5900000 0x20000>, 2236 <0x5a00000 0x00 0x5a00000 0x20000>; 2237 power-domains = <&k3_pds 338 TI_SCI_PD_EXCLUSIVE>; 2238 2239 main_r5fss2_core0: r5f@5900000 { 2240 compatible = "ti,j721s2-r5f"; 2241 reg = <0x5900000 0x00010000>, 2242 <0x5910000 0x00010000>; 2243 reg-names = "atcm", "btcm"; 2244 ti,sci = <&sms>; 2245 ti,sci-dev-id = <343>; 2246 ti,sci-proc-ids = <0x0a 0xff>; 2247 resets = <&k3_reset 343 1>; 2248 firmware-name = "j784s4-main-r5f2_0-fw"; 2249 ti,atcm-enable = <1>; 2250 ti,btcm-enable = <1>; 2251 ti,loczrama = <1>; 2252 }; 2253 2254 main_r5fss2_core1: r5f@5a00000 { 2255 compatible = "ti,j721s2-r5f"; 2256 reg = <0x5a00000 0x00010000>, 2257 <0x5a10000 0x00010000>; 2258 reg-names = "atcm", "btcm"; 2259 ti,sci = <&sms>; 2260 ti,sci-dev-id = <344>; 2261 ti,sci-proc-ids = <0x0b 0xff>; 2262 resets = <&k3_reset 344 1>; 2263 firmware-name = "j784s4-main-r5f2_1-fw"; 2264 ti,atcm-enable = <1>; 2265 ti,btcm-enable = <1>; 2266 ti,loczrama = <1>; 2267 }; 2268 }; 2269 2270 c71_0: dsp@64800000 { 2271 compatible = "ti,j721s2-c71-dsp"; 2272 reg = <0x00 0x64800000 0x00 0x00080000>, 2273 <0x00 0x64e00000 0x00 0x0000c000>; 2274 reg-names = "l2sram", "l1dram"; 2275 ti,sci = <&sms>; 2276 ti,sci-dev-id = <30>; 2277 ti,sci-proc-ids = <0x30 0xff>; 2278 resets = <&k3_reset 30 1>; 2279 firmware-name = "j784s4-c71_0-fw"; 2280 status = "disabled"; 2281 }; 2282 2283 c71_1: dsp@65800000 { 2284 compatible = "ti,j721s2-c71-dsp"; 2285 reg = <0x00 0x65800000 0x00 0x00080000>, 2286 <0x00 0x65e00000 0x00 0x0000c000>; 2287 reg-names = "l2sram", "l1dram"; 2288 ti,sci = <&sms>; 2289 ti,sci-dev-id = <33>; 2290 ti,sci-proc-ids = <0x31 0xff>; 2291 resets = <&k3_reset 33 1>; 2292 firmware-name = "j784s4-c71_1-fw"; 2293 status = "disabled"; 2294 }; 2295 2296 c71_2: dsp@66800000 { 2297 compatible = "ti,j721s2-c71-dsp"; 2298 reg = <0x00 0x66800000 0x00 0x00080000>, 2299 <0x00 0x66e00000 0x00 0x0000c000>; 2300 reg-names = "l2sram", "l1dram"; 2301 ti,sci = <&sms>; 2302 ti,sci-dev-id = <37>; 2303 ti,sci-proc-ids = <0x32 0xff>; 2304 resets = <&k3_reset 37 1>; 2305 firmware-name = "j784s4-c71_2-fw"; 2306 status = "disabled"; 2307 }; 2308 2309 main_esm: esm@700000 { 2310 compatible = "ti,j721e-esm"; 2311 reg = <0x00 0x700000 0x00 0x1000>; 2312 ti,esm-pins = <688>, <689>, <690>, <691>, <692>, <693>, <694>, 2313 <695>; 2314 bootph-pre-ram; 2315 }; 2316 2317 watchdog0: watchdog@2200000 { 2318 compatible = "ti,j7-rti-wdt"; 2319 reg = <0x00 0x2200000 0x00 0x100>; 2320 clocks = <&k3_clks 348 0>; 2321 power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 2322 assigned-clocks = <&k3_clks 348 0>; 2323 assigned-clock-parents = <&k3_clks 348 4>; 2324 }; 2325 2326 watchdog1: watchdog@2210000 { 2327 compatible = "ti,j7-rti-wdt"; 2328 reg = <0x00 0x2210000 0x00 0x100>; 2329 clocks = <&k3_clks 349 0>; 2330 power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 2331 assigned-clocks = <&k3_clks 349 0>; 2332 assigned-clock-parents = <&k3_clks 349 4>; 2333 }; 2334 2335 watchdog2: watchdog@2220000 { 2336 compatible = "ti,j7-rti-wdt"; 2337 reg = <0x00 0x2220000 0x00 0x100>; 2338 clocks = <&k3_clks 350 0>; 2339 power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>; 2340 assigned-clocks = <&k3_clks 350 0>; 2341 assigned-clock-parents = <&k3_clks 350 4>; 2342 }; 2343 2344 watchdog3: watchdog@2230000 { 2345 compatible = "ti,j7-rti-wdt"; 2346 reg = <0x00 0x2230000 0x00 0x100>; 2347 clocks = <&k3_clks 351 0>; 2348 power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>; 2349 assigned-clocks = <&k3_clks 351 0>; 2350 assigned-clock-parents = <&k3_clks 351 4>; 2351 }; 2352 2353 watchdog4: watchdog@2240000 { 2354 compatible = "ti,j7-rti-wdt"; 2355 reg = <0x00 0x2240000 0x00 0x100>; 2356 clocks = <&k3_clks 352 0>; 2357 power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>; 2358 assigned-clocks = <&k3_clks 352 0>; 2359 assigned-clock-parents = <&k3_clks 352 4>; 2360 }; 2361 2362 watchdog5: watchdog@2250000 { 2363 compatible = "ti,j7-rti-wdt"; 2364 reg = <0x00 0x2250000 0x00 0x100>; 2365 clocks = <&k3_clks 353 0>; 2366 power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>; 2367 assigned-clocks = <&k3_clks 353 0>; 2368 assigned-clock-parents = <&k3_clks 353 4>; 2369 }; 2370 2371 watchdog6: watchdog@2260000 { 2372 compatible = "ti,j7-rti-wdt"; 2373 reg = <0x00 0x2260000 0x00 0x100>; 2374 clocks = <&k3_clks 354 0>; 2375 power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>; 2376 assigned-clocks = <&k3_clks 354 0>; 2377 assigned-clock-parents = <&k3_clks 354 4>; 2378 }; 2379 2380 watchdog7: watchdog@2270000 { 2381 compatible = "ti,j7-rti-wdt"; 2382 reg = <0x00 0x2270000 0x00 0x100>; 2383 clocks = <&k3_clks 355 0>; 2384 power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>; 2385 assigned-clocks = <&k3_clks 355 0>; 2386 assigned-clock-parents = <&k3_clks 355 4>; 2387 }; 2388 2389 /* 2390 * The following RTI instances are coupled with MCU R5Fs, c7x and 2391 * GPU so keeping them reserved as these will be used by their 2392 * respective firmware 2393 */ 2394 watchdog8: watchdog@22f0000 { 2395 compatible = "ti,j7-rti-wdt"; 2396 reg = <0x00 0x22f0000 0x00 0x100>; 2397 clocks = <&k3_clks 360 0>; 2398 power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>; 2399 assigned-clocks = <&k3_clks 360 0>; 2400 assigned-clock-parents = <&k3_clks 360 4>; 2401 /* reserved for GPU */ 2402 status = "reserved"; 2403 }; 2404 2405 watchdog9: watchdog@2300000 { 2406 compatible = "ti,j7-rti-wdt"; 2407 reg = <0x00 0x2300000 0x00 0x100>; 2408 clocks = <&k3_clks 356 0>; 2409 power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>; 2410 assigned-clocks = <&k3_clks 356 0>; 2411 assigned-clock-parents = <&k3_clks 356 4>; 2412 /* reserved for C7X_0 DSP */ 2413 status = "reserved"; 2414 }; 2415 2416 watchdog10: watchdog@2310000 { 2417 compatible = "ti,j7-rti-wdt"; 2418 reg = <0x00 0x2310000 0x00 0x100>; 2419 clocks = <&k3_clks 357 0>; 2420 power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>; 2421 assigned-clocks = <&k3_clks 357 0>; 2422 assigned-clock-parents = <&k3_clks 357 4>; 2423 /* reserved for C7X_1 DSP */ 2424 status = "reserved"; 2425 }; 2426 2427 watchdog11: watchdog@2320000 { 2428 compatible = "ti,j7-rti-wdt"; 2429 reg = <0x00 0x2320000 0x00 0x100>; 2430 clocks = <&k3_clks 358 0>; 2431 power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>; 2432 assigned-clocks = <&k3_clks 358 0>; 2433 assigned-clock-parents = <&k3_clks 358 4>; 2434 /* reserved for C7X_2 DSP */ 2435 status = "reserved"; 2436 }; 2437 2438 watchdog12: watchdog@2330000 { 2439 compatible = "ti,j7-rti-wdt"; 2440 reg = <0x00 0x2330000 0x00 0x100>; 2441 clocks = <&k3_clks 359 0>; 2442 power-domains = <&k3_pds 359 TI_SCI_PD_EXCLUSIVE>; 2443 assigned-clocks = <&k3_clks 359 0>; 2444 assigned-clock-parents = <&k3_clks 359 4>; 2445 /* reserved for C7X_3 DSP */ 2446 status = "reserved"; 2447 }; 2448 2449 watchdog13: watchdog@23c0000 { 2450 compatible = "ti,j7-rti-wdt"; 2451 reg = <0x00 0x23c0000 0x00 0x100>; 2452 clocks = <&k3_clks 361 0>; 2453 power-domains = <&k3_pds 361 TI_SCI_PD_EXCLUSIVE>; 2454 assigned-clocks = <&k3_clks 361 0>; 2455 assigned-clock-parents = <&k3_clks 361 4>; 2456 /* reserved for MAIN_R5F0_0 */ 2457 status = "reserved"; 2458 }; 2459 2460 watchdog14: watchdog@23d0000 { 2461 compatible = "ti,j7-rti-wdt"; 2462 reg = <0x00 0x23d0000 0x00 0x100>; 2463 clocks = <&k3_clks 362 0>; 2464 power-domains = <&k3_pds 362 TI_SCI_PD_EXCLUSIVE>; 2465 assigned-clocks = <&k3_clks 362 0>; 2466 assigned-clock-parents = <&k3_clks 362 4>; 2467 /* reserved for MAIN_R5F0_1 */ 2468 status = "reserved"; 2469 }; 2470 2471 watchdog15: watchdog@23e0000 { 2472 compatible = "ti,j7-rti-wdt"; 2473 reg = <0x00 0x23e0000 0x00 0x100>; 2474 clocks = <&k3_clks 363 0>; 2475 power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>; 2476 assigned-clocks = <&k3_clks 363 0>; 2477 assigned-clock-parents = <&k3_clks 363 4>; 2478 /* reserved for MAIN_R5F1_0 */ 2479 status = "reserved"; 2480 }; 2481 2482 watchdog16: watchdog@23f0000 { 2483 compatible = "ti,j7-rti-wdt"; 2484 reg = <0x00 0x23f0000 0x00 0x100>; 2485 clocks = <&k3_clks 364 0>; 2486 power-domains = <&k3_pds 364 TI_SCI_PD_EXCLUSIVE>; 2487 assigned-clocks = <&k3_clks 364 0>; 2488 assigned-clock-parents = <&k3_clks 364 4>; 2489 /* reserved for MAIN_R5F1_1 */ 2490 status = "reserved"; 2491 }; 2492 2493 watchdog17: watchdog@2540000 { 2494 compatible = "ti,j7-rti-wdt"; 2495 reg = <0x00 0x2540000 0x00 0x100>; 2496 clocks = <&k3_clks 365 0>; 2497 power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>; 2498 assigned-clocks = <&k3_clks 365 0>; 2499 assigned-clock-parents = <&k3_clks 366 4>; 2500 /* reserved for MAIN_R5F2_0 */ 2501 status = "reserved"; 2502 }; 2503 2504 watchdog18: watchdog@2550000 { 2505 compatible = "ti,j7-rti-wdt"; 2506 reg = <0x00 0x2550000 0x00 0x100>; 2507 clocks = <&k3_clks 366 0>; 2508 power-domains = <&k3_pds 366 TI_SCI_PD_EXCLUSIVE>; 2509 assigned-clocks = <&k3_clks 366 0>; 2510 assigned-clock-parents = <&k3_clks 366 4>; 2511 /* reserved for MAIN_R5F2_1 */ 2512 status = "reserved"; 2513 }; 2514 2515 mhdp: bridge@a000000 { 2516 compatible = "ti,j721e-mhdp8546"; 2517 reg = <0x0 0xa000000 0x0 0x30a00>, 2518 <0x0 0x4f40000 0x0 0x20>; 2519 reg-names = "mhdptx", "j721e-intg"; 2520 clocks = <&k3_clks 217 11>; 2521 interrupt-parent = <&gic500>; 2522 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; 2523 power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>; 2524 status = "disabled"; 2525 2526 dp0_ports: ports { 2527 #address-cells = <1>; 2528 #size-cells = <0>; 2529 /* Remote-endpoints are on the boards so 2530 * ports are defined in the platform dt file. 2531 */ 2532 }; 2533 }; 2534 2535 dss: dss@4a00000 { 2536 compatible = "ti,j721e-dss"; 2537 reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ 2538 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ 2539 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ 2540 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ 2541 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ 2542 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ 2543 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ 2544 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ 2545 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ 2546 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ 2547 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ 2548 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ 2549 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ 2550 <0x00 0x04aa0000 0x00 0x10000>, /* vp1 */ 2551 <0x00 0x04ac0000 0x00 0x10000>, /* vp1 */ 2552 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ 2553 <0x00 0x04af0000 0x00 0x10000>; /* wb */ 2554 reg-names = "common_m", "common_s0", 2555 "common_s1", "common_s2", 2556 "vidl1", "vidl2","vid1","vid2", 2557 "ovr1", "ovr2", "ovr3", "ovr4", 2558 "vp1", "vp2", "vp3", "vp4", 2559 "wb"; 2560 clocks = <&k3_clks 218 0>, 2561 <&k3_clks 218 2>, 2562 <&k3_clks 218 5>, 2563 <&k3_clks 218 14>, 2564 <&k3_clks 218 18>; 2565 clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; 2566 power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>; 2567 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, 2570 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 2571 interrupt-names = "common_m", 2572 "common_s0", 2573 "common_s1", 2574 "common_s2"; 2575 status = "disabled"; 2576 2577 dss_ports: ports { 2578 /* Ports that DSS drives are platform specific 2579 * so they are defined in platform dt file. 2580 */ 2581 }; 2582 }; 2583 2584 mcasp0: mcasp@2b00000 { 2585 compatible = "ti,am33xx-mcasp-audio"; 2586 reg = <0x00 0x02b00000 0x00 0x2000>, 2587 <0x00 0x02b08000 0x00 0x1000>; 2588 reg-names = "mpu","dat"; 2589 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 2591 interrupt-names = "tx", "rx"; 2592 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 2593 dma-names = "tx", "rx"; 2594 clocks = <&k3_clks 265 0>; 2595 clock-names = "fck"; 2596 assigned-clocks = <&k3_clks 265 0>; 2597 assigned-clock-parents = <&k3_clks 265 1>; 2598 power-domains = <&k3_pds 265 TI_SCI_PD_EXCLUSIVE>; 2599 status = "disabled"; 2600 }; 2601 2602 mcasp1: mcasp@2b10000 { 2603 compatible = "ti,am33xx-mcasp-audio"; 2604 reg = <0x00 0x02b10000 0x00 0x2000>, 2605 <0x00 0x02b18000 0x00 0x1000>; 2606 reg-names = "mpu","dat"; 2607 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 2609 interrupt-names = "tx", "rx"; 2610 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 2611 dma-names = "tx", "rx"; 2612 clocks = <&k3_clks 266 0>; 2613 clock-names = "fck"; 2614 assigned-clocks = <&k3_clks 266 0>; 2615 assigned-clock-parents = <&k3_clks 266 1>; 2616 power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2617 status = "disabled"; 2618 }; 2619 2620 mcasp2: mcasp@2b20000 { 2621 compatible = "ti,am33xx-mcasp-audio"; 2622 reg = <0x00 0x02b20000 0x00 0x2000>, 2623 <0x00 0x02b28000 0x00 0x1000>; 2624 reg-names = "mpu","dat"; 2625 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 2627 interrupt-names = "tx", "rx"; 2628 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 2629 dma-names = "tx", "rx"; 2630 clocks = <&k3_clks 267 0>; 2631 clock-names = "fck"; 2632 assigned-clocks = <&k3_clks 267 0>; 2633 assigned-clock-parents = <&k3_clks 267 1>; 2634 power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2635 status = "disabled"; 2636 }; 2637 2638 mcasp3: mcasp@2b30000 { 2639 compatible = "ti,am33xx-mcasp-audio"; 2640 reg = <0x00 0x02b30000 0x00 0x2000>, 2641 <0x00 0x02b38000 0x00 0x1000>; 2642 reg-names = "mpu","dat"; 2643 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 2644 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 2645 interrupt-names = "tx", "rx"; 2646 dmas = <&main_udmap 0xc403>, <&main_udmap 0x4403>; 2647 dma-names = "tx", "rx"; 2648 clocks = <&k3_clks 268 0>; 2649 clock-names = "fck"; 2650 assigned-clocks = <&k3_clks 268 0>; 2651 assigned-clock-parents = <&k3_clks 268 1>; 2652 power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2653 status = "disabled"; 2654 }; 2655 2656 mcasp4: mcasp@2b40000 { 2657 compatible = "ti,am33xx-mcasp-audio"; 2658 reg = <0x00 0x02b40000 0x00 0x2000>, 2659 <0x00 0x02b48000 0x00 0x1000>; 2660 reg-names = "mpu","dat"; 2661 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 2663 interrupt-names = "tx", "rx"; 2664 dmas = <&main_udmap 0xc404>, <&main_udmap 0x4404>; 2665 dma-names = "tx", "rx"; 2666 clocks = <&k3_clks 269 0>; 2667 clock-names = "fck"; 2668 assigned-clocks = <&k3_clks 269 0>; 2669 assigned-clock-parents = <&k3_clks 269 1>; 2670 power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2671 status = "disabled"; 2672 }; 2673}; 2674