1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 6 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 7 */ 8/ { 9 chosen { 10 stdout-path = "serial2:115200n8"; 11 }; 12 13 aliases { 14 serial0 = &wkup_uart0; 15 serial1 = &mcu_uart0; 16 serial2 = &main_uart8; 17 mmc0 = &main_sdhci0; 18 mmc1 = &main_sdhci1; 19 i2c0 = &wkup_i2c0; 20 i2c3 = &main_i2c0; 21 ethernet0 = &mcu_cpsw_port1; 22 ethernet1 = &main_cpsw1_port1; 23 }; 24 25 reserved_memory: reserved-memory { 26 #address-cells = <2>; 27 #size-cells = <2>; 28 ranges; 29 30 secure_ddr: optee@9e800000 { 31 reg = <0x00 0x9e800000 0x00 0x01800000>; 32 no-map; 33 }; 34 35 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 36 compatible = "shared-dma-pool"; 37 reg = <0x00 0xa0000000 0x00 0x100000>; 38 no-map; 39 }; 40 41 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa0100000 0x00 0xf00000>; 44 no-map; 45 }; 46 47 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa1000000 0x00 0x100000>; 50 no-map; 51 }; 52 53 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa1100000 0x00 0xf00000>; 56 no-map; 57 }; 58 59 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa2000000 0x00 0x100000>; 62 no-map; 63 }; 64 65 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa2100000 0x00 0xf00000>; 68 no-map; 69 }; 70 71 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa3000000 0x00 0x100000>; 74 no-map; 75 }; 76 77 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa3100000 0x00 0xf00000>; 80 no-map; 81 }; 82 83 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa4000000 0x00 0x100000>; 86 no-map; 87 }; 88 89 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 90 compatible = "shared-dma-pool"; 91 reg = <0x00 0xa4100000 0x00 0xf00000>; 92 no-map; 93 }; 94 95 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 96 compatible = "shared-dma-pool"; 97 reg = <0x00 0xa5000000 0x00 0x100000>; 98 no-map; 99 }; 100 101 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 102 compatible = "shared-dma-pool"; 103 reg = <0x00 0xa5100000 0x00 0xf00000>; 104 no-map; 105 }; 106 107 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 108 compatible = "shared-dma-pool"; 109 reg = <0x00 0xa6000000 0x00 0x100000>; 110 no-map; 111 }; 112 113 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 114 compatible = "shared-dma-pool"; 115 reg = <0x00 0xa6100000 0x00 0xf00000>; 116 no-map; 117 }; 118 119 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 120 compatible = "shared-dma-pool"; 121 reg = <0x00 0xa7000000 0x00 0x100000>; 122 no-map; 123 }; 124 125 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 126 compatible = "shared-dma-pool"; 127 reg = <0x00 0xa7100000 0x00 0xf00000>; 128 no-map; 129 }; 130 131 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 132 compatible = "shared-dma-pool"; 133 reg = <0x00 0xa8000000 0x00 0x100000>; 134 no-map; 135 }; 136 137 c71_0_memory_region: c71-memory@a8100000 { 138 compatible = "shared-dma-pool"; 139 reg = <0x00 0xa8100000 0x00 0xf00000>; 140 no-map; 141 }; 142 143 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 144 compatible = "shared-dma-pool"; 145 reg = <0x00 0xa9000000 0x00 0x100000>; 146 no-map; 147 }; 148 149 c71_1_memory_region: c71-memory@a9100000 { 150 compatible = "shared-dma-pool"; 151 reg = <0x00 0xa9100000 0x00 0xf00000>; 152 no-map; 153 }; 154 155 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 156 compatible = "shared-dma-pool"; 157 reg = <0x00 0xaa000000 0x00 0x100000>; 158 no-map; 159 }; 160 161 c71_2_memory_region: c71-memory@aa100000 { 162 compatible = "shared-dma-pool"; 163 reg = <0x00 0xaa100000 0x00 0xf00000>; 164 no-map; 165 }; 166 }; 167 168 evm_12v0: regulator-evm12v0 { 169 /* main supply */ 170 compatible = "regulator-fixed"; 171 regulator-name = "evm_12v0"; 172 regulator-min-microvolt = <12000000>; 173 regulator-max-microvolt = <12000000>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 vsys_3v3: regulator-vsys3v3 { 179 /* Output of LM5140 */ 180 compatible = "regulator-fixed"; 181 regulator-name = "vsys_3v3"; 182 regulator-min-microvolt = <3300000>; 183 regulator-max-microvolt = <3300000>; 184 vin-supply = <&evm_12v0>; 185 regulator-always-on; 186 regulator-boot-on; 187 }; 188 189 vsys_5v0: regulator-vsys5v0 { 190 /* Output of LM5140 */ 191 compatible = "regulator-fixed"; 192 regulator-name = "vsys_5v0"; 193 regulator-min-microvolt = <5000000>; 194 regulator-max-microvolt = <5000000>; 195 vin-supply = <&evm_12v0>; 196 regulator-always-on; 197 regulator-boot-on; 198 }; 199 200 vdd_mmc1: regulator-sd { 201 /* Output of TPS22918 */ 202 compatible = "regulator-fixed"; 203 regulator-name = "vdd_mmc1"; 204 regulator-min-microvolt = <3300000>; 205 regulator-max-microvolt = <3300000>; 206 regulator-boot-on; 207 enable-active-high; 208 vin-supply = <&vsys_3v3>; 209 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 210 }; 211 212 vdd_sd_dv: regulator-TLV71033 { 213 /* Output of TLV71033 */ 214 compatible = "regulator-gpio"; 215 regulator-name = "tlv71033"; 216 pinctrl-names = "default"; 217 pinctrl-0 = <&vdd_sd_dv_pins_default>; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <3300000>; 220 regulator-boot-on; 221 vin-supply = <&vsys_5v0>; 222 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 223 states = <1800000 0x0>, 224 <3300000 0x1>; 225 }; 226 227 dp0_pwr_3v3: regulator-dp0-prw { 228 compatible = "regulator-fixed"; 229 regulator-name = "dp0-pwr"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 233 enable-active-high; 234 }; 235 236 dp0: connector-dp0 { 237 compatible = "dp-connector"; 238 label = "DP0"; 239 type = "full-size"; 240 dp-pwr-supply = <&dp0_pwr_3v3>; 241 242 port { 243 dp0_connector_in: endpoint { 244 remote-endpoint = <&dp0_out>; 245 }; 246 }; 247 }; 248 249 transceiver0: can-phy0 { 250 compatible = "ti,tcan1042"; 251 #phy-cells = <0>; 252 max-bitrate = <5000000>; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 255 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; 256 }; 257 258 transceiver1: can-phy1 { 259 compatible = "ti,tcan1042"; 260 #phy-cells = <0>; 261 max-bitrate = <5000000>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 264 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 265 }; 266 267 transceiver2: can-phy2 { 268 /* standby pin has been grounded by default */ 269 compatible = "ti,tcan1042"; 270 #phy-cells = <0>; 271 max-bitrate = <5000000>; 272 }; 273 274 transceiver3: can-phy3 { 275 compatible = "ti,tcan1042"; 276 #phy-cells = <0>; 277 max-bitrate = <5000000>; 278 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 279 mux-states = <&mux1 1>; 280 }; 281 282 mux1: mux-controller { 283 compatible = "gpio-mux"; 284 #mux-state-cells = <1>; 285 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; 286 idle-state = <1>; 287 }; 288 289 codec_audio: sound { 290 compatible = "ti,j7200-cpb-audio"; 291 model = "j784s4-cpb"; 292 293 ti,cpb-mcasp = <&mcasp0>; 294 ti,cpb-codec = <&pcm3168a_1>; 295 296 clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, 297 <&k3_clks 157 34>, <&k3_clks 157 63>; 298 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", 299 "cpb-codec-scki", "cpb-codec-scki-48000"; 300 }; 301}; 302 303&wkup_gpio0 { 304 status = "okay"; 305}; 306 307&main_pmx0 { 308 main_cpsw2g_default_pins: main-cpsw2g-default-pins { 309 pinctrl-single,pins = < 310 J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ 311 J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ 312 J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ 313 J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ 314 J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ 315 J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ 316 J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ 317 J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ 318 J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ 319 J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ 320 J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ 321 J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ 322 >; 323 }; 324 325 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { 326 pinctrl-single,pins = < 327 J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ 328 J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ 329 >; 330 }; 331 332 main_uart8_pins_default: main-uart8-default-pins { 333 bootph-all; 334 pinctrl-single,pins = < 335 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 336 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 337 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 338 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 339 >; 340 }; 341 342 main_i2c0_pins_default: main-i2c0-default-pins { 343 pinctrl-single,pins = < 344 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 345 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 346 >; 347 }; 348 349 main_i2c5_pins_default: main-i2c5-default-pins { 350 pinctrl-single,pins = < 351 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ 352 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ 353 >; 354 }; 355 356 main_mmc1_pins_default: main-mmc1-default-pins { 357 bootph-all; 358 pinctrl-single,pins = < 359 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 360 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 361 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 362 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 363 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 364 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 365 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 366 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 367 >; 368 }; 369 370 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 371 pinctrl-single,pins = < 372 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 373 >; 374 }; 375 376 dp0_pins_default: dp0-default-pins { 377 pinctrl-single,pins = < 378 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 379 >; 380 }; 381 382 main_i2c4_pins_default: main-i2c4-default-pins { 383 pinctrl-single,pins = < 384 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 385 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 386 >; 387 }; 388 389 main_mcan4_pins_default: main-mcan4-default-pins { 390 pinctrl-single,pins = < 391 J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ 392 J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ 393 >; 394 }; 395 396 main_mcan16_pins_default: main-mcan16-default-pins { 397 pinctrl-single,pins = < 398 J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ 399 J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ 400 >; 401 }; 402 403 main_usbss0_pins_default: main-usbss0-default-pins { 404 bootph-all; 405 pinctrl-single,pins = < 406 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 407 >; 408 }; 409 410 main_i2c3_pins_default: main-i2c3-default-pins { 411 pinctrl-single,pins = < 412 J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ 413 J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ 414 >; 415 }; 416 417 main_mcasp0_pins_default: main-mcasp0-default-pins { 418 pinctrl-single,pins = < 419 J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ 420 J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ 421 J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ 422 J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ 423 >; 424 }; 425 426 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 427 pinctrl-single,pins = < 428 J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ 429 >; 430 }; 431}; 432 433&wkup_pmx2 { 434 wkup_uart0_pins_default: wkup-uart0-default-pins { 435 bootph-all; 436 pinctrl-single,pins = < 437 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 438 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 439 >; 440 }; 441 442 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 443 bootph-all; 444 pinctrl-single,pins = < 445 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 446 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 447 >; 448 }; 449 450 mcu_uart0_pins_default: mcu-uart0-default-pins { 451 bootph-all; 452 pinctrl-single,pins = < 453 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 454 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 455 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 456 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 457 >; 458 }; 459 460 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 461 pinctrl-single,pins = < 462 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 463 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 464 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 465 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 466 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 467 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 468 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 469 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 470 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 471 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 472 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 473 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 474 >; 475 }; 476 477 mcu_mdio_pins_default: mcu-mdio-default-pins { 478 pinctrl-single,pins = < 479 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 480 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 481 >; 482 }; 483 484 mcu_adc0_pins_default: mcu-adc0-default-pins { 485 pinctrl-single,pins = < 486 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 487 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 488 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 489 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 490 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 491 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 492 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 493 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 494 >; 495 }; 496 497 mcu_adc1_pins_default: mcu-adc1-default-pins { 498 pinctrl-single,pins = < 499 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 500 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 501 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 502 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 503 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 504 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 505 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 506 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 507 >; 508 }; 509 510 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 511 pinctrl-single,pins = < 512 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 513 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 514 >; 515 }; 516 517 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 518 pinctrl-single,pins = < 519 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 520 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 521 >; 522 }; 523 524 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 525 pinctrl-single,pins = < 526 J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ 527 >; 528 }; 529 530 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 531 pinctrl-single,pins = < 532 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 533 >; 534 }; 535}; 536 537&wkup_pmx1 { 538 status = "okay"; 539 540 pmic_irq_pins_default: pmic-irq-default-pins { 541 pinctrl-single,pins = < 542 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 543 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 544 >; 545 }; 546}; 547 548&wkup_pmx0 { 549 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 550 bootph-all; 551 pinctrl-single,pins = < 552 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 553 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 554 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 555 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 556 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 557 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 558 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 559 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 560 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 561 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 562 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 563 >; 564 }; 565}; 566 567&wkup_pmx1 { 568 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 569 bootph-all; 570 pinctrl-single,pins = < 571 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 572 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 573 >; 574 }; 575 576 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 577 bootph-all; 578 pinctrl-single,pins = < 579 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 580 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 581 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 582 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 583 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 584 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 585 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 586 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 587 >; 588 }; 589}; 590 591&wkup_uart0 { 592 /* Firmware usage */ 593 status = "reserved"; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&wkup_uart0_pins_default>; 596}; 597 598&wkup_i2c0 { 599 bootph-all; 600 status = "okay"; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&wkup_i2c0_pins_default>; 603 clock-frequency = <400000>; 604 605 eeprom@50 { 606 /* CAV24C256WE-GT3 */ 607 compatible = "atmel,24c256"; 608 reg = <0x50>; 609 }; 610 611 tps659413: pmic@48 { 612 compatible = "ti,tps6594-q1"; 613 reg = <0x48>; 614 system-power-controller; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pmic_irq_pins_default>; 617 interrupt-parent = <&wkup_gpio0>; 618 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 ti,primary-pmic; 622 buck12-supply = <&vsys_3v3>; 623 buck3-supply = <&vsys_3v3>; 624 buck4-supply = <&vsys_3v3>; 625 buck5-supply = <&vsys_3v3>; 626 ldo1-supply = <&vsys_3v3>; 627 ldo2-supply = <&vsys_3v3>; 628 ldo3-supply = <&vsys_3v3>; 629 ldo4-supply = <&vsys_3v3>; 630 631 regulators { 632 bucka12: buck12 { 633 regulator-name = "vdd_ddr_1v1"; 634 regulator-min-microvolt = <1100000>; 635 regulator-max-microvolt = <1100000>; 636 regulator-boot-on; 637 regulator-always-on; 638 bootph-all; 639 }; 640 641 bucka3: buck3 { 642 regulator-name = "vdd_ram_0v85"; 643 regulator-min-microvolt = <850000>; 644 regulator-max-microvolt = <850000>; 645 regulator-boot-on; 646 regulator-always-on; 647 bootph-all; 648 }; 649 650 bucka4: buck4 { 651 regulator-name = "vdd_io_1v8"; 652 regulator-min-microvolt = <1800000>; 653 regulator-max-microvolt = <1800000>; 654 regulator-boot-on; 655 regulator-always-on; 656 bootph-all; 657 }; 658 659 bucka5: buck5 { 660 regulator-name = "vdd_mcu_0v85"; 661 regulator-min-microvolt = <850000>; 662 regulator-max-microvolt = <850000>; 663 regulator-boot-on; 664 regulator-always-on; 665 bootph-all; 666 }; 667 668 ldoa1: ldo1 { 669 regulator-name = "vdd_mcuio_1v8"; 670 regulator-min-microvolt = <1800000>; 671 regulator-max-microvolt = <1800000>; 672 regulator-boot-on; 673 regulator-always-on; 674 bootph-all; 675 }; 676 677 ldoa2: ldo2 { 678 regulator-name = "vdd_mcuio_3v3"; 679 regulator-min-microvolt = <3300000>; 680 regulator-max-microvolt = <3300000>; 681 regulator-boot-on; 682 regulator-always-on; 683 bootph-all; 684 }; 685 686 ldoa3: ldo3 { 687 regulator-name = "vds_dll_0v8"; 688 regulator-min-microvolt = <800000>; 689 regulator-max-microvolt = <800000>; 690 regulator-boot-on; 691 regulator-always-on; 692 bootph-all; 693 }; 694 695 ldoa4: ldo4 { 696 regulator-name = "vda_mcu_1v8"; 697 regulator-min-microvolt = <1800000>; 698 regulator-max-microvolt = <1800000>; 699 regulator-boot-on; 700 regulator-always-on; 701 bootph-all; 702 }; 703 }; 704 }; 705 706 tps62873a: regulator@40 { 707 compatible = "ti,tps62873"; 708 reg = <0x40>; 709 bootph-pre-ram; 710 regulator-name = "VDD_CPU_AVS"; 711 regulator-min-microvolt = <750000>; 712 regulator-max-microvolt = <1330000>; 713 regulator-boot-on; 714 regulator-always-on; 715 }; 716 717 tps62873b: regulator@43 { 718 compatible = "ti,tps62873"; 719 reg = <0x43>; 720 regulator-name = "VDD_CORE_0V8"; 721 regulator-min-microvolt = <760000>; 722 regulator-max-microvolt = <840000>; 723 regulator-boot-on; 724 regulator-always-on; 725 }; 726}; 727 728&mcu_uart0 { 729 bootph-all; 730 status = "okay"; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&mcu_uart0_pins_default>; 733}; 734 735&main_uart8 { 736 bootph-all; 737 status = "okay"; 738 pinctrl-names = "default"; 739 pinctrl-0 = <&main_uart8_pins_default>; 740}; 741 742&ufs_wrapper { 743 status = "okay"; 744}; 745 746&fss { 747 status = "okay"; 748}; 749 750&ospi0 { 751 status = "okay"; 752 pinctrl-names = "default"; 753 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 754 755 flash@0 { 756 compatible = "jedec,spi-nor"; 757 reg = <0x0>; 758 spi-tx-bus-width = <8>; 759 spi-rx-bus-width = <8>; 760 spi-max-frequency = <25000000>; 761 cdns,tshsl-ns = <60>; 762 cdns,tsd2d-ns = <60>; 763 cdns,tchsh-ns = <60>; 764 cdns,tslch-ns = <60>; 765 cdns,read-delay = <4>; 766 767 partitions { 768 compatible = "fixed-partitions"; 769 #address-cells = <1>; 770 #size-cells = <1>; 771 772 partition@0 { 773 label = "ospi.tiboot3"; 774 reg = <0x0 0x80000>; 775 }; 776 777 partition@80000 { 778 label = "ospi.tispl"; 779 reg = <0x80000 0x200000>; 780 }; 781 782 partition@280000 { 783 label = "ospi.u-boot"; 784 reg = <0x280000 0x400000>; 785 }; 786 787 partition@680000 { 788 label = "ospi.env"; 789 reg = <0x680000 0x40000>; 790 }; 791 792 partition@6c0000 { 793 label = "ospi.env.backup"; 794 reg = <0x6c0000 0x40000>; 795 }; 796 797 partition@800000 { 798 label = "ospi.rootfs"; 799 reg = <0x800000 0x37c0000>; 800 }; 801 802 partition@3fc0000 { 803 bootph-all; 804 label = "ospi.phypattern"; 805 reg = <0x3fc0000 0x40000>; 806 }; 807 }; 808 }; 809}; 810 811&ospi1 { 812 status = "okay"; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 815 816 flash@0 { 817 compatible = "jedec,spi-nor"; 818 reg = <0x0>; 819 spi-tx-bus-width = <1>; 820 spi-rx-bus-width = <4>; 821 spi-max-frequency = <40000000>; 822 cdns,tshsl-ns = <60>; 823 cdns,tsd2d-ns = <60>; 824 cdns,tchsh-ns = <60>; 825 cdns,tslch-ns = <60>; 826 cdns,read-delay = <2>; 827 828 partitions { 829 compatible = "fixed-partitions"; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 833 partition@0 { 834 label = "qspi.tiboot3"; 835 reg = <0x0 0x80000>; 836 }; 837 838 partition@80000 { 839 label = "qspi.tispl"; 840 reg = <0x80000 0x200000>; 841 }; 842 843 partition@280000 { 844 label = "qspi.u-boot"; 845 reg = <0x280000 0x400000>; 846 }; 847 848 partition@680000 { 849 label = "qspi.env"; 850 reg = <0x680000 0x40000>; 851 }; 852 853 partition@6c0000 { 854 label = "qspi.env.backup"; 855 reg = <0x6c0000 0x40000>; 856 }; 857 858 partition@800000 { 859 label = "qspi.rootfs"; 860 reg = <0x800000 0x37c0000>; 861 }; 862 863 partition@3fc0000 { 864 bootph-all; 865 label = "qspi.phypattern"; 866 reg = <0x3fc0000 0x40000>; 867 }; 868 }; 869 870 }; 871}; 872 873&main_i2c0 { 874 status = "okay"; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&main_i2c0_pins_default>; 877 878 clock-frequency = <400000>; 879 880 exp1: gpio@20 { 881 compatible = "ti,tca6416"; 882 reg = <0x20>; 883 gpio-controller; 884 #gpio-cells = <2>; 885 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 886 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 887 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 888 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 889 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 890 891 p12-hog { 892 /* P12 - AUDIO_MUX_SEL */ 893 gpio-hog; 894 gpios = <12 GPIO_ACTIVE_HIGH>; 895 output-low; 896 line-name = "AUDIO_MUX_SEL"; 897 }; 898 }; 899 900 exp2: gpio@22 { 901 compatible = "ti,tca6424"; 902 reg = <0x22>; 903 gpio-controller; 904 #gpio-cells = <2>; 905 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 906 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 907 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 908 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 909 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 910 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 911 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 912 "USER_INPUT1", "USER_LED1", "USER_LED2"; 913 914 p13-hog { 915 /* P13 - CANUART_MUX_SEL0 */ 916 gpio-hog; 917 gpios = <13 GPIO_ACTIVE_HIGH>; 918 output-high; 919 line-name = "CANUART_MUX_SEL0"; 920 }; 921 922 p15-hog { 923 /* P15 - CANUART_MUX1_SEL1 */ 924 gpio-hog; 925 gpios = <15 GPIO_ACTIVE_HIGH>; 926 output-high; 927 line-name = "CANUART_MUX1_SEL1"; 928 }; 929 }; 930}; 931 932&main_i2c5 { 933 pinctrl-names = "default"; 934 pinctrl-0 = <&main_i2c5_pins_default>; 935 clock-frequency = <400000>; 936 status = "okay"; 937 938 exp5: gpio@20 { 939 compatible = "ti,tca6408"; 940 reg = <0x20>; 941 gpio-controller; 942 #gpio-cells = <2>; 943 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 944 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", 945 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 946 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 947 }; 948}; 949 950&main_sdhci0 { 951 bootph-all; 952 /* eMMC */ 953 status = "okay"; 954 non-removable; 955 ti,driver-strength-ohm = <50>; 956 disable-wp; 957}; 958 959&main_sdhci1 { 960 bootph-all; 961 /* SD card */ 962 status = "okay"; 963 pinctrl-0 = <&main_mmc1_pins_default>; 964 pinctrl-names = "default"; 965 disable-wp; 966 vmmc-supply = <&vdd_mmc1>; 967 vqmmc-supply = <&vdd_sd_dv>; 968}; 969 970&main_gpio0 { 971 status = "okay"; 972}; 973 974&mcu_cpsw { 975 status = "okay"; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&mcu_cpsw_pins_default>; 978}; 979 980&davinci_mdio { 981 pinctrl-names = "default"; 982 pinctrl-0 = <&mcu_mdio_pins_default>; 983 984 mcu_phy0: ethernet-phy@0 { 985 reg = <0>; 986 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 987 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 988 ti,min-output-impedance; 989 }; 990}; 991 992&mcu_cpsw_port1 { 993 status = "okay"; 994 phy-mode = "rgmii-rxid"; 995 phy-handle = <&mcu_phy0>; 996}; 997 998&main_cpsw1 { 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&main_cpsw2g_default_pins>; 1001 status = "okay"; 1002}; 1003 1004&main_cpsw1_mdio { 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; 1007 status = "okay"; 1008 1009 main_cpsw1_phy0: ethernet-phy@0 { 1010 reg = <0>; 1011 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1012 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1013 ti,min-output-impedance; 1014 }; 1015}; 1016 1017&main_cpsw1_port1 { 1018 phy-mode = "rgmii-rxid"; 1019 phy-handle = <&main_cpsw1_phy0>; 1020 status = "okay"; 1021}; 1022 1023&mailbox0_cluster0 { 1024 status = "okay"; 1025 interrupts = <436>; 1026 1027 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1028 ti,mbox-rx = <0 0 0>; 1029 ti,mbox-tx = <1 0 0>; 1030 }; 1031 1032 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1033 ti,mbox-rx = <2 0 0>; 1034 ti,mbox-tx = <3 0 0>; 1035 }; 1036}; 1037 1038&mailbox0_cluster1 { 1039 status = "okay"; 1040 interrupts = <432>; 1041 1042 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1043 ti,mbox-rx = <0 0 0>; 1044 ti,mbox-tx = <1 0 0>; 1045 }; 1046 1047 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1048 ti,mbox-rx = <2 0 0>; 1049 ti,mbox-tx = <3 0 0>; 1050 }; 1051}; 1052 1053&mailbox0_cluster2 { 1054 status = "okay"; 1055 interrupts = <428>; 1056 1057 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1058 ti,mbox-rx = <0 0 0>; 1059 ti,mbox-tx = <1 0 0>; 1060 }; 1061 1062 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1063 ti,mbox-rx = <2 0 0>; 1064 ti,mbox-tx = <3 0 0>; 1065 }; 1066}; 1067 1068&mailbox0_cluster3 { 1069 status = "okay"; 1070 interrupts = <424>; 1071 1072 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 1073 ti,mbox-rx = <0 0 0>; 1074 ti,mbox-tx = <1 0 0>; 1075 }; 1076 1077 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 1078 ti,mbox-rx = <2 0 0>; 1079 ti,mbox-tx = <3 0 0>; 1080 }; 1081}; 1082 1083&mailbox0_cluster4 { 1084 status = "okay"; 1085 interrupts = <420>; 1086 1087 mbox_c71_0: mbox-c71-0 { 1088 ti,mbox-rx = <0 0 0>; 1089 ti,mbox-tx = <1 0 0>; 1090 }; 1091 1092 mbox_c71_1: mbox-c71-1 { 1093 ti,mbox-rx = <2 0 0>; 1094 ti,mbox-tx = <3 0 0>; 1095 }; 1096}; 1097 1098&mailbox0_cluster5 { 1099 status = "okay"; 1100 interrupts = <416>; 1101 1102 mbox_c71_2: mbox-c71-2 { 1103 ti,mbox-rx = <0 0 0>; 1104 ti,mbox-tx = <1 0 0>; 1105 }; 1106}; 1107 1108&mcu_r5fss0_core0 { 1109 status = "okay"; 1110 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1111 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1112 <&mcu_r5fss0_core0_memory_region>; 1113}; 1114 1115&mcu_r5fss0_core1 { 1116 status = "okay"; 1117 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1118 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1119 <&mcu_r5fss0_core1_memory_region>; 1120}; 1121 1122&main_r5fss0 { 1123 ti,cluster-mode = <0>; 1124}; 1125 1126&main_r5fss1 { 1127 ti,cluster-mode = <0>; 1128}; 1129 1130&main_r5fss2 { 1131 ti,cluster-mode = <0>; 1132}; 1133 1134/* Timers are used by Remoteproc firmware */ 1135&main_timer0 { 1136 status = "reserved"; 1137}; 1138 1139&main_timer1 { 1140 status = "reserved"; 1141}; 1142 1143&main_timer2 { 1144 status = "reserved"; 1145}; 1146 1147&main_timer3 { 1148 status = "reserved"; 1149}; 1150 1151&main_timer4 { 1152 status = "reserved"; 1153}; 1154 1155&main_timer5 { 1156 status = "reserved"; 1157}; 1158 1159&main_timer6 { 1160 status = "reserved"; 1161}; 1162 1163&main_timer7 { 1164 status = "reserved"; 1165}; 1166 1167&main_timer8 { 1168 status = "reserved"; 1169}; 1170 1171&main_timer9 { 1172 status = "reserved"; 1173}; 1174 1175&main_r5fss0_core0 { 1176 status = "okay"; 1177 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1178 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1179 <&main_r5fss0_core0_memory_region>; 1180}; 1181 1182&main_r5fss0_core1 { 1183 status = "okay"; 1184 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1185 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1186 <&main_r5fss0_core1_memory_region>; 1187}; 1188 1189&main_r5fss1_core0 { 1190 status = "okay"; 1191 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1192 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1193 <&main_r5fss1_core0_memory_region>; 1194}; 1195 1196&main_r5fss1_core1 { 1197 status = "okay"; 1198 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1199 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1200 <&main_r5fss1_core1_memory_region>; 1201}; 1202 1203&main_r5fss2_core0 { 1204 status = "okay"; 1205 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1206 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1207 <&main_r5fss2_core0_memory_region>; 1208}; 1209 1210&main_r5fss2_core1 { 1211 status = "okay"; 1212 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1213 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1214 <&main_r5fss2_core1_memory_region>; 1215}; 1216 1217&c71_0 { 1218 status = "okay"; 1219 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1220 memory-region = <&c71_0_dma_memory_region>, 1221 <&c71_0_memory_region>; 1222}; 1223 1224&c71_1 { 1225 status = "okay"; 1226 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1227 memory-region = <&c71_1_dma_memory_region>, 1228 <&c71_1_memory_region>; 1229}; 1230 1231&c71_2 { 1232 status = "okay"; 1233 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1234 memory-region = <&c71_2_dma_memory_region>, 1235 <&c71_2_memory_region>; 1236}; 1237 1238&tscadc0 { 1239 pinctrl-0 = <&mcu_adc0_pins_default>; 1240 pinctrl-names = "default"; 1241 status = "okay"; 1242 adc { 1243 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1244 }; 1245}; 1246 1247&tscadc1 { 1248 pinctrl-0 = <&mcu_adc1_pins_default>; 1249 pinctrl-names = "default"; 1250 status = "okay"; 1251 adc { 1252 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1253 }; 1254}; 1255 1256&serdes_refclk { 1257 status = "okay"; 1258 clock-frequency = <100000000>; 1259}; 1260 1261&dss { 1262 status = "okay"; 1263 assigned-clocks = <&k3_clks 218 2>, 1264 <&k3_clks 218 5>, 1265 <&k3_clks 218 14>, 1266 <&k3_clks 218 18>; 1267 assigned-clock-parents = <&k3_clks 218 3>, 1268 <&k3_clks 218 7>, 1269 <&k3_clks 218 16>, 1270 <&k3_clks 218 22>; 1271}; 1272 1273&serdes0 { 1274 status = "okay"; 1275 1276 serdes0_pcie1_link: phy@0 { 1277 reg = <0>; 1278 cdns,num-lanes = <2>; 1279 #phy-cells = <0>; 1280 cdns,phy-type = <PHY_TYPE_PCIE>; 1281 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 1282 }; 1283 1284 serdes0_usb_link: phy@3 { 1285 reg = <3>; 1286 cdns,num-lanes = <1>; 1287 #phy-cells = <0>; 1288 cdns,phy-type = <PHY_TYPE_USB3>; 1289 resets = <&serdes_wiz0 4>; 1290 }; 1291}; 1292 1293&serdes_wiz0 { 1294 status = "okay"; 1295}; 1296 1297&usb_serdes_mux { 1298 idle-states = <0>; /* USB0 to SERDES lane 3 */ 1299}; 1300 1301&usbss0 { 1302 status = "okay"; 1303 pinctrl-0 = <&main_usbss0_pins_default>; 1304 pinctrl-names = "default"; 1305 ti,vbus-divider; 1306}; 1307 1308&usb0 { 1309 dr_mode = "otg"; 1310 maximum-speed = "super-speed"; 1311 phys = <&serdes0_usb_link>; 1312 phy-names = "cdns3,usb3-phy"; 1313}; 1314 1315&serdes_wiz4 { 1316 status = "okay"; 1317}; 1318 1319&serdes4 { 1320 status = "okay"; 1321 serdes4_dp_link: phy@0 { 1322 reg = <0>; 1323 cdns,num-lanes = <4>; 1324 #phy-cells = <0>; 1325 cdns,phy-type = <PHY_TYPE_DP>; 1326 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1327 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1328 }; 1329}; 1330 1331&mhdp { 1332 status = "okay"; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&dp0_pins_default>; 1335 phys = <&serdes4_dp_link>; 1336 phy-names = "dpphy"; 1337}; 1338 1339&dss_ports { 1340 /* DP */ 1341 port { 1342 dpi0_out: endpoint { 1343 remote-endpoint = <&dp0_in>; 1344 }; 1345 }; 1346}; 1347 1348&main_i2c4 { 1349 status = "okay"; 1350 pinctrl-names = "default"; 1351 pinctrl-0 = <&main_i2c4_pins_default>; 1352 clock-frequency = <400000>; 1353 1354 exp4: gpio@20 { 1355 compatible = "ti,tca6408"; 1356 reg = <0x20>; 1357 gpio-controller; 1358 #gpio-cells = <2>; 1359 }; 1360}; 1361 1362&dp0_ports { 1363 port@0 { 1364 reg = <0>; 1365 1366 dp0_in: endpoint { 1367 remote-endpoint = <&dpi0_out>; 1368 }; 1369 }; 1370 1371 port@4 { 1372 reg = <4>; 1373 1374 dp0_out: endpoint { 1375 remote-endpoint = <&dp0_connector_in>; 1376 }; 1377 }; 1378}; 1379 1380&mcu_mcan0 { 1381 status = "okay"; 1382 pinctrl-names = "default"; 1383 pinctrl-0 = <&mcu_mcan0_pins_default>; 1384 phys = <&transceiver0>; 1385}; 1386 1387&mcu_mcan1 { 1388 status = "okay"; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&mcu_mcan1_pins_default>; 1391 phys = <&transceiver1>; 1392}; 1393 1394&main_mcan16 { 1395 status = "okay"; 1396 pinctrl-names = "default"; 1397 pinctrl-0 = <&main_mcan16_pins_default>; 1398 phys = <&transceiver2>; 1399}; 1400 1401&main_mcan4 { 1402 status = "okay"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&main_mcan4_pins_default>; 1405 phys = <&transceiver3>; 1406}; 1407 1408&pcie1_rc { 1409 status = "okay"; 1410 num-lanes = <2>; 1411 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 1412 phys = <&serdes0_pcie1_link>; 1413 phy-names = "pcie-phy"; 1414}; 1415 1416&serdes1 { 1417 status = "okay"; 1418 1419 serdes1_pcie0_link: phy@0 { 1420 reg = <0>; 1421 cdns,num-lanes = <4>; 1422 #phy-cells = <0>; 1423 cdns,phy-type = <PHY_TYPE_PCIE>; 1424 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, 1425 <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1426 }; 1427}; 1428 1429&serdes_wiz1 { 1430 status = "okay"; 1431}; 1432 1433&pcie0_rc { 1434 status = "okay"; 1435 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1436 phys = <&serdes1_pcie0_link>; 1437 phy-names = "pcie-phy"; 1438}; 1439 1440&k3_clks { 1441 /* Confiure AUDIO_EXT_REFCLK1 pin as output */ 1442 pinctrl-names = "default"; 1443 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 1444}; 1445 1446&main_i2c3 { 1447 status = "okay"; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&main_i2c3_pins_default>; 1450 clock-frequency = <400000>; 1451 1452 exp3: gpio@20 { 1453 compatible = "ti,tca6408"; 1454 reg = <0x20>; 1455 gpio-controller; 1456 #gpio-cells = <2>; 1457 }; 1458 1459 pcm3168a_1: audio-codec@44 { 1460 compatible = "ti,pcm3168a"; 1461 reg = <0x44>; 1462 #sound-dai-cells = <1>; 1463 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 1464 clocks = <&audio_refclk1>; 1465 clock-names = "scki"; 1466 VDD1-supply = <&vsys_3v3>; 1467 VDD2-supply = <&vsys_3v3>; 1468 VCCAD1-supply = <&vsys_5v0>; 1469 VCCAD2-supply = <&vsys_5v0>; 1470 VCCDA1-supply = <&vsys_5v0>; 1471 VCCDA2-supply = <&vsys_5v0>; 1472 }; 1473}; 1474 1475&mcasp0 { 1476 status = "okay"; 1477 #sound-dai-cells = <0>; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&main_mcasp0_pins_default>; 1480 op-mode = <0>; /* MCASP_IIS_MODE */ 1481 tdm-slots = <2>; 1482 auxclk-fs-ratio = <256>; 1483 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1484 0 0 0 1 1485 2 0 0 0 1486 0 0 0 0 1487 0 0 0 0 1488 >; 1489}; 1490