1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 22 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 23 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 24 #address-cells = <2>; 25 #size-cells = <2>; 26 ranges; 27 #interrupt-cells = <3>; 28 interrupt-controller; 29 /* 30 * vcpumntirq: 31 * virtual CPU interface maintenance interrupt 32 */ 33 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 35 gic_its: msi-controller@1820000 { 36 compatible = "arm,gic-v3-its"; 37 reg = <0x00 0x01820000 0x00 0x10000>; 38 socionext,synquacer-pre-its = <0x1000000 0x400000>; 39 msi-controller; 40 #msi-cells = <1>; 41 }; 42 }; 43 44 main_conf: bus@100000 { 45 compatible = "simple-bus"; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x00 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 }; 55 56 epwm_tbclk: clock-controller@4130 { 57 compatible = "ti,am62-epwm-tbclk"; 58 reg = <0x4130 0x4>; 59 #clock-cells = <1>; 60 }; 61 62 audio_refclk0: clock-controller@82e0 { 63 compatible = "ti,am62-audio-refclk"; 64 reg = <0x82e0 0x4>; 65 clocks = <&k3_clks 157 0>; 66 assigned-clocks = <&k3_clks 157 0>; 67 assigned-clock-parents = <&k3_clks 157 8>; 68 #clock-cells = <0>; 69 }; 70 71 audio_refclk1: clock-controller@82e4 { 72 compatible = "ti,am62-audio-refclk"; 73 reg = <0x82e4 0x4>; 74 clocks = <&k3_clks 157 10>; 75 assigned-clocks = <&k3_clks 157 10>; 76 assigned-clock-parents = <&k3_clks 157 18>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 dmss: bus@48000000 { 82 compatible = "simple-bus"; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 dma-ranges; 86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 87 88 ti,sci-dev-id = <25>; 89 90 secure_proxy_main: mailbox@4d000000 { 91 compatible = "ti,am654-secure-proxy"; 92 reg = <0x00 0x4d000000 0x00 0x80000>, 93 <0x00 0x4a600000 0x00 0x80000>, 94 <0x00 0x4a400000 0x00 0x80000>; 95 reg-names = "target_data", "rt", "scfg"; 96 #mbox-cells = <1>; 97 interrupt-names = "rx_012"; 98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 101 inta_main_dmss: interrupt-controller@48000000 { 102 compatible = "ti,sci-inta"; 103 reg = <0x00 0x48000000 0x00 0x100000>; 104 #interrupt-cells = <0>; 105 interrupt-controller; 106 interrupt-parent = <&gic500>; 107 msi-controller; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <28>; 110 ti,interrupt-ranges = <6 70 34>; 111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 112 }; 113 114 main_bcdma: dma-controller@485c0100 { 115 compatible = "ti,am64-dmss-bcdma"; 116 reg = <0x00 0x485c0100 0x00 0x100>, 117 <0x00 0x4c000000 0x00 0x20000>, 118 <0x00 0x4a820000 0x00 0x20000>, 119 <0x00 0x4aa40000 0x00 0x20000>, 120 <0x00 0x4bc00000 0x00 0x100000>, 121 <0x00 0x48600000 0x00 0x8000>, 122 <0x00 0x484a4000 0x00 0x2000>, 123 <0x00 0x484c2000 0x00 0x2000>, 124 <0x00 0x48420000 0x00 0x2000>; 125 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 126 "ring", "tchan", "rchan", "bchan"; 127 msi-parent = <&inta_main_dmss>; 128 #dma-cells = <3>; 129 ti,sci = <&dmsc>; 130 ti,sci-dev-id = <26>; 131 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 132 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 133 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 134 }; 135 136 main_pktdma: dma-controller@485c0000 { 137 compatible = "ti,am64-dmss-pktdma"; 138 reg = <0x00 0x485c0000 0x00 0x100>, 139 <0x00 0x4a800000 0x00 0x20000>, 140 <0x00 0x4aa00000 0x00 0x20000>, 141 <0x00 0x4b800000 0x00 0x200000>, 142 <0x00 0x485e0000 0x00 0x10000>, 143 <0x00 0x484a0000 0x00 0x2000>, 144 <0x00 0x484c0000 0x00 0x2000>, 145 <0x00 0x48430000 0x00 0x1000>; 146 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 147 "ring", "tchan", "rchan", "rflow"; 148 msi-parent = <&inta_main_dmss>; 149 #dma-cells = <2>; 150 ti,sci = <&dmsc>; 151 ti,sci-dev-id = <30>; 152 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 153 <0x24>, /* CPSW_TX_CHAN */ 154 <0x25>, /* SAUL_TX_0_CHAN */ 155 <0x26>; /* SAUL_TX_1_CHAN */ 156 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 157 <0x11>, /* RING_CPSW_TX_CHAN */ 158 <0x12>, /* RING_SAUL_TX_0_CHAN */ 159 <0x13>; /* RING_SAUL_TX_1_CHAN */ 160 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 161 <0x2b>, /* CPSW_RX_CHAN */ 162 <0x2d>, /* SAUL_RX_0_CHAN */ 163 <0x2f>, /* SAUL_RX_1_CHAN */ 164 <0x31>, /* SAUL_RX_2_CHAN */ 165 <0x33>; /* SAUL_RX_3_CHAN */ 166 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 167 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 168 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 169 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 170 }; 171 }; 172 173 dmss_csi: bus@4e000000 { 174 compatible = "simple-bus"; 175 #address-cells = <2>; 176 #size-cells = <2>; 177 dma-ranges; 178 ranges = <0x00 0x4e000000 0x00 0x4e000000 0x00 0x300000>; 179 180 ti,sci-dev-id = <198>; 181 182 inta_main_dmss_csi: interrupt-controller@4e0a0000 { 183 compatible = "ti,sci-inta"; 184 reg = <0x00 0x4e0a0000 0x00 0x8000>; 185 #interrupt-cells = <0>; 186 interrupt-controller; 187 interrupt-parent = <&gic500>; 188 msi-controller; 189 ti,sci = <&dmsc>; 190 ti,sci-dev-id = <200>; 191 ti,interrupt-ranges = <0 237 8>; 192 ti,unmapped-event-sources = <&main_bcdma_csi>; 193 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 194 }; 195 196 main_bcdma_csi: dma-controller@4e230000 { 197 compatible = "ti,am62a-dmss-bcdma-csirx"; 198 reg = <0x00 0x4e230000 0x00 0x100>, 199 <0x00 0x4e180000 0x00 0x8000>, 200 <0x00 0x4e100000 0x00 0x10000>; 201 reg-names = "gcfg", "rchanrt", "ringrt"; 202 msi-parent = <&inta_main_dmss_csi>; 203 #dma-cells = <3>; 204 ti,sci = <&dmsc>; 205 ti,sci-dev-id = <199>; 206 ti,sci-rm-range-rchan = <0x21>; 207 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 208 }; 209 }; 210 211 dmsc: system-controller@44043000 { 212 compatible = "ti,k2g-sci"; 213 reg = <0x00 0x44043000 0x00 0xfe0>; 214 reg-names = "debug_messages"; 215 ti,host-id = <12>; 216 mbox-names = "rx", "tx"; 217 mboxes = <&secure_proxy_main 12>, 218 <&secure_proxy_main 13>; 219 220 k3_pds: power-controller { 221 compatible = "ti,sci-pm-domain"; 222 #power-domain-cells = <2>; 223 }; 224 225 k3_clks: clock-controller { 226 compatible = "ti,k2g-sci-clk"; 227 #clock-cells = <2>; 228 }; 229 230 k3_reset: reset-controller { 231 compatible = "ti,sci-reset"; 232 #reset-cells = <2>; 233 }; 234 }; 235 236 crypto: crypto@40900000 { 237 compatible = "ti,am62-sa3ul"; 238 reg = <0x00 0x40900000 0x00 0x1200>; 239 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 240 <&main_pktdma 0x7507 0>; 241 dma-names = "tx", "rx1", "rx2"; 242 }; 243 244 secure_proxy_sa3: mailbox@43600000 { 245 compatible = "ti,am654-secure-proxy"; 246 #mbox-cells = <1>; 247 reg-names = "target_data", "rt", "scfg"; 248 reg = <0x00 0x43600000 0x00 0x10000>, 249 <0x00 0x44880000 0x00 0x20000>, 250 <0x00 0x44860000 0x00 0x20000>; 251 /* 252 * Marked Disabled: 253 * Node is incomplete as it is meant for bootloaders and 254 * firmware on non-MPU processors 255 */ 256 status = "disabled"; 257 }; 258 259 main_pmx0: pinctrl@f4000 { 260 compatible = "pinctrl-single"; 261 reg = <0x00 0xf4000 0x00 0x2ac>; 262 #pinctrl-cells = <1>; 263 pinctrl-single,register-width = <32>; 264 pinctrl-single,function-mask = <0xffffffff>; 265 }; 266 267 main_esm: esm@420000 { 268 compatible = "ti,j721e-esm"; 269 reg = <0x0 0x420000 0x0 0x1000>; 270 bootph-pre-ram; 271 /* Interrupt sources: rti0, rti1, wrti0, rti4, rti2, rti3 */ 272 ti,esm-pins = <192>, <193>, <195>, <204>, <209>, <210>; 273 }; 274 275 main_timer0: timer@2400000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x2400000 0x00 0x400>; 278 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 36 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 36 2>; 282 assigned-clock-parents = <&k3_clks 36 3>; 283 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 }; 286 287 main_timer1: timer@2410000 { 288 compatible = "ti,am654-timer"; 289 reg = <0x00 0x2410000 0x00 0x400>; 290 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&k3_clks 37 2>; 292 clock-names = "fck"; 293 assigned-clocks = <&k3_clks 37 2>; 294 assigned-clock-parents = <&k3_clks 37 3>; 295 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 296 ti,timer-pwm; 297 }; 298 299 main_timer2: timer@2420000 { 300 compatible = "ti,am654-timer"; 301 reg = <0x00 0x2420000 0x00 0x400>; 302 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&k3_clks 38 2>; 304 clock-names = "fck"; 305 assigned-clocks = <&k3_clks 38 2>; 306 assigned-clock-parents = <&k3_clks 38 3>; 307 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 308 ti,timer-pwm; 309 }; 310 311 main_timer3: timer@2430000 { 312 compatible = "ti,am654-timer"; 313 reg = <0x00 0x2430000 0x00 0x400>; 314 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&k3_clks 39 2>; 316 clock-names = "fck"; 317 assigned-clocks = <&k3_clks 39 2>; 318 assigned-clock-parents = <&k3_clks 39 3>; 319 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 320 ti,timer-pwm; 321 }; 322 323 main_timer4: timer@2440000 { 324 compatible = "ti,am654-timer"; 325 reg = <0x00 0x2440000 0x00 0x400>; 326 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&k3_clks 40 2>; 328 clock-names = "fck"; 329 assigned-clocks = <&k3_clks 40 2>; 330 assigned-clock-parents = <&k3_clks 40 3>; 331 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 332 ti,timer-pwm; 333 }; 334 335 main_timer5: timer@2450000 { 336 compatible = "ti,am654-timer"; 337 reg = <0x00 0x2450000 0x00 0x400>; 338 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&k3_clks 41 2>; 340 clock-names = "fck"; 341 assigned-clocks = <&k3_clks 41 2>; 342 assigned-clock-parents = <&k3_clks 41 3>; 343 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 344 ti,timer-pwm; 345 }; 346 347 main_timer6: timer@2460000 { 348 compatible = "ti,am654-timer"; 349 reg = <0x00 0x2460000 0x00 0x400>; 350 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&k3_clks 42 2>; 352 clock-names = "fck"; 353 assigned-clocks = <&k3_clks 42 2>; 354 assigned-clock-parents = <&k3_clks 42 3>; 355 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 356 ti,timer-pwm; 357 }; 358 359 main_timer7: timer@2470000 { 360 compatible = "ti,am654-timer"; 361 reg = <0x00 0x2470000 0x00 0x400>; 362 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&k3_clks 43 2>; 364 clock-names = "fck"; 365 assigned-clocks = <&k3_clks 43 2>; 366 assigned-clock-parents = <&k3_clks 43 3>; 367 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 368 ti,timer-pwm; 369 }; 370 371 main_uart0: serial@2800000 { 372 compatible = "ti,am64-uart", "ti,am654-uart"; 373 reg = <0x00 0x02800000 0x00 0x100>; 374 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 375 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 376 clocks = <&k3_clks 146 0>; 377 clock-names = "fclk"; 378 status = "disabled"; 379 }; 380 381 main_uart1: serial@2810000 { 382 compatible = "ti,am64-uart", "ti,am654-uart"; 383 reg = <0x00 0x02810000 0x00 0x100>; 384 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 385 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 386 clocks = <&k3_clks 152 0>; 387 clock-names = "fclk"; 388 status = "disabled"; 389 }; 390 391 main_uart2: serial@2820000 { 392 compatible = "ti,am64-uart", "ti,am654-uart"; 393 reg = <0x00 0x02820000 0x00 0x100>; 394 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 395 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 396 clocks = <&k3_clks 153 0>; 397 clock-names = "fclk"; 398 status = "disabled"; 399 }; 400 401 main_uart3: serial@2830000 { 402 compatible = "ti,am64-uart", "ti,am654-uart"; 403 reg = <0x00 0x02830000 0x00 0x100>; 404 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 405 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 406 clocks = <&k3_clks 154 0>; 407 clock-names = "fclk"; 408 status = "disabled"; 409 }; 410 411 main_uart4: serial@2840000 { 412 compatible = "ti,am64-uart", "ti,am654-uart"; 413 reg = <0x00 0x02840000 0x00 0x100>; 414 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 415 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 416 clocks = <&k3_clks 155 0>; 417 clock-names = "fclk"; 418 status = "disabled"; 419 }; 420 421 main_uart5: serial@2850000 { 422 compatible = "ti,am64-uart", "ti,am654-uart"; 423 reg = <0x00 0x02850000 0x00 0x100>; 424 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 425 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 426 clocks = <&k3_clks 156 0>; 427 clock-names = "fclk"; 428 status = "disabled"; 429 }; 430 431 main_uart6: serial@2860000 { 432 compatible = "ti,am64-uart", "ti,am654-uart"; 433 reg = <0x00 0x02860000 0x00 0x100>; 434 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 435 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 436 clocks = <&k3_clks 158 0>; 437 clock-names = "fclk"; 438 status = "disabled"; 439 }; 440 441 main_i2c0: i2c@20000000 { 442 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 443 reg = <0x00 0x20000000 0x00 0x100>; 444 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 448 clocks = <&k3_clks 102 2>; 449 clock-names = "fck"; 450 status = "disabled"; 451 }; 452 453 main_i2c1: i2c@20010000 { 454 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 455 reg = <0x00 0x20010000 0x00 0x100>; 456 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 460 clocks = <&k3_clks 103 2>; 461 clock-names = "fck"; 462 status = "disabled"; 463 }; 464 465 main_i2c2: i2c@20020000 { 466 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 467 reg = <0x00 0x20020000 0x00 0x100>; 468 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 472 clocks = <&k3_clks 104 2>; 473 clock-names = "fck"; 474 status = "disabled"; 475 }; 476 477 main_i2c3: i2c@20030000 { 478 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 479 reg = <0x00 0x20030000 0x00 0x100>; 480 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 484 clocks = <&k3_clks 105 2>; 485 clock-names = "fck"; 486 status = "disabled"; 487 }; 488 489 main_spi0: spi@20100000 { 490 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 491 reg = <0x00 0x20100000 0x00 0x400>; 492 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 496 clocks = <&k3_clks 141 0>; 497 status = "disabled"; 498 }; 499 500 main_spi1: spi@20110000 { 501 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 502 reg = <0x00 0x20110000 0x00 0x400>; 503 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 507 clocks = <&k3_clks 142 0>; 508 status = "disabled"; 509 }; 510 511 main_spi2: spi@20120000 { 512 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 513 reg = <0x00 0x20120000 0x00 0x400>; 514 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 518 clocks = <&k3_clks 143 0>; 519 status = "disabled"; 520 }; 521 522 main_gpio_intr: interrupt-controller@a00000 { 523 compatible = "ti,sci-intr"; 524 reg = <0x00 0x00a00000 0x00 0x800>; 525 ti,intr-trigger-type = <1>; 526 interrupt-controller; 527 interrupt-parent = <&gic500>; 528 #interrupt-cells = <1>; 529 ti,sci = <&dmsc>; 530 ti,sci-dev-id = <3>; 531 ti,interrupt-ranges = <0 32 16>; 532 status = "disabled"; 533 }; 534 535 main_gpio0: gpio@600000 { 536 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 537 reg = <0x00 0x00600000 0x0 0x100>; 538 gpio-controller; 539 #gpio-cells = <2>; 540 interrupt-parent = <&main_gpio_intr>; 541 interrupts = <190>, <191>, <192>, 542 <193>, <194>, <195>; 543 interrupt-controller; 544 #interrupt-cells = <2>; 545 ti,ngpio = <92>; 546 ti,davinci-gpio-unbanked = <0>; 547 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 548 clocks = <&k3_clks 77 0>; 549 clock-names = "gpio"; 550 status = "disabled"; 551 }; 552 553 main_gpio1: gpio@601000 { 554 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 555 reg = <0x00 0x00601000 0x0 0x100>; 556 gpio-controller; 557 #gpio-cells = <2>; 558 interrupt-parent = <&main_gpio_intr>; 559 interrupts = <180>, <181>, <182>, 560 <183>, <184>, <185>; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 ti,ngpio = <52>; 564 ti,davinci-gpio-unbanked = <0>; 565 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 566 clocks = <&k3_clks 78 0>; 567 clock-names = "gpio"; 568 status = "disabled"; 569 }; 570 571 sdhci0: mmc@fa10000 { 572 compatible = "ti,am62-sdhci"; 573 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 574 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 575 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; 577 clock-names = "clk_ahb", "clk_xin"; 578 assigned-clocks = <&k3_clks 57 6>; 579 assigned-clock-parents = <&k3_clks 57 8>; 580 bus-width = <8>; 581 mmc-hs200-1_8v; 582 ti,clkbuf-sel = <0x7>; 583 ti,otap-del-sel-legacy = <0x0>; 584 ti,otap-del-sel-mmc-hs = <0x0>; 585 ti,otap-del-sel-hs200 = <0x6>; 586 status = "disabled"; 587 }; 588 589 sdhci1: mmc@fa00000 { 590 compatible = "ti,am62-sdhci"; 591 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 592 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 593 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 594 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 595 clock-names = "clk_ahb", "clk_xin"; 596 bus-width = <4>; 597 ti,clkbuf-sel = <0x7>; 598 ti,otap-del-sel-legacy = <0x0>; 599 ti,otap-del-sel-sd-hs = <0x0>; 600 ti,otap-del-sel-sdr12 = <0xf>; 601 ti,otap-del-sel-sdr25 = <0xf>; 602 ti,otap-del-sel-sdr50 = <0xc>; 603 ti,otap-del-sel-sdr104 = <0x6>; 604 ti,otap-del-sel-ddr50 = <0x9>; 605 ti,itap-del-sel-legacy = <0x0>; 606 ti,itap-del-sel-sd-hs = <0x0>; 607 ti,itap-del-sel-sdr12 = <0x0>; 608 ti,itap-del-sel-sdr25 = <0x0>; 609 status = "disabled"; 610 }; 611 612 sdhci2: mmc@fa20000 { 613 compatible = "ti,am62-sdhci"; 614 reg = <0x00 0xfa20000 0x00 0x260>, <0x00 0xfa28000 0x00 0x134>; 615 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 616 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 617 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 618 clock-names = "clk_ahb", "clk_xin"; 619 bus-width = <4>; 620 ti,clkbuf-sel = <0x7>; 621 ti,otap-del-sel-legacy = <0x0>; 622 ti,otap-del-sel-sd-hs = <0x0>; 623 ti,otap-del-sel-sdr12 = <0xf>; 624 ti,otap-del-sel-sdr25 = <0xf>; 625 ti,otap-del-sel-sdr50 = <0xc>; 626 ti,otap-del-sel-sdr104 = <0x6>; 627 ti,otap-del-sel-ddr50 = <0x9>; 628 ti,itap-del-sel-legacy = <0x0>; 629 ti,itap-del-sel-sd-hs = <0x0>; 630 ti,itap-del-sel-sdr12 = <0x0>; 631 ti,itap-del-sel-sdr25 = <0x0>; 632 status = "disabled"; 633 }; 634 635 usbss0: dwc3-usb@f900000 { 636 compatible = "ti,am62-usb"; 637 reg = <0x00 0x0f900000 0x00 0x800>, 638 <0x00 0x0f908000 0x00 0x400>; 639 clocks = <&k3_clks 161 3>; 640 clock-names = "ref"; 641 ti,syscon-phy-pll-refclk = <&usb0_phy_ctrl 0x0>; 642 #address-cells = <2>; 643 #size-cells = <2>; 644 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 645 ranges; 646 status = "disabled"; 647 648 usb0: usb@31000000 { 649 compatible = "snps,dwc3"; 650 reg = <0x00 0x31000000 0x00 0x50000>; 651 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 652 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 653 interrupt-names = "host", "peripheral"; 654 maximum-speed = "high-speed"; 655 dr_mode = "otg"; 656 snps,usb2-gadget-lpm-disable; 657 snps,usb2-lpm-disable; 658 }; 659 }; 660 661 usbss1: dwc3-usb@f910000 { 662 compatible = "ti,am62-usb"; 663 reg = <0x00 0x0f910000 0x00 0x800>, 664 <0x00 0x0f918000 0x00 0x400>; 665 clocks = <&k3_clks 162 3>; 666 clock-names = "ref"; 667 ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>; 668 #address-cells = <2>; 669 #size-cells = <2>; 670 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 671 ranges; 672 status = "disabled"; 673 674 usb1: usb@31100000 { 675 compatible = "snps,dwc3"; 676 reg = <0x00 0x31100000 0x00 0x50000>; 677 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 678 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 679 interrupt-names = "host", "peripheral"; 680 maximum-speed = "high-speed"; 681 dr_mode = "otg"; 682 snps,usb2-gadget-lpm-disable; 683 snps,usb2-lpm-disable; 684 }; 685 }; 686 687 fss: bus@fc00000 { 688 compatible = "simple-bus"; 689 reg = <0x00 0x0fc00000 0x00 0x70000>; 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges; 693 status = "disabled"; 694 695 ospi0: spi@fc40000 { 696 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 697 reg = <0x00 0x0fc40000 0x00 0x100>, 698 <0x05 0x00000000 0x01 0x00000000>; 699 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 700 cdns,fifo-depth = <256>; 701 cdns,fifo-width = <4>; 702 cdns,trigger-address = <0x0>; 703 clocks = <&k3_clks 75 7>; 704 assigned-clocks = <&k3_clks 75 7>; 705 assigned-clock-parents = <&k3_clks 75 8>; 706 assigned-clock-rates = <166666666>; 707 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 }; 711 }; 712 713 cpsw3g: ethernet@8000000 { 714 compatible = "ti,am642-cpsw-nuss"; 715 #address-cells = <2>; 716 #size-cells = <2>; 717 reg = <0x0 0x8000000 0x0 0x200000>; 718 reg-names = "cpsw_nuss"; 719 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 720 clocks = <&k3_clks 13 0>; 721 assigned-clocks = <&k3_clks 13 3>; 722 assigned-clock-parents = <&k3_clks 13 11>; 723 clock-names = "fck"; 724 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 725 status = "disabled"; 726 727 dmas = <&main_pktdma 0xc600 15>, 728 <&main_pktdma 0xc601 15>, 729 <&main_pktdma 0xc602 15>, 730 <&main_pktdma 0xc603 15>, 731 <&main_pktdma 0xc604 15>, 732 <&main_pktdma 0xc605 15>, 733 <&main_pktdma 0xc606 15>, 734 <&main_pktdma 0xc607 15>, 735 <&main_pktdma 0x4600 15>; 736 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 737 "tx7", "rx"; 738 739 ethernet-ports { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 743 cpsw_port1: port@1 { 744 reg = <1>; 745 ti,mac-only; 746 label = "port1"; 747 phys = <&phy_gmii_sel 1>; 748 mac-address = [00 00 00 00 00 00]; 749 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 750 }; 751 752 cpsw_port2: port@2 { 753 reg = <2>; 754 ti,mac-only; 755 label = "port2"; 756 phys = <&phy_gmii_sel 2>; 757 mac-address = [00 00 00 00 00 00]; 758 }; 759 }; 760 761 cpsw3g_mdio: mdio@f00 { 762 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 763 reg = <0x0 0xf00 0x0 0x100>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 clocks = <&k3_clks 13 0>; 767 clock-names = "fck"; 768 bus_freq = <1000000>; 769 }; 770 771 cpts@3d000 { 772 compatible = "ti,j721e-cpts"; 773 reg = <0x0 0x3d000 0x0 0x400>; 774 clocks = <&k3_clks 13 3>; 775 clock-names = "cpts"; 776 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-names = "cpts"; 778 ti,cpts-ext-ts-inputs = <4>; 779 ti,cpts-periodic-outputs = <2>; 780 }; 781 }; 782 783 hwspinlock: spinlock@2a000000 { 784 compatible = "ti,am64-hwspinlock"; 785 reg = <0x00 0x2a000000 0x00 0x1000>; 786 #hwlock-cells = <1>; 787 }; 788 789 mailbox0_cluster0: mailbox@29000000 { 790 compatible = "ti,am64-mailbox"; 791 reg = <0x00 0x29000000 0x00 0x200>; 792 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 793 #mbox-cells = <1>; 794 ti,mbox-num-users = <4>; 795 ti,mbox-num-fifos = <16>; 796 }; 797 798 mailbox0_cluster1: mailbox@29010000 { 799 compatible = "ti,am64-mailbox"; 800 reg = <0x00 0x29010000 0x00 0x200>; 801 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 802 #mbox-cells = <1>; 803 ti,mbox-num-users = <4>; 804 ti,mbox-num-fifos = <16>; 805 }; 806 807 mailbox0_cluster2: mailbox@29020000 { 808 compatible = "ti,am64-mailbox"; 809 reg = <0x00 0x29020000 0x00 0x200>; 810 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 811 #mbox-cells = <1>; 812 ti,mbox-num-users = <4>; 813 ti,mbox-num-fifos = <16>; 814 }; 815 816 mailbox0_cluster3: mailbox@29030000 { 817 compatible = "ti,am64-mailbox"; 818 reg = <0x00 0x29030000 0x00 0x200>; 819 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 820 #mbox-cells = <1>; 821 ti,mbox-num-users = <4>; 822 ti,mbox-num-fifos = <16>; 823 }; 824 825 main_mcan0: can@20701000 { 826 compatible = "bosch,m_can"; 827 reg = <0x00 0x20701000 0x00 0x200>, 828 <0x00 0x20708000 0x00 0x8000>; 829 reg-names = "m_can", "message_ram"; 830 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 831 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 832 clock-names = "hclk", "cclk"; 833 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 835 interrupt-names = "int0", "int1"; 836 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 837 status = "disabled"; 838 }; 839 840 main_rti0: watchdog@e000000 { 841 compatible = "ti,j7-rti-wdt"; 842 reg = <0x00 0x0e000000 0x00 0x100>; 843 clocks = <&k3_clks 125 0>; 844 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 845 assigned-clocks = <&k3_clks 125 0>; 846 assigned-clock-parents = <&k3_clks 125 2>; 847 }; 848 849 main_rti1: watchdog@e010000 { 850 compatible = "ti,j7-rti-wdt"; 851 reg = <0x00 0x0e010000 0x00 0x100>; 852 clocks = <&k3_clks 126 0>; 853 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 854 assigned-clocks = <&k3_clks 126 0>; 855 assigned-clock-parents = <&k3_clks 126 2>; 856 }; 857 858 main_rti2: watchdog@e020000 { 859 compatible = "ti,j7-rti-wdt"; 860 reg = <0x00 0x0e020000 0x00 0x100>; 861 clocks = <&k3_clks 127 0>; 862 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 863 assigned-clocks = <&k3_clks 127 0>; 864 assigned-clock-parents = <&k3_clks 127 2>; 865 }; 866 867 main_rti3: watchdog@e030000 { 868 compatible = "ti,j7-rti-wdt"; 869 reg = <0x00 0x0e030000 0x00 0x100>; 870 clocks = <&k3_clks 128 0>; 871 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 872 assigned-clocks = <&k3_clks 128 0>; 873 assigned-clock-parents = <&k3_clks 128 2>; 874 }; 875 876 main_rti4: watchdog@e040000 { 877 compatible = "ti,j7-rti-wdt"; 878 reg = <0x00 0x0e040000 0x00 0x100>; 879 clocks = <&k3_clks 205 0>; 880 power-domains = <&k3_pds 205 TI_SCI_PD_EXCLUSIVE>; 881 assigned-clocks = <&k3_clks 205 0>; 882 assigned-clock-parents = <&k3_clks 205 2>; 883 }; 884 885 epwm0: pwm@23000000 { 886 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 887 #pwm-cells = <3>; 888 reg = <0x00 0x23000000 0x00 0x100>; 889 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 890 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 891 clock-names = "tbclk", "fck"; 892 status = "disabled"; 893 }; 894 895 epwm1: pwm@23010000 { 896 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 897 #pwm-cells = <3>; 898 reg = <0x00 0x23010000 0x00 0x100>; 899 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 900 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 901 clock-names = "tbclk", "fck"; 902 status = "disabled"; 903 }; 904 905 epwm2: pwm@23020000 { 906 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 907 #pwm-cells = <3>; 908 reg = <0x00 0x23020000 0x00 0x100>; 909 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 911 clock-names = "tbclk", "fck"; 912 status = "disabled"; 913 }; 914 915 ecap0: pwm@23100000 { 916 compatible = "ti,am3352-ecap"; 917 #pwm-cells = <3>; 918 reg = <0x00 0x23100000 0x00 0x100>; 919 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 920 clocks = <&k3_clks 51 0>; 921 clock-names = "fck"; 922 status = "disabled"; 923 }; 924 925 ecap1: pwm@23110000 { 926 compatible = "ti,am3352-ecap"; 927 #pwm-cells = <3>; 928 reg = <0x00 0x23110000 0x00 0x100>; 929 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 930 clocks = <&k3_clks 52 0>; 931 clock-names = "fck"; 932 status = "disabled"; 933 }; 934 935 ecap2: pwm@23120000 { 936 compatible = "ti,am3352-ecap"; 937 #pwm-cells = <3>; 938 reg = <0x00 0x23120000 0x00 0x100>; 939 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 940 clocks = <&k3_clks 53 0>; 941 clock-names = "fck"; 942 status = "disabled"; 943 }; 944 945 eqep0: counter@23200000 { 946 compatible = "ti,am62-eqep"; 947 reg = <0x00 0x23200000 0x00 0x100>; 948 power-domains = <&k3_pds 59 TI_SCI_PD_EXCLUSIVE>; 949 clocks = <&k3_clks 59 0>; 950 interrupts = <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>; 951 status = "disabled"; 952 }; 953 954 eqep1: counter@23210000 { 955 compatible = "ti,am62-eqep"; 956 reg = <0x00 0x23210000 0x00 0x100>; 957 power-domains = <&k3_pds 60 TI_SCI_PD_EXCLUSIVE>; 958 clocks = <&k3_clks 60 0>; 959 interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>; 960 status = "disabled"; 961 }; 962 963 eqep2: counter@23220000 { 964 compatible = "ti,am62-eqep"; 965 reg = <0x00 0x23220000 0x00 0x100>; 966 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 967 clocks = <&k3_clks 62 0>; 968 interrupts = <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>; 969 status = "disabled"; 970 }; 971 972 mcasp0: audio-controller@2b00000 { 973 compatible = "ti,am33xx-mcasp-audio"; 974 reg = <0x00 0x02b00000 0x00 0x2000>, 975 <0x00 0x02b08000 0x00 0x400>; 976 reg-names = "mpu", "dat"; 977 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 979 interrupt-names = "tx", "rx"; 980 981 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 982 dma-names = "tx", "rx"; 983 984 clocks = <&k3_clks 190 0>; 985 clock-names = "fck"; 986 assigned-clocks = <&k3_clks 190 0>; 987 assigned-clock-parents = <&k3_clks 190 2>; 988 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 989 status = "disabled"; 990 }; 991 992 mcasp1: audio-controller@2b10000 { 993 compatible = "ti,am33xx-mcasp-audio"; 994 reg = <0x00 0x02b10000 0x00 0x2000>, 995 <0x00 0x02b18000 0x00 0x400>; 996 reg-names = "mpu", "dat"; 997 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 999 interrupt-names = "tx", "rx"; 1000 1001 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 1002 dma-names = "tx", "rx"; 1003 1004 clocks = <&k3_clks 191 0>; 1005 clock-names = "fck"; 1006 assigned-clocks = <&k3_clks 191 0>; 1007 assigned-clock-parents = <&k3_clks 191 2>; 1008 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 1009 status = "disabled"; 1010 }; 1011 1012 mcasp2: audio-controller@2b20000 { 1013 compatible = "ti,am33xx-mcasp-audio"; 1014 reg = <0x00 0x02b20000 0x00 0x2000>, 1015 <0x00 0x02b28000 0x00 0x400>; 1016 reg-names = "mpu", "dat"; 1017 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "tx", "rx"; 1020 1021 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 1022 dma-names = "tx", "rx"; 1023 1024 clocks = <&k3_clks 192 0>; 1025 clock-names = "fck"; 1026 assigned-clocks = <&k3_clks 192 0>; 1027 assigned-clock-parents = <&k3_clks 192 2>; 1028 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 1029 status = "disabled"; 1030 }; 1031 1032 ti_csi2rx0: ticsi2rx@30102000 { 1033 compatible = "ti,j721e-csi2rx-shim"; 1034 dmas = <&main_bcdma_csi 0 0x5000 0>; 1035 dma-names = "rx0"; 1036 reg = <0x00 0x30102000 0x00 0x1000>; 1037 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>; 1038 #address-cells = <2>; 1039 #size-cells = <2>; 1040 ranges; 1041 status = "disabled"; 1042 1043 cdns_csi2rx0: csi-bridge@30101000 { 1044 compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; 1045 reg = <0x00 0x30101000 0x00 0x1000>; 1046 clocks = <&k3_clks 182 0>, <&k3_clks 182 3>, <&k3_clks 182 0>, 1047 <&k3_clks 182 0>, <&k3_clks 182 4>, <&k3_clks 182 4>; 1048 clock-names = "sys_clk", "p_clk", "pixel_if0_clk", 1049 "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; 1050 phys = <&dphy0>; 1051 phy-names = "dphy"; 1052 1053 ports { 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 csi0_port0: port@0 { 1058 reg = <0>; 1059 status = "disabled"; 1060 }; 1061 1062 csi0_port1: port@1 { 1063 reg = <1>; 1064 status = "disabled"; 1065 }; 1066 1067 csi0_port2: port@2 { 1068 reg = <2>; 1069 status = "disabled"; 1070 }; 1071 1072 csi0_port3: port@3 { 1073 reg = <3>; 1074 status = "disabled"; 1075 }; 1076 1077 csi0_port4: port@4 { 1078 reg = <4>; 1079 status = "disabled"; 1080 }; 1081 }; 1082 }; 1083 }; 1084 1085 dphy0: phy@30110000 { 1086 compatible = "cdns,dphy-rx"; 1087 reg = <0x00 0x30110000 0x00 0x1100>; 1088 #phy-cells = <0>; 1089 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>; 1090 status = "disabled"; 1091 }; 1092 1093 dss: dss@30200000 { 1094 compatible = "ti,am62a7-dss"; 1095 reg = <0x00 0x30200000 0x00 0x1000>, /* common */ 1096 <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ 1097 <0x00 0x30206000 0x00 0x1000>, /* vid */ 1098 <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ 1099 <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ 1100 <0x00 0x3020a000 0x00 0x1000>, /* vp1: Tied OFF in the SoC */ 1101 <0x00 0x3020b000 0x00 0x1000>, /* vp2: Used as DPI Out */ 1102 <0x00 0x30201000 0x00 0x1000>; /* common1 */ 1103 reg-names = "common", "vidl1", "vid", 1104 "ovr1", "ovr2", "vp1", "vp2", "common1"; 1105 power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; 1106 clocks = <&k3_clks 186 6>, 1107 <&k3_clks 186 0>, 1108 <&k3_clks 186 2>; 1109 clock-names = "fck", "vp1", "vp2"; 1110 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1111 status = "disabled"; 1112 1113 dss_ports: ports { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 }; 1117 }; 1118 1119 vpu: video-codec@30210000 { 1120 compatible = "ti,j721s2-wave521c", "cnm,wave521c"; 1121 reg = <0x00 0x30210000 0x00 0x10000>; 1122 clocks = <&k3_clks 204 2>; 1123 power-domains = <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; 1124 }; 1125 1126 e5010: jpeg-encoder@fd20000 { 1127 compatible = "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; 1128 reg = <0x00 0xfd20000 0x00 0x100>, 1129 <0x00 0xfd20200 0x00 0x200>; 1130 reg-names = "core", "mmu"; 1131 clocks = <&k3_clks 201 0>; 1132 power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>; 1133 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1134 }; 1135}; 1136