1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __INPUT_SYSTEM_2400_PUBLIC_H_INCLUDED__ 8 #define __INPUT_SYSTEM_2400_PUBLIC_H_INCLUDED__ 9 10 #include <type_support.h> 11 12 /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] 13 14 \param ID[in] RECEIVER identifier 15 \param cfg_ID[in] Configuration identifier 16 \param comp[in] Compression method 17 \param pred[in] Predictor method 18 19 \NOTE: the storage of compression configuration is 20 implementation specific. The config can be 21 carried either on MIPI ports or on MIPI channels 22 23 \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} 24 */ 25 void receiver_set_compression( 26 const rx_ID_t ID, 27 const unsigned int cfg_ID, 28 const mipi_compressor_t comp, 29 const mipi_predictor_t pred); 30 31 /*! Enable PORT[port_ID] of RECEIVER[ID] 32 33 \param ID[in] RECEIVER identifier 34 \param port_ID[in] mipi PORT identifier 35 \param cnd[in] irq predicate 36 37 \return None, enable(RECEIVER[ID].PORT[port_ID]) 38 */ 39 void receiver_port_enable( 40 const rx_ID_t ID, 41 const enum mipi_port_id port_ID, 42 const bool cnd); 43 44 /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled 45 46 \param ID[in] RECEIVER identifier 47 \param port_ID[in] mipi PORT identifier 48 49 \return enable(RECEIVER[ID].PORT[port_ID]) == true 50 */ 51 bool is_receiver_port_enabled( 52 const rx_ID_t ID, 53 const enum mipi_port_id port_ID); 54 55 /*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID] 56 57 \param ID[in] RECEIVER identifier 58 \param port_ID[in] mipi PORT identifier 59 \param irq_info[in] irq channels 60 61 \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info) 62 */ 63 void receiver_irq_enable( 64 const rx_ID_t ID, 65 const enum mipi_port_id port_ID, 66 const rx_irq_info_t irq_info); 67 68 /*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID] 69 70 \param ID[in] RECEIVER identifier 71 \param port_ID[in] mipi PORT identifier 72 73 \return RECEIVER[ID].PORT[port_ID].irq_info 74 */ 75 rx_irq_info_t receiver_get_irq_info( 76 const rx_ID_t ID, 77 const enum mipi_port_id port_ID); 78 79 /*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID] 80 81 \param ID[in] RECEIVER identifier 82 \param port_ID[in] mipi PORT identifier 83 \param irq_info[in] irq status 84 85 \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info) 86 */ 87 void receiver_irq_clear( 88 const rx_ID_t ID, 89 const enum mipi_port_id port_ID, 90 const rx_irq_info_t irq_info); 91 92 /*! Write to a control register of INPUT_SYSTEM[ID] 93 94 \param ID[in] INPUT_SYSTEM identifier 95 \param reg[in] register index 96 \param value[in] The data to be written 97 98 \return none, INPUT_SYSTEM[ID].ctrl[reg] = value 99 */ 100 STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store( 101 const input_system_ID_t ID, 102 const hrt_address reg, 103 const hrt_data value); 104 105 /*! Read from a control register of INPUT_SYSTEM[ID] 106 107 \param ID[in] INPUT_SYSTEM identifier 108 \param reg[in] register index 109 \param value[in] The data to be written 110 111 \return INPUT_SYSTEM[ID].ctrl[reg] 112 */ 113 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load( 114 const input_system_ID_t ID, 115 const hrt_address reg); 116 117 /*! Write to a control register of RECEIVER[ID] 118 119 \param ID[in] RECEIVER identifier 120 \param reg[in] register index 121 \param value[in] The data to be written 122 123 \return none, RECEIVER[ID].ctrl[reg] = value 124 */ 125 STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store( 126 const rx_ID_t ID, 127 const hrt_address reg, 128 const hrt_data value); 129 130 /*! Read from a control register of RECEIVER[ID] 131 132 \param ID[in] RECEIVER identifier 133 \param reg[in] register index 134 \param value[in] The data to be written 135 136 \return RECEIVER[ID].ctrl[reg] 137 */ 138 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load( 139 const rx_ID_t ID, 140 const hrt_address reg); 141 142 /*! Write to a control register of PORT[port_ID] of RECEIVER[ID] 143 144 \param ID[in] RECEIVER identifier 145 \param port_ID[in] mipi PORT identifier 146 \param reg[in] register index 147 \param value[in] The data to be written 148 149 \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value 150 */ 151 STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store( 152 const rx_ID_t ID, 153 const enum mipi_port_id port_ID, 154 const hrt_address reg, 155 const hrt_data value); 156 157 /*! Read from a control register PORT[port_ID] of RECEIVER[ID] 158 159 \param ID[in] RECEIVER identifier 160 \param port_ID[in] mipi PORT identifier 161 \param reg[in] register index 162 \param value[in] The data to be written 163 164 \return RECEIVER[ID].PORT[port_ID].ctrl[reg] 165 */ 166 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load( 167 const rx_ID_t ID, 168 const enum mipi_port_id port_ID, 169 const hrt_address reg); 170 171 /*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 172 173 \param ID[in] INPUT_SYSTEM identifier 174 \param port_ID[in] sub system identifier 175 \param reg[in] register index 176 \param value[in] The data to be written 177 178 \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value 179 */ 180 STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store( 181 const input_system_ID_t ID, 182 const sub_system_ID_t sub_ID, 183 const hrt_address reg, 184 const hrt_data value); 185 186 /*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 187 188 \param ID[in] INPUT_SYSTEM identifier 189 \param port_ID[in] sub system identifier 190 \param reg[in] register index 191 \param value[in] The data to be written 192 193 \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] 194 */ 195 STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load( 196 const input_system_ID_t ID, 197 const sub_system_ID_t sub_ID, 198 const hrt_address reg); 199 200 /////////////////////////////////////////////////////////////////////////// 201 // 202 // Functions for configuration phase on input system. 203 // 204 /////////////////////////////////////////////////////////////////////////// 205 206 // Function that resets current configuration. 207 // remove the argument since it should be private. 208 input_system_err_t input_system_configuration_reset(void); 209 210 // Function that commits current configuration. 211 // remove the argument since it should be private. 212 input_system_err_t input_system_configuration_commit(void); 213 214 /////////////////////////////////////////////////////////////////////////// 215 // 216 // User functions: 217 // (encoded generic function) 218 // - no checking 219 // - decoding name and agruments into the generic (channel) configuration 220 // function. 221 // 222 /////////////////////////////////////////////////////////////////////////// 223 224 // FIFO channel config function user 225 226 input_system_err_t input_system_csi_fifo_channel_cfg( 227 u32 ch_id, 228 input_system_csi_port_t port, 229 backend_channel_cfg_t backend_ch, 230 target_cfg2400_t target 231 ); 232 233 input_system_err_t input_system_csi_fifo_channel_with_counting_cfg( 234 u32 ch_id, 235 u32 nof_frame, 236 input_system_csi_port_t port, 237 backend_channel_cfg_t backend_ch, 238 u32 mem_region_size, 239 u32 nof_mem_regions, 240 target_cfg2400_t target 241 ); 242 243 // SRAM channel config function user 244 245 input_system_err_t input_system_csi_sram_channel_cfg( 246 u32 ch_id, 247 input_system_csi_port_t port, 248 backend_channel_cfg_t backend_ch, 249 u32 csi_mem_region_size, 250 u32 csi_nof_mem_regions, 251 target_cfg2400_t target 252 ); 253 254 //XMEM channel config function user 255 256 input_system_err_t input_system_csi_xmem_channel_cfg( 257 u32 ch_id, 258 input_system_csi_port_t port, 259 backend_channel_cfg_t backend_ch, 260 u32 mem_region_size, 261 u32 nof_mem_regions, 262 u32 acq_mem_region_size, 263 u32 acq_nof_mem_regions, 264 target_cfg2400_t target, 265 uint32_t nof_xmem_buffers 266 ); 267 268 input_system_err_t input_system_csi_xmem_capture_only_channel_cfg( 269 u32 ch_id, 270 u32 nof_frames, 271 input_system_csi_port_t port, 272 u32 csi_mem_region_size, 273 u32 csi_nof_mem_regions, 274 u32 acq_mem_region_size, 275 u32 acq_nof_mem_regions, 276 target_cfg2400_t target 277 ); 278 279 input_system_err_t input_system_csi_xmem_acquire_only_channel_cfg( 280 u32 ch_id, 281 u32 nof_frames, 282 input_system_csi_port_t port, 283 backend_channel_cfg_t backend_ch, 284 u32 acq_mem_region_size, 285 u32 acq_nof_mem_regions, 286 target_cfg2400_t target 287 ); 288 289 // Non - CSI channel config function user 290 291 input_system_err_t input_system_prbs_channel_cfg( 292 u32 ch_id, 293 u32 nof_frames, 294 u32 seed, 295 u32 sync_gen_width, 296 u32 sync_gen_height, 297 u32 sync_gen_hblank_cycles, 298 u32 sync_gen_vblank_cycles, 299 target_cfg2400_t target 300 ); 301 302 input_system_err_t input_system_gpfifo_channel_cfg( 303 u32 ch_id, 304 u32 nof_frames, 305 target_cfg2400_t target 306 ); 307 308 #endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */ 309