1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 /**
24 * @file iris_screen.c
25 *
26 * Screen related driver hooks and capability lists.
27 *
28 * A program may use multiple rendering contexts (iris_context), but
29 * they all share a common screen (iris_screen). Global driver state
30 * can be stored in the screen; it may be accessed by multiple threads.
31 */
32
33 #include <stdio.h>
34 #include <errno.h>
35 #include <sys/ioctl.h>
36 #include "pipe/p_defines.h"
37 #include "pipe/p_state.h"
38 #include "pipe/p_context.h"
39 #include "pipe/p_screen.h"
40 #include "util/u_debug.h"
41 #include "util/os_file.h"
42 #include "util/u_cpu_detect.h"
43 #include "util/u_inlines.h"
44 #include "util/format/u_format.h"
45 #include "util/u_transfer_helper.h"
46 #include "util/u_upload_mgr.h"
47 #include "util/ralloc.h"
48 #include "util/xmlconfig.h"
49 #include "iris_context.h"
50 #include "iris_defines.h"
51 #include "iris_fence.h"
52 #include "iris_perf.h"
53 #include "iris_pipe.h"
54 #include "iris_resource.h"
55 #include "iris_screen.h"
56 #include "compiler/glsl_types.h"
57 #include "intel/common/intel_debug_identifier.h"
58 #include "intel/common/intel_gem.h"
59 #include "intel/common/intel_l3_config.h"
60 #include "intel/common/intel_uuid.h"
61 #include "iris_monitor.h"
62
63 #define genX_call(devinfo, func, ...) \
64 switch ((devinfo)->verx10) { \
65 case 200: \
66 gfx20_##func(__VA_ARGS__); \
67 break; \
68 case 125: \
69 gfx125_##func(__VA_ARGS__); \
70 break; \
71 case 120: \
72 gfx12_##func(__VA_ARGS__); \
73 break; \
74 case 110: \
75 gfx11_##func(__VA_ARGS__); \
76 break; \
77 case 90: \
78 gfx9_##func(__VA_ARGS__); \
79 break; \
80 case 80: \
81 gfx8_##func(__VA_ARGS__); \
82 break; \
83 default: \
84 unreachable("Unknown hardware generation"); \
85 }
86
87 static const char *
iris_get_vendor(struct pipe_screen * pscreen)88 iris_get_vendor(struct pipe_screen *pscreen)
89 {
90 return "Intel";
91 }
92
93 static const char *
iris_get_device_vendor(struct pipe_screen * pscreen)94 iris_get_device_vendor(struct pipe_screen *pscreen)
95 {
96 return "Intel";
97 }
98
99 static void
iris_get_device_uuid(struct pipe_screen * pscreen,char * uuid)100 iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
101 {
102 struct iris_screen *screen = (struct iris_screen *)pscreen;
103
104 intel_uuid_compute_device_id((uint8_t *)uuid, screen->devinfo, PIPE_UUID_SIZE);
105 }
106
107 static void
iris_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)108 iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
109 {
110 struct iris_screen *screen = (struct iris_screen *)pscreen;
111 const struct intel_device_info *devinfo = screen->devinfo;
112
113 intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
114 }
115
116 static bool
iris_enable_clover()117 iris_enable_clover()
118 {
119 static int enable = -1;
120 if (enable < 0)
121 enable = debug_get_bool_option("IRIS_ENABLE_CLOVER", false);
122 return enable;
123 }
124
125 static void
iris_warn_cl()126 iris_warn_cl()
127 {
128 static bool warned = false;
129 if (warned || INTEL_DEBUG(DEBUG_CL_QUIET))
130 return;
131
132 warned = true;
133 fprintf(stderr, "WARNING: OpenCL support via iris driver is incomplete.\n"
134 "For a complete and conformant OpenCL implementation, use\n"
135 "https://github.com/intel/compute-runtime instead\n");
136 }
137
138 static const char *
iris_get_name(struct pipe_screen * pscreen)139 iris_get_name(struct pipe_screen *pscreen)
140 {
141 struct iris_screen *screen = (struct iris_screen *)pscreen;
142 const struct intel_device_info *devinfo = screen->devinfo;
143 static char buf[128];
144
145 snprintf(buf, sizeof(buf), "Mesa %s", devinfo->name);
146 return buf;
147 }
148
149 static const char *
iris_get_cl_cts_version(struct pipe_screen * pscreen)150 iris_get_cl_cts_version(struct pipe_screen *pscreen)
151 {
152 struct iris_screen *screen = (struct iris_screen *)pscreen;
153 const struct intel_device_info *devinfo = screen->devinfo;
154
155 /* https://www.khronos.org/conformance/adopters/conformant-products/opencl#submission_405 */
156 if (devinfo->verx10 == 120)
157 return "v2022-04-22-00";
158
159 return NULL;
160 }
161
162 static int
iris_get_video_memory(struct iris_screen * screen)163 iris_get_video_memory(struct iris_screen *screen)
164 {
165 uint64_t vram = iris_bufmgr_vram_size(screen->bufmgr);
166 uint64_t sram = iris_bufmgr_sram_size(screen->bufmgr);
167 if (vram) {
168 return vram / (1024 * 1024);
169 } else if (sram) {
170 return sram / (1024 * 1024);
171 } else {
172 /* This is the old code path, it get the GGTT size from the kernel
173 * (which should always be 4Gb on Gfx8+).
174 *
175 * We should probably never end up here. This is just a fallback to get
176 * some kind of value in case os_get_available_system_memory fails.
177 */
178 const struct intel_device_info *devinfo = screen->devinfo;
179 /* Once a batch uses more than 75% of the maximum mappable size, we
180 * assume that there's some fragmentation, and we start doing extra
181 * flushing, etc. That's the big cliff apps will care about.
182 */
183 const unsigned gpu_mappable_megabytes =
184 (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024);
185
186 const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
187 const long system_page_size = sysconf(_SC_PAGE_SIZE);
188
189 if (system_memory_pages <= 0 || system_page_size <= 0)
190 return -1;
191
192 const uint64_t system_memory_bytes =
193 (uint64_t) system_memory_pages * (uint64_t) system_page_size;
194
195 const unsigned system_memory_megabytes =
196 (unsigned) (system_memory_bytes / (1024 * 1024));
197
198 return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
199 }
200 }
201
202 static int
iris_get_param(struct pipe_screen * pscreen,enum pipe_cap param)203 iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
204 {
205 struct iris_screen *screen = (struct iris_screen *)pscreen;
206 const struct intel_device_info *devinfo = screen->devinfo;
207
208 switch (param) {
209 case PIPE_CAP_NPOT_TEXTURES:
210 case PIPE_CAP_ANISOTROPIC_FILTER:
211 case PIPE_CAP_OCCLUSION_QUERY:
212 case PIPE_CAP_QUERY_TIME_ELAPSED:
213 case PIPE_CAP_TEXTURE_SWIZZLE:
214 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
215 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
216 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
217 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
218 case PIPE_CAP_PRIMITIVE_RESTART:
219 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
220 case PIPE_CAP_INDEP_BLEND_ENABLE:
221 case PIPE_CAP_INDEP_BLEND_FUNC:
222 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
223 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
224 case PIPE_CAP_DEPTH_CLIP_DISABLE:
225 case PIPE_CAP_VS_INSTANCEID:
226 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
227 case PIPE_CAP_SEAMLESS_CUBE_MAP:
228 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
229 case PIPE_CAP_CONDITIONAL_RENDER:
230 case PIPE_CAP_TEXTURE_BARRIER:
231 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
232 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
233 case PIPE_CAP_COMPUTE:
234 case PIPE_CAP_START_INSTANCE:
235 case PIPE_CAP_QUERY_TIMESTAMP:
236 case PIPE_CAP_TEXTURE_MULTISAMPLE:
237 case PIPE_CAP_CUBE_MAP_ARRAY:
238 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
239 case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
240 case PIPE_CAP_TEXTURE_QUERY_LOD:
241 case PIPE_CAP_SAMPLE_SHADING:
242 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
243 case PIPE_CAP_DRAW_INDIRECT:
244 case PIPE_CAP_MULTI_DRAW_INDIRECT:
245 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
246 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
247 case PIPE_CAP_VS_LAYER_VIEWPORT:
248 case PIPE_CAP_TES_LAYER_VIEWPORT:
249 case PIPE_CAP_FS_FINE_DERIVATIVE:
250 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
251 case PIPE_CAP_ACCELERATED:
252 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
253 case PIPE_CAP_CLIP_HALFZ:
254 case PIPE_CAP_TGSI_TEXCOORD:
255 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
256 case PIPE_CAP_DOUBLES:
257 case PIPE_CAP_INT64:
258 case PIPE_CAP_SAMPLER_VIEW_TARGET:
259 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
260 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
261 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
262 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
263 case PIPE_CAP_CULL_DISTANCE:
264 case PIPE_CAP_PACKED_UNIFORMS:
265 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
266 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
267 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
268 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
269 case PIPE_CAP_QUERY_SO_OVERFLOW:
270 case PIPE_CAP_QUERY_BUFFER_OBJECT:
271 case PIPE_CAP_TGSI_TEX_TXF_LZ:
272 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
273 case PIPE_CAP_SHADER_CLOCK:
274 case PIPE_CAP_SHADER_BALLOT:
275 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
276 case PIPE_CAP_CLEAR_SCISSORED:
277 case PIPE_CAP_SHADER_GROUP_VOTE:
278 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
279 case PIPE_CAP_TEXTURE_GATHER_SM5:
280 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
281 case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
282 case PIPE_CAP_LOAD_CONSTBUF:
283 case PIPE_CAP_DRAW_PARAMETERS:
284 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
285 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
286 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
287 case PIPE_CAP_INVALIDATE_BUFFER:
288 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
289 case PIPE_CAP_TEXTURE_SHADOW_LOD:
290 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
291 case PIPE_CAP_GL_SPIRV:
292 case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
293 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
294 case PIPE_CAP_NATIVE_FENCE_FD:
295 case PIPE_CAP_MEMOBJ:
296 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
297 case PIPE_CAP_FENCE_SIGNAL:
298 case PIPE_CAP_IMAGE_STORE_FORMATTED:
299 case PIPE_CAP_LEGACY_MATH_RULES:
300 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
301 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
302 case PIPE_CAP_HAS_CONST_BW:
303 case PIPE_CAP_CL_GL_SHARING:
304 return true;
305 case PIPE_CAP_UMA:
306 return iris_bufmgr_vram_size(screen->bufmgr) == 0;
307 case PIPE_CAP_QUERY_MEMORY_INFO:
308 return iris_bufmgr_vram_size(screen->bufmgr) != 0;
309 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
310 return false;
311 case PIPE_CAP_FBFETCH:
312 return IRIS_MAX_DRAW_BUFFERS;
313 case PIPE_CAP_FBFETCH_COHERENT:
314 return devinfo->ver >= 9 && devinfo->ver < 20;
315 case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
316 case PIPE_CAP_POST_DEPTH_COVERAGE:
317 case PIPE_CAP_SHADER_STENCIL_EXPORT:
318 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
319 case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
320 case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
321 return devinfo->ver >= 9;
322 case PIPE_CAP_DEPTH_BOUNDS_TEST:
323 return devinfo->ver >= 12;
324 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
325 return 1;
326 case PIPE_CAP_MAX_RENDER_TARGETS:
327 return IRIS_MAX_DRAW_BUFFERS;
328 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
329 return 16384;
330 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
331 return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
332 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
333 return 12; /* 2048x2048 */
334 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
335 return 4;
336 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
337 return 2048;
338 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
339 return IRIS_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
340 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
341 return IRIS_MAX_SOL_BINDINGS;
342 case PIPE_CAP_GLSL_FEATURE_LEVEL:
343 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
344 return 460;
345 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
346 /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
347 return 32;
348 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
349 return IRIS_MAP_BUFFER_ALIGNMENT;
350 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
351 return 4;
352 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
353 return 1 << 27;
354 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
355 return 16; // XXX: u_screen says 256 is the minimum value...
356 case PIPE_CAP_LINEAR_IMAGE_PITCH_ALIGNMENT:
357 return 1;
358 case PIPE_CAP_LINEAR_IMAGE_BASE_ADDRESS_ALIGNMENT:
359 return 1;
360 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
361 return PIPE_TEXTURE_TRANSFER_BLIT;
362 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
363 return IRIS_MAX_TEXTURE_BUFFER_SIZE;
364 case PIPE_CAP_MAX_VIEWPORTS:
365 return 16;
366 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
367 return 256;
368 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
369 return 1024;
370 case PIPE_CAP_MAX_GS_INVOCATIONS:
371 return 32;
372 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
373 return 4;
374 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
375 return -32;
376 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
377 return 31;
378 case PIPE_CAP_MAX_VERTEX_STREAMS:
379 return 4;
380 case PIPE_CAP_VENDOR_ID:
381 return 0x8086;
382 case PIPE_CAP_DEVICE_ID:
383 return screen->devinfo->pci_device_id;
384 case PIPE_CAP_VIDEO_MEMORY:
385 return iris_get_video_memory(screen);
386 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
387 case PIPE_CAP_MAX_VARYINGS:
388 return 32;
389 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
390 /* We want immediate arrays to go get uploaded as nir->constant_data by
391 * nir_opt_large_constants() instead.
392 */
393 return 0;
394 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
395 /* AMD_pinned_memory assumes the flexibility of using client memory
396 * for any buffer (incl. vertex buffers) which rules out the prospect
397 * of using snooped buffers, as using snooped buffers without
398 * cogniscience is likely to be detrimental to performance and require
399 * extensive checking in the driver for correctness, e.g. to prevent
400 * illegal snoop <-> snoop transfers.
401 */
402 return devinfo->has_llc;
403 case PIPE_CAP_THROTTLE:
404 return screen->driconf.disable_throttling ? 0 : 1;
405
406 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
407 return PIPE_CONTEXT_PRIORITY_LOW |
408 PIPE_CONTEXT_PRIORITY_MEDIUM |
409 PIPE_CONTEXT_PRIORITY_HIGH;
410
411 case PIPE_CAP_FRONTEND_NOOP:
412 return true;
413
414 // XXX: don't hardcode 00:00:02.0 PCI here
415 case PIPE_CAP_PCI_GROUP:
416 return 0;
417 case PIPE_CAP_PCI_BUS:
418 return 0;
419 case PIPE_CAP_PCI_DEVICE:
420 return 2;
421 case PIPE_CAP_PCI_FUNCTION:
422 return 0;
423
424 case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
425 case PIPE_CAP_INTEGER_MULTIPLY_32X16:
426 return true;
427
428 case PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH:
429 /* Internal details of VF cache make this optimization harmful on GFX
430 * version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached
431 * separately.
432 */
433 return devinfo->ver >= 11;
434
435 case PIPE_CAP_TIMER_RESOLUTION:
436 return DIV_ROUND_UP(1000000000ull, devinfo->timestamp_frequency);
437
438 case PIPE_CAP_DEVICE_PROTECTED_CONTEXT:
439 return screen->kernel_features & KERNEL_HAS_PROTECTED_CONTEXT;
440
441 case PIPE_CAP_ASTC_VOID_EXTENTS_NEED_DENORM_FLUSH:
442 return devinfo->ver == 9 && !intel_device_info_is_9lp(devinfo);
443
444 default:
445 return u_pipe_screen_get_param_defaults(pscreen, param);
446 }
447 return 0;
448 }
449
450 static float
iris_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)451 iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
452 {
453 switch (param) {
454 case PIPE_CAPF_MIN_LINE_WIDTH:
455 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
456 case PIPE_CAPF_MIN_POINT_SIZE:
457 case PIPE_CAPF_MIN_POINT_SIZE_AA:
458 return 1;
459
460 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
461 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
462 return 0.1;
463
464 case PIPE_CAPF_MAX_LINE_WIDTH:
465 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
466 return 7.375f;
467
468 case PIPE_CAPF_MAX_POINT_SIZE:
469 case PIPE_CAPF_MAX_POINT_SIZE_AA:
470 return 255.0f;
471
472 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
473 return 16.0f;
474 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
475 return 15.0f;
476 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
477 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
478 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
479 return 0.0f;
480 default:
481 unreachable("unknown param");
482 }
483 }
484
485 static int
iris_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type p_stage,enum pipe_shader_cap param)486 iris_get_shader_param(struct pipe_screen *pscreen,
487 enum pipe_shader_type p_stage,
488 enum pipe_shader_cap param)
489 {
490 gl_shader_stage stage = stage_from_pipe(p_stage);
491
492 if (p_stage == PIPE_SHADER_MESH ||
493 p_stage == PIPE_SHADER_TASK)
494 return 0;
495
496 /* this is probably not totally correct.. but it's a start: */
497 switch (param) {
498 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
499 return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
500 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
501 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
502 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
503 return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
504
505 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
506 return UINT_MAX;
507
508 case PIPE_SHADER_CAP_MAX_INPUTS:
509 return stage == MESA_SHADER_VERTEX ? 16 : 32;
510 case PIPE_SHADER_CAP_MAX_OUTPUTS:
511 return 32;
512 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
513 return 16 * 1024 * sizeof(float);
514 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
515 return 16;
516 case PIPE_SHADER_CAP_MAX_TEMPS:
517 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
518 case PIPE_SHADER_CAP_CONT_SUPPORTED:
519 return 0;
520 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
521 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
522 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
523 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
524 /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
525 * which we don't want. Our compiler backend will check brw_compiler's
526 * options and call nir_lower_indirect_derefs appropriately anyway.
527 */
528 return true;
529 case PIPE_SHADER_CAP_SUBROUTINES:
530 return 0;
531 case PIPE_SHADER_CAP_INTEGERS:
532 return 1;
533 case PIPE_SHADER_CAP_INT64_ATOMICS:
534 case PIPE_SHADER_CAP_FP16:
535 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
536 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
537 case PIPE_SHADER_CAP_INT16:
538 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
539 return 0;
540 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
541 return IRIS_MAX_SAMPLERS;
542 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
543 return IRIS_MAX_TEXTURES;
544 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
545 return IRIS_MAX_IMAGES;
546 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
547 return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
548 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
549 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
550 return 0;
551 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
552 int irs = 1 << PIPE_SHADER_IR_NIR;
553 if (iris_enable_clover())
554 irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
555 return irs;
556 }
557 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
558 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
559 return 0;
560 default:
561 unreachable("unknown shader param");
562 }
563 }
564
565 static int
iris_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)566 iris_get_compute_param(struct pipe_screen *pscreen,
567 enum pipe_shader_ir ir_type,
568 enum pipe_compute_cap param,
569 void *ret)
570 {
571 struct iris_screen *screen = (struct iris_screen *)pscreen;
572 const struct intel_device_info *devinfo = screen->devinfo;
573
574 const uint32_t max_invocations =
575 MIN2(1024, 32 * devinfo->max_cs_workgroup_threads);
576
577 #define RET(x) do { \
578 if (ret) \
579 memcpy(ret, x, sizeof(x)); \
580 return sizeof(x); \
581 } while (0)
582
583 switch (param) {
584 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
585 /* This gets queried on OpenCL device init and is never queried by the
586 * OpenGL state tracker.
587 */
588 iris_warn_cl();
589 RET((uint32_t []){ 64 });
590
591 case PIPE_COMPUTE_CAP_IR_TARGET:
592 if (ret)
593 strcpy(ret, "gen");
594 return 4;
595
596 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
597 RET((uint64_t []) { 3 });
598
599 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
600 RET(((uint64_t []) { UINT32_MAX, UINT32_MAX, UINT32_MAX }));
601
602 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
603 /* MaxComputeWorkGroupSize[0..2] */
604 RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
605
606 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
607 /* MaxComputeWorkGroupInvocations */
608 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
609 /* MaxComputeVariableGroupInvocations */
610 RET((uint64_t []) { max_invocations });
611
612 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
613 /* MaxComputeSharedMemorySize */
614 RET((uint64_t []) { 64 * 1024 });
615
616 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
617 RET((uint32_t []) { 1 });
618
619 case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
620 RET((uint32_t []) { 32 | 16 | 8 });
621
622 case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
623 RET((uint32_t []) { devinfo->max_cs_workgroup_threads });
624
625 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
626 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
627 RET((uint64_t []) { 1 << 30 }); /* TODO */
628
629 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
630 RET((uint32_t []) { 400 }); /* TODO */
631
632 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: {
633 RET((uint32_t []) { intel_device_info_subslice_total(devinfo) });
634 }
635
636 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
637 /* MaxComputeSharedMemorySize */
638 RET((uint64_t []) { 64 * 1024 });
639
640 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
641 /* We could probably allow more; this is the OpenCL minimum */
642 RET((uint64_t []) { 1024 });
643
644 default:
645 unreachable("unknown compute param");
646 }
647 }
648
649 static uint64_t
iris_get_timestamp(struct pipe_screen * pscreen)650 iris_get_timestamp(struct pipe_screen *pscreen)
651 {
652 struct iris_screen *screen = (struct iris_screen *) pscreen;
653 uint64_t result;
654
655 if (!intel_gem_read_render_timestamp(iris_bufmgr_get_fd(screen->bufmgr),
656 screen->devinfo->kmd_type, &result))
657 return 0;
658
659 result = intel_device_info_timebase_scale(screen->devinfo, result);
660
661 return result;
662 }
663
664 void
iris_screen_destroy(struct iris_screen * screen)665 iris_screen_destroy(struct iris_screen *screen)
666 {
667 intel_perf_free(screen->perf_cfg);
668 iris_destroy_screen_measure(screen);
669 util_queue_destroy(&screen->shader_compiler_queue);
670 glsl_type_singleton_decref();
671 iris_bo_unreference(screen->workaround_bo);
672 iris_bo_unreference(screen->breakpoint_bo);
673 u_transfer_helper_destroy(screen->base.transfer_helper);
674 iris_bufmgr_unref(screen->bufmgr);
675 disk_cache_destroy(screen->disk_cache);
676 close(screen->winsys_fd);
677 ralloc_free(screen);
678 }
679
680 static void
iris_screen_unref(struct pipe_screen * pscreen)681 iris_screen_unref(struct pipe_screen *pscreen)
682 {
683 iris_pscreen_unref(pscreen);
684 }
685
686 static void
iris_query_memory_info(struct pipe_screen * pscreen,struct pipe_memory_info * info)687 iris_query_memory_info(struct pipe_screen *pscreen,
688 struct pipe_memory_info *info)
689 {
690 struct iris_screen *screen = (struct iris_screen *)pscreen;
691 struct intel_device_info di;
692 memcpy(&di, screen->devinfo, sizeof(di));
693
694 if (!intel_device_info_update_memory_info(&di, screen->fd))
695 return;
696
697 info->total_device_memory =
698 (di.mem.vram.mappable.size + di.mem.vram.unmappable.size) / 1024;
699 info->avail_device_memory =
700 (di.mem.vram.mappable.free + di.mem.vram.unmappable.free) / 1024;
701 info->total_staging_memory = di.mem.sram.mappable.size / 1024;
702 info->avail_staging_memory = di.mem.sram.mappable.free / 1024;
703
704 /* Neither kernel gives us any way to calculate this information */
705 info->device_memory_evicted = 0;
706 info->nr_device_memory_evictions = 0;
707 }
708
709 static struct disk_cache *
iris_get_disk_shader_cache(struct pipe_screen * pscreen)710 iris_get_disk_shader_cache(struct pipe_screen *pscreen)
711 {
712 struct iris_screen *screen = (struct iris_screen *) pscreen;
713 return screen->disk_cache;
714 }
715
716 static const struct intel_l3_config *
iris_get_default_l3_config(const struct intel_device_info * devinfo,bool compute)717 iris_get_default_l3_config(const struct intel_device_info *devinfo,
718 bool compute)
719 {
720 bool wants_dc_cache = true;
721 bool has_slm = compute;
722 const struct intel_l3_weights w =
723 intel_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
724 return intel_get_l3_config(devinfo, w);
725 }
726
727 static void
iris_detect_kernel_features(struct iris_screen * screen)728 iris_detect_kernel_features(struct iris_screen *screen)
729 {
730 const struct intel_device_info *devinfo = screen->devinfo;
731 /* Kernel 5.2+ */
732 if (intel_gem_supports_syncobj_wait(screen->fd))
733 screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
734 if (intel_gem_supports_protected_context(screen->fd, devinfo->kmd_type))
735 screen->kernel_features |= KERNEL_HAS_PROTECTED_CONTEXT;
736 }
737
738 static bool
iris_init_identifier_bo(struct iris_screen * screen)739 iris_init_identifier_bo(struct iris_screen *screen)
740 {
741 void *bo_map;
742
743 bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
744 if (!bo_map)
745 return false;
746
747 assert(iris_bo_is_real(screen->workaround_bo));
748
749 screen->workaround_address = (struct iris_address) {
750 .bo = screen->workaround_bo,
751 .offset = ALIGN(
752 intel_debug_write_identifiers(bo_map, 4096, "Iris"), 32),
753 };
754
755 iris_bo_unmap(screen->workaround_bo);
756
757 return true;
758 }
759
760 static int
iris_screen_get_fd(struct pipe_screen * pscreen)761 iris_screen_get_fd(struct pipe_screen *pscreen)
762 {
763 struct iris_screen *screen = (struct iris_screen *) pscreen;
764
765 return screen->winsys_fd;
766 }
767
768 struct pipe_screen *
iris_screen_create(int fd,const struct pipe_screen_config * config)769 iris_screen_create(int fd, const struct pipe_screen_config *config)
770 {
771 struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
772 if (!screen)
773 return NULL;
774
775 driParseConfigFiles(config->options, config->options_info, 0, "iris",
776 NULL, NULL, NULL, 0, NULL, 0);
777
778 bool bo_reuse = false;
779 int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
780 switch (bo_reuse_mode) {
781 case DRI_CONF_BO_REUSE_DISABLED:
782 break;
783 case DRI_CONF_BO_REUSE_ALL:
784 bo_reuse = true;
785 break;
786 }
787
788 process_intel_debug_variable();
789
790 screen->bufmgr = iris_bufmgr_get_for_fd(fd, bo_reuse);
791 if (!screen->bufmgr)
792 return NULL;
793
794 screen->devinfo = iris_bufmgr_get_device_info(screen->bufmgr);
795 p_atomic_set(&screen->refcount, 1);
796
797 /* Here are the i915 features we need for Iris (in chronological order) :
798 * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10)
799 * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10)
800 * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13)
801 * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14)
802 * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
803 *
804 * Checking the last feature availability will include all previous ones.
805 */
806 if (!screen->devinfo->has_context_isolation) {
807 debug_error("Kernel is too old (4.16+ required) or unusable for Iris.\n"
808 "Check your dmesg logs for loading failures.\n");
809 return NULL;
810 }
811
812 screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
813 screen->winsys_fd = os_dupfd_cloexec(fd);
814
815 screen->id = iris_bufmgr_create_screen_id(screen->bufmgr);
816
817 screen->workaround_bo =
818 iris_bo_alloc(screen->bufmgr, "workaround", 4096, 4096,
819 IRIS_MEMZONE_OTHER, BO_ALLOC_NO_SUBALLOC | BO_ALLOC_CAPTURE);
820 if (!screen->workaround_bo)
821 return NULL;
822
823 screen->breakpoint_bo = iris_bo_alloc(screen->bufmgr, "breakpoint", 4, 4,
824 IRIS_MEMZONE_OTHER, BO_ALLOC_ZEROED);
825 if (!screen->breakpoint_bo)
826 return NULL;
827
828 if (!iris_init_identifier_bo(screen))
829 return NULL;
830
831 screen->driconf.dual_color_blend_by_location =
832 driQueryOptionb(config->options, "dual_color_blend_by_location");
833 screen->driconf.disable_throttling =
834 driQueryOptionb(config->options, "disable_throttling");
835 screen->driconf.always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
836 driQueryOptionb(config->options, "always_flush_cache");
837 screen->driconf.sync_compile =
838 driQueryOptionb(config->options, "sync_compile");
839 screen->driconf.limit_trig_input_range =
840 driQueryOptionb(config->options, "limit_trig_input_range");
841 screen->driconf.lower_depth_range_rate =
842 driQueryOptionf(config->options, "lower_depth_range_rate");
843 screen->driconf.intel_enable_wa_14018912822 =
844 driQueryOptionb(config->options, "intel_enable_wa_14018912822");
845 screen->driconf.enable_tbimr =
846 driQueryOptionb(config->options, "intel_tbimr");
847 screen->driconf.generated_indirect_threshold =
848 driQueryOptioni(config->options, "generated_indirect_threshold");
849
850 screen->precompile = debug_get_bool_option("shader_precompile", true);
851
852 isl_device_init(&screen->isl_dev, screen->devinfo);
853 screen->isl_dev.dummy_aux_address = iris_bufmgr_get_dummy_aux_address(screen->bufmgr);
854
855 screen->isl_dev.sampler_route_to_lsc =
856 driQueryOptionb(config->options, "intel_sampler_route_to_lsc");
857
858 iris_compiler_init(screen);
859
860 screen->l3_config_3d = iris_get_default_l3_config(screen->devinfo, false);
861 screen->l3_config_cs = iris_get_default_l3_config(screen->devinfo, true);
862
863 iris_disk_cache_init(screen);
864
865 slab_create_parent(&screen->transfer_pool,
866 sizeof(struct iris_transfer), 64);
867
868 iris_detect_kernel_features(screen);
869
870 struct pipe_screen *pscreen = &screen->base;
871
872 iris_init_screen_fence_functions(pscreen);
873 iris_init_screen_resource_functions(pscreen);
874 iris_init_screen_measure(screen);
875
876 pscreen->destroy = iris_screen_unref;
877 pscreen->get_name = iris_get_name;
878 pscreen->get_vendor = iris_get_vendor;
879 pscreen->get_device_vendor = iris_get_device_vendor;
880 pscreen->get_cl_cts_version = iris_get_cl_cts_version;
881 pscreen->get_screen_fd = iris_screen_get_fd;
882 pscreen->get_param = iris_get_param;
883 pscreen->get_shader_param = iris_get_shader_param;
884 pscreen->get_compute_param = iris_get_compute_param;
885 pscreen->get_paramf = iris_get_paramf;
886 pscreen->get_compiler_options = iris_get_compiler_options;
887 pscreen->get_device_uuid = iris_get_device_uuid;
888 pscreen->get_driver_uuid = iris_get_driver_uuid;
889 pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
890 pscreen->is_format_supported = iris_is_format_supported;
891 pscreen->context_create = iris_create_context;
892 pscreen->get_timestamp = iris_get_timestamp;
893 pscreen->query_memory_info = iris_query_memory_info;
894 pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
895 pscreen->get_driver_query_info = iris_get_monitor_info;
896 iris_init_screen_program_functions(pscreen);
897
898 genX_call(screen->devinfo, init_screen_state, screen);
899 genX_call(screen->devinfo, init_screen_gen_state, screen);
900
901 glsl_type_singleton_init_or_ref();
902
903 intel_driver_ds_init();
904
905 /* FINISHME: Big core vs little core (for CPUs that have both kinds of
906 * cores) and, possibly, thread vs core should be considered here too.
907 */
908 unsigned compiler_threads = 1;
909 const struct util_cpu_caps_t *caps = util_get_cpu_caps();
910 unsigned hw_threads = caps->nr_cpus;
911
912 if (hw_threads >= 12) {
913 compiler_threads = hw_threads * 3 / 4;
914 } else if (hw_threads >= 6) {
915 compiler_threads = hw_threads - 2;
916 } else if (hw_threads >= 2) {
917 compiler_threads = hw_threads - 1;
918 }
919
920 if (!util_queue_init(&screen->shader_compiler_queue,
921 "sh", 64, compiler_threads,
922 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
923 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY,
924 NULL)) {
925 iris_screen_destroy(screen);
926 return NULL;
927 }
928
929 return pscreen;
930 }
931