1 /* 2 * Copyright © 2022 Google, Inc. 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #ifndef IR3_DESCRIPTOR_H_ 7 #define IR3_DESCRIPTOR_H_ 8 9 #include "ir3/ir3_shader.h" 10 11 /* 12 * When using bindless descriptor sets for image/SSBO (and fb-read) state, 13 * since the descriptor sets are large, layout the descriptor set with the 14 * first IR3_BINDLESS_SSBO_COUNT slots for SSBOs followed by 15 * IR3_BINDLESS_IMAGE_COUNT slots for images. (For fragment shaders, the 16 * last image slot is reserved for fb-read tex descriptor.) 17 * 18 * Note that these limits are more or less arbitrary. But the enable_mask 19 * in fd_shaderbuf_stateobj / fd_shaderimg_stateobj would need to be more 20 * than uint32_t to support more than 32. 21 */ 22 23 #define IR3_BINDLESS_SSBO_OFFSET 0 24 #define IR3_BINDLESS_SSBO_COUNT 32 25 #define IR3_BINDLESS_IMAGE_OFFSET IR3_BINDLESS_SSBO_COUNT 26 #define IR3_BINDLESS_IMAGE_COUNT 32 27 #define IR3_BINDLESS_DESC_COUNT (IR3_BINDLESS_IMAGE_OFFSET + IR3_BINDLESS_IMAGE_COUNT) 28 29 /** 30 * When using bindless descriptor sets for IBO/etc, each shader stage gets 31 * it's own descriptor set, avoiding the need to merge image/ssbo state 32 * across shader stages. 33 */ 34 static inline unsigned ir3_shader_descriptor_set(enum pipe_shader_type shader)35ir3_shader_descriptor_set(enum pipe_shader_type shader) 36 { 37 switch (shader) { 38 case PIPE_SHADER_VERTEX: return 0; 39 case PIPE_SHADER_TESS_CTRL: return 1; 40 case PIPE_SHADER_TESS_EVAL: return 2; 41 case PIPE_SHADER_GEOMETRY: return 3; 42 case PIPE_SHADER_FRAGMENT: return 4; 43 case PIPE_SHADER_COMPUTE: return 0; 44 default: 45 unreachable("bad shader stage"); 46 return ~0; 47 } 48 } 49 50 bool ir3_nir_lower_io_to_bindless(nir_shader *shader); 51 52 #endif /* IR3_DESCRIPTOR_H_ */ 53