xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/include/intelblocks/nvs.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_INTEL_COMMON_BLOCK_NVS_H
4 #define SOC_INTEL_COMMON_BLOCK_NVS_H
5 
6 #include <stdint.h>
7 
8 struct __packed global_nvs {
9 	/* Miscellaneous */
10 	u16	unused_was_osys; /* 0x00 - 0x01 Operating System */
11 	u8	smif; /* 0x02 - SMI function call ("TRAP") */
12 	u8	unused_was_pcnt; /* 0x03 - Processor Count */
13 	u8	ppcm; /* 0x04 - Max PPC State */
14 	u8	tlvl; /* 0x05 - Throttle Level Limit */
15 	u8	lids; /* 0x06 - LID State */
16 	u8	unused_was_pwrs; /* 0x07 - AC Power State */
17 	u32	unused_was_cbmc; /* 0x08 - 0xb coreboot Memory Console */
18 	u64	pm1i; /* 0x0c - 0x13 PM1 wake status bit */
19 	u64	gpei; /* 0x14 - 0x1b GPE wake status bit */
20 	u8	dpte; /* 0x1c - Enable DPTF */
21 	u64	nhla; /* 0x1d - 0x24 NHLT Address */
22 	u32	nhll; /* 0x25 - 0x28 NHLT Length */
23 	u16	unused_was_cid1; /* 0x29 - 0x2a Wifi Country Identifier */
24 	u16	u2we; /* 0x2b - 0x2c USB2 Wake Enable Bitmap */
25 	u16	u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */
26 	u8	uior; /* 0x2f - UART debug controller init on S3 resume */
27 	u64	hest_log_addr; /* 0x30 - 0x37 err log addr (used in SMM, not ASL code) */
28 };
29 
30 #endif
31