1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_MP_INIT_H 4 #define SOC_INTEL_COMMON_BLOCK_MP_INIT_H 5 6 #include <cpu/intel/cpu_ids.h> 7 #include <device/device.h> 8 9 /* Supported CPUIDs for different SOCs */ 10 /* 11 * MP Init callback function to Find CPU Topology. This function is common 12 * among all SOCs and thus its in Common CPU block. 13 */ 14 int get_cpu_count(void); 15 16 /* 17 * MP Init callback function(get_microcode_info) to find the Microcode at 18 * Pre MP Init phase. This function is common among all SOCs and thus its in 19 * Common CPU block. 20 * This function also fills in the microcode patch (in *microcode), and also 21 * sets the argument *parallel to 1, which allows microcode loading in all 22 * APs to occur in parallel during MP Init. 23 */ 24 void get_microcode_info(const void **microcode, int *parallel); 25 26 /* 27 * Perform BSP and AP initialization 28 * This function can be called in below cases 29 * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude 30 * this call if user has selected USE_INTEL_FSP_MP_INIT) 31 * 2. coreboot would like to take APs control back after FSP-S has done with MP 32 * initialization based on user select USE_INTEL_FSP_MP_INIT 33 */ 34 void init_cpus(void); 35 36 /* 37 * This function will perform any recommended CPU (BSP and AP) initialization 38 * after coreboot has done the multiprocessor initialization (before FSP-S) 39 * and prior to coreboot perform post_cpus_init (after DRAM resources are set). 40 */ 41 void before_post_cpus_init(void); 42 43 /* 44 * SoC Overrides 45 * 46 * All new SoC must implement below functionality for ramstage. 47 */ 48 49 /* 50 * In this function SOC must perform CPU feature programming 51 * during Ramstage phase. 52 */ 53 void soc_core_init(struct device *dev); 54 55 #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */ 56