1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H 4 #define SOC_INTEL_COMMON_BLOCK_LPSS_H 5 6 #include <device/device.h> 7 #include <stdint.h> 8 9 /* D0 and D3 enable config */ 10 enum lpss_pwr_state { 11 STATE_D0 = 0, 12 STATE_D3 = 3 13 }; 14 15 /* Gets controller out of reset */ 16 void lpss_reset_release(uintptr_t base); 17 18 /* 19 * Update clock divider parameters. Clock frequency is dependent on source 20 * clock frequency of each IP block. Resulting clock will be src_freq * (M / N). 21 */ 22 void lpss_clk_update(uintptr_t base, uint32_t clk_m_val, uint32_t clk_n_val); 23 24 /* Check if controller is in reset. */ 25 bool lpss_is_controller_in_reset(uintptr_t base); 26 27 /* Set controller power state to D0 or D3*/ 28 void lpss_set_power_state(pci_devfn_t devfn, enum lpss_pwr_state state); 29 30 #endif /* SOC_INTEL_COMMON_BLOCK_LPSS_H */ 31