xref: /aosp_15_r20/external/coreboot/src/soc/intel/common/block/include/intelblocks/itss.h (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef SOC_INTEL_COMMON_BLOCK_ITSS_H
4 #define SOC_INTEL_COMMON_BLOCK_ITSS_H
5 
6 /* PIRQA Routing Control Register */
7 #define PCR_ITSS_PIRQA_ROUT	0x3100
8 /* PIRQB Routing Control Register */
9 #define PCR_ITSS_PIRQB_ROUT	0x3101
10 /* PIRQC Routing Control Register */
11 #define PCR_ITSS_PIRQC_ROUT	0x3102
12 /* PIRQD Routing Control Register */
13 #define PCR_ITSS_PIRQD_ROUT	0x3103
14 /* PIRQE Routing Control Register */
15 #define PCR_ITSS_PIRQE_ROUT	0x3104
16 /* PIRQF Routing Control Register */
17 #define PCR_ITSS_PIRQF_ROUT	0x3105
18 /* PIRQG Routing Control Register */
19 #define PCR_ITSS_PIRQG_ROUT	0x3106
20 /* PIRQH Routing Control Register */
21 #define PCR_ITSS_PIRQH_ROUT	0x3107
22 /* ITSS Interrupt polarity control */
23 #define PCR_ITSS_IPC0_CONF	0x3200
24 /* ITSS Power reduction control */
25 #define PCR_ITSS_ITSSPRC	0x3300
26 
27 #if !defined(__ACPI__)
28 
29 #include <southbridge/intel/common/acpi_pirq_gen.h>
30 #include <stdint.h>
31 
32 /* Set the interrupt polarity for provided IRQ to the APIC. */
33 void itss_set_irq_polarity(int irq, int active_low);
34 
35 /* Snapshot and restore IRQ polarity settings for the inclusive range. */
36 void itss_snapshot_irq_polarities(int start, int end);
37 void itss_restore_irq_polarities(int start, int end);
38 
39 void itss_irq_init(const uint8_t pch_interrupt_routing[PIRQ_COUNT]);
40 void itss_clock_gate_8254(void);
41 
42 #endif /* !defined(__ACPI__) */
43 
44 #endif /* SOC_INTEL_COMMON_BLOCK_ITSS_H */
45