1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef _SOC_INTELBLOCKS_GPIO_H_ 4 #define _SOC_INTELBLOCKS_GPIO_H_ 5 6 #include <soc/gpio.h> 7 #include "gpio_defs.h" 8 9 /* GPIO community IOSF sideband VNNREQ/ACK handshake */ 10 #define MISCCFG_GPVNNREQEN (1 << 7) 11 /* GPIO community PGCB clock gating */ 12 #define MISCCFG_GPPGCBDPCGEN (1 << 6) 13 /* GPIO community IOSF sideband clock gating */ 14 #define MISCCFG_GPSIDEDPCGEN (1 << 5) 15 /* GPIO community RCOMP clock gating */ 16 #define MISCCFG_GPRCOMPCDLCGEN (1 << 4) 17 /* GPIO community RTC clock gating */ 18 #define MISCCFG_GPRTCDLCGEN (1 << 3) 19 /* GFX controller clock gating */ 20 #define MISCCFG_GSXSLCGEN (1 << 2) 21 /* GPIO community partition clock gating */ 22 #define MISCCFG_GPDPCGEN (1 << 1) 23 /* GPIO community local clock gating */ 24 #define MISCCFG_GPDLCGEN (1 << 0) 25 26 #ifndef __ACPI__ 27 #include <types.h> 28 #include <device/device.h> 29 30 /* 31 * GPIO numbers may not be contiguous and instead will have a different 32 * starting pin number for each pad group. 33 */ 34 #define INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ 35 group_pad_base) \ 36 { \ 37 .first_pad = (start_of_group) - (first_of_community), \ 38 .size = (end_of_group) - (start_of_group) + 1, \ 39 .acpi_pad_base = (group_pad_base), \ 40 } 41 42 /* 43 * A pad base of -1 indicates that this group uses contiguous numbering 44 * and a pad base should not be used for this group. 45 */ 46 #define PAD_BASE_NONE -1 47 48 /* The common/default group numbering is contiguous */ 49 #define INTEL_GPP(first_of_community, start_of_group, end_of_group) \ 50 INTEL_GPP_BASE(first_of_community, start_of_group, end_of_group,\ 51 PAD_BASE_NONE) 52 53 /* 54 * Following should be defined in soc/gpio.h 55 * GPIO_MISCCFG - offset to GPIO MISCCFG Register 56 * 57 * GPIO_NUM_PAD_CFG_REGS - number of PAD config registers in the SOC 58 * For SOCs that have DW0 and DW1, it should be 2 59 * NUM_GPI_STATUS_REGS - total number of GPI status registers across all 60 * GPIO communities in the SOC 61 * 62 * The register offsets specific to the soc communities should be provided in 63 * struct pad_community table returned from soc_gpio_get_community 64 */ 65 66 typedef uint32_t gpio_t; 67 68 enum gpio_lock_action { 69 GPIO_UNLOCK = 0x0, 70 GPIO_LOCK_CONFIG = 0x1, 71 GPIO_LOCK_TX = 0x2, 72 GPIO_LOCK_FULL = GPIO_LOCK_CONFIG | GPIO_LOCK_TX, 73 }; 74 75 struct pad_config { 76 gpio_t pad;/* offset of pad within community */ 77 uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];/* 78 Pad config data corresponding to DW0, DW1,.... */ 79 enum gpio_lock_action lock_action; /* Pad lock configuration */ 80 }; 81 82 /* 83 * Structure provides the logical to actual value for PADRSTCFG in DW0. Note 84 * that the values are expected to be within the field placement of the register 85 * itself. i.e. if the reset field is at 31:30 then the values within logical 86 * and chipset should occupy 31:30. 87 */ 88 struct reset_mapping { 89 uint32_t logical; 90 uint32_t chipset; 91 }; 92 93 /* Structure describes the groups within each community */ 94 struct pad_group { 95 int first_pad; /* offset of first pad of the group relative 96 to the community */ 97 unsigned int size; /* Size of the group */ 98 /* 99 * This is the starting pin number for the pads in this group when 100 * they are used in ACPI. This is only needed if the pins are not 101 * contiguous across groups, most groups will have this set to 102 * PAD_BASE_NONE and use contiguous numbering for ACPI. 103 */ 104 int acpi_pad_base; 105 }; 106 107 /* A range of consecutive virtual-wire entries in a community */ 108 struct vw_entries { 109 gpio_t first_pad; 110 gpio_t last_pad; 111 }; 112 113 /* This structure will be used to describe a community or each group within a 114 * community when multiple groups exist inside a community 115 */ 116 struct pad_community { 117 const char *name; 118 const char *acpi_path; 119 size_t num_gpi_regs;/* number of gpi registers in community */ 120 size_t max_pads_per_group; /* number of pads in each group; 121 Number of pads bit mapped in each GPI status/en and Host Own Reg */ 122 gpio_t first_pad; /* first pad in community */ 123 gpio_t last_pad; /* last pad in community */ 124 uint16_t host_own_reg_0; /* offset to Host Ownership Reg 0 */ 125 uint16_t gpi_int_sts_reg_0; /* offset to GPI Int STS Reg 0 */ 126 uint16_t gpi_int_en_reg_0; /* offset to GPI Int Enable Reg 0 */ 127 uint16_t gpi_smi_sts_reg_0; /* offset to GPI SMI STS Reg 0 */ 128 uint16_t gpi_smi_en_reg_0; /* offset to GPI SMI EN Reg 0 */ 129 uint16_t gpi_gpe_sts_reg_0; /* offset to GPI GPE STS Reg 0 */ 130 uint16_t gpi_gpe_en_reg_0; /* offset to GPI GPE EN Reg 0 */ 131 uint16_t gpi_nmi_sts_reg_0; /* offset to GPI NMI STS Reg 0 */ 132 uint16_t gpi_nmi_en_reg_0; /* offset to GPI NMI EN Reg 0 */ 133 uint16_t pad_cfg_base; /* offset to first PAD_GFG_DW0 Reg */ 134 uint16_t pad_cfg_lock_offset; /* offset to first PADCFGLOCK Reg */ 135 uint8_t gpi_status_offset; /* specifies offset in struct 136 gpi_status */ 137 uint8_t port; /* PCR Port ID */ 138 uint8_t cpu_port; /* CPU Port ID */ 139 const struct reset_mapping *reset_map; /* PADRSTCFG logical to 140 chipset mapping */ 141 size_t num_reset_vals; 142 const struct pad_group *groups; 143 size_t num_groups; 144 unsigned int vw_base; 145 /* 146 * Note: The entries must be in the same order here as the order in 147 * which they map to VW indexes (beginning with VW base) 148 */ 149 const struct vw_entries *vw_entries; 150 size_t num_vw_entries; 151 }; 152 153 /* 154 * Provides storage for all GPI status registers from all communities 155 */ 156 struct gpi_status { 157 uint32_t grp[NUM_GPI_STATUS_REGS]; 158 }; 159 160 /* 161 * Structure provides the pmc to gpio group mapping 162 */ 163 struct pmc_to_gpio_route { 164 int pmc; 165 int gpio; 166 }; 167 168 /* 169 * Returns the first community in the list. This will help to iterate 170 * through the list. It also returns total number of gpio communities. 171 * The soc layer provides a table describing available gpio communities. 172 */ 173 const struct pad_community *soc_gpio_get_community(size_t *num_communities); 174 175 /* 176 * Clear GPI SMI status and fill in the structure representing enabled 177 * and set status. 178 */ 179 void gpi_clear_get_smi_status(struct gpi_status *sts); 180 181 /* Return 1 if gpio is set in the sts. Otherwise 0. */ 182 int gpi_status_get(const struct gpi_status *sts, gpio_t gpi); 183 184 /* 185 * Configuration for raw pads. Some pads are designated as only special function 186 * pins, and don't have an associated GPIO number, so we need to expose the raw 187 * pad configuration functionality. 188 */ 189 void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); 190 191 /* 192 * gpio_configure_pads_with_override accepts as input two GPIO tables: 193 * 1. Base config 194 * 2. Override config 195 * 196 * This function configures raw pads in base config and applies override in 197 * override config if any. Thus, for every GPIO_x in base config, this function 198 * looks up the GPIO in override config and if it is present there, then applies 199 * the configuration from override config. GPIOs that are only specified in the 200 * override, but not in the base configuration, will be ignored. 201 */ 202 void gpio_configure_pads_with_override(const struct pad_config *base_cfg, 203 size_t base_num_pads, 204 const struct pad_config *override_cfg, 205 size_t override_num_pads); 206 207 /* 208 * Calculate Address of DW0 register for given GPIO 209 */ 210 void *gpio_dwx_address(const gpio_t pad); 211 212 struct gpio_lock_config { 213 gpio_t pad; 214 enum gpio_lock_action lock_action; 215 }; 216 217 /* 218 * Lock a GPIO's configuration. 219 * 220 * The caller may specify if they wish to only lock the pad configuration, only 221 * the TX state, or both. When the configuration is locked, the following 222 * registers become Read-Only and software writes to these registers have no 223 * effect. 224 * 225 * Pad Configuration registers, 226 * GPI_NMI_EN, 227 * GPI_SMI_EN, 228 * GPI_GPE_EN 229 * 230 * Note that this is only effective if the pad is owned by the host and this 231 * function may only be called in SMM. 232 * 233 * @param pad: GPIO pad number 234 * @param lock_action: Which register to lock. 235 * @return 0 if successful, 236 * 1 - unsuccessful 237 * 2 - powered down 238 * 3 - multi-cast mixed 239 * -1 - sideband message failed or other error 240 */ 241 int gpio_lock_pad(const gpio_t pad, enum gpio_lock_action lock_action); 242 243 /* 244 * gpio_lock_pads() can be used to lock an array of gpio pads, avoiding 245 * the p2sb_unhide() and p2sb_hide() calls between each gpio lock that would 246 * occur if gpio_lock_pad() were used to lock each pad in the list. 247 * 248 * @param pad_list: array of gpio_lock_config structures, one for each gpio to lock 249 * @param count: number of gpio_lock_config structs in the pad_list array 250 * @return 0 if successful, 251 * 1 - unsuccessful 252 * 2 - powered down 253 * 3 - multi-cast mixed 254 * -1 - sideband message failed or other error 255 */ 256 int gpio_lock_pads(const struct gpio_lock_config *pad_list, const size_t count); 257 258 /* 259 * Returns an array of gpio_lock_config entries that the SoC 260 * deems security risks that should be locked down. 261 */ 262 const struct gpio_lock_config *soc_gpio_lock_config(size_t *num); 263 264 /* 265 * Returns the pmc_gpe to gpio_gpe mapping table 266 * 267 */ 268 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num); 269 270 /* 271 * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG 272 * are passed which is then mapped to proper groups for MISCCFG. This basically 273 * sets the MISCCFG register bits: 274 * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. 275 * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. 276 * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. 277 */ 278 void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); 279 280 /* 281 * Function returns PCR port ID for this pad 282 */ 283 uint8_t gpio_get_pad_portid(const gpio_t pad); 284 285 /* 286 * Function to patch GPIO settings for SoC specifically 287 * cfg = pad config contains pad number and reg value. 288 * dw_reg = pad config dword number. 289 * reg_val = the reg value need to be patched. 290 * Returns gpio setting patched for SoC specifically 291 */ 292 uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, 293 int dw_reg, uint32_t reg_val); 294 295 /* 296 * Function to reset/clear the GPI Interrupt Enable & Status registers for 297 * all GPIO pad communities. 298 */ 299 void gpi_clear_int_cfg(void); 300 301 /* The function performs GPIO Power Management programming. */ 302 void gpio_pm_configure(const uint8_t *misccfg_pm_values, size_t num); 303 304 /* 305 * Set gpio ops of the device to gpio block ops. 306 * Shall be called by all SoCs that use intelblocks/gpio. 307 */ 308 void block_gpio_enable(struct device *dev); 309 310 /* 311 * Returns true if any GPIO that uses the specified IRQ is also programmed to 312 * route IRQs to IOAPIC. 313 */ 314 bool gpio_routes_ioapic_irq(unsigned int irq); 315 316 size_t gpio_get_index_in_group(gpio_t pad); 317 318 /* 319 * Returns true and stuffs out params for virtual-wire index and bit position 320 * for the given GPIO, otherwise false if there is no VW index for the pad. 321 */ 322 bool gpio_get_vw_info(gpio_t pad, unsigned int *vw_index, unsigned int *vw_bit); 323 324 /* Returns PCR port ID for this pad for the CPU; will be 0 if not available */ 325 unsigned int gpio_get_pad_cpu_portid(gpio_t pad); 326 327 /* Return the gpio pad number based table */ 328 struct pad_config *new_padbased_table(void); 329 330 /* Must pass the table with pad number based */ 331 void gpio_padbased_override(struct pad_config *padbased_table, 332 const struct pad_config *override_cfg, 333 size_t override_num_pads); 334 335 /* 336 * Must pass the table with pad number based, will skip configures the unmapped 337 * pins by check pad and DW0 are 0. 338 */ 339 void gpio_configure_pads_with_padbased(struct pad_config *padbased_table); 340 341 #endif 342 #endif /* _SOC_INTELBLOCKS_GPIO_H_ */ 343