1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "dev/intel_device_info.h"
25 #include "intel_nir.h"
26 #include "isl/isl.h"
27 #include "nir_builder.h"
28
29 static bool
intel_nir_blockify_uniform_loads_instr(nir_builder * b,nir_instr * instr,void * cb_data)30 intel_nir_blockify_uniform_loads_instr(nir_builder *b,
31 nir_instr *instr,
32 void *cb_data)
33 {
34 if (instr->type != nir_instr_type_intrinsic)
35 return false;
36
37 const struct intel_device_info *devinfo = cb_data;
38
39 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
40 switch (intrin->intrinsic) {
41 case nir_intrinsic_load_ubo:
42 case nir_intrinsic_load_ssbo:
43 /* BDW PRMs, Volume 7: 3D-Media-GPGPU: OWord Block ReadWrite:
44 *
45 * "The surface base address must be OWord-aligned."
46 *
47 * We can't make that guarantee with SSBOs where the alignment is
48 * 4bytes.
49 */
50 if (devinfo->ver < 9)
51 return false;
52
53 if (nir_src_is_divergent(intrin->src[1]))
54 return false;
55
56 if (intrin->def.bit_size != 32)
57 return false;
58
59 /* Without the LSC, we can only do block loads of at least 4dwords (1
60 * oword).
61 */
62 if (!devinfo->has_lsc && intrin->def.num_components < 4)
63 return false;
64
65 intrin->intrinsic =
66 intrin->intrinsic == nir_intrinsic_load_ubo ?
67 nir_intrinsic_load_ubo_uniform_block_intel :
68 nir_intrinsic_load_ssbo_uniform_block_intel;
69 return true;
70
71 case nir_intrinsic_load_shared:
72 /* Block loads on shared memory are not supported before Icelake. */
73 if (devinfo->ver < 11)
74 return false;
75
76 if (nir_src_is_divergent(intrin->src[0]))
77 return false;
78
79 if (intrin->def.bit_size != 32)
80 return false;
81
82 /* Without the LSC, we have to use OWord Block Load messages (the one
83 * that requires OWord aligned offsets, too).
84 */
85 if (!devinfo->has_lsc &&
86 (intrin->def.num_components < 4 ||
87 nir_intrinsic_align(intrin) < 16))
88 return false;
89
90 intrin->intrinsic = nir_intrinsic_load_shared_uniform_block_intel;
91 return true;
92
93 case nir_intrinsic_load_global_constant:
94 if (nir_src_is_divergent(intrin->src[0]))
95 return false;
96
97 if (intrin->def.bit_size != 32)
98 return false;
99
100 /* Without the LSC, we can only do block loads of at least 4dwords (1
101 * oword).
102 */
103 if (!devinfo->has_lsc && intrin->def.num_components < 4)
104 return false;
105
106 intrin->intrinsic = nir_intrinsic_load_global_constant_uniform_block_intel;
107 return true;
108
109 default:
110 return false;
111 }
112 }
113
114 bool
intel_nir_blockify_uniform_loads(nir_shader * shader,const struct intel_device_info * devinfo)115 intel_nir_blockify_uniform_loads(nir_shader *shader,
116 const struct intel_device_info *devinfo)
117 {
118 return nir_shader_instructions_pass(shader,
119 intel_nir_blockify_uniform_loads_instr,
120 nir_metadata_control_flow |
121 nir_metadata_live_defs,
122 (void *) devinfo);
123 }
124