1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _input_system_defs_h 8 #define _input_system_defs_h 9 10 /* csi controller modes */ 11 #define HIVE_CSI_CONFIG_MAIN 0 12 #define HIVE_CSI_CONFIG_STEREO1 4 13 #define HIVE_CSI_CONFIG_STEREO2 8 14 15 /* general purpose register IDs */ 16 17 /* Stream Multicast select modes */ 18 #define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 19 #define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 20 #define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 21 22 /* Stream Mux select modes */ 23 #define HIVE_ISYS_GPREG_MUX_IDX 3 24 25 /* streaming monitor status and control */ 26 #define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 27 #define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 28 #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 29 #define HIVE_ISYS_GPREG_SRST_IDX 7 30 #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 31 #define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 32 #define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 33 34 /* Bit numbers of the soft reset register */ 35 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 36 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 37 #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 38 #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 39 #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 40 #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 41 #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 42 #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 43 #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 44 #define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 45 /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ 46 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ 47 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 48 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 49 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 50 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 51 #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 52 /* -- */ 53 #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 54 #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 55 #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 56 #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv 57 #define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 58 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 59 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 60 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 61 #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 62 #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 63 64 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 65 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 66 #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 67 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 68 #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 69 #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 70 71 /* streaming monitor port id's */ 72 #define HIVE_ISYS_STR_MON_PORT_CAPA 0 73 #define HIVE_ISYS_STR_MON_PORT_CAPB 1 74 #define HIVE_ISYS_STR_MON_PORT_CAPC 2 75 #define HIVE_ISYS_STR_MON_PORT_ACQ 3 76 #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 77 #define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 78 #define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 79 #define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 80 #define HIVE_ISYS_STR_MON_PORT_PIXA 8 81 #define HIVE_ISYS_STR_MON_PORT_PIXB 9 82 83 /* interrupt bit ID's */ 84 #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 85 #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 86 #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 87 #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 88 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 89 #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 90 #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 91 #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 92 /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ 93 #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 94 #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 95 /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ 96 #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 97 #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 98 /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ 99 #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 100 /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ 101 #define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 102 #define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 103 #define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 104 #define HIVE_ISYS_IRQ_CIO2AHB 16 105 #define HIVE_ISYS_IRQ_DMA_BIT_ID 17 106 #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 107 #define HIVE_ISYS_IRQ_NUM_BITS 19 108 109 /* DMA */ 110 #define HIVE_ISYS_DMA_CHANNEL 0 111 #define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 112 #define HIVE_ISYS_DMA_HEIGHT 1 113 #define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ 114 #define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ 115 #define HIVE_ISYS_DMA_CROP 0 /* no cropping */ 116 #define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ 117 118 #endif /* _input_system_defs_h */ 119