1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments System Control Interface Protocol
4 *
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6 * Nishanth Menon
7 */
8
9 #ifndef __TISCI_PROTOCOL_H
10 #define __TISCI_PROTOCOL_H
11
12 /**
13 * struct ti_sci_version_info - version information structure
14 * @abi_major: Major ABI version. Change here implies risk of backward
15 * compatibility break.
16 * @abi_minor: Minor ABI version. Change here implies new feature addition,
17 * or compatible change in ABI.
18 * @firmware_revision: Firmware revision (not usually used).
19 * @firmware_description: Firmware description (not usually used).
20 */
21 struct ti_sci_version_info {
22 u8 abi_major;
23 u8 abi_minor;
24 u16 firmware_revision;
25 char firmware_description[32];
26 };
27
28 struct ti_sci_handle;
29
30 /**
31 * struct ti_sci_core_ops - SoC Core Operations
32 * @reboot_device: Reboot the SoC
33 * Returns 0 for successful request(ideally should never return),
34 * else returns corresponding error value.
35 */
36 struct ti_sci_core_ops {
37 int (*reboot_device)(const struct ti_sci_handle *handle);
38 };
39
40 /**
41 * struct ti_sci_dev_ops - Device control operations
42 * @get_device: Command to request for device managed by TISCI
43 * Returns 0 for successful exclusive request, else returns
44 * corresponding error message.
45 * @idle_device: Command to idle a device managed by TISCI
46 * Returns 0 for successful exclusive request, else returns
47 * corresponding error message.
48 * @put_device: Command to release a device managed by TISCI
49 * Returns 0 for successful release, else returns corresponding
50 * error message.
51 * @is_valid: Check if the device ID is a valid ID.
52 * Returns 0 if the ID is valid, else returns corresponding error.
53 * @get_context_loss_count: Command to retrieve context loss counter - this
54 * increments every time the device looses context. Overflow
55 * is possible.
56 * - count: pointer to u32 which will retrieve counter
57 * Returns 0 for successful information request and count has
58 * proper data, else returns corresponding error message.
59 * @is_idle: Reports back about device idle state
60 * - req_state: Returns requested idle state
61 * Returns 0 for successful information request and req_state and
62 * current_state has proper data, else returns corresponding error
63 * message.
64 * @is_stop: Reports back about device stop state
65 * - req_state: Returns requested stop state
66 * - current_state: Returns current stop state
67 * Returns 0 for successful information request and req_state and
68 * current_state has proper data, else returns corresponding error
69 * message.
70 * @is_on: Reports back about device ON(or active) state
71 * - req_state: Returns requested ON state
72 * - current_state: Returns current ON state
73 * Returns 0 for successful information request and req_state and
74 * current_state has proper data, else returns corresponding error
75 * message.
76 * @is_transitioning: Reports back if the device is in the middle of transition
77 * of state.
78 * -current_state: Returns 'true' if currently transitioning.
79 * @set_device_resets: Command to configure resets for device managed by TISCI.
80 * -reset_state: Device specific reset bit field
81 * Returns 0 for successful request, else returns
82 * corresponding error message.
83 * @get_device_resets: Command to read state of resets for device managed
84 * by TISCI.
85 * -reset_state: pointer to u32 which will retrieve resets
86 * Returns 0 for successful request, else returns
87 * corresponding error message.
88 *
89 * NOTE: for all these functions, the following parameters are generic in
90 * nature:
91 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
92 * -id: Device Identifier
93 *
94 * Request for the device - NOTE: the client MUST maintain integrity of
95 * usage count by balancing get_device with put_device. No refcounting is
96 * managed by driver for that purpose.
97 */
98 struct ti_sci_dev_ops {
99 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
100 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
101 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
102 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
103 u32 id);
104 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
105 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
106 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
107 u32 id, u32 *count);
108 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
109 bool *requested_state);
110 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
111 bool *req_state, bool *current_state);
112 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
113 bool *req_state, bool *current_state);
114 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
115 bool *current_state);
116 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
117 u32 reset_state);
118 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
119 u32 *reset_state);
120 };
121
122 /**
123 * struct ti_sci_clk_ops - Clock control operations
124 * @get_clock: Request for activation of clock and manage by processor
125 * - needs_ssc: 'true' if Spread Spectrum clock is desired.
126 * - can_change_freq: 'true' if frequency change is desired.
127 * - enable_input_term: 'true' if input termination is desired.
128 * @idle_clock: Request for Idling a clock managed by processor
129 * @put_clock: Release the clock to be auto managed by TISCI
130 * @is_auto: Is the clock being auto managed
131 * - req_state: state indicating if the clock is auto managed
132 * @is_on: Is the clock ON
133 * - req_state: if the clock is requested to be forced ON
134 * - current_state: if the clock is currently ON
135 * @is_off: Is the clock OFF
136 * - req_state: if the clock is requested to be forced OFF
137 * - current_state: if the clock is currently Gated
138 * @set_parent: Set the clock source of a specific device clock
139 * - parent_id: Parent clock identifier to set.
140 * @get_parent: Get the current clock source of a specific device clock
141 * - parent_id: Parent clock identifier which is the parent.
142 * @get_num_parents: Get the number of parents of the current clock source
143 * - num_parents: returns the number of parent clocks.
144 * @get_best_match_freq: Find a best matching frequency for a frequency
145 * range.
146 * - match_freq: Best matching frequency in Hz.
147 * @set_freq: Set the Clock frequency
148 * @get_freq: Get the Clock frequency
149 * - current_freq: Frequency in Hz that the clock is at.
150 *
151 * NOTE: for all these functions, the following parameters are generic in
152 * nature:
153 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
154 * -did: Device identifier this request is for
155 * -cid: Clock identifier for the device for this request.
156 * Each device has it's own set of clock inputs. This indexes
157 * which clock input to modify.
158 * -min_freq: The minimum allowable frequency in Hz. This is the minimum
159 * allowable programmed frequency and does not account for clock
160 * tolerances and jitter.
161 * -target_freq: The target clock frequency in Hz. A frequency will be
162 * processed as close to this target frequency as possible.
163 * -max_freq: The maximum allowable frequency in Hz. This is the maximum
164 * allowable programmed frequency and does not account for clock
165 * tolerances and jitter.
166 *
167 * Request for the clock - NOTE: the client MUST maintain integrity of
168 * usage count by balancing get_clock with put_clock. No refcounting is
169 * managed by driver for that purpose.
170 */
171 struct ti_sci_clk_ops {
172 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
173 bool needs_ssc, bool can_change_freq,
174 bool enable_input_term);
175 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
176 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
177 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
178 bool *req_state);
179 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
180 bool *req_state, bool *current_state);
181 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
182 bool *req_state, bool *current_state);
183 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
184 u32 parent_id);
185 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
186 u32 *parent_id);
187 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
188 u32 cid, u32 *num_parents);
189 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
190 u32 cid, u64 min_freq, u64 target_freq,
191 u64 max_freq, u64 *match_freq);
192 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
193 u64 min_freq, u64 target_freq, u64 max_freq);
194 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
195 u64 *current_freq);
196 };
197
198 /* TISCI LPM IO isolation control values */
199 #define TISCI_MSG_VALUE_IO_ENABLE 1
200 #define TISCI_MSG_VALUE_IO_DISABLE 0
201
202 /* TISCI LPM constraint state values */
203 #define TISCI_MSG_CONSTRAINT_SET 1
204 #define TISCI_MSG_CONSTRAINT_CLR 0
205
206 /**
207 * struct ti_sci_pm_ops - Low Power Mode (LPM) control operations
208 * @lpm_wake_reason: Get the wake up source that woke the SoC from LPM
209 * - source: The wake up source that woke soc from LPM.
210 * - timestamp: Timestamp at which soc woke.
211 * @set_device_constraint: Set LPM constraint on behalf of a device
212 * - id: Device Identifier
213 * - state: The desired state of device constraint: set or clear.
214 * @set_latency_constraint: Set LPM resume latency constraint
215 * - latency: maximum acceptable latency to wake up from low power mode
216 * - state: The desired state of latency constraint: set or clear.
217 */
218 struct ti_sci_pm_ops {
219 int (*lpm_wake_reason)(const struct ti_sci_handle *handle,
220 u32 *source, u64 *timestamp, u8 *pin, u8 *mode);
221 int (*set_device_constraint)(const struct ti_sci_handle *handle,
222 u32 id, u8 state);
223 int (*set_latency_constraint)(const struct ti_sci_handle *handle,
224 u16 latency, u8 state);
225 };
226
227 /**
228 * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
229 * @start: Start index of the first resource range.
230 * @num: Number of resources in the first range.
231 * @start_sec: Start index of the second resource range.
232 * @num_sec: Number of resources in the second range.
233 * @res_map: Bitmap to manage the allocation of these resources.
234 */
235 struct ti_sci_resource_desc {
236 u16 start;
237 u16 num;
238 u16 start_sec;
239 u16 num_sec;
240 unsigned long *res_map;
241 };
242
243 /**
244 * struct ti_sci_rm_core_ops - Resource management core operations
245 * @get_range: Get a range of resources belonging to ti sci host.
246 * @get_rage_from_shost: Get a range of resources belonging to
247 * specified host id.
248 * - s_host: Host processing entity to which the
249 * resources are allocated
250 *
251 * NOTE: for these functions, all the parameters are consolidated and defined
252 * as below:
253 * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
254 * - dev_id: TISCI device ID.
255 * - subtype: Resource assignment subtype that is being requested
256 * from the given device.
257 * - desc: Pointer to ti_sci_resource_desc to be updated with the resource
258 * range start index and number of resources
259 */
260 struct ti_sci_rm_core_ops {
261 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
262 u8 subtype, struct ti_sci_resource_desc *desc);
263 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
264 u32 dev_id, u8 subtype, u8 s_host,
265 struct ti_sci_resource_desc *desc);
266 };
267
268 #define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0
269 #define TI_SCI_RESASG_SUBTYPE_IA_VINT 0xa
270 #define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT 0xd
271 /**
272 * struct ti_sci_rm_irq_ops: IRQ management operations
273 * @set_irq: Set an IRQ route between the requested source
274 * and destination
275 * @set_event_map: Set an Event based peripheral irq to Interrupt
276 * Aggregator.
277 * @free_irq: Free an IRQ route between the requested source
278 * and destination.
279 * @free_event_map: Free an event based peripheral irq to Interrupt
280 * Aggregator.
281 */
282 struct ti_sci_rm_irq_ops {
283 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
284 u16 src_index, u16 dst_id, u16 dst_host_irq);
285 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
286 u16 src_index, u16 ia_id, u16 vint,
287 u16 global_event, u8 vint_status_bit);
288 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
289 u16 src_index, u16 dst_id, u16 dst_host_irq);
290 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
291 u16 src_index, u16 ia_id, u16 vint,
292 u16 global_event, u8 vint_status_bit);
293 };
294
295 /* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
296 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
297 /* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
298 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
299 /* RA config.count parameter is valid for RM ring configure TI_SCI message */
300 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
301 /* RA config.mode parameter is valid for RM ring configure TI_SCI message */
302 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
303 /* RA config.size parameter is valid for RM ring configure TI_SCI message */
304 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
305 /* RA config.order_id parameter is valid for RM ring configure TISCI message */
306 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
307 /* RA config.virtid parameter is valid for RM ring configure TISCI message */
308 #define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6)
309 /* RA config.asel parameter is valid for RM ring configure TISCI message */
310 #define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7)
311
312 #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
313 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
314 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
315 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
316 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
317 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
318 TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
319
320 /**
321 * struct ti_sci_msg_rm_ring_cfg - Ring configuration
322 *
323 * Parameters for Navigator Subsystem ring configuration
324 * See @ti_sci_msg_rm_ring_cfg_req
325 */
326 struct ti_sci_msg_rm_ring_cfg {
327 u32 valid_params;
328 u16 nav_id;
329 u16 index;
330 u32 addr_lo;
331 u32 addr_hi;
332 u32 count;
333 u8 mode;
334 u8 size;
335 u8 order_id;
336 u16 virtid;
337 u8 asel;
338 };
339
340 /**
341 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
342 * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
343 */
344 struct ti_sci_rm_ringacc_ops {
345 int (*set_cfg)(const struct ti_sci_handle *handle,
346 const struct ti_sci_msg_rm_ring_cfg *params);
347 };
348
349 /**
350 * struct ti_sci_rm_psil_ops - PSI-L thread operations
351 * @pair: pair PSI-L source thread to a destination thread.
352 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
353 * TCHAN_THRD_ID register is updated.
354 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
355 * RCHAN_THRD_ID register is updated.
356 * @unpair: unpair PSI-L source thread from a destination thread.
357 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
358 * TCHAN_THRD_ID register is cleared.
359 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
360 * RCHAN_THRD_ID register is cleared.
361 */
362 struct ti_sci_rm_psil_ops {
363 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
364 u32 src_thread, u32 dst_thread);
365 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
366 u32 src_thread, u32 dst_thread);
367 };
368
369 /* UDMAP channel types */
370 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
371 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
372 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
373 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
374 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
375 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
376
377 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
378 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
379
380 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
381 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
382 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
383
384 #define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
385 #define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
386
387 /* UDMAP TX/RX channel valid_params common declarations */
388 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
389 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
390 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
391 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
392 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
393 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
394 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
395 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
396 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
397 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
398
399 /**
400 * Configures a Navigator Subsystem UDMAP transmit channel
401 *
402 * Configures a Navigator Subsystem UDMAP transmit channel registers.
403 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
404 */
405 struct ti_sci_msg_rm_udmap_tx_ch_cfg {
406 u32 valid_params;
407 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
408 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
409 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
410 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
411 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
412 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
413 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
414 u16 nav_id;
415 u16 index;
416 u8 tx_pause_on_err;
417 u8 tx_filt_einfo;
418 u8 tx_filt_pswords;
419 u8 tx_atype;
420 u8 tx_chan_type;
421 u8 tx_supr_tdpkt;
422 u16 tx_fetch_size;
423 u8 tx_credit_count;
424 u16 txcq_qnum;
425 u8 tx_priority;
426 u8 tx_qos;
427 u8 tx_orderid;
428 u16 fdepth;
429 u8 tx_sched_priority;
430 u8 tx_burst_size;
431 u8 tx_tdtype;
432 u8 extended_ch_type;
433 };
434
435 /**
436 * Configures a Navigator Subsystem UDMAP receive channel
437 *
438 * Configures a Navigator Subsystem UDMAP receive channel registers.
439 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
440 */
441 struct ti_sci_msg_rm_udmap_rx_ch_cfg {
442 u32 valid_params;
443 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
444 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
445 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
446 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
447 u16 nav_id;
448 u16 index;
449 u16 rx_fetch_size;
450 u16 rxcq_qnum;
451 u8 rx_priority;
452 u8 rx_qos;
453 u8 rx_orderid;
454 u8 rx_sched_priority;
455 u16 flowid_start;
456 u16 flowid_cnt;
457 u8 rx_pause_on_err;
458 u8 rx_atype;
459 u8 rx_chan_type;
460 u8 rx_ignore_short;
461 u8 rx_ignore_long;
462 u8 rx_burst_size;
463 };
464
465 /**
466 * Configures a Navigator Subsystem UDMAP receive flow
467 *
468 * Configures a Navigator Subsystem UDMAP receive flow's registers.
469 * See @tis_ci_msg_rm_udmap_flow_cfg_req
470 */
471 struct ti_sci_msg_rm_udmap_flow_cfg {
472 u32 valid_params;
473 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
474 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
475 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
476 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
477 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
478 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
479 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
480 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
481 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
482 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
483 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
484 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
485 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
486 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
487 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
488 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
489 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
490 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
491 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
492 u16 nav_id;
493 u16 flow_index;
494 u8 rx_einfo_present;
495 u8 rx_psinfo_present;
496 u8 rx_error_handling;
497 u8 rx_desc_type;
498 u16 rx_sop_offset;
499 u16 rx_dest_qnum;
500 u8 rx_src_tag_hi;
501 u8 rx_src_tag_lo;
502 u8 rx_dest_tag_hi;
503 u8 rx_dest_tag_lo;
504 u8 rx_src_tag_hi_sel;
505 u8 rx_src_tag_lo_sel;
506 u8 rx_dest_tag_hi_sel;
507 u8 rx_dest_tag_lo_sel;
508 u16 rx_fdq0_sz0_qnum;
509 u16 rx_fdq1_qnum;
510 u16 rx_fdq2_qnum;
511 u16 rx_fdq3_qnum;
512 u8 rx_ps_location;
513 };
514
515 /**
516 * struct ti_sci_rm_udmap_ops - UDMA Management operations
517 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
518 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
519 * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
520 */
521 struct ti_sci_rm_udmap_ops {
522 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
523 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
524 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
525 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
526 int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
527 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
528 };
529
530 /**
531 * struct ti_sci_proc_ops - Processor Control operations
532 * @request: Request to control a physical processor. The requesting host
533 * should be in the processor access list
534 * @release: Relinquish a physical processor control
535 * @handover: Handover a physical processor control to another host
536 * in the permitted list
537 * @set_config: Set base configuration of a processor
538 * @set_control: Setup limited control flags in specific cases
539 * @get_status: Get the state of physical processor
540 *
541 * NOTE: The following paramteres are generic in nature for all these ops,
542 * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
543 * -pid: Processor ID
544 * -hid: Host ID
545 */
546 struct ti_sci_proc_ops {
547 int (*request)(const struct ti_sci_handle *handle, u8 pid);
548 int (*release)(const struct ti_sci_handle *handle, u8 pid);
549 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
550 int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
551 u64 boot_vector, u32 cfg_set, u32 cfg_clr);
552 int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
553 u32 ctrl_set, u32 ctrl_clr);
554 int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
555 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
556 u32 *status_flags);
557 };
558
559 /**
560 * struct ti_sci_ops - Function support for TI SCI
561 * @dev_ops: Device specific operations
562 * @clk_ops: Clock specific operations
563 * @rm_core_ops: Resource management core operations.
564 * @rm_irq_ops: IRQ management specific operations
565 * @proc_ops: Processor Control specific operations
566 */
567 struct ti_sci_ops {
568 struct ti_sci_core_ops core_ops;
569 struct ti_sci_dev_ops dev_ops;
570 struct ti_sci_clk_ops clk_ops;
571 struct ti_sci_pm_ops pm_ops;
572 struct ti_sci_rm_core_ops rm_core_ops;
573 struct ti_sci_rm_irq_ops rm_irq_ops;
574 struct ti_sci_rm_ringacc_ops rm_ring_ops;
575 struct ti_sci_rm_psil_ops rm_psil_ops;
576 struct ti_sci_rm_udmap_ops rm_udmap_ops;
577 struct ti_sci_proc_ops proc_ops;
578 };
579
580 /**
581 * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
582 * @version: structure containing version information
583 * @ops: operations that are made available to TI SCI clients
584 */
585 struct ti_sci_handle {
586 struct ti_sci_version_info version;
587 struct ti_sci_ops ops;
588 };
589
590 #define TI_SCI_RESOURCE_NULL 0xffff
591
592 /**
593 * struct ti_sci_resource - Structure representing a resource assigned
594 * to a device.
595 * @sets: Number of sets available from this resource type
596 * @lock: Lock to guard the res map in each set.
597 * @desc: Array of resource descriptors.
598 */
599 struct ti_sci_resource {
600 u16 sets;
601 raw_spinlock_t lock;
602 struct ti_sci_resource_desc *desc;
603 };
604
605 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
606 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
607 int ti_sci_put_handle(const struct ti_sci_handle *handle);
608 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
609 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
610 const char *property);
611 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
612 const char *property);
613 u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
614 void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
615 u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
616 struct ti_sci_resource *
617 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
618 struct device *dev, u32 dev_id, char *of_prop);
619 struct ti_sci_resource *
620 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
621 u32 dev_id, u32 sub_type);
622
623 #else /* CONFIG_TI_SCI_PROTOCOL */
624
ti_sci_get_handle(struct device * dev)625 static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
626 {
627 return ERR_PTR(-EINVAL);
628 }
629
ti_sci_put_handle(const struct ti_sci_handle * handle)630 static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
631 {
632 return -EINVAL;
633 }
634
635 static inline
devm_ti_sci_get_handle(struct device * dev)636 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
637 {
638 return ERR_PTR(-EINVAL);
639 }
640
641 static inline
ti_sci_get_by_phandle(struct device_node * np,const char * property)642 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
643 const char *property)
644 {
645 return ERR_PTR(-EINVAL);
646 }
647
648 static inline
devm_ti_sci_get_by_phandle(struct device * dev,const char * property)649 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
650 const char *property)
651 {
652 return ERR_PTR(-EINVAL);
653 }
654
ti_sci_get_free_resource(struct ti_sci_resource * res)655 static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
656 {
657 return TI_SCI_RESOURCE_NULL;
658 }
659
ti_sci_release_resource(struct ti_sci_resource * res,u16 id)660 static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
661 {
662 }
663
ti_sci_get_num_resources(struct ti_sci_resource * res)664 static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
665 {
666 return 0;
667 }
668
669 static inline struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle * handle,struct device * dev,u32 dev_id,char * of_prop)670 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
671 struct device *dev, u32 dev_id, char *of_prop)
672 {
673 return ERR_PTR(-EINVAL);
674 }
675
676 static inline struct ti_sci_resource *
devm_ti_sci_get_resource(const struct ti_sci_handle * handle,struct device * dev,u32 dev_id,u32 sub_type)677 devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
678 u32 dev_id, u32 sub_type)
679 {
680 return ERR_PTR(-EINVAL);
681 }
682 #endif /* CONFIG_TI_SCI_PROTOCOL */
683
684 #endif /* __TISCI_PROTOCOL_H */
685