1 /*
2 * Copyright © 2022 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "i915/intel_engine.h"
25
26 #include <stdlib.h>
27
28 #include "i915/intel_gem.h"
29
30 static enum intel_engine_class
i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915)31 i915_engine_class_to_intel(enum drm_i915_gem_engine_class i915)
32 {
33 switch (i915) {
34 case I915_ENGINE_CLASS_RENDER:
35 return INTEL_ENGINE_CLASS_RENDER;
36 case I915_ENGINE_CLASS_COPY:
37 return INTEL_ENGINE_CLASS_COPY;
38 case I915_ENGINE_CLASS_VIDEO:
39 return INTEL_ENGINE_CLASS_VIDEO;
40 case I915_ENGINE_CLASS_VIDEO_ENHANCE:
41 return INTEL_ENGINE_CLASS_VIDEO_ENHANCE;
42 case I915_ENGINE_CLASS_COMPUTE:
43 return INTEL_ENGINE_CLASS_COMPUTE;
44 default:
45 return INTEL_ENGINE_CLASS_INVALID;
46 }
47 }
48
49 enum drm_i915_gem_engine_class
intel_engine_class_to_i915(enum intel_engine_class intel)50 intel_engine_class_to_i915(enum intel_engine_class intel)
51 {
52 switch (intel) {
53 case INTEL_ENGINE_CLASS_RENDER:
54 return I915_ENGINE_CLASS_RENDER;
55 case INTEL_ENGINE_CLASS_COPY:
56 return I915_ENGINE_CLASS_COPY;
57 case INTEL_ENGINE_CLASS_VIDEO:
58 return I915_ENGINE_CLASS_VIDEO;
59 case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
60 return I915_ENGINE_CLASS_VIDEO_ENHANCE;
61 case INTEL_ENGINE_CLASS_COMPUTE:
62 return I915_ENGINE_CLASS_COMPUTE;
63 default:
64 return I915_ENGINE_CLASS_INVALID;
65 }
66 }
67
68 struct intel_query_engine_info *
i915_engine_get_info(int fd)69 i915_engine_get_info(int fd)
70 {
71 struct drm_i915_query_engine_info *i915_engines_info;
72 i915_engines_info = intel_i915_query_alloc(fd, DRM_I915_QUERY_ENGINE_INFO, NULL);
73 if (!i915_engines_info)
74 return NULL;
75
76 struct intel_query_engine_info *intel_engines_info;
77 intel_engines_info = calloc(1, sizeof(*intel_engines_info) +
78 sizeof(*intel_engines_info->engines) *
79 i915_engines_info->num_engines);
80 if (!intel_engines_info) {
81 free(i915_engines_info);
82 return NULL;
83 }
84
85 for (int i = 0; i < i915_engines_info->num_engines; i++) {
86 struct drm_i915_engine_info *i915_engine = &i915_engines_info->engines[i];
87 struct intel_engine_class_instance *intel_engine = &intel_engines_info->engines[i];
88
89 intel_engine->engine_class = i915_engine_class_to_intel(i915_engine->engine.engine_class);
90 intel_engine->engine_instance = i915_engine->engine.engine_instance;
91 intel_engine->gt_id = 0;
92 }
93
94 intel_engines_info->num_engines = i915_engines_info->num_engines;
95
96 free(i915_engines_info);
97 return intel_engines_info;
98 }
99
100 bool
i915_engines_is_guc_semaphore_functional(int fd,const struct intel_device_info * info)101 i915_engines_is_guc_semaphore_functional(int fd, const struct intel_device_info *info)
102 {
103 struct drm_i915_query_guc_submission_version *guc_submission_ver =
104 intel_i915_query_alloc(fd, DRM_I915_QUERY_GUC_SUBMISSION_VERSION, NULL);
105 uint32_t read_ver, min_ver;
106
107 if (guc_submission_ver == NULL)
108 return false;
109
110 /* branch == 0 is mainline branch, any other branch value indicates that
111 * other version numbers cannot be used to infer whether features or fixes
112 * are present in the release.
113 *
114 * major, minor and patch are u8 for GuC, uAPI have it as u32 because of HuC.
115 */
116 if (guc_submission_ver->branch == 0) {
117 read_ver = guc_submission_ver->major << 16;
118 read_ver |= guc_submission_ver->minor << 8;
119 read_ver |= guc_submission_ver->patch;
120 } else {
121 read_ver = 0;
122 }
123
124 free(guc_submission_ver);
125
126 /* Requires at least GuC submission version 1.1.3 */
127 min_ver = 1ULL << 16 | 1ULL << 8 | 3;
128
129 return read_ver >= min_ver;
130 }
131