1 /***********************************************************************************************************************
2 * Copyright [2015-2017] Renesas Electronics Corporation and/or its licensors. All Rights Reserved.
3 *
4 * This file is part of Renesas SynergyTM Software Package (SSP)
5 *
6 * The contents of this file (the "contents") are proprietary and confidential to Renesas Electronics Corporation
7 * and/or its licensors ("Renesas") and subject to statutory and contractual protections.
8 *
9 * This file is subject to a Renesas SSP license agreement. Unless otherwise agreed in an SSP license agreement with
10 * Renesas: 1) you may not use, copy, modify, distribute, display, or perform the contents; 2) you may not use any name
11 * or mark of Renesas for advertising or publicity purposes or in connection with your use of the contents; 3) RENESAS
12 * MAKES NO WARRANTY OR REPRESENTATIONS ABOUT THE SUITABILITY OF THE CONTENTS FOR ANY PURPOSE; THE CONTENTS ARE PROVIDED
13 * "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
14 * PARTICULAR PURPOSE, AND NON-INFRINGEMENT; AND 4) RENESAS SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, OR
15 * CONSEQUENTIAL DAMAGES, INCLUDING DAMAGES RESULTING FROM LOSS OF USE, DATA, OR PROJECTS, WHETHER IN AN ACTION OF
16 * CONTRACT OR TORT, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THE CONTENTS. Third-party contents
17 * included in this file may be subject to different terms.
18 **********************************************************************************************************************/
19 /**********************************************************************************************************************
20 * File Name : hw_sci_uart_private.h
21 * @brief SCI HAL driver for UART
22 ***********************************************************************************************************************/
23 #ifndef HW_SCI_UART_PRIVATE_H
24 #define HW_SCI_UART_PRIVATE_H
25
26 /***********************************************************************************************************************
27 Includes
28 ***********************************************************************************************************************/
29 /* Includes board and MCU related header files. */
30 #include "bsp_api.h"
31 /* Public interface header file for this module. */
32 #include "r_sci_uart.h"
33
34 /* Common macro for SSP header files. There is also a corresponding SSP_FOOTER macro at the end of this file. */
35 SSP_HEADER
36
37 /***********************************************************************************************************************
38 Macro definitions
39 ***********************************************************************************************************************/
40 #define RDR_TDAT_MASK_8BITS (0x00FFU)
41 #define TDR_TDAT_MASK_9BITS (0x01FFU)
42 #define RDR_TDAT_MASK_9BITS (0x01FFU)
43 #define FTDR_TDAT_MASK_8BITS (0x00FFU)
44 #define FTDR_TDAT_MASK_9BITS (0x01FFU)
45 #define FRDR_TDAT_MASK_8BITS (0x00FFU)
46 #define FRDR_TDAT_MASK_9BITS (0x01FFU)
47 #define FCR_RTRG_MASK_4BITS (0x000FU)
48 #define SPTR_SPB2D_BIT (1U)
49 #define SPTR_OUTPUT_ENABLE_MASK (0x04U)
50 #define SCI_SCR_TE_MASK (0x20U)
51 #define SCI_SCR_RE_MASK (0x10U)
52 #define SCI_SCR_TIE_MASK (0x80U)
53 #define SCI_SCR_RIE_MASK (0x40U)
54 #define SCI_SCR_TEIE_MASK (0x04U)
55
56
57 /***********************************************************************************************************************
58 Typedef definitions
59 ***********************************************************************************************************************/
60
61 /***********************************************************************************************************************
62 Private function prototypes
63 ***********************************************************************************************************************/
64
65 /***********************************************************************************************************************
66 Private global variables
67 ***********************************************************************************************************************/
68
69 /***********************************************************************************************************************
70 Private Functions
71 ***********************************************************************************************************************/
72
73 /*******************************************************************************************************************//**
74 * @brief Enable FIFO mode
75 * @param[in] p_reg SCI base register
76 * @retval void
77 * @note Channel number is not checked in this function, caller function must check it.
78 ***********************************************************************************************************************/
HW_SCI_FifoEnable(R_SCI0_Type * p_reg)79 __STATIC_INLINE void HW_SCI_FifoEnable (R_SCI0_Type * p_reg)
80 {
81 p_reg->FCR_b.FM = 1U; /* FCRL.FM (select FIFO mode) */
82 } /* End of function HW_SCI_FifoEnable() */
83
84 /*******************************************************************************************************************//**
85 * @brief Receive FIFO reset
86 * @param[in] p_reg SCI base register
87 * @retval void
88 * @note Channel number is not checked in this function, caller function must check it.
89 ***********************************************************************************************************************/
HW_SCI_ReceiveFifoReset(R_SCI0_Type * p_reg)90 __STATIC_INLINE void HW_SCI_ReceiveFifoReset (R_SCI0_Type * p_reg)
91 {
92 p_reg->FCR_b.RFRST = 1U; /* FCRL.RFRST (reset Receive FIFO Data Register) */
93 } /* End of function HW_SCI_ReceiveFifoReset() */
94
95 /*******************************************************************************************************************//**
96 * @brief Select RXI event which happens when detecting a reception data ready
97 * @param[in] p_reg SCI base register
98 * @retval void
99 * @note Channel number is not checked in this function, caller function must check it.
100 ***********************************************************************************************************************/
HW_SCI_RXIeventSelect(R_SCI0_Type * p_reg)101 __STATIC_INLINE void HW_SCI_RXIeventSelect (R_SCI0_Type * p_reg)
102 {
103 p_reg->FCR_b.DRES = 0U; /* FCRL.DRES (select RXI happen when detecting a reception data ready) */
104 } /* End of function HW_SCI_RXIeventSelect() */
105
106 /*******************************************************************************************************************//**
107 * @brief RXI happens when number of received data in FIFO becomes equal or greater than this value
108 * @param[in] p_reg SCI base register
109 * @param[in] number Receive trigger number
110 * @retval void
111 * @note Channel number is not checked in this function, caller function must check it.
112 ***********************************************************************************************************************/
HW_SCI_RxTriggerNumberSet(R_SCI0_Type * p_reg,uint16_t const number)113 __STATIC_INLINE void HW_SCI_RxTriggerNumberSet (R_SCI0_Type * p_reg, uint16_t const number)
114 {
115 /* FCRL.RTRG (RXI happens when number of received data in FIFO becomes equal or greater than this value) */
116 p_reg->FCR_b.RTRG = number & FCR_RTRG_MASK_4BITS;
117 } /* End of function HW_SCI_RxTriggerNumberSet() */
118
119 /*******************************************************************************************************************//**
120 * @brief RTS signal is asserted when number of receive data in FIFO becomes equal or less than this value
121 * @param[in] p_reg SCI base register
122 * @param[in] number RTS trigger number
123 * @retval void
124 * @note Channel number is not checked in this function, caller function must check it.
125 ***********************************************************************************************************************/
HW_SCI_RTSTriggerNumberSet(R_SCI0_Type * p_reg,uint16_t const number)126 __STATIC_INLINE void HW_SCI_RTSTriggerNumberSet (R_SCI0_Type * p_reg, uint16_t const number)
127 {
128 /* FCRL.RSTRG (RTS asserts when number of receive data comes equal or less than this value ) */
129 p_reg->FCR_b.RSTRG = (uint16_t) (number & 0xF);
130 } /* End of function HW_SCI_RTSTriggerNumberSet() */
131
132 /*******************************************************************************************************************//**
133 * @brief Transmit FIFO reset
134 * @param[in] p_reg SCI base register
135 * @retval void
136 * @note Channel number is not checked in this function, caller function must check it.
137 ***********************************************************************************************************************/
HW_SCI_TransmitFifoReset(R_SCI0_Type * p_reg)138 __STATIC_INLINE void HW_SCI_TransmitFifoReset (R_SCI0_Type * p_reg)
139 {
140 p_reg->FCR_b.TFRST = 1U; /* FCRL.TFRST (reset Transmit FIFO Data Register) */
141 while(p_reg->FCR_b.TFRST)
142 {
143 /* Wait until RFRST cleared */
144 }
145 } /* End of function HW_SCI_TransmitFifoReset() */
146
147 /*******************************************************************************************************************//**
148 * @brief TXI happens when number of transmit data becomes equal or less than this value
149 * @param[in] p_reg SCI base register
150 * @param[in] number Transmit trigger number
151 * @retval void
152 * @note Channel number is not checked in this function, caller function must check it.
153 ***********************************************************************************************************************/
HW_SCI_TxTriggerNumberSet(R_SCI0_Type * p_reg,uint16_t const number)154 __STATIC_INLINE void HW_SCI_TxTriggerNumberSet (R_SCI0_Type * p_reg, uint16_t const number)
155 {
156 /* FCRL.TTRG (TXI happens when number of transmit data comes equal or less than this value ) */
157 p_reg->FCR_b.TTRG = number & 0xFU;
158 } /* End of function HW_SCI_TxTriggerNumberSet() */
159
160 /*******************************************************************************************************************//**
161 * @brief This function sets the parity based on user configuration.
162 * @param[in] p_reg SCI base register
163 * @param[in] parity Parity to set
164 * @retval void
165 * @note Channel number is not checked in this function, caller function must check it.
166 ***********************************************************************************************************************/
HW_SCI_ParitySet(R_SCI0_Type * p_reg,uart_parity_t parity)167 __STATIC_INLINE void HW_SCI_ParitySet (R_SCI0_Type * p_reg, uart_parity_t parity)
168 {
169 p_reg->SMR |= (uint8_t) ((uint8_t) parity << 4U); /* Set the SMR.PE bit (Parity Enable) */
170 } /* End of function HW_SCI_ParitySet() */
171
172 /*******************************************************************************************************************//**
173 * @brief This function selects 7-bit data length
174 * @param[in] p_reg SCI base register
175 * @retval void
176 * @note Channel number is not checked in this function, caller function must check it.
177 ***********************************************************************************************************************/
HW_SCI_DataBits7bitsSelect(R_SCI0_Type * p_reg)178 __STATIC_INLINE void HW_SCI_DataBits7bitsSelect (R_SCI0_Type * p_reg)
179 {
180 /* Set the SMR.CM bit to 0 (0: Communications Mode = Asynchronous) */
181 /* Set the SMR.CHR bit & SCMR.CHR1 bit as selected (Character Length)
182 * Character Length
183 * (CHR1,CHR)
184 * (1, 1) Transmit/receive in 7-bit data length*3
185 */
186 p_reg->SMR_b.CHR = 1U;
187 p_reg->SCMR_b.CHR1 = 1U;
188 } /* End of function HW_SCI_DataBits7bitsSelect() */
189
190 /*******************************************************************************************************************//**
191 * @brief This function selects 9-bit data length
192 * @param[in] p_reg SCI base register
193 * @retval void
194 * @note Channel number is not checked in this function, caller function must check it.
195 ***********************************************************************************************************************/
HW_SCI_DataBits9bitsSelect(R_SCI0_Type * p_reg)196 __STATIC_INLINE void HW_SCI_DataBits9bitsSelect (R_SCI0_Type * p_reg)
197 {
198 /* Set the SMR.CM bit to 0 (0: Communications Mode = Asynchronous) */
199 /* Set the SMR.CHR bit & SCMR.CHR1 bit as selected (Character Length)
200 * Character Length
201 * (CHR1,CHR)
202 * (0, 0) Transmit/receive in 9-bit data length
203 */
204 p_reg->SMR_b.CHR = 0U;
205 p_reg->SCMR_b.CHR1 = 0U;
206 } /* End of function HW_SCI_DataBits9bitsSelect() */
207
208 /*******************************************************************************************************************//**
209 * @brief This function selects number of stop-bits as per user configuration
210 * @param[in] p_reg SCI base register
211 * @param[in] stop_bits Stop bits setting
212 * @retval void
213 ***********************************************************************************************************************/
HW_SCI_StopBitsSelect(R_SCI0_Type * p_reg,uart_stop_bits_t stop_bits)214 __STATIC_INLINE void HW_SCI_StopBitsSelect (R_SCI0_Type * p_reg, uart_stop_bits_t stop_bits)
215 {
216 p_reg->SMR_b.STOP = stop_bits;
217 } /* End of function HW_SCI_StopBitsSelect() */
218
219 /*******************************************************************************************************************//**
220 * @brief This function writes data to transmit data register.
221 * @param[in] p_reg SCI base register
222 * @param[in] data Data to be sent
223 * @retval void
224 * @note All the parameter check must be handled by HLD
225 ***********************************************************************************************************************/
HW_SCI_Write9bits(R_SCI0_Type * p_reg,uint16_t const data)226 __STATIC_INLINE void HW_SCI_Write9bits (R_SCI0_Type * p_reg, uint16_t const data)
227 {
228 while (0U == p_reg->SSR_b.TDRE)
229 {
230 /* Wait until TDRE is cleared */
231 }
232
233 /* Write 9-bit data. */
234 p_reg->TDRHL = data;
235
236 return;
237 } /* End of function HW_SCI_Write9bits() */
238
239 /*******************************************************************************************************************//**
240 * @brief This function reads data from receive data register, read in order from Higher byte to Lower bytes.
241 * @param[in] p_reg SCI Channel number
242 * @retval Received data
243 * @note Channel number is not checked in this function, caller function must check it.
244 ***********************************************************************************************************************/
HW_SCI_Read9bits(R_SCI0_Type * p_reg)245 __STATIC_INLINE uint16_t HW_SCI_Read9bits (R_SCI0_Type * p_reg)
246 {
247 uint16_t temp_data;
248 temp_data = (uint16_t)((p_reg->RDRH) << 8U);
249 temp_data |= (uint16_t)(p_reg->RDRL);
250 return temp_data;
251 } /* End of function HW_SCI_Read9bits() */
252
253 /*******************************************************************************************************************//**
254 * @brief This function returns the address of the write FIFO
255 * @param[in] p_reg SCI channel
256 * @param[in] data_bytes Size of each data to transmit or receive
257 * @retval void
258 * @note Channel number is not checked in this function, caller function must check it.
259 ***********************************************************************************************************************/
HW_SCI_WriteAddrGet(R_SCI0_Type * p_reg,uint32_t data_bytes)260 __STATIC_INLINE void * HW_SCI_WriteAddrGet (R_SCI0_Type * p_reg, uint32_t data_bytes)
261 {
262 if (2U == data_bytes)
263 {
264 /* Casting for compatibility with 7 or 8 bit mode. */
265 return (void *) (&(p_reg->FTDR));
266 }
267 else
268 {
269 /* Casting for compatibility with 7 or 8 bit mode. */
270 return (void *) ((uint32_t) (&p_reg->FTDR) + 1);
271 }
272 } /* End of function HW_SCI_WriteAddrGet() */
273
274 /*******************************************************************************************************************//**
275 * @brief This function returns the address of the write non FIFO
276 * @param[in] p_reg SCI channel
277 * @param[in] data_bytes Size of each data to transmit or receive
278 * @retval void
279 * @note Channel number is not checked in this function, caller function must check it.
280 ***********************************************************************************************************************/
HW_SCI_Non_FIFO_WriteAddrGet(R_SCI0_Type * p_reg,uint32_t data_bytes)281 __STATIC_INLINE void * HW_SCI_Non_FIFO_WriteAddrGet (R_SCI0_Type * p_reg, uint32_t data_bytes)
282 {
283 if (1U == data_bytes)
284 {
285 /* Casting for compatibility with 7 or 8 bit mode. */
286 return (void *) (&(p_reg->TDR));
287 }
288 else
289 {
290 /* Casting for compatibility with 7 or 8 bit mode. */
291 return (void *) ((uint32_t) &(p_reg->TDRHL));
292 }
293 } /* End of function HW_SCI_Non_FIFO_WriteAddrGet() */
294
295 /*******************************************************************************************************************//**
296 * @brief This function writes data to transmit FIFO register
297 * @param[in] p_reg SCI channel
298 * @param[in] data Data to be sent
299 * @retval void
300 * @note Channel number is not checked in this function, caller function must check it.
301 ***********************************************************************************************************************/
HW_SCI_WriteFIFO(R_SCI0_Type * p_reg,uint16_t const data)302 __STATIC_INLINE void HW_SCI_WriteFIFO(R_SCI0_Type * p_reg, uint16_t const data)
303 {
304 while (0U == p_reg->SSR_b.TDRE)
305 {
306 /* Wait until TDRE is cleared */
307 }
308
309 /* Write data to FTDRx register */
310 p_reg->FTDR = data;
311
312 return;
313 } /* End of function HW_SCI_WriteFIFO() */
314
315 /*******************************************************************************************************************//**
316 * @brief This function returns the address of the read FIFO.
317 * @param[in] p_reg SCI Channel number
318 * @param[in] data_bytes Size of each data to transmit or receive
319 * @retval void
320 * @note Channel number is not checked in this function, caller function must check it.
321 ***********************************************************************************************************************/
HW_SCI_ReadAddrGet(R_SCI0_Type * p_reg,uint32_t data_bytes)322 __STATIC_INLINE void const * HW_SCI_ReadAddrGet (R_SCI0_Type * p_reg, uint32_t data_bytes)
323 {
324 if (2U == data_bytes)
325 {
326 /* Casting for compatibility with 7 or 8 bit mode. */
327 return (void const *) (&(p_reg->FRDRH));
328 }
329 else
330 {
331 /* Casting for compatibility with 7 or 8 bit mode. */
332 return (void const *) ((uint32_t) &(p_reg->FRDRH) + 1);
333 }
334 } /* End of function HW_SCI_ReadAddrGet() */
335
336 /*******************************************************************************************************************//**
337 * @brief This function returns the address of the read non FIFO.
338 * @param[in] p_reg SCI Channel number
339 * @param[in] data_bytes Size of each data to transmit or receive
340 * @retval void
341 * @note Channel number is not checked in this function, caller function must check it.
342 ***********************************************************************************************************************/
HW_SCI_Non_FIFO_ReadAddrGet(R_SCI0_Type * p_reg,uint32_t data_bytes)343 __STATIC_INLINE void const * HW_SCI_Non_FIFO_ReadAddrGet (R_SCI0_Type * p_reg, uint32_t data_bytes)
344 {
345 if (1U == data_bytes)
346 {
347 /* Casting for compatibility with 7 or 8 bit mode. */
348 return (void const *) (&(p_reg->RDR));
349 }
350 else
351 {
352 /* Casting for compatibility with 7 or 8 bit mode. */
353 return (void const *) ((uint32_t) &(p_reg->RDRH));
354 }
355 } /* End of function HW_SCI_Non_FIFO_ReadAddrGet() */
356
357 /*******************************************************************************************************************//**
358 * @brief This function reads data from receive FIFO register, read in order from FRDRH to FRDRL.
359 * @param[in] p_reg SCI Channel number
360 * @retval Received data and related status information
361 * @note Channel number is not checked in this function, caller function must check it.
362 ***********************************************************************************************************************/
HW_SCI_ReadFIFO(R_SCI0_Type * p_reg)363 __STATIC_INLINE uint16_t HW_SCI_ReadFIFO (R_SCI0_Type * p_reg)
364 {
365 uint16_t temp_data;
366 temp_data = (uint16_t)((p_reg->FRDRH) << 8U);
367 temp_data |= (uint16_t)(p_reg->FRDRL);
368 return (temp_data & FRDR_TDAT_MASK_9BITS);
369 } /* End of function HW_SCI_ReadFIFO() */
370
371 /*******************************************************************************************************************//**
372 * @brief This function clears TDFE flag
373 * @param[in] p_reg SCI Channel number
374 * @retval none
375 * @note Channel number is not checked in this function, caller function must check it.
376 ***********************************************************************************************************************/
HW_SCI_TDFEClear(R_SCI0_Type * p_reg)377 __STATIC_INLINE void HW_SCI_TDFEClear (R_SCI0_Type * p_reg)
378 {
379 /* Clear TDFE flag */
380 p_reg->SSR_FIFO_b.TDFE = 0U;
381 } /* End of function HW_SCI_TDFEClear() */
382
383 /*******************************************************************************************************************//**
384 * @brief This function clears RDF flag
385 * @param[in] p_reg SCI Channel number
386 * @retval none
387 * @note Channel number is not checked in this function, caller function must check it.
388 ***********************************************************************************************************************/
HW_SCI_RDFClear(R_SCI0_Type * p_reg)389 __STATIC_INLINE void HW_SCI_RDFClear (R_SCI0_Type * p_reg)
390 {
391 /* Clear RDF flag */
392 p_reg->SSR_FIFO = 0xBFU;
393 } /* End of function HW_SCI_RDFClear() */
394
395 /*******************************************************************************************************************//**
396 * @brief This function clear DR flag.
397 * @param[in] p_reg SCI Channel number
398 * @retval none
399 * @note Channel number is not checked in this function, caller function must check it.
400 ***********************************************************************************************************************/
HW_SCI_DRClear(R_SCI0_Type * p_reg)401 __STATIC_INLINE void HW_SCI_DRClear (R_SCI0_Type * p_reg)
402 {
403 /* Clear DR flag */
404 p_reg->SSR_FIFO = 0xFEU;
405 } /* End of function HW_SCI_DRClear() */
406
407
408 /*******************************************************************************************************************//**
409 *@brief Get the state of Receive Data Ready Flag (DR).
410 *@param[in] p_reg SCI Channel number.
411 * @return The state of the DR bit.
412 **********************************************************************************************************************/
HW_SCI_DRBitGet(R_SCI0_Type * p_reg)413 __STATIC_INLINE bool HW_SCI_DRBitGet (R_SCI0_Type * p_reg)
414 {
415 return (bool) p_reg->SSR_FIFO_b.DR;
416 }/* End of function HW_SCI_DRbitGet() */
417
418 /*******************************************************************************************************************//**
419 * @brief This function reads data number in transmit FIFO
420 * @param[in] p_reg SCI Channel number
421 * @retval Data number in transmit FIFO
422 * @note Channel number is not checked in this function, caller function must check it.
423 ***********************************************************************************************************************/
HW_SCI_FIFO_WriteCount(R_SCI0_Type * p_reg)424 __STATIC_INLINE uint32_t HW_SCI_FIFO_WriteCount (R_SCI0_Type * p_reg)
425 {
426 return (uint32_t)(p_reg->FDR_b.T);
427 } /* End of function HW_SCI_FIFO_WriteCount() */
428
429 /*******************************************************************************************************************//**
430 * @brief This function reads data number in receive FIFO
431 * @param[in] p_reg SCI Channel number
432 * @retval Data number in receive FIFO
433 * @note Channel number is not checked in this function, caller function must check it.
434 ***********************************************************************************************************************/
HW_SCI_FIFO_ReadCount(R_SCI0_Type * p_reg)435 __STATIC_INLINE uint32_t HW_SCI_FIFO_ReadCount (R_SCI0_Type * p_reg)
436 {
437 return (uint32_t)(p_reg->FDR_b.R);
438 } /* End of function HW_SCI_FIFO_ReadCount() */
439
440 /*******************************************************************************************************************//**
441 * @brief Enables CTS
442 * @param[in] p_reg SCI base register
443 * @retval void
444 * @note Channel number is not checked in this function, caller function must check it.
445 ***********************************************************************************************************************/
HW_SCI_CtsInEnable(R_SCI0_Type * p_reg)446 __STATIC_INLINE void HW_SCI_CtsInEnable (R_SCI0_Type * p_reg)
447 {
448 p_reg->SPMR_b.CTSE = 1U; /* enables CTS (disables RTS) */
449 } /* End of function HW_SCI_CtsInEnable() */
450
451 /*******************************************************************************************************************//**
452 * @brief Sets start bit detection when RXDn has falling edge if enabled is true.
453 * This mode stops data reception during BREAK condition.
454 * @param[in] p_reg SCI base register
455 * @param[in] enabled Reception on falling edge enabled
456 * @retval void
457 * @note Channel number is not checked in this function, caller function must check it.
458 ***********************************************************************************************************************/
HW_SCI_StartBitSet(R_SCI0_Type * p_reg,bool enabled)459 __STATIC_INLINE void HW_SCI_StartBitSet (R_SCI0_Type * p_reg, bool enabled)
460 {
461 p_reg->SEMR_b.RXDESEL = (uint8_t) (enabled & 1U); /* detect start bit if RXDn has falling edge */
462 } /* End of function HW_SCI_StartBitSet() */
463
464 /*******************************************************************************************************************//**
465 * Sets transmitter level.
466 * @param[in] p_reg SCI base register
467 * @param[in] level Default level of transmit pin, 0 is low, 1 is high
468 * @retval void
469 * @note Channel number is not checked in this function, caller function must check it.
470 ***********************************************************************************************************************/
HW_SCI_TransmitterLevelSet(R_SCI0_Type * p_reg,uint8_t level)471 __STATIC_INLINE void HW_SCI_TransmitterLevelSet (R_SCI0_Type * p_reg, uint8_t level)
472 {
473 p_reg->SPTR = (uint8_t) (level << SPTR_SPB2D_BIT) | SPTR_OUTPUT_ENABLE_MASK;
474 } /* End of function HW_SCI_TransmitterLevelSet() */
475
476 /*******************************************************************************************************************//**
477 * Enables receive interrupt.
478 * @param[in] p_reg SCI base register
479 * @param[in] p_ctrl UART instance control block
480 * @retval void
481 **********************************************************************************************************************/
HW_SCI_RxIrqEnable(R_SCI0_Type * p_reg,sci_uart_instance_ctrl_t * const p_ctrl)482 __STATIC_INLINE void HW_SCI_RxIrqEnable(R_SCI0_Type * p_reg, sci_uart_instance_ctrl_t * const p_ctrl)
483 {
484 NVIC_EnableIRQ(p_ctrl->rxi_irq);
485 if (SSP_INVALID_VECTOR != p_ctrl->eri_irq)
486 {
487 NVIC_EnableIRQ(p_ctrl->eri_irq);
488 }
489 p_reg->SCR_b.RIE = 1U;
490 } /* End of function HW_SCI_RxIrqEnable() */
491
492 /*******************************************************************************************************************//**
493 * Enables transmit end interrupt.
494 * @param[in] p_reg SCI base register
495 * @param[in] p_ctrl UART instance control block
496 * @retval void
497 **********************************************************************************************************************/
HW_SCI_TeIrqEnable(R_SCI0_Type * p_reg,sci_uart_instance_ctrl_t * const p_ctrl)498 __STATIC_INLINE void HW_SCI_TeIrqEnable(R_SCI0_Type * p_reg, sci_uart_instance_ctrl_t * const p_ctrl)
499 {
500 R_BSP_IrqStatusClear(p_ctrl->tei_irq);
501 NVIC_ClearPendingIRQ(p_ctrl->tei_irq);
502
503 uint8_t scr_temp = p_reg->SCR;
504 scr_temp |= SCI_SCR_TEIE_MASK;
505 scr_temp &= (uint8_t) ~SCI_SCR_TIE_MASK;
506 p_reg->SCR = scr_temp;
507
508 NVIC_DisableIRQ(p_ctrl->txi_irq);
509 NVIC_EnableIRQ(p_ctrl->tei_irq);
510 } /* End of function HW_SCI_TeIrqEnable() */
511
512 /*******************************************************************************************************************//**
513 * Enables serial transmission.
514 * @param[in] p_reg SCI base register
515 * @retval void
516 **********************************************************************************************************************/
HW_SCI_UartTransmitterEnable(R_SCI0_Type * p_reg)517 __STATIC_INLINE void HW_SCI_UartTransmitterEnable (R_SCI0_Type * p_reg)
518 {
519 p_reg->SCR |= (SCI_SCR_TE_MASK | SCI_SCR_TIE_MASK);
520 } /* End of function HW_SCI_UartTransmitterEnable() */
521
522 /*******************************************************************************************************************//**
523 * Disables serial transmission.
524 * @param[in] p_reg SCI base register
525 * @retval void
526 **********************************************************************************************************************/
HW_SCI_UartTransmitterDisable(R_SCI0_Type * p_reg)527 __STATIC_INLINE void HW_SCI_UartTransmitterDisable (R_SCI0_Type * p_reg)
528 {
529 p_reg->SCR &= (uint8_t) ~(SCI_SCR_TE_MASK | SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
530 } /* End of function HW_SCI_UartTransmitterDisable() */
531
532 /*******************************************************************************************************************//**
533 * Disables transmit interrupt requests.
534 * @param[in] p_reg SCI base register
535 * @retval void
536 **********************************************************************************************************************/
HW_SCI_UartTransmitIrqDisable(R_SCI0_Type * p_reg)537 __STATIC_INLINE void HW_SCI_UartTransmitIrqDisable (R_SCI0_Type * p_reg)
538 {
539 p_reg->SCR &= (uint8_t) ~(SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK);
540 } /* End of function HW_SCI_UartTransmitIrqDisable() */
541
542 /*******************************************************************************************************************//**
543 * Enables serial reception.
544 * @param[in] p_reg SCI base register
545 * @retval void
546 **********************************************************************************************************************/
HW_SCI_UartReceiverEnable(R_SCI0_Type * p_reg)547 __STATIC_INLINE void HW_SCI_UartReceiverEnable (R_SCI0_Type * p_reg)
548 {
549 p_reg->SCR |= (SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK);
550 } /* End of function HW_SCI_UartReceiverEnable() */
551
552 /*******************************************************************************************************************//**
553 * Disables serial transmission and reception.
554 * @param[in] p_reg SCI base register
555 * @retval void
556 **********************************************************************************************************************/
HW_SCI_UartTransmitterReceiverDisable(R_SCI0_Type * p_reg)557 __STATIC_INLINE void HW_SCI_UartTransmitterReceiverDisable (R_SCI0_Type * p_reg)
558 {
559 p_reg->SCR &= (uint8_t) ~(SCI_SCR_TE_MASK | SCI_SCR_TIE_MASK | SCI_SCR_TEIE_MASK |
560 SCI_SCR_RE_MASK | SCI_SCR_RIE_MASK);
561 } /* End of function HW_SCI_UartTransmitterReceiverDisable() */
562
563 /* Common macro for SSP header files. There is also a corresponding SSP_HEADER macro at the top of this file. */
564 SSP_FOOTER
565
566 #endif /* HW_SCI_UART_PRIVATE_H */
567