1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef GPIO_NAMES_CANNONLAKE_H 4 #define GPIO_NAMES_CANNONLAKE_H 5 6 #include "gpio_groups.h" 7 8 static const char *const cannonlake_pch_h_group_a_names[] = { 9 "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", 10 "GPP_A1", "LAD0", "n/a", "ESPI_IO0", 11 "GPP_A2", "LAD1", "n/a", "ESPI_IO1", 12 "GPP_A3", "LAD2", "n/a", "ESPI_IO2", 13 "GPP_A4", "LAD3", "n/a", "ESPI_IO3", 14 "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", 15 "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", 16 "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", 17 "GPP_A8", "CLKRUN#", "n/a", "n/a", 18 "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", 19 "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", 20 "GPP_A11", "PME#", "SD_VDD2_PWR_EN#", "n/a", 21 "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", 22 "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", 23 "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", 24 "GPP_A15", "SUSACK#", "n/a", "n/a", 25 "GPP_A16", "CLKOUT_48", "n/a", "n/a", 26 "GPP_A17", "SD_VDD1_PWR_EN#", "ISH_GP7", "n/a", 27 "GPP_A18", "ISH_GP0", "n/a", "n/a", 28 "GPP_A19", "ISH_GP1", "n/a", "n/a", 29 "GPP_A20", "ISH_GP2", "n/a", "n/a", 30 "GPP_A21", "ISH_GP3", "n/a", "n/a", 31 "GPP_A22", "ISH_GP4", "n/a", "n/a", 32 "GPP_A23", "ISH_GP5", "n/a", "n/a", 33 "ESPI_CLK_LOOPBK", "ESPI_CLK_LOOPBK", "n/a", "n/a", 34 }; 35 36 static const char *const cannonlake_pch_h_group_b_names[] = { 37 "GPP_B0", "GSPI0_CS1#", "n/a", 38 "GPP_B1", "GSPI1_CS1#", "TIME_SYNC1", 39 "GPP_B2", "VRALERT#", "n/a", 40 "GPP_B3", "CPU_GP2", "n/a", 41 "GPP_B4", "CPU_GP3", "n/a", 42 "GPP_B5", "SRCCLKREQ0#", "n/a", 43 "GPP_B6", "SRCCLKREQ1#", "n/a", 44 "GPP_B7", "SRCCLKREQ2#", "n/a", 45 "GPP_B8", "SRCCLKREQ3#", "n/a", 46 "GPP_B9", "SRCCLKREQ4#", "n/a", 47 "GPP_B10", "SRCCLKREQ5#", "n/a", 48 "GPP_B11", "I2S_MCLK", "n/a", 49 "GPP_B12", "SLP_S0#", "n/a", 50 "GPP_B13", "PLTRST#", "n/a", 51 "GPP_B14", "SPKR", "n/a", 52 "GPP_B15", "GSPI0_CS0#", "n/a", 53 "GPP_B16", "GSPI0_CLK", "n/a", 54 "GPP_B17", "GSPI0_MISO", "n/a", 55 "GPP_B18", "GSPI0_MOSI", "n/a", 56 "GPP_B19", "GSPI1_CS0#", "n/a", 57 "GPP_B20", "GSPI1_CLK", "n/a", 58 "GPP_B21", "GSPI1_MISO", "n/a", 59 "GPP_B22", "GSPI1_MOSI", "n/a", 60 "GPP_B23", "SML1ALERT#", "PCHHOT#", 61 "GSPI0_CLK_LOOPBK", "GSPI0_CLK_LOOPBK", "n/a", 62 "GSPI1_CLK_LOOPBK", "GSPI1_CLK_LOOPBK", "n/a", 63 }; 64 65 static const char *const cannonlake_pch_h_group_c_names[] = { 66 "GPP_C0", "SMBCLK", "n/a", 67 "GPP_C1", "SMBDATA", "n/a", 68 "GPP_C2", "SMBALERT#", "n/a", 69 "GPP_C3", "SML0CLK", "n/a", 70 "GPP_C4", "SML0DATA", "n/a", 71 "GPP_C5", "SML0ALERT#", "n/a", 72 "GPP_C6", "SML1CLK", "n/a", 73 "GPP_C7", "SML1DATA", "n/a", 74 "GPP_C8", "UART0A_RXD", "n/a", 75 "GPP_C9", "UART0A_TXD", "n/a", 76 "GPP_C10", "UART0A_RTS#", "n/a", 77 "GPP_C11", "UART0A_CTS#", "n/a", 78 "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", 79 "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", 80 "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", 81 "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", 82 "GPP_C16", "I2C0_SDA", "n/a", 83 "GPP_C17", "I2C0_SCL", "n/a", 84 "GPP_C18", "I2C1_SDA", "n/a", 85 "GPP_C19", "I2C1_SCL", "n/a", 86 "GPP_C20", "UART2_RXD", "n/a", 87 "GPP_C21", "UART2_TXD", "n/a", 88 "GPP_C22", "UART2_RTS#", "n/a", 89 "GPP_C23", "UART2_CTS#", "n/a", 90 }; 91 92 static const char *const cannonlake_pch_h_group_d_names[] = { 93 "GPP_D0", "SPI1_CS#", "n/a", "SBK0", "BK0", 94 "GPP_D1", "SPI1_CLK", "n/a", "SBK1", "BK1", 95 "GPP_D2", "SPI1_MISO", "n/a", "SBK2", "BK2", 96 "GPP_D3", "SPI1_MOSI", "n/a", "SBK3", "BK3", 97 "GPP_D4", "I2C2_SDA", "I2C3_SDA", "SBK4", "BK4", 98 "GPP_D5", "I2S2_SFRM", "n/a", "CNV_RF_RESET#", "n/a", 99 "GPP_D6", "I2S2_TXD", "n/a", "MODEM_CLKREQ", "n/a", 100 "GPP_D7", "I2S2_RXD", "n/a", "n/a", "n/a", 101 "GPP_D8", "I2S2_SCLK", "n/a", "n/a", "n/a", 102 "GPP_D9", "ISH_SPI_CS#", "n/a", "GSPI2_CS0#", "n/a", 103 "GPP_D10", "ISH_SPI_CLK", "n/a", "GSPI2_CLK", "n/a", 104 "GPP_D11", "ISH_SPI_MISO", "GP_BSSB_CLK", "GSPI2_MISO", "n/a", 105 "GPP_D12", "ISH_SPI_MOSI", "GP_BSSB_DI", "GSPI2_MOSI", "n/a", 106 "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", "n/a", 107 "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", "n/a", 108 "GPP_D15", "ISH_UART0_RTS#", "GSPI2_CS1#", "n/a", "CNV_WFEN", 109 "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", "CNV_WCEN", 110 "GPP_D17", "DMIC_CLK1", "SNDW3_CLK", "n/a", "n/a", 111 "GPP_D18", "DMIC_DATA1", "SNDW3_DATA", "n/a", "n/a", 112 "GPP_D19", "DMIC_CLK0", "SNDW4_CLK", "n/a", "n/a", 113 "GPP_D20", "DMIC_DATA0", "SNDW4_DATA", "n/a", "n/a", 114 "GPP_D21", "SPI1_IO2", "n/a", "n/a", "n/a", 115 "GPP_D22", "SPI1_IO3", "n/a", "n/a", "n/a", 116 "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", "n/a", 117 }; 118 119 static const char *const cannonlake_pch_h_group_e_names[] = { 120 "GPP_E0", "SATAXPCIE0", "SATAGP0", 121 "GPP_E1", "SATAXPCIE1", "SATAGP1", 122 "GPP_E2", "SATAXPCIE2", "SATAGP2", 123 "GPP_E3", "CPU_GP0", "n/a", 124 "GPP_E4", "SATA_DEVSLP0", "n/a", 125 "GPP_E5", "SATA_DEVSLP1", "n/a", 126 "GPP_E6", "SATA_DEVSLP2", "n/a", 127 "GPP_E7", "CPU_GP1", "n/a", 128 "GPP_E8", "SATALED#", "n/a", 129 "GPP_E9", "USB2_OC0#", "n/a", 130 "GPP_E10", "USB2_OC1#", "n/a", 131 "GPP_E11", "USB2_OC2#", "n/a", 132 "GPP_E12", "USB2_OC3#", "n/a", 133 }; 134 135 static const char *const cannonlake_pch_h_group_f_names[] = { 136 "GPP_F0", "SATAXPCIE3", "SATAGP3", 137 "GPP_F1", "SATAXPCIE4", "SATAGP4", 138 "GPP_F2", "SATAXPCIE5", "SATAGP5", 139 "GPP_F3", "SATAXPCIE6", "SATAGP6", 140 "GPP_F4", "SATAXPCIE7", "SATAGP7", 141 "GPP_F5", "SATA_DEVSLP3", "n/a", 142 "GPP_F6", "SATA_DEVSLP4", "n/a", 143 "GPP_F7", "SATA_DEVSLP5", "n/a", 144 "GPP_F8", "SATA_DEVSLP6", "n/a", 145 "GPP_F9", "SATA_DEVSLP7", "n/a", 146 "GPP_F10", "SATA_SCLOCK", "n/a", 147 "GPP_F11", "SATA_SLOAD", "n/a", 148 "GPP_F12", "SATA_SDATAOUT1", "n/a", 149 "GPP_F13", "SATA_SDATAOUT0", "n/a", 150 "GPP_F14", "n/a", "PS_ON#", 151 "GPP_F15", "USB2_OC4#", "n/a", 152 "GPP_F16", "USB2_OC5#", "n/a", 153 "GPP_F17", "USB2_OC6#", "n/a", 154 "GPP_F18", "USB2_OC7#", "n/a", 155 "GPP_F19", "eDP_VDDEN", "n/a", 156 "GPP_F20", "eDP_BKLTEN", "n/a", 157 "GPP_F21", "eDP_BKLTCTL", "n/a", 158 "GPP_F22", "DDPF_CTRLCLK", "n/a", 159 "GPP_F23", "DDPF_CTRLDATA", "n/a", 160 }; 161 162 static const char *const cannonlake_pch_h_group_spi_names[] = { 163 "SPI0_IO_2", "SPI0_IO_2", 164 "SPI0_IO_3", "SPI0_IO_3", 165 "SPI0_MISO", "SPI0_MISO", 166 "SPI0_MOSI", "SPI0_MOSI", 167 "SPI0_CS2_B", "SPI0_CS2#", 168 "SPI0_CS0_B", "SPI0_CS0#", 169 "SPI0_CS1_B", "SPI0_CS1#", 170 "SPI0_CLK", "SPI0_CLK", 171 "SPI0_CLK_LOOPBK", "SPI0_CLK_LOOPBK", 172 }; 173 174 static const char *const cannonlake_pch_h_group_g_names[] = { 175 "GPP_G0", "SD_CMD", 176 "GPP_G1", "SD_DATA0", 177 "GPP_G2", "SD_DATA1", 178 "GPP_G3", "SD_DATA2", 179 "GPP_G4", "SD_DATA3", 180 "GPP_G5", "SD_CD#", 181 "GPP_G6", "SD_CLK", 182 "GPP_G7", "SD_WP", 183 }; 184 185 static const char *const cannonlake_pch_h_group_aza_names[] = { 186 "HDA_BCLK", "HDA_BCLK", "I2S0_SCLK", "n/a", 187 "HDA_RST_B", "HDA_RST#", "I2S1_SCLK", "SNDW1_CLK", 188 "HDA_SYNC", "HDA_SYNC", "I2S0_SFRM", "n/a", 189 "HDA_SDO", "HDA_SDO", "I2S0_TXD", "n/a", 190 "HDA_SDI0", "HDA_SDI0", "I2S0_RXD", "n/a", 191 "HDA_SDI1", "HDA_SDI1", "I2S1_RXD", "SNDW1_DATA", 192 "I2S1_SFRM", "I2S1_SFRM", "SNDW2_CLK", "n/a", 193 "I2S1_TXD", "I2S1_TXD", "SNDW2_DATA", "n/a", 194 }; 195 196 static const char *const cannonlake_pch_h_group_vgpio_0_names[] = { 197 "CNV_BTEN", "n/a", "n/a", "n/a", 198 "CNV_GNEN", "n/a", "n/a", "n/a", 199 "CNV_WFEN", "n/a", "n/a", "n/a", 200 "CNV_WCEN", "n/a", "n/a", "n/a", 201 "vCNV_GNSS_HOST_WAKE_B", "n/a", "n/a", "n/a", 202 "vSD3_CD_B", "n/a", "n/a", "n/a", 203 "CNV_BT_HOST_WAKE_B", "n/a", "n/a", "n/a", 204 "CNV_BT_IF_SELECT", "n/a", "n/a", "n/a", 205 "vCNV_BT_UART_TXD", "ISH UART0", "SIo UART2", "n/a", 206 "vCNV_BT_UART_RXD", "ISH UART0", "SIo UART2", "n/a", 207 "vCNV_BT_UART_CTS_B", "ISH UART0", "SIo UART2", "n/a", 208 "vCNV_BT_UART_RTS_B", "ISH UART0", "SIo UART2", "n/a", 209 "vCNV_MFUART1_TXD", "ISH UART0", "SIo UART2", "n/a", 210 "vCNV_MFUART1_RXD", "ISH UART0", "SIo UART2", "n/a", 211 "vCNV_MFUART1_CTS_B", "ISH UART0", "SIo UART2", "n/a", 212 "vCNV_MFUART1_RTS_B", "ISH UART0", "SIo UART2", "n/a", 213 "vCNV_GNSS_UART_TXD", "n/a", "n/a", "n/a", 214 "vCNV_GNSS_UART_RXD", "n/a", "n/a", "n/a", 215 "vCNV_GNSS_UART_CTS_B", "n/a", "n/a", "n/a", 216 "vCNV_GNSS_UART_RTS_B", "n/a", "n/a", "n/a", 217 "vUART0_TXD", "mapped", "n/a", "n/a", 218 "vUART0_RXD", "mapped", "n/a", "n/a", 219 "vUART0_CTS_B", "mapped", "n/a", "n/a", 220 "vUART0_RTS_B", "mapped", "n/a", "n/a", 221 "vISH_UART0_TXD", "mapped", "n/a", "n/a", 222 "vISH_UART0_RXD", "mapped", "n/a", "n/a", 223 "vISH_UART0_CTS_B", "mapped", "n/a", "n/a", 224 "vISH_UART0_RTS_B", "mapped", "n/a", "n/a", 225 "vISH_UART1_TXD", "mapped", "n/a", "n/a", 226 "vISH_UART1_RXD", "mapped", "n/a", "n/a", 227 "vISH_UART1_CTS_B", "mapped", "n/a", "n/a", 228 "vISH_UART1_RTS_B", "mapped", "n/a", "n/a", 229 }; 230 231 static const char *const cannonlake_pch_h_group_vgpio_1_names[] = { 232 "vCNV_BT_I2S_BCLK", "SSP0", "SSP1", "SSP2", 233 "vCNV_BT_I2S_WS_SYNC", "SSP0", "SSP1", "SSP2", 234 "vCNV_BT_I2S_SDO", "SSP0", "SSP1", "SSP2", 235 "vCNV_BT_I2S_SDI", "SSP0", "SSP1", "SSP2", 236 "vSSP2_SCLK", "mapped", "n/a", "n/a", 237 "vSSP2_SFRM", "mapped", "n/a", "n/a", 238 "vSSP2_TXD", "mapped", "n/a", "n/a", 239 "vSSP2_RXD", "n/a", "n/a", "n/a", 240 }; 241 242 static const char *const cannonlake_pch_h_group_h_names[] = { 243 "GPP_H0", "SRCCLKREQ6#", 244 "GPP_H1", "SRCCLKREQ7#", 245 "GPP_H2", "SRCCLKREQ8#", 246 "GPP_H3", "SRCCLKREQ9#", 247 "GPP_H4", "SRCCLKREQ10#", 248 "GPP_H5", "SRCCLKREQ11#", 249 "GPP_H6", "SRCCLKREQ12#", 250 "GPP_H7", "SRCCLKREQ13#", 251 "GPP_H8", "SRCCLKREQ14#", 252 "GPP_H9", "SRCCLKREQ15#", 253 "GPP_H10", "SML2CLK", 254 "GPP_H11", "SML2DATA", 255 "GPP_H12", "SML2ALERT#", 256 "GPP_H13", "SML3CLK", 257 "GPP_H14", "SML3DATA", 258 "GPP_H15", "SML3ALERT#", 259 "GPP_H16", "SML4CLK", 260 "GPP_H17", "SML4DATA", 261 "GPP_H18", "SML4ALERT#", 262 "GPP_H19", "ISH_I2C0_SDA", 263 "GPP_H20", "ISH_I2C0_SCL", 264 "GPP_H21", "ISH_I2C1_SDA", 265 "GPP_H22", "ISH_I2C1_SCL", 266 "GPP_H23", "TIME_SYNC0", 267 }; 268 269 const char *const cannonlake_pch_h_group_cpu_names[] = { 270 "HDACPU_SDI", "HDACPU_SDI", 271 "HDACPU_SDO", "HDACPU_SDO", 272 "HDACPU_SCLK", "HDACPU_SCLK", 273 "PM_SYNC", "PM_SYNC", 274 "PECI", "PECI", 275 "CPUPWRGD", "CPUPWRG#", 276 "THRMTRIP_B", "THRMTRIP#", 277 "PLTRST_CPU_B", "PLTRST_CPU#", 278 "PM_DOWN", "PM_DOWN", 279 "TRIGGER_IN", "TRIGGER_IN", 280 "TRIGGER_OUT", "TRIGGER_OUT", 281 }; 282 283 const char *const cannonlake_pch_h_group_jtag_names[] = { 284 "PCH_TDO", "PCH_TDO", 285 "PCH_JTAGX", "PCH_JTAGX", 286 "PROC_PRDY_B", "PROC_RDY#", 287 "PROC_PREQ_B", "PROC_REQ#", 288 "CPU_TRST_B", "CPU_TRST#", 289 "PCH_TDI", "PCH_TDI", 290 "PCH_TMS", "PCH_TMS", 291 "PCH_TCK", "PCH_TCK", 292 "ITP_PMODE", "ITP_PMODE", 293 }; 294 295 static const char *const cannonlake_pch_h_group_i_names[] = { 296 "GPP_I0", "DDPB_HPD0", "DISP_MISC0", 297 "GPP_I1", "DDPB_HPD1", "DISP_MISC1", 298 "GPP_I2", "DDPB_HPD2", "DISP_MISC2", 299 "GPP_I3", "DDPB_HPD3", "DISP_MISC3", 300 "GPP_I4", "EDP_HPD", "DISP_MISC4", 301 "GPP_I5", "DDPB_CTRLCLK", "n/a", 302 "GPP_I6", "DDPB_CTRLDATA", "n/a", 303 "GPP_I7", "DDPC_CTRLCLK", "n/a", 304 "GPP_I8", "DDPC_CTRLDATA", "n/a", 305 "GPP_I9", "DDPD_CTRLCLK", "n/a", 306 "GPP_I10", "DDPD_CTRLDATA", "n/a", 307 "GPP_I11", "M2_SKT2_CFG0", "n/a", 308 "GPP_I12", "M2_SKT2_CFG1", "n/a", 309 "GPP_I13", "M2_SKT2_CFG2", "n/a", 310 "GPP_I14", "M2_SKT2_CFG3", "n/a", 311 "SYS_PWROK", "SYS_PWROK", "n/a", 312 "SYS_RESET_B", "SYS_RESET#", "n/a", 313 "CL_RST_B", "CL_RST#", "n/a", 314 }; 315 316 static const char *const cannonlake_pch_h_group_j_names[] = { 317 "GPP_J0", "CNV_PA_BLANKING", "n/a", 318 "GPP_J1", "n/a", "CPU_C10_GATE#", 319 "GPP_J2", "n/a", "n/a", 320 "GPP_J3", "n/a", "n/a", 321 "GPP_J4", "CNV_BRI_DT", "UART0B_RTS#", 322 "GPP_J5", "CNV_BRI_RSP", "UART0B_RXD", 323 "GPP_J6", "CNV_RGI_DT", "UART0B_TXD", 324 "GPP_J7", "CNV_RGI_RSP", "UART0B_CTS#", 325 "GPP_J8", "CNV_MFUART2_RXD", "n/a", 326 "GPP_J9", "CNV_MFUART2_TXD", "n/a", 327 "GPP_J10", "n/a", "n/a", 328 "GPP_J11", "A4WP_PRESENT", "n/a", 329 }; 330 331 static const char *const cannonlake_pch_h_group_k_names[] = { 332 "GPP_K0", "n/a", 333 "GPP_K1", "n/a", 334 "GPP_K2", "n/a", 335 "GPP_K3", "n/a", 336 "GPP_K4", "n/a", 337 "GPP_K5", "n/a", 338 "GPP_K6", "n/a", 339 "GPP_K7", "n/a", 340 "GPP_K8", "Reserved", 341 "GPP_K9", "Reserved", 342 "GPP_K10", "Reserved", 343 "GPP_K11", "Reserved", 344 "GPP_K12", "GSXOUT", 345 "GPP_K13", "GSXSLOAD", 346 "GPP_K14", "GSXDIN", 347 "GPP_K15", "GSXSRESET#", 348 "GPP_K16", "GSXCLK", 349 "GPP_K17", "ADR_COMPLETE", 350 "GPP_K18", "NMI#", 351 "GPP_K19", "SMI#", 352 "GPP_K20", "Reserved", 353 "GPP_K21", "Reserved", 354 "GPP_K22", "IMGCLKOUT0", 355 "GPP_K23", "IMGCLKOUT1", 356 }; 357 358 static const char *const cannonlake_pch_h_group_gpd_names[] = { 359 "GPD0", "BATLOW#", 360 "GPD1", "ACPRESENT", 361 "GPD2", "LAN_WAKE#", 362 "GPD3", "PRWBTN#", 363 "GPD4", "SLP_S3#", 364 "GPD5", "SLP_S4#", 365 "GPD6", "SLP_A#", 366 "GPD7", "n/a", 367 "GPD8", "SUSCLK", 368 "GPD9", "SLP_WLAN#", 369 "GPD10", "SLP_S5#", 370 "GPD11", "LANPHYPC", 371 "SLP_LAN_B", "SLP_LAN#", 372 "SLP_SUS_B", "SLP_SUS#", 373 "WAKE_B", "WAKE#", 374 "DRAM_RESET_B", "DRAM_RESET#", 375 }; 376 377 static const struct gpio_group cannonlake_pch_h_group_a = { 378 .display = "------- GPIO Group GPP_A -------", 379 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_a_names) / 4, 380 .func_count = 4, 381 .pad_names = cannonlake_pch_h_group_a_names, 382 }; 383 384 static const struct gpio_group cannonlake_pch_h_group_b = { 385 .display = "------- GPIO Group GPP_B -------", 386 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_b_names) / 3, 387 .func_count = 3, 388 .pad_names = cannonlake_pch_h_group_b_names, 389 }; 390 391 static const struct gpio_group cannonlake_pch_h_group_c = { 392 .display = "------- GPIO Group GPP_C -------", 393 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_c_names) / 3, 394 .func_count = 3, 395 .pad_names = cannonlake_pch_h_group_c_names, 396 }; 397 398 static const struct gpio_group cannonlake_pch_h_group_d = { 399 .display = "------- GPIO Group GPP_D -------", 400 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_d_names) / 5, 401 .func_count = 5, 402 .pad_names = cannonlake_pch_h_group_d_names, 403 }; 404 405 static const struct gpio_group cannonlake_pch_h_group_e = { 406 .display = "------- GPIO Group GPP_E -------", 407 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_e_names) / 3, 408 .func_count = 3, 409 .pad_names = cannonlake_pch_h_group_e_names, 410 }; 411 412 static const struct gpio_group cannonlake_pch_h_group_f = { 413 .display = "------- GPIO Group GPP_F -------", 414 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_f_names) / 3, 415 .func_count = 3, 416 .pad_names = cannonlake_pch_h_group_f_names, 417 }; 418 419 static const struct gpio_group cannonlake_pch_h_group_spi = { 420 .display = "------- GPIO Group SPI -------", 421 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_spi_names) / 2, 422 .func_count = 2, 423 .pad_names = cannonlake_pch_h_group_spi_names, 424 }; 425 426 static const struct gpio_group cannonlake_pch_h_group_g = { 427 .display = "------- GPIO Group GPP_G -------", 428 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_g_names) / 2, 429 .func_count = 2, 430 .pad_names = cannonlake_pch_h_group_g_names, 431 }; 432 433 static const struct gpio_group cannonlake_pch_h_group_aza = { 434 .display = "------- GPIO Group AZA -------", 435 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_aza_names) / 4, 436 .func_count = 4, 437 .pad_names = cannonlake_pch_h_group_aza_names, 438 }; 439 440 static const struct gpio_group cannonlake_pch_h_group_vgpio_0 = { 441 .display = "------- GPIO Group VGPIO_0 -------", 442 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_0_names) / 4, 443 .func_count = 4, 444 .pad_names = cannonlake_pch_h_group_vgpio_0_names, 445 }; 446 447 static const struct gpio_group cannonlake_pch_h_group_vgpio_1 = { 448 .display = "------- GPIO Group VGPIO_1 -------", 449 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_vgpio_1_names) / 4, 450 .func_count = 4, 451 .pad_names = cannonlake_pch_h_group_vgpio_1_names, 452 }; 453 454 static const struct gpio_group cannonlake_pch_h_group_h = { 455 .display = "------- GPIO Group GPP_H -------", 456 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_h_names) / 2, 457 .func_count = 2, 458 .pad_names = cannonlake_pch_h_group_h_names, 459 }; 460 461 static const struct gpio_group cannonlake_pch_h_group_cpu = { 462 .display = "------- GPIO Group CPU -------", 463 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_cpu_names) / 2, 464 .func_count = 2, 465 .pad_names = cannonlake_pch_h_group_cpu_names, 466 }; 467 468 static const struct gpio_group cannonlake_pch_h_group_jtag = { 469 .display = "------- GPIO Group JTAG -------", 470 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_jtag_names) / 2, 471 .func_count = 2, 472 .pad_names = cannonlake_pch_h_group_jtag_names, 473 }; 474 475 static const struct gpio_group cannonlake_pch_h_group_i = { 476 .display = "------- GPIO Group GPP_I -------", 477 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_i_names) / 3, 478 .func_count = 3, 479 .pad_names = cannonlake_pch_h_group_i_names, 480 }; 481 482 static const struct gpio_group cannonlake_pch_h_group_j = { 483 .display = "------- GPIO Group GPP_J -------", 484 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_j_names) / 3, 485 .func_count = 3, 486 .pad_names = cannonlake_pch_h_group_j_names, 487 }; 488 489 static const struct gpio_group cannonlake_pch_h_group_k = { 490 .display = "------- GPIO Group GPP_K -------", 491 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_k_names) / 2, 492 .func_count = 2, 493 .pad_names = cannonlake_pch_h_group_k_names, 494 }; 495 496 static const struct gpio_group cannonlake_pch_h_group_gpd = { 497 .display = "------- GPIO Group GPD -------", 498 .pad_count = ARRAY_SIZE(cannonlake_pch_h_group_gpd_names) / 2, 499 .func_count = 2, 500 .pad_names = cannonlake_pch_h_group_gpd_names, 501 }; 502 503 static const struct gpio_group *const cannonlake_pch_h_community_0_groups[] = { 504 &cannonlake_pch_h_group_a, 505 &cannonlake_pch_h_group_b, 506 }; 507 static const struct gpio_community cannonlake_pch_h_community_0 = { 508 .name = "------- GPIO Community 0 -------", 509 .pcr_port_id = 0x6e, 510 .group_count = ARRAY_SIZE(cannonlake_pch_h_community_0_groups), 511 .groups = cannonlake_pch_h_community_0_groups, 512 }; 513 514 static const struct gpio_group *const cannonlake_pch_h_community_1_groups[] = { 515 &cannonlake_pch_h_group_c, 516 &cannonlake_pch_h_group_d, 517 &cannonlake_pch_h_group_g, 518 &cannonlake_pch_h_group_aza, 519 &cannonlake_pch_h_group_vgpio_0, 520 &cannonlake_pch_h_group_vgpio_1, 521 }; 522 static const struct gpio_community cannonlake_pch_h_community_1 = { 523 .name = "------- GPIO Community 1 -------", 524 .pcr_port_id = 0x6d, 525 .group_count = ARRAY_SIZE(cannonlake_pch_h_community_1_groups), 526 .groups = cannonlake_pch_h_community_1_groups, 527 }; 528 529 static const struct gpio_group *const cannonlake_pch_h_community_2_groups[] = { 530 &cannonlake_pch_h_group_gpd, 531 }; 532 static const struct gpio_community cannonlake_pch_h_community_2 = { 533 .name = "------- GPIO Community 2 -------", 534 .pcr_port_id = 0x6c, 535 .group_count = ARRAY_SIZE(cannonlake_pch_h_community_2_groups), 536 .groups = cannonlake_pch_h_community_2_groups, 537 }; 538 539 static const struct gpio_group *const cannonlake_pch_h_community_3_groups[] = { 540 &cannonlake_pch_h_group_k, 541 &cannonlake_pch_h_group_h, 542 &cannonlake_pch_h_group_e, 543 &cannonlake_pch_h_group_f, 544 &cannonlake_pch_h_group_spi, 545 }; 546 static const struct gpio_community cannonlake_pch_h_community_3 = { 547 .name = "------- GPIO Community 3 -------", 548 .pcr_port_id = 0x6b, 549 .group_count = ARRAY_SIZE(cannonlake_pch_h_community_3_groups), 550 .groups = cannonlake_pch_h_community_3_groups, 551 }; 552 553 static const struct gpio_group *const cannonlake_pch_h_community_4_groups[] = { 554 &cannonlake_pch_h_group_cpu, 555 &cannonlake_pch_h_group_jtag, 556 &cannonlake_pch_h_group_i, 557 &cannonlake_pch_h_group_j, 558 }; 559 static const struct gpio_community cannonlake_pch_h_community_4 = { 560 .name = "------- GPIO Community 4 -------", 561 .pcr_port_id = 0x6a, 562 .group_count = ARRAY_SIZE(cannonlake_pch_h_community_4_groups), 563 .groups = cannonlake_pch_h_community_4_groups, 564 }; 565 566 static const struct gpio_community *const cannonlake_pch_h_communities[] = { 567 &cannonlake_pch_h_community_0, 568 &cannonlake_pch_h_community_1, 569 &cannonlake_pch_h_community_2, 570 &cannonlake_pch_h_community_3, 571 &cannonlake_pch_h_community_4, 572 }; 573 574 #endif 575