1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2010-2015, Intel Corporation. 5 */ 6 7 #ifndef __GP_DEVICE_LOCAL_H_INCLUDED__ 8 #define __GP_DEVICE_LOCAL_H_INCLUDED__ 9 10 #include "gp_device_global.h" 11 12 /* @ GP_REGS_BASE -> GP_DEVICE_BASE */ 13 #define _REG_GP_SDRAM_WAKEUP_ADDR 0x00 14 #define _REG_GP_IDLE_ADDR 0x04 15 /* #define _REG_GP_IRQ_REQ0_ADDR 0x08 */ 16 /* #define _REG_GP_IRQ_REQ1_ADDR 0x0C */ 17 #define _REG_GP_SP_STREAM_STAT_ADDR 0x10 18 #define _REG_GP_SP_STREAM_STAT_B_ADDR 0x14 19 #define _REG_GP_ISP_STREAM_STAT_ADDR 0x18 20 #define _REG_GP_MOD_STREAM_STAT_ADDR 0x1C 21 #define _REG_GP_SP_STREAM_STAT_IRQ_COND_ADDR 0x20 22 #define _REG_GP_SP_STREAM_STAT_B_IRQ_COND_ADDR 0x24 23 #define _REG_GP_ISP_STREAM_STAT_IRQ_COND_ADDR 0x28 24 #define _REG_GP_MOD_STREAM_STAT_IRQ_COND_ADDR 0x2C 25 #define _REG_GP_SP_STREAM_STAT_IRQ_ENABLE_ADDR 0x30 26 #define _REG_GP_SP_STREAM_STAT_B_IRQ_ENABLE_ADDR 0x34 27 #define _REG_GP_ISP_STREAM_STAT_IRQ_ENABLE_ADDR 0x38 28 #define _REG_GP_MOD_STREAM_STAT_IRQ_ENABLE_ADDR 0x3C 29 /* 30 #define _REG_GP_SWITCH_IF_ADDR 0x40 31 #define _REG_GP_SWITCH_GDC1_ADDR 0x44 32 #define _REG_GP_SWITCH_GDC2_ADDR 0x48 33 */ 34 #define _REG_GP_SLV_REG_RST_ADDR 0x50 35 #define _REG_GP_SWITCH_ISYS2401_ADDR 0x54 36 37 /* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ 38 /* 39 #define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 40 #define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 41 #define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 42 #define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C 43 #define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 44 #define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 45 #define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 46 #define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C 47 #define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 48 #define _REG_GP_IFMT_srst 0x00030824 49 #define _REG_GP_IFMT_slv_reg_srst 0x00030828 50 #define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C 51 */ 52 /* @ GP_DEVICE_BASE */ 53 /* 54 #define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 55 #define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 56 #define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 57 #define _REG_GP_NR_FRAMES_ADDR 0x0009000C 58 #define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 59 #define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 60 #define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 61 #define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C 62 #define _REG_GP_ISEL_SOF_ADDR 0x00090020 63 #define _REG_GP_ISEL_EOF_ADDR 0x00090024 64 #define _REG_GP_ISEL_SOL_ADDR 0x00090028 65 #define _REG_GP_ISEL_EOL_ADDR 0x0009002C 66 #define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 67 #define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 68 #define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 69 #define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C 70 #define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 71 #define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 72 #define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 73 #define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C 74 #define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 75 #define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 76 #define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 77 #define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C 78 #define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 79 #define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 80 #define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 81 #define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C 82 #define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 83 #define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 84 #define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 85 #define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C 86 #define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 87 #define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 88 #define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 89 #define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C 90 #define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 91 #define _REG_GP_SOFT_RESET_ADDR 0x00090094 92 */ 93 94 struct gp_device_state_s { 95 int syncgen_enable; 96 int syncgen_free_running; 97 int syncgen_pause; 98 int nr_frames; 99 int syngen_nr_pix; 100 int syngen_nr_lines; 101 int syngen_hblank_cycles; 102 int syngen_vblank_cycles; 103 int isel_sof; 104 int isel_eof; 105 int isel_sol; 106 int isel_eol; 107 int isel_lfsr_enable; 108 int isel_lfsr_enable_b; 109 int isel_lfsr_reset_value; 110 int isel_tpg_enable; 111 int isel_tpg_enable_b; 112 int isel_hor_cnt_mask; 113 int isel_ver_cnt_mask; 114 int isel_xy_cnt_mask; 115 int isel_hor_cnt_delta; 116 int isel_ver_cnt_delta; 117 int isel_tpg_mode; 118 int isel_tpg_red1; 119 int isel_tpg_green1; 120 int isel_tpg_blue1; 121 int isel_tpg_red2; 122 int isel_tpg_green2; 123 int isel_tpg_blue2; 124 int isel_ch_id; 125 int isel_fmt_type; 126 int isel_data_sel; 127 int isel_sband_sel; 128 int isel_sync_sel; 129 int syncgen_hor_cnt; 130 int syncgen_ver_cnt; 131 int syncgen_frame_cnt; 132 int soft_reset; 133 }; 134 135 #endif /* __GP_DEVICE_LOCAL_H_INCLUDED__ */ 136