1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef __GDC_GLOBAL_H_INCLUDED__ 8 #define __GDC_GLOBAL_H_INCLUDED__ 9 10 #define IS_GDC_VERSION_2 11 12 #include <type_support.h> 13 #include "gdc_v2_defs.h" 14 15 /* 16 * Storage addresses for packed data transfer 17 */ 18 #define GDC_PARAM_ICX_LEFT_ROUNDED_IDX 0 19 #define GDC_PARAM_OXDIM_FLOORED_IDX 1 20 #define GDC_PARAM_OXDIM_LAST_IDX 2 21 #define GDC_PARAM_WOIX_LAST_IDX 3 22 #define GDC_PARAM_IY_TOPLEFT_IDX 4 23 #define GDC_PARAM_CHUNK_CNT_IDX 5 24 /*#define GDC_PARAM_ELEMENTS_PER_XMEM_ADDR_IDX 6 */ /* Derived from bpp */ 25 #define GDC_PARAM_BPP_IDX 6 26 #define GDC_PARAM_BLOCK_HEIGHT_IDX 7 27 /*#define GDC_PARAM_DMA_CHANNEL_STRIDE_A_IDX 8*/ /* The DMA stride == the GDC buffer stride */ 28 #define GDC_PARAM_WOIX_IDX 8 29 #define GDC_PARAM_DMA_CHANNEL_STRIDE_B_IDX 9 30 #define GDC_PARAM_DMA_CHANNEL_WIDTH_A_IDX 10 31 #define GDC_PARAM_DMA_CHANNEL_WIDTH_B_IDX 11 32 #define GDC_PARAM_VECTORS_PER_LINE_IN_IDX 12 33 #define GDC_PARAM_VECTORS_PER_LINE_OUT_IDX 13 34 #define GDC_PARAM_VMEM_IN_DIMY_IDX 14 35 #define GDC_PARAM_COMMAND_IDX 15 36 #define N_GDC_PARAM 16 37 38 /* Because of the packed parameter transfer max(params) == max(fragments) */ 39 #define N_GDC_FRAGMENTS N_GDC_PARAM 40 41 /* The GDC is capable of higher internal precision than the parameter data structures */ 42 #define HRT_GDC_COORD_SCALE_BITS 6 43 #define HRT_GDC_COORD_SCALE BIT(HRT_GDC_COORD_SCALE_BITS) 44 45 typedef enum { 46 GDC_CH0_ID = 0, 47 N_GDC_CHANNEL_ID 48 } gdc_channel_ID_t; 49 50 typedef enum { 51 gdc_8_bpp = 8, 52 gdc_10_bpp = 10, 53 gdc_12_bpp = 12, 54 gdc_14_bpp = 14 55 } gdc_bits_per_pixel_t; 56 57 typedef struct gdc_scale_param_mem_s { 58 u16 params[N_GDC_PARAM]; 59 u16 ipx_start_array[N_GDC_PARAM]; 60 u16 ibuf_offset[N_GDC_PARAM]; 61 u16 obuf_offset[N_GDC_PARAM]; 62 } gdc_scale_param_mem_t; 63 64 typedef struct gdc_warp_param_mem_s { 65 u32 origin_x; 66 u32 origin_y; 67 u32 in_addr_offset; 68 u32 in_block_width; 69 u32 in_block_height; 70 u32 p0_x; 71 u32 p0_y; 72 u32 p1_x; 73 u32 p1_y; 74 u32 p2_x; 75 u32 p2_y; 76 u32 p3_x; 77 u32 p3_y; 78 u32 padding[3]; 79 } gdc_warp_param_mem_t; 80 81 #endif /* __GDC_GLOBAL_H_INCLUDED__ */ 82