1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <device/pnp.h>
6 #include "chip.h"
7 #include "fintek_internal.h"
8
9 /*
10 * The Fintek F71869AD Super I/O Hardware Monitor permits the configuration of
11 * three fans individually, where fan1 is typically taken as the CPU fan. Each
12 * fan is controlled by the relation:
13 *
14 * Tfan? = Tnow + (Ta - Tb)*Ct
15 *
16 * Parameters in this relation are specified in the devicetree.cb.
17 */
18
19 /*
20 * Register CR01 ~ CR03 -> Configuration Registers
21 * Register CR0A ~ CR0F -> PECI/TSI Control Register
22 * Register CR10 ~ CR37 -> Voltage Setting Register
23 * Register CR40 ~ CR4E -> PECI 3.0 Command and Register
24 * Register CR60 ~ CR8E -> Temperature Setting Register
25 * Register CR90 ~ CRDF -> Fan Control Setting Register
26 */
27 #define HWM_SMBUS_ADDR 0x08
28 #define HWM_SMBUS_CONTROL_REG 0x0A
29 #define HWM_FAN_TYPE_SEL_REG 0x94
30 #define HWM_FAN1_TEMP_ADJ_RATE_REG 0x95
31 #define HWM_FAN_MODE_SEL_REG 0x96
32 #define HWM_FAN_FAULT_TIME_REG 0x9F /* bit7 FAN_PROG_SEL */
33 #define HWM_FAN1_IDX_RPM_MODE 0xA3
34 #define HWM_FAN1_SEG1_SPEED_COUNT 0xAA
35 #define HWM_FAN1_SEG2_SPEED_COUNT 0xAB
36 #define HWM_FAN1_SEG3_SPEED_COUNT 0xAC
37 #define HWM_FAN1_TEMP_MAP_SEL 0xAF
38 #define HWM_TEMP_SENSOR_TYPE 0x6B
39
40 /* note: multifunc registers need to be tweaked before here */
f71869ad_hwm_init(struct device * dev)41 void f71869ad_hwm_init(struct device *dev)
42 {
43 const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
44 struct resource *res = probe_resource(dev, PNP_IDX_IO0);
45
46 if (!res) {
47 printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
48 return;
49 }
50 u16 port = res->base; /* data-sheet default base = 0x229 */
51
52 printk(BIOS_INFO,
53 "Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n");
54 printk(BIOS_DEBUG,
55 "Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port);
56
57 pnp_enter_conf_mode(dev);
58 pnp_set_logical_device(dev);
59
60 /* Fintek F71869AD HWM (ordered) programming sequence. */
61
62 /* SMBus Address p.53 */
63 pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address);
64 /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
65 pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg);
66 /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
67 /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
68 pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel);
69 /* set FAN_PROG_SEL = 1 */
70 pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a);
71 /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL = 1, p.64-65 */
72 pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg);
73 /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
74 pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg);
75 /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct = 1/4 up & down) in 0x95 when FAN_PROG_SEL =
76 1, p.88 */
77 pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg);
78 /* set FAN_PROG_SEL = 0 */
79 pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a);
80 /* FAN1 RPM mode p.70 */
81 pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode);
82 /* FAN1 Segment X Speed Count */
83 pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count);
84 pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count);
85 pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);
86 /* Temperature sensor type */
87 pnp_write_index(port, HWM_TEMP_SENSOR_TYPE, conf->hwm_temp_sensor_type);
88
89 pnp_exit_conf_mode(dev);
90 }
91