1## SPDX-License-Identifier: GPL-2.0-only 2 3ifeq ($(CONFIG_SOC_QC_IPQ40XX),y) 4 5bootblock-y += clock.c 6bootblock-y += gpio.c 7bootblock-$(CONFIG_SPI_FLASH) += spi.c 8bootblock-y += timer.c 9bootblock-y += uart.c 10 11verstage-y += clock.c 12verstage-y += gpio.c 13verstage-y += blsp.c 14verstage-y += i2c.c 15verstage-y += qup.c 16verstage-y += spi.c 17verstage-y += timer.c 18verstage-y += uart.c 19 20romstage-y += clock.c 21romstage-y += blobs_init.c 22romstage-y += gpio.c 23romstage-$(CONFIG_SPI_FLASH) += spi.c 24romstage-y += timer.c 25romstage-y += uart.c 26romstage-y += cbmem.c 27romstage-y += i2c.c 28romstage-y += blsp.c 29romstage-y += qup.c 30 31ramstage-y += blobs_init.c 32ramstage-y += clock.c 33ramstage-y += gpio.c 34ramstage-y += lcc.c 35ramstage-y += soc.c 36ramstage-$(CONFIG_SPI_FLASH) += spi.c 37ramstage-y += timer.c 38ramstage-y += uart.c # Want the UART always ready for the kernels' earlyprintk 39ramstage-y += usb.c 40ramstage-y += tz_wrapper.S 41 42ramstage-y += blsp.c 43ramstage-y += i2c.c 44ramstage-y += qup.c 45ramstage-y += spi.c 46 47ifeq ($(CONFIG_USE_BLOBS),y) 48 49$(objcbfs)/bootblock.bin: $(call strip_quotes,$(CONFIG_SBL_ELF)) \ 50 $(objcbfs)/bootblock.elf 51 @printf " CRXBL $(subst $(obj)/,,$(^)) $(subst $(obj)/,,$(@))\n" 52 @$(CONFIG_SBL_UTIL_PATH)/createxbl.py -f $(CONFIG_SBL_ELF) \ 53 -s $(objcbfs)/bootblock.elf -o $@ -a 32 -b 32 54 55endif 56 57CPPFLAGS_common += -Isrc/soc/qualcomm/ipq40xx/include 58 59# List of binary blobs coreboot needs in CBFS to be able to boot up this SOC 60mbn-files := $(CONFIG_CDT_MBN) $(CONFIG_DDR_MBN) $(CONFIG_TZ_MBN) 61 62# Location of the binary blobs 63mbn-root := 3rdparty/blobs/cpu/qualcomm/ipq40xx 64 65# Create make variables to aid cbfs-files-handler in processing the blobs (add 66# them all as raw binaries at the root level). 67$(foreach f,$(mbn-files),$(eval cbfs-files-y += $(f))\ 68 $(eval $(f)-file := $(mbn-root)/$(f))\ 69 $(eval $(f)-type := raw)) 70 71endif 72