1## SPDX-License-Identifier: GPL-2.0-only 2ifeq ($(CONFIG_SOC_NVIDIA_TEGRA210),y) 3 4CBOOTIMAGE_OPTS = --soc tegra210 5 6bootblock-y += bootblock.c 7bootblock-y += bootblock_asm.S 8bootblock-y += clock.c 9bootblock-y += spi.c 10bootblock-y += i2c.c 11bootblock-y += dma.c 12bootblock-y += monotonic_timer.c 13bootblock-y += padconfig.c 14bootblock-y += power.c 15bootblock-y += funitcfg.c 16bootblock-y += ../tegra/gpio.c 17bootblock-y += ../tegra/i2c.c 18bootblock-y += ../tegra/pingroup.c 19bootblock-y += ../tegra/pinmux.c 20bootblock-y += ../tegra/apbmisc.c 21bootblock-y += ../tegra/usb.c 22bootblock-y += uart.c 23 24verstage-y += dma.c 25verstage-y += monotonic_timer.c 26verstage-y += spi.c 27verstage-y += padconfig.c 28verstage-y += funitcfg.c 29verstage-y += uart.c 30verstage-y += ../tegra/gpio.c 31verstage-y += ../tegra/i2c.c 32verstage-y += ../tegra/pinmux.c 33verstage-y += clock.c 34verstage-y += i2c.c 35 36romstage-y += romstage_asm.S 37romstage-y += addressmap.c 38romstage-y += cbmem.c 39romstage-y += ccplex.c 40romstage-y += clock.c 41romstage-y += cpu.c 42romstage-y += spi.c 43romstage-y += i2c.c 44romstage-y += dma.c 45romstage-y += monotonic_timer.c 46romstage-y += padconfig.c 47romstage-y += funitcfg.c 48romstage-y += romstage.c 49romstage-y += power.c 50romstage-y += ram_code.c 51ifneq ($(CONFIG_BOOTROM_SDRAM_INIT),y) 52romstage-y += sdram.c 53romstage-y += sdram_lp0.c 54endif 55romstage-y += ../tegra/gpio.c 56romstage-y += ../tegra/i2c.c 57romstage-y += ../tegra/pinmux.c 58romstage-y += ../tegra/usb.c 59romstage-y += uart.c 60 61ramstage-y += addressmap.c 62ramstage-y += cbmem.c 63ramstage-y += cpu.c 64ramstage-y += clock.c 65ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c 66ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += dsi.c 67ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi_dsi.c 68ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi.c 69ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += mipi-phy.c 70ramstage-$(CONFIG_MAINBOARD_DO_DSI_INIT) += ./jdi_25x18_display/panel-jdi-lpm102a188a.c 71ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += dp.c 72ramstage-$(CONFIG_MAINBOARD_DO_SOR_INIT) += sor.c 73ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c 74 75ramstage-y += sdram_lp0.c 76ramstage-y += soc.c 77ramstage-y += spi.c 78ramstage-y += i2c.c 79ramstage-y += i2c6.c 80ramstage-y += ape.c 81ramstage-y += power.c 82ramstage-y += dma.c 83ramstage-y += monotonic_timer.c 84ramstage-y += padconfig.c 85ramstage-y += funitcfg.c 86ramstage-y += ram_code.c 87ramstage-y += ../tegra/apbmisc.c 88ramstage-y += ../tegra/gpio.c 89ramstage-y += ../tegra/i2c.c 90ramstage-y += ../tegra/pinmux.c 91ramstage-y += ramstage.c 92ramstage-y += mmu_operations.c 93ramstage-y += uart.c 94ramstage-y += ../tegra/usb.c 95ramstage-$(CONFIG_HAVE_MTC) += mtc.c 96ramstage-y += stage_entry.S 97 98rmodules_arm-y += monotonic_timer.c 99 100CPPFLAGS_common += -Isrc/soc/nvidia/tegra210/include/ 101 102# We want to grab the bootblock right before it goes into the image and wrap 103# it inside a BCT, but ideally we would do that without making special, one 104# use modifications to the main ARM Makefile. We do this in two ways. First, 105# we copy bootblock.elf to bootblock.raw.elf and allow the %.bin: %.elf 106# template rule to turn it into bootblock.raw.bin. This makes sure whatever 107# processing is supposed to happen to turn an .elf into a .bin happens. 108# 109# Second, we add our own rule for creating bootblock.bin from 110# bootblock.raw.bin which displaces the template rule. When other rules that 111# package up the image pull in bootblock.bin, it will be this wrapped version 112# instead of the raw bootblock. 113 114$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf 115 cp $< $@ 116 117$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) 118 @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" 119 $(CBOOTIMAGE) -gbct $(CBOOTIMAGE_OPTS) $< $@ 120 121BCT_BIN = $(obj)/generated/bct.bin 122BCT_WRAPPER = $(obj)/generated/bct.wrapper 123$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) 124 echo "Version = 1;" > $(BCT_WRAPPER) 125 echo "Redundancy = 1;" >> $(BCT_WRAPPER) 126 echo "Bctcopy = 1;" >> $(BCT_WRAPPER) 127 echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER) 128 echo "BootLoader = $<,$(call loadaddr,bootblock),$(call loadaddr,bootblock),Complete;" >> $(BCT_WRAPPER) 129 @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" 130 $(CBOOTIMAGE) $(CBOOTIMAGE_OPTS) $(BCT_WRAPPER) $@ 131 132# We need to ensure that TZ memory has enough space to hold TTB and resident EL3 133# components (including BL31 and Secure OS) 134ttb_size=$(shell printf "%d" $(CONFIG_TTB_SIZE_MB)) 135sec_size=$(shell printf "%d" $(CONFIG_SEC_COMPONENT_SIZE_MB)) 136req_tz_size=$(shell expr $(ttb_size) + $(sec_size)) 137 138tz_size=$(shell printf "%d" $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) 139 140ifeq ($(shell test $(tz_size) -lt $(req_tz_size) && echo 1), 1) 141 $(error "TRUSTZONE_CARVEOUT_SIZE_MB should be at least as big as TTB_SIZE_MB + SEC_COMPONENT_SIZE_MB") 142endif 143 144# BL31 component is placed towards the end of 32-bit address space. This assumes 145# that TrustZone memory is placed at the end of 32-bit address space. Within the 146# TZ memory, we place BL31 and BL32(if available) towards the beginning and TTB 147# towards the end. Calculate TZDRAM_BASE i.e. base of BL31 component by: 148# 0x1000 = end of 32-bit address space in MiB 149# 0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB) = start of TZ memory in MiB 150BL31_MAKEARGS += TZDRAM_BASE=$$(((0x1000 - $(CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB)) << 20)) 151BL31_MAKEARGS += PLAT=tegra TARGET_SOC=t210 152 153# MTC fw 154MTC_DIR = $(CONFIG_MTC_DIRECTORY) 155MTC_FILE = $(MTC_DIR)/$(CONFIG_MTC_FILE) 156MTC_FILE_CBFS = $(CONFIG_MTC_FILE) 157cbfs-files-$(CONFIG_HAVE_MTC) += $(MTC_FILE_CBFS) 158$(MTC_FILE_CBFS)-file := $(MTC_FILE) 159$(MTC_FILE_CBFS)-type := raw 160 161endif 162