xref: /aosp_15_r20/external/coreboot/src/soc/mediatek/mt8173/Makefile.mk (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1## SPDX-License-Identifier: GPL-2.0-only
2
3ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
4
5bootblock-y += bootblock.c
6bootblock-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
7bootblock-y += ../common/i2c.c i2c.c
8bootblock-y += ../common/pll.c pll.c
9bootblock-y += ../common/spi.c spi.c
10bootblock-y += ../common/timer.c
11bootblock-y += timer.c
12
13bootblock-y += ../common/uart.c
14
15bootblock-y += ../common/gpio.c gpio.c gpio_init.c
16bootblock-y +=  ../common/pmic_wrap.c pmic_wrap.c mt6391.c
17bootblock-y += ../common/wdt.c ../common/reset.c
18bootblock-y += ../common/mmu_operations.c mmu_operations.c
19
20################################################################################
21
22verstage-y += ../common/i2c.c i2c.c
23verstage-y += ../common/spi.c spi.c
24
25verstage-y += ../common/uart.c
26
27verstage-y += ../common/timer.c
28verstage-y += timer.c
29verstage-y += ../common/wdt.c ../common/reset.c
30verstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
31verstage-y += ../common/gpio.c gpio.c
32
33################################################################################
34
35romstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
36romstage-y += ../common/pll.c pll.c
37romstage-y += ../common/timer.c
38romstage-y += timer.c
39romstage-y += ../common/i2c.c i2c.c
40
41romstage-y += ../common/uart.c
42romstage-y += ../common/cbmem.c
43romstage-y += ../common/gpio.c gpio.c
44romstage-y += ../common/spi.c spi.c
45romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
46romstage-y += memory.c
47romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c
48romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c
49romstage-y += ../common/wdt.c ../common/reset.c
50romstage-y += ../common/mmu_operations.c mmu_operations.c
51romstage-y += ../common/rtc.c rtc.c
52
53################################################################################
54
55ramstage-y += emi.c
56ramstage-y += ../common/spi.c spi.c
57ramstage-$(CONFIG_SPI_FLASH) += ../common/flash_controller.c
58ramstage-y += soc.c ../common/mtcmos.c
59ramstage-y += ../common/timer.c
60ramstage-y += timer.c
61ramstage-y += ../common/uart.c
62ramstage-y += ../common/i2c.c i2c.c
63ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c
64ramstage-y += mt6311.c
65ramstage-y += da9212.c
66ramstage-y += ../common/gpio.c gpio.c
67ramstage-y += ../common/wdt.c ../common/reset.c
68ramstage-y += ../common/pll.c pll.c
69ramstage-y += ../common/rtc.c rtc.c
70
71ramstage-y += ../common/usb.c usb.c
72
73ramstage-y += ../common/ddp.c ddp.c
74ramstage-y += ../common/dsi.c dsi.c
75
76BL31_MAKEARGS += PLAT=mt8173
77
78################################################################################
79
80# Generate the actual coreboot bootblock code
81$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
82	./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
83
84CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
85CPPFLAGS_common += -Isrc/soc/mediatek/common/include
86
87endif
88