1## SPDX-License-Identifier: GPL-2.0-only 2ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) 3 4subdirs-y += ../../../cpu/intel/common 5subdirs-y += ../../../cpu/intel/microcode 6subdirs-y += ../../../cpu/intel/turbo 7 8bootblock-$(CONFIG_TPM_MEASURED_BOOT) += bootblock/bootblock_measure.c 9bootblock-y += bootblock/bootblock.c 10bootblock-y += ../common/block/cpu/pm_timer_emulation.c 11bootblock-y += car.c 12bootblock-y += heci.c 13bootblock-y += gspi.c 14bootblock-y += i2c.c 15bootblock-y += lpc.c 16bootblock-y += mmap_boot.c 17bootblock-y += pmutil.c 18bootblock-y += spi.c 19bootblock-y += uart.c 20 21romstage-y += car.c 22romstage-y += ../../../cpu/intel/car/romstage.c 23romstage-y += romstage.c 24romstage-y += report_platform.c 25romstage-y += gspi.c 26romstage-y += heci.c 27romstage-y += i2c.c 28romstage-y += uart.c 29romstage-y += meminit.c 30ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) 31romstage-y += meminit_util_glk.c 32else 33romstage-y += meminit_util_apl.c 34endif 35romstage-y += mmap_boot.c 36romstage-y += pmutil.c 37romstage-y += reset.c 38romstage-y += spi.c 39 40smm-y += mmap_boot.c 41smm-y += pmutil.c 42smm-y += smihandler.c 43smm-y += spi.c 44smm-y += uart.c 45smm-y += elog.c 46smm-y += xhci.c 47 48ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c 49ramstage-y += ahci.c 50ramstage-y += cpu.c 51ramstage-y += chip.c 52ramstage-y += cse.c 53ramstage-y += elog.c 54ramstage-y += graphics.c 55ramstage-y += gspi.c 56ramstage-y += heci.c 57ramstage-y += i2c.c 58ramstage-y += lockdown.c 59ramstage-y += lpc.c 60ramstage-y += mmap_boot.c 61ramstage-y += uart.c 62ramstage-y += nhlt.c 63ramstage-y += spi.c 64ramstage-y += systemagent.c 65ramstage-y += pmutil.c 66ramstage-y += pnpconfig.c 67ramstage-y += pmc.c 68ramstage-y += reset.c 69ramstage-y += xdci.c 70ramstage-y += sd.c 71ramstage-y += xhci.c 72 73postcar-y += mmap_boot.c 74postcar-y += spi.c 75postcar-y += i2c.c 76postcar-y += heci.c 77postcar-y += reset.c 78postcar-y += uart.c 79postcar-y += gspi.c 80 81verstage-y += car.c 82verstage-y += i2c.c 83verstage-y += gspi.c 84verstage-y += heci.c 85verstage-y += mmap_boot.c 86verstage-y += uart.c 87verstage-y += pmutil.c 88verstage-y += reset.c 89verstage-y += spi.c 90 91ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) 92bootblock-y += gpio_glk.c 93romstage-y += gpio_glk.c 94smm-y += gpio_glk.c 95ramstage-y += gpio_glk.c 96verstage-y += gpio_glk.c 97else 98bootblock-y += gpio_apl.c 99romstage-y += gpio_apl.c 100smm-y += gpio_apl.c 101ramstage-y += gpio_apl.c 102verstage-y += gpio_apl.c 103endif 104 105CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include 106 107# Since FSP-M runs in CAR we need to relocate it to a specific address 108$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) 109 110# Handle GLK paging requirements 111ifeq ($(CONFIG_PAGING_IN_CACHE_AS_RAM),y) 112cbfs-files-y += pt 113pt-file := pt.c:struct 114pt-type := raw 115cbfs-files-y += pdpt 116pdpt-file := pdpt.c:struct 117pdpt-type := raw 118endif 119 120ifeq ($(CONFIG_NEED_LBP2),y) 121$(objcbfs)/lbp2.bin: $(IFWITOOL) 122ifeq ($(CONFIG_LBP2_FROM_IFWI),y) 123 $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $@ -s 124 $(IFWITOOL) $@ delete -n OBBP 125else 126 cp $(CONFIG_LBP2_FILE_NAME) $@ 127endif 128 129$(call add_intermediate, write_lbp2, $(objcbfs)/lbp2.bin) 130 @printf " FMAP writing lbp2 to %s\n" $(CONFIG_LBP2_FMAP_NAME) 131 $(CBFSTOOL) $< write -r $(CONFIG_LBP2_FMAP_NAME) -f $< --fill-upward 132endif 133 134# Bootblock on Apollolake platform lies in the IFWI region. In order to place 135# the bootblock at the right location in IFWI image - 136# a. Using ifwitool: 137# 1. Create IFWI image (ifwi.bin.tmp) from input image 138# (CONFIG_IFWI_FILE_NAME). 139# 2. Delete OBBP sub-partition, if present. 140# 3. Replace IBBL directory entry in IBBP sub-partition with currently 141# generated bootblock.bin. 142# b. Using cbfstool: 143# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME. 144ifeq ($(CONFIG_NEED_IFWI),y) 145$(call add_intermediate, write_ifwi, $(objcbfs)/bootblock.bin $(IFWITOOL)) 146 @printf " IFWI Embedding %s in %s\n" $(objcbfs)/bootblock.bin $(CONFIG_IFWI_FMAP_NAME) 147 $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp 148 $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP 149 $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL 150 $(CBFSTOOL) $< write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward 151endif 152 153# When booting APL the IBBL loader places the microcode updates embedded 154# in the IFWI image and a matching FIT table in SRAM. After copying the 155# bootblock to SRAM, it updates the FIT pointer at 0xffffffc0 to point 156# to that table. Before releasing the x86 cores from reset, the regular FIT 157# mechanism does the updates. So coreboot does not need to generate a FIT 158# table + pointer, but reserving the pointer is still needed. Otherwise the 159# IBBL loader thrashes code there. So include fit.c so that the linker 160# reserves that pointer. 161bootblock-y += bootblock/fit.c 162 163# DSP firmware settings files. 164ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) 165NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/glk/nhlt-blobs 166else 167NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs 168endif 169DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin 170DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin 171DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin 172MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin 173DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin 174RT5682_RENDER_CAPTURE = rt5682-2ch-48khz-24b.bin 175 176cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B) 177$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B) 178$(DMIC_1CH_48KHZ_16B)-type := raw 179 180cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) 181$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) 182$(DMIC_2CH_48KHZ_16B)-type := raw 183 184cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) 185$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) 186$(DMIC_4CH_48KHZ_16B)-type := raw 187 188cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER) 189$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER) 190$(MAX98357_RENDER)-type := raw 191 192cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) 193$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) 194$(DA7219_RENDER_CAPTURE)-type := raw 195 196cbfs-files-$(CONFIG_NHLT_RT5682) += $(RT5682_RENDER_CAPTURE) 197$(RT5682_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(RT5682_RENDER_CAPTURE) 198$(RT5682_RENDER_CAPTURE)-type := raw 199 200ifeq ($(CONFIG_SOC_INTEL_GEMINILAKE),y) 201# Gemini Lake B0 (706a1) only atm. 202cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-7a-*) 203else 204# Apollo Lake 506c2, B0 (506c9) and E0 (506ca) only atm. 205cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-5c-*) 206endif 207 208endif # if CONFIG_SOC_INTEL_APOLLOLAKE 209