xref: /aosp_15_r20/external/coreboot/src/soc/amd/genoa_poc/Makefile.mk (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c) 
1## SPDX-License-Identifier: GPL-2.0-only
2ifeq ($(CONFIG_SOC_AMD_GENOA_POC),y)
3
4all-y		+= mmap_boot.c
5all-y		+= reset.c
6all-y		+= config.c
7all-y		+= gpio.c
8all-y		+= i2c.c
9all-y		+= uart.c
10
11bootblock-y	+= early_fch.c
12bootblock-y	+= aoac.c
13
14ramstage-y	+= acpi.c
15ramstage-y	+= aoac.c
16ramstage-y	+= chip.c
17ramstage-y	+= cpu.c
18ramstage-y	+= domain.c
19ramstage-y	+= fch.c
20ramstage-y	+= root_complex.c
21ramstage-y	+= smihandler.c
22ramstage-y	+= mca.c
23
24smm-y		+= smihandler.c
25smm-$(CONFIG_DEBUG_SMI) += uart.c
26
27CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/acpi
28CPPFLAGS_common += -I$(src)/soc/amd/genoa_poc/include
29
30ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
31CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
32endif
33
34#
35# PSP Directory Table items
36#
37# Certain ordering requirements apply, however these are ensured by amdfwtool.
38# For more information see "AMD Platform Security Processor BIOS Implementation
39# Guide for Server EPYC Processors" #57299
40#
41
42FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
43
44ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
45PSP_SOFTFUSE_BITS += 7
46endif
47
48ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
49# Enable secure debug unlock
50PSP_SOFTFUSE_BITS += 0
51OPT_TOKEN_UNLOCK="--token-unlock"
52endif
53
54# Use additional Soft Fuse bits specified in Kconfig
55PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
56
57# type = 0x3a
58ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
59PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
60endif
61
62# type = 0x55
63SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
64
65#
66# BIOS Directory Table items - proper ordering is managed by amdfwtool
67#
68
69# type = 0x60
70PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2)
71
72# type = 0x61
73PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
74
75# type = 0x62
76PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
77PSP_ELF_FILE=$(objcbfs)/bootblock.elf
78PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
79PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
80
81# Helper function to return a value with given bit set
82# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
83set-bit=$(call int-shift-left, 1 $(call _toint,$1))
84PSP_SOFTFUSE=$(shell A=$(call int-add, \
85		$(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A)
86
87#
88# Build the arguments to amdfwtool (order is unimportant).  Missing file names
89# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
90#
91
92add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
93
94OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
95                    $(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \
96                    $(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
97                    $(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \
98                    $(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \
99                    $(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
100
101OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
102OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
103OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
104OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
105
106OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
107OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
108OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
109OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
110
111OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
112OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
113
114AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
115		$(OPT_APOB_ADDR) \
116		$(OPT_DEBUG_AMDFWTOOL) \
117		$(OPT_PSP_BIOSBIN_FILE) \
118		$(OPT_PSP_BIOSBIN_DEST) \
119		$(OPT_PSP_BIOSBIN_SIZE) \
120		$(OPT_PSP_SOFTFUSE) \
121		--use-pspsecureos \
122		$(OPT_TOKEN_UNLOCK) \
123		$(OPT_WHITELIST_FILE) \
124		$(OPT_SPL_TABLE_FILE) \
125		$(OPT_EFS_SPI_READ_MODE) \
126		$(OPT_EFS_SPI_SPEED) \
127		$(OPT_EFS_SPI_MICRON_FLAG) \
128		--config $(CONFIG_AMDFW_CONFIG_FILE) \
129		--flashsize 0x1000000
130
131$(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
132			$$(PSP_APCB_FILES) \
133			$(DEP_FILES) \
134			$(AMDFWTOOL) \
135			$(obj)/fmap_config.h \
136			$(objcbfs)/bootblock.elf # this target also creates the .map file
137	$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
138	rm -f $@
139	@printf "    AMDFWTOOL  $(subst $(obj)/,,$(@))\n"
140	$(AMDFWTOOL) \
141		$(AMDFW_COMMON_ARGS) \
142		--location $(CONFIG_AMD_FWM_POSITION) \
143		--multilevel \
144		--output $@
145
146$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
147	rm -f $@
148	@printf "    AMDCOMPRS  $(subst $(obj)/,,$(@))\n"
149	$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
150		--maxsize $(PSP_BIOSBIN_SIZE)
151
152endif
153