1 /*
2 * Copyright (c) 2014-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <[email protected]>
25 */
26
27 #include "etnaviv_emit.h"
28
29 #include "etnaviv_blend.h"
30 #include "etnaviv_compiler.h"
31 #include "etnaviv_context.h"
32 #include "etnaviv_rasterizer.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_rs.h"
35 #include "etnaviv_screen.h"
36 #include "etnaviv_shader.h"
37 #include "etnaviv_texture.h"
38 #include "etnaviv_translate.h"
39 #include "etnaviv_uniforms.h"
40 #include "etnaviv_util.h"
41 #include "etnaviv_zsa.h"
42 #include "hw/state.xml.h"
43 #include "hw/state_blt.xml.h"
44 #include "util/u_math.h"
45
46 /* Queue a STALL command (queues 2 words) */
47 static inline void
CMD_STALL(struct etna_cmd_stream * stream,uint32_t from,uint32_t to)48 CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
49 {
50 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL);
51 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
52 }
53
54 void
etna_stall(struct etna_cmd_stream * stream,uint32_t from,uint32_t to)55 etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
56 {
57 bool blt = (from == SYNC_RECIPIENT_BLT) || (to == SYNC_RECIPIENT_BLT);
58 etna_cmd_stream_reserve(stream, blt ? 8 : 4);
59
60 if (blt) {
61 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
62 etna_cmd_stream_emit(stream, 1);
63 }
64
65 /* TODO: set bit 28/29 of token after BLT COPY_BUFFER */
66 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
67 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to));
68
69 if (from == SYNC_RECIPIENT_FE) {
70 /* if the frontend is to be stalled, queue a STALL frontend command */
71 CMD_STALL(stream, from, to);
72 } else {
73 /* otherwise, load the STALL token state */
74 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
75 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to));
76 }
77
78 if (blt) {
79 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
80 etna_cmd_stream_emit(stream, 0);
81 }
82 }
83
84 #define EMIT_STATE(state_name, src_value) \
85 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
86
87 #define EMIT_STATE_FIXP(state_name, src_value) \
88 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
89
90 #define EMIT_STATE_RELOC(state_name, src_value) \
91 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
92
93 #define ETNA_3D_CONTEXT_SIZE (400) /* keep this number above "Total state updates (fixed)" from gen_weave_state tool */
94
95 static unsigned
required_stream_size(struct etna_context * ctx)96 required_stream_size(struct etna_context *ctx)
97 {
98 unsigned size = ETNA_3D_CONTEXT_SIZE;
99
100 /* stall + flush */
101 size += 2 + 4;
102
103 /* vertex elements */
104 size += ctx->vertex_elements->num_elements + 1;
105
106 /* uniforms - worst case (2 words per uniform load) */
107 size += ctx->shader.vs->uniforms.count * 2;
108 size += ctx->shader.fs->uniforms.count * 2;
109
110 /* shader */
111 size += ctx->shader_state.vs_inst_mem_size + 1;
112 size += ctx->shader_state.ps_inst_mem_size + 1;
113
114 /* DRAW_INDEXED_PRIMITIVES command */
115 size += 6;
116
117 /* reserve for alignment etc. */
118 size += 64;
119
120 return size;
121 }
122
123 /* Emit state that only exists on HALTI5+ */
124 static void
emit_halti5_only_state(struct etna_context * ctx,int vs_output_count)125 emit_halti5_only_state(struct etna_context *ctx, int vs_output_count)
126 {
127 struct etna_cmd_stream *stream = ctx->stream;
128 uint32_t dirty = ctx->dirty;
129 struct etna_coalesce coalesce;
130
131 etna_coalesce_start(stream, &coalesce);
132 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
133 /* Magic states (load balancing, inter-unit sync, buffers) */
134 /*007C4*/ EMIT_STATE(FE_HALTI5_ID_CONFIG, ctx->shader_state.FE_HALTI5_ID_CONFIG);
135 /*00870*/ EMIT_STATE(VS_HALTI5_OUTPUT_COUNT, vs_output_count | ((vs_output_count * 0x10) << 8));
136 /*008A0*/ EMIT_STATE(VS_HALTI5_UNK008A0, 0x0001000e | ((0x110/vs_output_count) << 20));
137 for (int x = 0; x < VIVS_VS_HALTI5_OUTPUT__LEN; ++x) {
138 /*008E0*/ EMIT_STATE(VS_HALTI5_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
139 }
140 }
141 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
142 for (int x = 0; x < 4; ++x) {
143 /*008C0*/ EMIT_STATE(VS_HALTI5_INPUT(x), ctx->shader_state.VS_INPUT[x]);
144 }
145 }
146 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
147 /*00A90*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
148 /*00A94*/ EMIT_STATE(PA_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
149 /*00AA8*/ EMIT_STATE(PA_VS_OUTPUT_COUNT, vs_output_count);
150 /*01080*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(0), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
151 /*01084*/ EMIT_STATE(PS_VARYING_NUM_COMPONENTS(1), ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
152 /*03888*/ EMIT_STATE(GL_HALTI5_SH_SPECIALS, ctx->shader_state.GL_HALTI5_SH_SPECIALS);
153 }
154 etna_coalesce_end(stream, &coalesce);
155 }
156
157 /* Emit state that no longer exists on HALTI5 */
158 static void
emit_pre_halti5_state(struct etna_context * ctx)159 emit_pre_halti5_state(struct etna_context *ctx)
160 {
161 struct etna_cmd_stream *stream = ctx->stream;
162 uint32_t dirty = ctx->dirty;
163 struct etna_coalesce coalesce;
164
165 etna_coalesce_start(stream, &coalesce);
166 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
167 /*00800*/ EMIT_STATE(VS_END_PC, ctx->shader_state.VS_END_PC);
168 }
169 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
170 for (int x = 0; x < VIVS_VS_OUTPUT__LEN; ++x) {
171 /*00810*/ EMIT_STATE(VS_OUTPUT(x), ctx->shader_state.VS_OUTPUT[x]);
172 }
173 }
174 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
175 for (int x = 0; x < 4; ++x) {
176 /*00820*/ EMIT_STATE(VS_INPUT(x), ctx->shader_state.VS_INPUT[x]);
177 }
178 }
179 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
180 /*00838*/ EMIT_STATE(VS_START_PC, ctx->shader_state.VS_START_PC);
181 }
182 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
183 for (int x = 0; x < VIVS_PA_SHADER_ATTRIBUTES__LEN; ++x) {
184 /*00A40*/ EMIT_STATE(PA_SHADER_ATTRIBUTES(x), ctx->shader_state.PA_SHADER_ATTRIBUTES[x]);
185 }
186 }
187 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
188 /*00E04*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E04, ctx->framebuffer.RA_MULTISAMPLE_UNK00E04);
189 for (int x = 0; x < 4; ++x) {
190 /*00E10*/ EMIT_STATE(RA_MULTISAMPLE_UNK00E10(x), ctx->framebuffer.RA_MULTISAMPLE_UNK00E10[x]);
191 }
192 for (int x = 0; x < 16; ++x) {
193 /*00E40*/ EMIT_STATE(RA_CENTROID_TABLE(x), ctx->framebuffer.RA_CENTROID_TABLE[x]);
194 }
195 }
196 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
197 /*01000*/ EMIT_STATE(PS_END_PC, ctx->shader_state.PS_END_PC);
198 }
199 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
200 /*01018*/ EMIT_STATE(PS_START_PC, ctx->shader_state.PS_START_PC);
201 }
202 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
203 /*03820*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[0]);
204 for (int x = 0; x < 2; ++x) {
205 /*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
206 }
207 /*03834*/ EMIT_STATE(GL_VARYING_NUM_COMPONENTS2, ctx->shader_state.GL_VARYING_NUM_COMPONENTS[1]);
208 }
209 etna_coalesce_end(stream, &coalesce);
210 }
211
212 /* Weave state before draw operation. This function merges all the compiled
213 * state blocks under the context into one device register state. Parts of
214 * this state that are changed since last call (dirty) will be uploaded as
215 * state changes in the command buffer. */
216 void
etna_emit_state(struct etna_context * ctx)217 etna_emit_state(struct etna_context *ctx)
218 {
219 struct etna_cmd_stream *stream = ctx->stream;
220 struct etna_screen *screen = ctx->screen;
221 unsigned ccw = ctx->rasterizer->front_ccw;
222
223
224 /* Pre-reserve the command buffer space which we are likely to need.
225 * This must cover all the state emitted below, and the following
226 * draw command. */
227 etna_cmd_stream_reserve(stream, required_stream_size(ctx));
228
229 uint32_t dirty = ctx->dirty;
230
231 /* Pre-processing: see what caches we need to flush before making state changes. */
232 uint32_t to_flush = 0, to_flush_separate = 0;
233 if (unlikely(dirty & (ETNA_DIRTY_BLEND)))
234 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR;
235 if (unlikely(dirty & ETNA_DIRTY_ZSA))
236 to_flush |= VIVS_GL_FLUSH_CACHE_DEPTH;
237 if (unlikely(dirty & (ETNA_DIRTY_TEXTURE_CACHES))) {
238 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE;
239 to_flush_separate |= VIVS_GL_FLUSH_CACHE_TEXTUREVS;
240 }
241 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) /* Framebuffer config changed? */
242 to_flush |= VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH;
243 if (DBG_ENABLED(ETNA_DBG_CFLUSH_ALL)) {
244 to_flush |= VIVS_GL_FLUSH_CACHE_TEXTURE | VIVS_GL_FLUSH_CACHE_COLOR |
245 VIVS_GL_FLUSH_CACHE_DEPTH;
246 to_flush_separate |= VIVS_GL_FLUSH_CACHE_TEXTUREVS;
247 }
248
249 if (to_flush) {
250 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush);
251 if (to_flush_separate)
252 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush_separate);
253 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
254 }
255
256 /* Flush TS cache before changing TS configuration. */
257 if (unlikely(dirty & ETNA_DIRTY_TS)) {
258 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
259 }
260
261 /* Update vertex elements. This is different from any of the other states, in that
262 * a) the number of vertex elements written matters: so write only active ones
263 * b) the vertex element states must all be written: do not skip entries that stay the same */
264 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
265 if (screen->info->halti >= 5) {
266 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0),
267 ctx->vertex_elements->num_elements,
268 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG0);
269 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0),
270 ctx->vertex_elements->num_elements,
271 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
272 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0),
273 ctx->vertex_elements->num_elements,
274 ctx->vertex_elements->NFE_GENERIC_ATTRIB_CONFIG1);
275 } else {
276 /* Special case: vertex elements must always be sent in full if changed */
277 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
278 ctx->vertex_elements->num_elements,
279 ctx->vertex_elements->FE_VERTEX_ELEMENT_CONFIG);
280 if (screen->info->halti >= 2) {
281 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0),
282 ctx->vertex_elements->num_elements,
283 ctx->vertex_elements->NFE_GENERIC_ATTRIB_SCALE);
284 }
285 }
286 }
287 unsigned vs_output_count = etna_rasterizer_state(ctx->rasterizer)->point_size_per_vertex
288 ? ctx->shader_state.VS_OUTPUT_COUNT_PSIZE
289 : ctx->shader_state.VS_OUTPUT_COUNT;
290
291 /* The following code is originally generated by gen_merge_state.py, to
292 * emit state in increasing order of address (this makes it possible to merge
293 * consecutive register updates into one SET_STATE command)
294 *
295 * There have been some manual changes, where the weaving operation is not
296 * simply bitwise or:
297 * - scissor fixp
298 * - num vertex elements
299 * - scissor handling
300 * - num samplers
301 * - texture lod
302 * - ETNA_DIRTY_TS
303 * - removed ETNA_DIRTY_BASE_SETUP statements -- these are guaranteed to not
304 * change anyway
305 * - PS / framebuffer interaction for MSAA
306 * - move update of GL_MULTI_SAMPLE_CONFIG first
307 * - add unlikely()/likely()
308 */
309 struct etna_coalesce coalesce;
310
311 etna_coalesce_start(stream, &coalesce);
312
313 /* begin only EMIT_STATE -- make sure no new etna_reserve calls are done here
314 * directly
315 * or indirectly */
316 /* multi sample config is set first, and outside of the normal sorting
317 * order, as changing the multisample state clobbers PS.INPUT_COUNT (and
318 * possibly PS.TEMP_REGISTER_CONTROL).
319 */
320 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_SAMPLE_MASK))) {
321 uint32_t val = VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(ctx->sample_mask);
322 val |= ctx->framebuffer.GL_MULTI_SAMPLE_CONFIG;
323
324 /*03818*/ EMIT_STATE(GL_MULTI_SAMPLE_CONFIG, val);
325 }
326 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
327 /*00644*/ EMIT_STATE_RELOC(FE_INDEX_STREAM_BASE_ADDR, &ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR);
328 /*00648*/ EMIT_STATE(FE_INDEX_STREAM_CONTROL, ctx->index_buffer.FE_INDEX_STREAM_CONTROL);
329 }
330 if (likely(dirty & (ETNA_DIRTY_INDEX_BUFFER))) {
331 /*00674*/ EMIT_STATE(FE_PRIMITIVE_RESTART_INDEX, ctx->index_buffer.FE_PRIMITIVE_RESTART_INDEX);
332 }
333 if (likely(dirty & (ETNA_DIRTY_VERTEX_BUFFERS))) {
334 if (screen->info->halti >= 2) { /* HALTI2+: NFE_VERTEX_STREAMS */
335 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
336 /*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
337 }
338 } else if(screen->info->gpu.stream_count > 1) { /* hw w/ multiple vertex streams */
339 for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
340 /*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
341 }
342 } else { /* hw w/ single vertex stream */
343 /*0064C*/ EMIT_STATE_RELOC(FE_VERTEX_STREAM_BASE_ADDR, &ctx->vertex_buffer.cvb[0].FE_VERTEX_STREAM_BASE_ADDR);
344 }
345 }
346 /* gallium has instance divisor as part of elements state */
347 if (dirty & (ETNA_DIRTY_VERTEX_ELEMENTS)) {
348 for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) {
349 if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
350 if (screen->info->halti >= 2)
351 /*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
352 else if (screen->info->gpu.stream_count > 1)
353 /*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
354 else
355 /*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[0]);
356 }
357 }
358 if (screen->info->halti >= 2) {
359 for (int x = 0; x < ctx->vertex_elements->num_buffers; ++x) {
360 /*14680*/ EMIT_STATE(NFE_VERTEX_STREAMS_VERTEX_DIVISOR(x), ctx->vertex_elements->NFE_VERTEX_STREAMS_VERTEX_DIVISOR[x]);
361 }
362 }
363 }
364
365 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_RASTERIZER))) {
366
367 /*00804*/ EMIT_STATE(VS_OUTPUT_COUNT, vs_output_count);
368 }
369 if (unlikely(dirty & (ETNA_DIRTY_VERTEX_ELEMENTS | ETNA_DIRTY_SHADER))) {
370 /*00808*/ EMIT_STATE(VS_INPUT_COUNT, ctx->shader_state.VS_INPUT_COUNT);
371 /*0080C*/ EMIT_STATE(VS_TEMP_REGISTER_CONTROL, ctx->shader_state.VS_TEMP_REGISTER_CONTROL);
372 }
373 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
374 /*00830*/ EMIT_STATE(VS_LOAD_BALANCING, ctx->shader_state.VS_LOAD_BALANCING);
375 }
376 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
377 /*00A00*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_X, ctx->viewport.PA_VIEWPORT_SCALE_X);
378 /*00A04*/ EMIT_STATE_FIXP(PA_VIEWPORT_SCALE_Y, ctx->viewport.PA_VIEWPORT_SCALE_Y);
379 /*00A08*/ EMIT_STATE(PA_VIEWPORT_SCALE_Z, ctx->viewport.PA_VIEWPORT_SCALE_Z);
380 /*00A0C*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_X, ctx->viewport.PA_VIEWPORT_OFFSET_X);
381 /*00A10*/ EMIT_STATE_FIXP(PA_VIEWPORT_OFFSET_Y, ctx->viewport.PA_VIEWPORT_OFFSET_Y);
382 /*00A14*/ EMIT_STATE(PA_VIEWPORT_OFFSET_Z, ctx->viewport.PA_VIEWPORT_OFFSET_Z);
383 }
384 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
385 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
386
387 /*00A18*/ EMIT_STATE(PA_LINE_WIDTH, rasterizer->PA_LINE_WIDTH);
388 /*00A1C*/ EMIT_STATE(PA_POINT_SIZE, rasterizer->PA_POINT_SIZE);
389 /*00A28*/ EMIT_STATE(PA_SYSTEM_MODE, rasterizer->PA_SYSTEM_MODE);
390 }
391 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
392 /*00A30*/ EMIT_STATE(PA_ATTRIBUTE_ELEMENT_COUNT, ctx->shader_state.PA_ATTRIBUTE_ELEMENT_COUNT);
393 }
394 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_SHADER))) {
395 uint32_t val = etna_rasterizer_state(ctx->rasterizer)->PA_CONFIG;
396 /*00A34*/ EMIT_STATE(PA_CONFIG, val & ctx->shader_state.PA_CONFIG);
397 }
398 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
399 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
400 /*00A38*/ EMIT_STATE(PA_WIDE_LINE_WIDTH0, rasterizer->PA_LINE_WIDTH);
401 /*00A3C*/ EMIT_STATE(PA_WIDE_LINE_WIDTH1, rasterizer->PA_LINE_WIDTH);
402 }
403 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) {
404 /*00C00*/ EMIT_STATE_FIXP(SE_SCISSOR_LEFT, ctx->clipping.minx << 16);
405 /*00C04*/ EMIT_STATE_FIXP(SE_SCISSOR_TOP, ctx->clipping.miny << 16);
406 /*00C08*/ EMIT_STATE_FIXP(SE_SCISSOR_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_SCISSOR_MARGIN_RIGHT);
407 /*00C0C*/ EMIT_STATE_FIXP(SE_SCISSOR_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_SCISSOR_MARGIN_BOTTOM);
408 }
409 if (unlikely(dirty & (ETNA_DIRTY_RASTERIZER))) {
410 struct etna_rasterizer_state *rasterizer = etna_rasterizer_state(ctx->rasterizer);
411
412 /*00C10*/ EMIT_STATE(SE_DEPTH_SCALE, rasterizer->SE_DEPTH_SCALE);
413 /*00C14*/ EMIT_STATE(SE_DEPTH_BIAS, rasterizer->SE_DEPTH_BIAS);
414 /*00C18*/ EMIT_STATE(SE_CONFIG, rasterizer->SE_CONFIG);
415 }
416 if (unlikely(dirty & (ETNA_DIRTY_SCISSOR_CLIP))) {
417 /*00C20*/ EMIT_STATE_FIXP(SE_CLIP_RIGHT, (ctx->clipping.maxx << 16) + ETNA_SE_CLIP_MARGIN_RIGHT);
418 /*00C24*/ EMIT_STATE_FIXP(SE_CLIP_BOTTOM, (ctx->clipping.maxy << 16) + ETNA_SE_CLIP_MARGIN_BOTTOM);
419 }
420 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
421 /*00E00*/ EMIT_STATE(RA_CONTROL, ctx->shader_state.RA_CONTROL);
422 }
423 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
424 /*00E08*/ EMIT_STATE(RA_EARLY_DEPTH, etna_zsa_state(ctx->zsa)->RA_DEPTH_CONFIG);
425 }
426 if (unlikely(dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_FRAMEBUFFER))) {
427 /*01004*/ EMIT_STATE(PS_OUTPUT_REG, ctx->shader_state.PS_OUTPUT_REG);
428 /*01008*/ EMIT_STATE(PS_INPUT_COUNT,
429 ctx->framebuffer.msaa_mode
430 ? ctx->shader_state.PS_INPUT_COUNT_MSAA
431 : ctx->shader_state.PS_INPUT_COUNT);
432 /*0100C*/ EMIT_STATE(PS_TEMP_REGISTER_CONTROL,
433 ctx->framebuffer.msaa_mode
434 ? ctx->shader_state.PS_TEMP_REGISTER_CONTROL_MSAA
435 : ctx->shader_state.PS_TEMP_REGISTER_CONTROL);
436 /*01010*/ EMIT_STATE(PS_CONTROL, ctx->framebuffer.PS_CONTROL);
437 /*01030*/ EMIT_STATE(PS_CONTROL_EXT, ctx->framebuffer.PS_CONTROL_EXT);
438 }
439 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_FRAMEBUFFER))) {
440 /*01400*/ EMIT_STATE(PE_DEPTH_CONFIG, (etna_zsa_state(ctx->zsa)->PE_DEPTH_CONFIG |
441 ctx->framebuffer.PE_DEPTH_CONFIG));
442 }
443 if (unlikely(dirty & (ETNA_DIRTY_VIEWPORT))) {
444 /*01404*/ EMIT_STATE(PE_DEPTH_NEAR, ctx->viewport.PE_DEPTH_NEAR);
445 /*01408*/ EMIT_STATE(PE_DEPTH_FAR, ctx->viewport.PE_DEPTH_FAR);
446 }
447 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
448 /*0140C*/ EMIT_STATE(PE_DEPTH_NORMALIZE, ctx->framebuffer.PE_DEPTH_NORMALIZE);
449
450 if (screen->info->halti < 0 || screen->info->model == 0x880) {
451 /*01410*/ EMIT_STATE_RELOC(PE_DEPTH_ADDR, &ctx->framebuffer.PE_DEPTH_ADDR);
452 }
453
454 /*01414*/ EMIT_STATE(PE_DEPTH_STRIDE, ctx->framebuffer.PE_DEPTH_STRIDE);
455 }
456
457 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
458 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_OP[ccw];
459 /*01418*/ EMIT_STATE(PE_STENCIL_OP, val);
460 }
461 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER))) {
462 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG[ccw];
463 /*0141C*/ EMIT_STATE(PE_STENCIL_CONFIG, val | ctx->stencil_ref.PE_STENCIL_CONFIG[ccw]);
464 }
465 if (unlikely(dirty & (ETNA_DIRTY_ZSA))) {
466 uint32_t val = etna_zsa_state(ctx->zsa)->PE_ALPHA_OP;
467 /*01420*/ EMIT_STATE(PE_ALPHA_OP, val);
468 }
469 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR))) {
470 /*01424*/ EMIT_STATE(PE_ALPHA_BLEND_COLOR, ctx->blend_color.PE_ALPHA_BLEND_COLOR);
471 }
472 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
473 uint32_t val = etna_blend_state(ctx->blend)->PE_ALPHA_CONFIG;
474 /*01428*/ EMIT_STATE(PE_ALPHA_CONFIG, val);
475 }
476 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
477 uint32_t val;
478 /* Use the components and overwrite bits in framebuffer.PE_COLOR_FORMAT
479 * as a mask to enable the bits from blend PE_COLOR_FORMAT */
480 val = ~(VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK |
481 VIVS_PE_COLOR_FORMAT_OVERWRITE);
482 val |= etna_blend_state(ctx->blend)->PE_COLOR_FORMAT;
483 val &= ctx->framebuffer.PE_COLOR_FORMAT;
484 /*0142C*/ EMIT_STATE(PE_COLOR_FORMAT, val);
485 }
486 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER))) {
487 if (screen->info->halti >= 0 && screen->info->model != 0x880) {
488 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
489 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
490 /*01460*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(0), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[0]);
491 /*01464*/ EMIT_STATE_RELOC(PE_PIPE_COLOR_ADDR(1), &ctx->framebuffer.PE_PIPE_COLOR_ADDR[1]);
492 /*01480*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(0), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[0]);
493 /*01484*/ EMIT_STATE_RELOC(PE_PIPE_DEPTH_ADDR(1), &ctx->framebuffer.PE_PIPE_DEPTH_ADDR[1]);
494 } else {
495 /*01430*/ EMIT_STATE_RELOC(PE_COLOR_ADDR, &ctx->framebuffer.PE_COLOR_ADDR);
496 /*01434*/ EMIT_STATE(PE_COLOR_STRIDE, ctx->framebuffer.PE_COLOR_STRIDE);
497 /*01454*/ EMIT_STATE(PE_HDEPTH_CONTROL, ctx->framebuffer.PE_HDEPTH_CONTROL);
498 }
499 }
500 if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF | ETNA_DIRTY_RASTERIZER | ETNA_DIRTY_ZSA))) {
501 uint32_t val = etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT;
502 if (!ctx->zsa->stencil[1].enabled &&
503 ctx->zsa->stencil[0].enabled &&
504 ctx->zsa->stencil[0].valuemask)
505 val |= ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[!ccw];
506 else
507 val |= ctx->stencil_ref.PE_STENCIL_CONFIG_EXT[ccw];
508 /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, val);
509 }
510 if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) {
511 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
512 /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP);
513 }
514 if (unlikely(dirty & (ETNA_DIRTY_BLEND))) {
515 struct etna_blend_state *blend = etna_blend_state(ctx->blend);
516 for (int x = 0; x < 2; ++x) {
517 /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]);
518 }
519 }
520 if (unlikely(dirty & (ETNA_DIRTY_BLEND_COLOR)) &&
521 VIV_FEATURE(screen, ETNA_FEATURE_HALF_FLOAT)) {
522 /*014B0*/ EMIT_STATE(PE_ALPHA_COLOR_EXT0, ctx->blend_color.PE_ALPHA_COLOR_EXT0);
523 /*014B4*/ EMIT_STATE(PE_ALPHA_COLOR_EXT1, ctx->blend_color.PE_ALPHA_COLOR_EXT1);
524 }
525 if (unlikely(dirty & (ETNA_DIRTY_ZSA | ETNA_DIRTY_RASTERIZER))) {
526 /*014B8*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT2, etna_zsa_state(ctx->zsa)->PE_STENCIL_CONFIG_EXT2[ccw]);
527 }
528 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER)) && screen->info->halti >= 3)
529 /*014BC*/ EMIT_STATE(PE_MEM_CONFIG, ctx->framebuffer.PE_MEM_CONFIG);
530 if (unlikely(dirty & (ETNA_DIRTY_FRAMEBUFFER | ETNA_DIRTY_TS))) {
531 /*01654*/ EMIT_STATE(TS_MEM_CONFIG, ctx->framebuffer.TS_MEM_CONFIG);
532 /*01658*/ EMIT_STATE_RELOC(TS_COLOR_STATUS_BASE, &ctx->framebuffer.TS_COLOR_STATUS_BASE);
533 /*0165C*/ EMIT_STATE_RELOC(TS_COLOR_SURFACE_BASE, &ctx->framebuffer.TS_COLOR_SURFACE_BASE);
534 /*01660*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE, ctx->framebuffer.TS_COLOR_CLEAR_VALUE);
535 /*01664*/ EMIT_STATE_RELOC(TS_DEPTH_STATUS_BASE, &ctx->framebuffer.TS_DEPTH_STATUS_BASE);
536 /*01668*/ EMIT_STATE_RELOC(TS_DEPTH_SURFACE_BASE, &ctx->framebuffer.TS_DEPTH_SURFACE_BASE);
537 /*0166C*/ EMIT_STATE(TS_DEPTH_CLEAR_VALUE, ctx->framebuffer.TS_DEPTH_CLEAR_VALUE);
538 /*016BC*/ EMIT_STATE(TS_COLOR_CLEAR_VALUE_EXT, ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT);
539 }
540 if (unlikely(dirty & (ETNA_DIRTY_SHADER))) {
541 /*0381C*/ EMIT_STATE(GL_VARYING_TOTAL_COMPONENTS, ctx->shader_state.GL_VARYING_TOTAL_COMPONENTS);
542 }
543 etna_coalesce_end(stream, &coalesce);
544 /* end only EMIT_STATE */
545
546 /* Emit strongly architecture-specific state */
547 if (screen->info->halti >= 5)
548 emit_halti5_only_state(ctx, vs_output_count);
549 else
550 emit_pre_halti5_state(ctx);
551
552 /* Beginning from Halti0 some of the new shader and sampler states are not
553 * self-synchronizing anymore. Thus we need to stall the FE on PE completion
554 * before loading the new states to avoid corrupting the state of the
555 * in-flight draw.
556 */
557 if (screen->info->halti >= 0 &&
558 (ctx->dirty & (ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF |
559 ETNA_DIRTY_SAMPLERS | ETNA_DIRTY_SAMPLER_VIEWS)))
560 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
561
562 ctx->emit_texture_state(ctx);
563
564 /* We need to update the uniform cache only if one of the following bits are
565 * set in ctx->dirty:
566 * - ETNA_DIRTY_SHADER
567 * - ETNA_DIRTY_CONSTBUF
568 * - uniforms_dirty_bits
569 *
570 * In case of ETNA_DIRTY_SHADER we need load all uniforms from the cache. In
571 * all
572 * other cases we can load on the changed uniforms.
573 */
574 static const uint32_t uniform_dirty_bits =
575 ETNA_DIRTY_SHADER | ETNA_DIRTY_CONSTBUF;
576
577 /**** Large dynamically-sized state ****/
578 bool do_uniform_flush = screen->info->halti < 5;
579 if (dirty & (ETNA_DIRTY_SHADER)) {
580 /* Special case: a new shader was loaded; simply re-load all uniforms and
581 * shader code at once */
582 /* This sequence is special, do not change ordering unless necessary. According to comment
583 snippets in the Vivante kernel driver a process called "steering" goes on while programming
584 shader state. This (as I understand it) means certain unified states are "steered"
585 toward a specific shader unit (VS/PS/...) based on either explicit flags in register
586 00860, or what other state is written before "auto-steering". So this means some
587 state can legitimately be programmed multiple times.
588 */
589
590 if (screen->info->halti >= 5) { /* ICACHE (HALTI5) */
591 assert(ctx->shader_state.VS_INST_ADDR.bo && ctx->shader_state.PS_INST_ADDR.bo);
592 /* Set icache (VS) */
593 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
594 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
595 assert(ctx->shader_state.VS_INST_ADDR.bo);
596 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
597 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
598 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
599 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
600
601 /* Set icache (PS) */
602 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
603 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
604 assert(ctx->shader_state.PS_INST_ADDR.bo);
605 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
606 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
607 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
608 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
609
610 } else if (ctx->shader_state.VS_INST_ADDR.bo || ctx->shader_state.PS_INST_ADDR.bo) {
611 /* ICACHE (pre-HALTI5) */
612 assert(screen->specs.has_icache && screen->specs.has_shader_range_registers);
613 /* Set icache (VS) */
614 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
615 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
616 VIVS_VS_ICACHE_CONTROL_ENABLE |
617 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
618 assert(ctx->shader_state.VS_INST_ADDR.bo);
619 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
620
621 /* Set icache (PS) */
622 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16);
623 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
624 VIVS_VS_ICACHE_CONTROL_ENABLE |
625 VIVS_VS_ICACHE_CONTROL_FLUSH_PS);
626 assert(ctx->shader_state.PS_INST_ADDR.bo);
627 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
628 } else {
629 /* Upload shader directly, first flushing and disabling icache if
630 * supported on this hw */
631 if (screen->specs.has_icache) {
632 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
633 VIVS_VS_ICACHE_CONTROL_FLUSH_PS |
634 VIVS_VS_ICACHE_CONTROL_FLUSH_VS);
635 }
636 if (screen->specs.has_shader_range_registers) {
637 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
638 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
639 0x100);
640 }
641 etna_set_state_multi(stream, screen->specs.vs_offset,
642 ctx->shader_state.vs_inst_mem_size,
643 ctx->shader_state.VS_INST_MEM);
644 etna_set_state_multi(stream, screen->specs.ps_offset,
645 ctx->shader_state.ps_inst_mem_size,
646 ctx->shader_state.PS_INST_MEM);
647 }
648
649 if (screen->specs.has_unified_uniforms) {
650 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0);
651 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, screen->specs.max_vs_uniforms);
652 }
653
654 if (do_uniform_flush)
655 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
656
657 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
658
659 if (do_uniform_flush)
660 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
661
662 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
663
664 if (screen->info->halti >= 5) {
665 /* HALTI5 needs to be prompted to pre-fetch shaders */
666 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000);
667 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000);
668 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
669 }
670 } else {
671 /* ideally this cache would only be flushed if there are VS uniform changes */
672 if (do_uniform_flush)
673 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
674
675 if (dirty & (uniform_dirty_bits | ctx->shader.vs->uniforms_dirty_bits))
676 etna_uniforms_write(ctx, ctx->shader.vs, ctx->constant_buffer[PIPE_SHADER_VERTEX].cb);
677
678 /* ideally this cache would only be flushed if there are PS uniform changes */
679 if (do_uniform_flush)
680 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
681
682 if (dirty & (uniform_dirty_bits | ctx->shader.fs->uniforms_dirty_bits))
683 etna_uniforms_write(ctx, ctx->shader.fs, ctx->constant_buffer[PIPE_SHADER_FRAGMENT].cb);
684 }
685 /**** End of state update ****/
686 #undef EMIT_STATE
687 #undef EMIT_STATE_FIXP
688 #undef EMIT_STATE_RELOC
689 ctx->dirty = 0;
690 ctx->dirty_sampler_views = 0;
691 }
692