1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file elk_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "elk_eu.h"
31 #include "elk_disasm_info.h"
32 #include "elk_fs.h"
33 #include "elk_cfg.h"
34 #include "dev/intel_debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/half_float.h"
37
38 static enum elk_reg_file
elk_file_from_reg(elk_fs_reg * reg)39 elk_file_from_reg(elk_fs_reg *reg)
40 {
41 switch (reg->file) {
42 case ARF:
43 return ELK_ARCHITECTURE_REGISTER_FILE;
44 case FIXED_GRF:
45 case VGRF:
46 return ELK_GENERAL_REGISTER_FILE;
47 case MRF:
48 return ELK_MESSAGE_REGISTER_FILE;
49 case IMM:
50 return ELK_IMMEDIATE_VALUE;
51 case BAD_FILE:
52 case ATTR:
53 case UNIFORM:
54 unreachable("not reached");
55 }
56 return ELK_ARCHITECTURE_REGISTER_FILE;
57 }
58
59 static struct elk_reg
elk_reg_from_fs_reg(const struct intel_device_info * devinfo,elk_fs_inst * inst,elk_fs_reg * reg,bool compressed)60 elk_reg_from_fs_reg(const struct intel_device_info *devinfo, elk_fs_inst *inst,
61 elk_fs_reg *reg, bool compressed)
62 {
63 struct elk_reg elk_reg;
64
65 switch (reg->file) {
66 case MRF:
67 assert((reg->nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver));
68 FALLTHROUGH;
69 case VGRF:
70 if (reg->stride == 0) {
71 elk_reg = elk_vec1_reg(elk_file_from_reg(reg), reg->nr, 0);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * "VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries."
78 *
79 * The maximum width value that could satisfy this restriction is:
80 */
81 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
82
83 /* Because the hardware can only split source regions at a whole
84 * multiple of width during decompression (i.e. vertically), clamp
85 * the value obtained above to the physical execution size of a
86 * single decompressed chunk of the instruction:
87 */
88 const unsigned phys_width = compressed ? inst->exec_size / 2 :
89 inst->exec_size;
90
91 const unsigned max_hw_width = 16;
92
93 /* XXX - The equation above is strictly speaking not correct on
94 * hardware that supports unbalanced GRF writes -- On Gfx9+
95 * each decompressed chunk of the instruction may have a
96 * different execution size when the number of components
97 * written to each destination GRF is not the same.
98 */
99 if (reg->stride > 4) {
100 assert(reg != &inst->dst);
101 assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
102 elk_reg = elk_vecn_reg(1, elk_file_from_reg(reg), reg->nr, 0);
103 elk_reg = stride(elk_reg, reg->stride, 1, 0);
104 } else {
105 const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
106 elk_reg = elk_vecn_reg(width, elk_file_from_reg(reg), reg->nr, 0);
107 elk_reg = stride(elk_reg, width * reg->stride, width, reg->stride);
108 }
109
110 if (devinfo->verx10 == 70) {
111 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
112 * "Each DF (Double Float) operand uses an element size of 4 rather
113 * than 8 and all regioning parameters are twice what the values
114 * would be based on the true element size: ExecSize, Width,
115 * HorzStride, and VertStride. Each DF operand uses a pair of
116 * channels and all masking and swizzing should be adjusted
117 * appropriately."
118 *
119 * From the IvyBridge PRM (Special Requirements for Handling Double
120 * Precision Data Types, page 71):
121 * "In Align1 mode, all regioning parameters like stride, execution
122 * size, and width must use the syntax of a pair of packed
123 * floats. The offsets for these data types must be 64-bit
124 * aligned. The execution size and regioning parameters are in terms
125 * of floats."
126 *
127 * Summarized: when handling DF-typed arguments, ExecSize,
128 * VertStride, and Width must be doubled.
129 *
130 * It applies to BayTrail too.
131 */
132 if (type_sz(reg->type) == 8) {
133 elk_reg.width++;
134 if (elk_reg.vstride > 0)
135 elk_reg.vstride++;
136 assert(elk_reg.hstride == ELK_HORIZONTAL_STRIDE_1);
137 }
138
139 /* When converting from DF->F, we set the destination stride to 2
140 * because each d2f conversion implicitly writes 2 floats, being
141 * the first one the converted value. IVB/BYT actually writes two
142 * F components per SIMD channel, and every other component is
143 * filled with garbage.
144 */
145 if (reg == &inst->dst && get_exec_type_size(inst) == 8 &&
146 type_sz(inst->dst.type) < 8) {
147 assert(elk_reg.hstride > ELK_HORIZONTAL_STRIDE_1);
148 elk_reg.hstride--;
149 }
150 }
151 }
152
153 elk_reg = retype(elk_reg, reg->type);
154 elk_reg = byte_offset(elk_reg, reg->offset);
155 elk_reg.abs = reg->abs;
156 elk_reg.negate = reg->negate;
157 break;
158 case ARF:
159 case FIXED_GRF:
160 case IMM:
161 assert(reg->offset == 0);
162 elk_reg = reg->as_elk_reg();
163 break;
164 case BAD_FILE:
165 /* Probably unused. */
166 elk_reg = elk_null_reg();
167 break;
168 case ATTR:
169 case UNIFORM:
170 unreachable("not reached");
171 }
172
173 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
174 * region, but on IVB and BYT DF regions must be programmed in terms of
175 * floats. A <0,2,1> region accomplishes this.
176 */
177 if (devinfo->verx10 == 70 &&
178 type_sz(reg->type) == 8 &&
179 elk_reg.vstride == ELK_VERTICAL_STRIDE_0 &&
180 elk_reg.width == ELK_WIDTH_1 &&
181 elk_reg.hstride == ELK_HORIZONTAL_STRIDE_0) {
182 elk_reg.width = ELK_WIDTH_2;
183 elk_reg.hstride = ELK_HORIZONTAL_STRIDE_1;
184 }
185
186 return elk_reg;
187 }
188
elk_fs_generator(const struct elk_compiler * compiler,const struct elk_compile_params * params,struct elk_stage_prog_data * prog_data,bool runtime_check_aads_emit,gl_shader_stage stage)189 elk_fs_generator::elk_fs_generator(const struct elk_compiler *compiler,
190 const struct elk_compile_params *params,
191 struct elk_stage_prog_data *prog_data,
192 bool runtime_check_aads_emit,
193 gl_shader_stage stage)
194
195 : compiler(compiler), params(params),
196 devinfo(compiler->devinfo),
197 prog_data(prog_data), dispatch_width(0),
198 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
199 shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx)
200 {
201 p = rzalloc(mem_ctx, struct elk_codegen);
202 elk_init_codegen(&compiler->isa, p, mem_ctx);
203
204 /* In the FS code generator, we are very careful to ensure that we always
205 * set the right execution size so we don't need the EU code to "help" us
206 * by trying to infer it. Sometimes, it infers the wrong thing.
207 */
208 p->automatic_exec_sizes = false;
209 }
210
~elk_fs_generator()211 elk_fs_generator::~elk_fs_generator()
212 {
213 }
214
215 class ip_record : public exec_node {
216 public:
217 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
218
ip_record(int ip)219 ip_record(int ip)
220 {
221 this->ip = ip;
222 }
223
224 int ip;
225 };
226
227 bool
patch_halt_jumps()228 elk_fs_generator::patch_halt_jumps()
229 {
230 if (this->discard_halt_patches.is_empty())
231 return false;
232
233 int scale = elk_jump_scale(p->devinfo);
234
235 if (devinfo->ver >= 6) {
236 /* There is a somewhat strange undocumented requirement of using
237 * HALT, according to the simulator. If some channel has HALTed to
238 * a particular UIP, then by the end of the program, every channel
239 * must have HALTed to that UIP. Furthermore, the tracking is a
240 * stack, so you can't do the final halt of a UIP after starting
241 * halting to a new UIP.
242 *
243 * Symptoms of not emitting this instruction on actual hardware
244 * included GPU hangs and sparkly rendering on the piglit discard
245 * tests.
246 */
247 elk_inst *last_halt = elk_HALT(p);
248 elk_inst_set_uip(p->devinfo, last_halt, 1 * scale);
249 elk_inst_set_jip(p->devinfo, last_halt, 1 * scale);
250 }
251
252 int ip = p->nr_insn;
253
254 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
255 elk_inst *patch = &p->store[patch_ip->ip];
256
257 assert(elk_inst_opcode(p->isa, patch) == ELK_OPCODE_HALT);
258 if (devinfo->ver >= 6) {
259 /* HALT takes a half-instruction distance from the pre-incremented IP. */
260 elk_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
261 } else {
262 elk_set_src1(p, patch, elk_imm_d((ip - patch_ip->ip) * scale));
263 }
264 }
265
266 this->discard_halt_patches.make_empty();
267
268 if (devinfo->ver < 6) {
269 /* From the g965 PRM:
270 *
271 * "As DMask is not automatically reloaded into AMask upon completion
272 * of this instruction, software has to manually restore AMask upon
273 * completion."
274 *
275 * DMask lives in the bottom 16 bits of sr0.1.
276 */
277 elk_inst *reset = elk_MOV(p, elk_mask_reg(ELK_AMASK),
278 retype(elk_sr0_reg(1), ELK_REGISTER_TYPE_UW));
279 elk_inst_set_exec_size(devinfo, reset, ELK_EXECUTE_1);
280 elk_inst_set_mask_control(devinfo, reset, ELK_MASK_DISABLE);
281 elk_inst_set_qtr_control(devinfo, reset, ELK_COMPRESSION_NONE);
282 elk_inst_set_thread_control(devinfo, reset, ELK_THREAD_SWITCH);
283 }
284
285 if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) {
286 /* From the g965 PRM:
287 *
288 * "[DevBW, DevCL] Erratum: The subfields in mask stack register are
289 * reset to zero during graphics reset, however, they are not
290 * initialized at thread dispatch. These subfields will retain the
291 * values from the previous thread. Software should make sure the
292 * mask stack is empty (reset to zero) before terminating the thread.
293 * In case that this is not practical, software may have to reset the
294 * mask stack at the beginning of each kernel, which will impact the
295 * performance."
296 *
297 * Luckily we can rely on:
298 *
299 * "[DevBW, DevCL] This register access restriction is not
300 * applicable, hardware does ensure execution pipeline coherency,
301 * when a mask stack register is used as an explicit source and/or
302 * destination."
303 */
304 elk_push_insn_state(p);
305 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
306 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
307
308 elk_set_default_exec_size(p, ELK_EXECUTE_2);
309 elk_MOV(p, vec2(elk_mask_stack_depth_reg(0)), elk_imm_uw(0));
310
311 elk_set_default_exec_size(p, ELK_EXECUTE_16);
312 /* Reset the if stack. */
313 elk_MOV(p, retype(elk_mask_stack_reg(0), ELK_REGISTER_TYPE_UW),
314 elk_imm_uw(0));
315
316 elk_pop_insn_state(p);
317 }
318
319 return true;
320 }
321
322 void
generate_send(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg desc,struct elk_reg payload)323 elk_fs_generator::generate_send(elk_fs_inst *inst,
324 struct elk_reg dst,
325 struct elk_reg desc,
326 struct elk_reg payload)
327 {
328 const bool dst_is_null = dst.file == ELK_ARCHITECTURE_REGISTER_FILE &&
329 dst.nr == ELK_ARF_NULL;
330 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE;
331
332 uint32_t desc_imm = inst->desc |
333 elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size);
334
335 elk_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
336 inst->eot);
337 if (inst->check_tdr)
338 elk_inst_set_opcode(p->isa, elk_last_inst, ELK_OPCODE_SENDC);
339 }
340
341 void
fire_fb_write(elk_fs_inst * inst,struct elk_reg payload,struct elk_reg implied_header,GLuint nr)342 elk_fs_generator::fire_fb_write(elk_fs_inst *inst,
343 struct elk_reg payload,
344 struct elk_reg implied_header,
345 GLuint nr)
346 {
347 struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data);
348
349 if (devinfo->ver < 6) {
350 elk_push_insn_state(p);
351 elk_set_default_exec_size(p, ELK_EXECUTE_8);
352 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
353 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
354 elk_set_default_flag_reg(p, 0, 0);
355 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
356 elk_MOV(p, offset(retype(payload, ELK_REGISTER_TYPE_UD), 1),
357 offset(retype(implied_header, ELK_REGISTER_TYPE_UD), 1));
358 elk_pop_insn_state(p);
359 }
360
361 uint32_t msg_control = elk_fb_write_msg_control(inst, prog_data);
362
363 /* We assume render targets start at 0, because headerless FB write
364 * messages set "Render Target Index" to 0. Using a different binding
365 * table index would make it impossible to use headerless messages.
366 */
367 const uint32_t surf_index = inst->target;
368
369 elk_inst *insn = elk_fb_WRITE(p,
370 payload,
371 retype(implied_header, ELK_REGISTER_TYPE_UW),
372 msg_control,
373 surf_index,
374 nr,
375 0,
376 inst->eot,
377 inst->last_rt,
378 inst->header_size != 0);
379
380 if (devinfo->ver >= 6)
381 elk_inst_set_rt_slot_group(devinfo, insn, inst->group / 16);
382 }
383
384 void
generate_fb_write(elk_fs_inst * inst,struct elk_reg payload)385 elk_fs_generator::generate_fb_write(elk_fs_inst *inst, struct elk_reg payload)
386 {
387 assert(devinfo->ver < 7);
388
389 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
390 elk_set_default_flag_reg(p, 0, 0);
391
392 const struct elk_reg implied_header =
393 devinfo->ver < 6 ? payload : elk_null_reg();
394
395 if (inst->base_mrf >= 0)
396 payload = elk_message_reg(inst->base_mrf);
397
398 if (!runtime_check_aads_emit) {
399 fire_fb_write(inst, payload, implied_header, inst->mlen);
400 } else {
401 /* This can only happen in gen < 6 */
402 assert(devinfo->ver < 6);
403
404 struct elk_reg v1_null_ud = vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD));
405
406 /* Check runtime bit to detect if we have to send AA data or not */
407 elk_push_insn_state(p);
408 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
409 elk_set_default_exec_size(p, ELK_EXECUTE_1);
410 elk_AND(p,
411 v1_null_ud,
412 retype(elk_vec1_grf(1, 6), ELK_REGISTER_TYPE_UD),
413 elk_imm_ud(1<<26));
414 elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
415
416 int jmp = elk_JMPI(p, elk_imm_ud(0), ELK_PREDICATE_NORMAL) - p->store;
417 elk_pop_insn_state(p);
418 {
419 /* Don't send AA data */
420 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
421 }
422 elk_land_fwd_jump(p, jmp);
423 fire_fb_write(inst, payload, implied_header, inst->mlen);
424 }
425 }
426
427 void
generate_mov_indirect(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg reg,struct elk_reg indirect_byte_offset)428 elk_fs_generator::generate_mov_indirect(elk_fs_inst *inst,
429 struct elk_reg dst,
430 struct elk_reg reg,
431 struct elk_reg indirect_byte_offset)
432 {
433 assert(indirect_byte_offset.type == ELK_REGISTER_TYPE_UD);
434 assert(indirect_byte_offset.file == ELK_GENERAL_REGISTER_FILE);
435 assert(!reg.abs && !reg.negate);
436
437 /* Gen12.5 adds the following region restriction:
438 *
439 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
440 * and Quad-Word data must not be used."
441 *
442 * We require the source and destination types to match so stomp to an
443 * unsigned integer type.
444 */
445 assert(reg.type == dst.type);
446 reg.type = dst.type = elk_reg_type_from_bit_size(type_sz(reg.type) * 8,
447 ELK_REGISTER_TYPE_UD);
448
449 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
450
451 if (indirect_byte_offset.file == ELK_IMMEDIATE_VALUE) {
452 imm_byte_offset += indirect_byte_offset.ud;
453
454 reg.nr = imm_byte_offset / REG_SIZE;
455 reg.subnr = imm_byte_offset % REG_SIZE;
456 if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
457 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0),
458 subscript(reg, ELK_REGISTER_TYPE_D, 0));
459 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1),
460 subscript(reg, ELK_REGISTER_TYPE_D, 1));
461 } else {
462 elk_MOV(p, dst, reg);
463 }
464 } else {
465 /* Prior to Broadwell, there are only 8 address registers. */
466 assert(inst->exec_size <= 8 || devinfo->ver >= 8);
467
468 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
469 struct elk_reg addr = vec8(elk_address_reg(0));
470
471 /* Whether we can use destination dependency control without running the
472 * risk of a hang if an instruction gets shot down.
473 */
474 const bool use_dep_ctrl = !inst->predicate &&
475 inst->exec_size == dispatch_width;
476 elk_inst *insn;
477
478 /* The destination stride of an instruction (in bytes) must be greater
479 * than or equal to the size of the rest of the instruction. Since the
480 * address register is of type UW, we can't use a D-type instruction.
481 * In order to get around this, re retype to UW and use a stride.
482 */
483 indirect_byte_offset =
484 retype(spread(indirect_byte_offset, 2), ELK_REGISTER_TYPE_UW);
485
486 /* There are a number of reasons why we don't use the base offset here.
487 * One reason is that the field is only 9 bits which means we can only
488 * use it to access the first 16 GRFs. Also, from the Haswell PRM
489 * section "Register Region Restrictions":
490 *
491 * "The lower bits of the AddressImmediate must not overflow to
492 * change the register address. The lower 5 bits of Address
493 * Immediate when added to lower 5 bits of address register gives
494 * the sub-register offset. The upper bits of Address Immediate
495 * when added to upper bits of address register gives the register
496 * address. Any overflow from sub-register offset is dropped."
497 *
498 * Since the indirect may cause us to cross a register boundary, this
499 * makes the base offset almost useless. We could try and do something
500 * clever where we use a actual base offset if base_offset % 32 == 0 but
501 * that would mean we were generating different code depending on the
502 * base offset. Instead, for the sake of consistency, we'll just do the
503 * add ourselves. This restriction is only listed in the Haswell PRM
504 * but empirical testing indicates that it applies on all older
505 * generations and is lifted on Broadwell.
506 *
507 * In the end, while base_offset is nice to look at in the generated
508 * code, using it saves us 0 instructions and would require quite a bit
509 * of case-by-case work. It's just not worth it.
510 *
511 * Due to a hardware bug some platforms (particularly Gfx11+) seem to
512 * require the address components of all channels to be valid whether or
513 * not they're active, which causes issues if we use VxH addressing
514 * under non-uniform control-flow. We can easily work around that by
515 * initializing the whole address register with a pipelined NoMask MOV
516 * instruction.
517 */
518 if (devinfo->ver >= 7) {
519 insn = elk_MOV(p, addr, elk_imm_uw(imm_byte_offset));
520 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
521 elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE);
522 elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
523 }
524
525 insn = elk_ADD(p, addr, indirect_byte_offset, elk_imm_uw(imm_byte_offset));
526 if (devinfo->ver >= 7)
527 elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
528
529 if (type_sz(reg.type) > 4 &&
530 (devinfo->verx10 == 70 || devinfo->platform == INTEL_PLATFORM_CHV ||
531 !devinfo->has_64bit_float)) {
532 /* IVB has an issue (which we found empirically) where it reads two
533 * address register components per channel for indirectly addressed
534 * 64-bit sources.
535 *
536 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
537 *
538 * "When source or destination datatype is 64b or operation is
539 * integer DWord multiply, indirect addressing must not be used."
540 *
541 * To work around both of these, we do two integer MOVs insead of one
542 * 64-bit MOV. Because no double value should ever cross a register
543 * boundary, it's safe to use the immediate offset in the indirect
544 * here to handle adding 4 bytes to the offset and avoid the extra
545 * ADD to the register file.
546 */
547 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0),
548 retype(elk_VxH_indirect(0, 0), ELK_REGISTER_TYPE_D));
549 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1),
550 retype(elk_VxH_indirect(0, 4), ELK_REGISTER_TYPE_D));
551 } else {
552 struct elk_reg ind_src = elk_VxH_indirect(0, 0);
553
554 elk_inst *mov = elk_MOV(p, dst, retype(ind_src, reg.type));
555
556 if (devinfo->ver == 6 && dst.file == ELK_MESSAGE_REGISTER_FILE &&
557 !inst->get_next()->is_tail_sentinel() &&
558 ((elk_fs_inst *)inst->get_next())->mlen > 0) {
559 /* From the Sandybridge PRM:
560 *
561 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
562 * instruction that “indexed/indirect” source AND is followed
563 * by a send, the instruction requires a “Switch”. This is to
564 * avoid race condition where send may dispatch before MRF is
565 * updated."
566 */
567 elk_inst_set_thread_control(devinfo, mov, ELK_THREAD_SWITCH);
568 }
569 }
570 }
571 }
572
573 void
generate_shuffle(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src,struct elk_reg idx)574 elk_fs_generator::generate_shuffle(elk_fs_inst *inst,
575 struct elk_reg dst,
576 struct elk_reg src,
577 struct elk_reg idx)
578 {
579 assert(src.file == ELK_GENERAL_REGISTER_FILE);
580 assert(!src.abs && !src.negate);
581
582 /* Ivy bridge has some strange behavior that makes this a real pain to
583 * implement for 64-bit values so we just don't bother.
584 */
585 assert((devinfo->verx10 >= 75 && devinfo->has_64bit_float) ||
586 type_sz(src.type) <= 4);
587
588 /* Gen12.5 adds the following region restriction:
589 *
590 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
591 * and Quad-Word data must not be used."
592 *
593 * We require the source and destination types to match so stomp to an
594 * unsigned integer type.
595 */
596 assert(src.type == dst.type);
597 src.type = dst.type = elk_reg_type_from_bit_size(type_sz(src.type) * 8,
598 ELK_REGISTER_TYPE_UD);
599
600 /* Because we're using the address register, we're limited to 8-wide
601 * execution on gfx7. On gfx8, we're limited to 16-wide by the address
602 * register file and 8-wide for 64-bit types. We could try and make this
603 * instruction splittable higher up in the compiler but that gets weird
604 * because it reads all of the channels regardless of execution size. It's
605 * easier just to split it here.
606 */
607 const unsigned lower_width =
608 devinfo->ver <= 7 || element_sz(src) > 4 || element_sz(dst) > 4 ? 8 :
609 MIN2(16, inst->exec_size);
610
611 elk_set_default_exec_size(p, cvt(lower_width) - 1);
612 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
613 elk_set_default_group(p, group);
614
615 if ((src.vstride == 0 && src.hstride == 0) ||
616 idx.file == ELK_IMMEDIATE_VALUE) {
617 /* Trivial, the source is already uniform or the index is a constant.
618 * We will typically not get here if the optimizer is doing its job,
619 * but asserting would be mean.
620 */
621 const unsigned i = idx.file == ELK_IMMEDIATE_VALUE ? idx.ud : 0;
622 struct elk_reg group_src = stride(suboffset(src, i), 0, 1, 0);
623 struct elk_reg group_dst = suboffset(dst, group << (dst.hstride - 1));
624 elk_MOV(p, group_dst, group_src);
625 } else {
626 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
627 struct elk_reg addr = vec8(elk_address_reg(0));
628
629 struct elk_reg group_idx = suboffset(idx, group);
630
631 if (lower_width == 8 && group_idx.width == ELK_WIDTH_16) {
632 /* Things get grumpy if the register is too wide. */
633 group_idx.width--;
634 group_idx.vstride--;
635 }
636
637 assert(type_sz(group_idx.type) <= 4);
638 if (type_sz(group_idx.type) == 4) {
639 /* The destination stride of an instruction (in bytes) must be
640 * greater than or equal to the size of the rest of the
641 * instruction. Since the address register is of type UW, we
642 * can't use a D-type instruction. In order to get around this,
643 * re retype to UW and use a stride.
644 */
645 group_idx = retype(spread(group_idx, 2), ELK_REGISTER_TYPE_W);
646 }
647
648 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
649
650 /* From the Haswell PRM:
651 *
652 * "When a sequence of NoDDChk and NoDDClr are used, the last
653 * instruction that completes the scoreboard clear must have a
654 * non-zero execution mask. This means, if any kind of predication
655 * can change the execution mask or channel enable of the last
656 * instruction, the optimization must be avoided. This is to
657 * avoid instructions being shot down the pipeline when no writes
658 * are required."
659 *
660 * Whenever predication is enabled or the instructions being emitted
661 * aren't the full width, it's possible that it will be run with zero
662 * channels enabled so we can't use dependency control without
663 * running the risk of a hang if an instruction gets shot down.
664 */
665 const bool use_dep_ctrl = !inst->predicate &&
666 lower_width == dispatch_width;
667 elk_inst *insn;
668
669 /* Due to a hardware bug some platforms (particularly Gfx11+) seem
670 * to require the address components of all channels to be valid
671 * whether or not they're active, which causes issues if we use VxH
672 * addressing under non-uniform control-flow. We can easily work
673 * around that by initializing the whole address register with a
674 * pipelined NoMask MOV instruction.
675 */
676 insn = elk_MOV(p, addr, elk_imm_uw(src_start_offset));
677 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
678 elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE);
679 elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
680
681 /* Take into account the component size and horizontal stride. */
682 assert(src.vstride == src.hstride + src.width);
683 insn = elk_SHL(p, addr, group_idx,
684 elk_imm_uw(util_logbase2(type_sz(src.type)) +
685 src.hstride - 1));
686 elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
687
688 /* Add on the register start offset */
689 elk_ADD(p, addr, addr, elk_imm_uw(src_start_offset));
690 elk_MOV(p, suboffset(dst, group << (dst.hstride - 1)),
691 retype(elk_VxH_indirect(0, 0), src.type));
692 }
693 }
694 }
695
696 void
generate_quad_swizzle(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src,unsigned swiz)697 elk_fs_generator::generate_quad_swizzle(const elk_fs_inst *inst,
698 struct elk_reg dst, struct elk_reg src,
699 unsigned swiz)
700 {
701 /* Requires a quad. */
702 assert(inst->exec_size >= 4);
703
704 if (src.file == ELK_IMMEDIATE_VALUE ||
705 has_scalar_region(src)) {
706 /* The value is uniform across all channels */
707 elk_MOV(p, dst, src);
708
709 } else if (type_sz(src.type) == 4) {
710 /* This only works on 8-wide 32-bit values */
711 assert(inst->exec_size == 8);
712 assert(src.hstride == ELK_HORIZONTAL_STRIDE_1);
713 assert(src.vstride == src.width + 1);
714 elk_set_default_access_mode(p, ELK_ALIGN_16);
715 struct elk_reg swiz_src = stride(src, 4, 4, 1);
716 swiz_src.swizzle = swiz;
717 elk_MOV(p, dst, swiz_src);
718
719 } else {
720 assert(src.hstride == ELK_HORIZONTAL_STRIDE_1);
721 assert(src.vstride == src.width + 1);
722 const struct elk_reg src_0 = suboffset(src, ELK_GET_SWZ(swiz, 0));
723
724 switch (swiz) {
725 case ELK_SWIZZLE_XXXX:
726 case ELK_SWIZZLE_YYYY:
727 case ELK_SWIZZLE_ZZZZ:
728 case ELK_SWIZZLE_WWWW:
729 elk_MOV(p, dst, stride(src_0, 4, 4, 0));
730 break;
731
732 case ELK_SWIZZLE_XXZZ:
733 case ELK_SWIZZLE_YYWW:
734 elk_MOV(p, dst, stride(src_0, 2, 2, 0));
735 break;
736
737 case ELK_SWIZZLE_XYXY:
738 case ELK_SWIZZLE_ZWZW:
739 assert(inst->exec_size == 4);
740 elk_MOV(p, dst, stride(src_0, 0, 2, 1));
741 break;
742
743 default:
744 assert(inst->force_writemask_all);
745 elk_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
746
747 for (unsigned c = 0; c < 4; c++) {
748 elk_inst *insn = elk_MOV(
749 p, stride(suboffset(dst, c),
750 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
751 stride(suboffset(src, ELK_GET_SWZ(swiz, c)), 4, 1, 0));
752
753 elk_inst_set_no_dd_clear(devinfo, insn, c < 3);
754 elk_inst_set_no_dd_check(devinfo, insn, c > 0);
755 }
756
757 break;
758 }
759 }
760 }
761
762 void
generate_cs_terminate(elk_fs_inst * inst,struct elk_reg payload)763 elk_fs_generator::generate_cs_terminate(elk_fs_inst *inst, struct elk_reg payload)
764 {
765 struct elk_inst *insn;
766
767 insn = elk_next_insn(p, ELK_OPCODE_SEND);
768
769 elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW));
770 elk_set_src0(p, insn, retype(payload, ELK_REGISTER_TYPE_UW));
771 elk_set_src1(p, insn, elk_imm_ud(0u));
772
773 elk_inst_set_sfid(devinfo, insn, ELK_SFID_THREAD_SPAWNER);
774 elk_inst_set_mlen(devinfo, insn, 1);
775 elk_inst_set_rlen(devinfo, insn, 0);
776 elk_inst_set_eot(devinfo, insn, inst->eot);
777 elk_inst_set_header_present(devinfo, insn, false);
778
779 elk_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
780
781 elk_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
782
783 /* Note that even though the thread has a URB resource associated with it,
784 * we set the "do not dereference URB" bit, because the URB resource is
785 * managed by the fixed-function unit, so it will free it automatically.
786 */
787 elk_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
788
789 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
790 }
791
792 void
generate_barrier(elk_fs_inst *,struct elk_reg src)793 elk_fs_generator::generate_barrier(elk_fs_inst *, struct elk_reg src)
794 {
795 elk_barrier(p, src);
796 elk_WAIT(p);
797 }
798
799 bool
generate_linterp(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg * src)800 elk_fs_generator::generate_linterp(elk_fs_inst *inst,
801 struct elk_reg dst, struct elk_reg *src)
802 {
803 /* PLN reads:
804 * / in SIMD16 \
805 * -----------------------------------
806 * | src1+0 | src1+1 | src1+2 | src1+3 |
807 * |-----------------------------------|
808 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
809 * -----------------------------------
810 *
811 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
812 *
813 * -----------------------------------
814 * | src1+0 | src1+1 | src1+2 | src1+3 |
815 * |-----------------------------------|
816 * |(x0, x1)|(y0, y1)| | | in SIMD8
817 * |-----------------------------------|
818 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
819 * -----------------------------------
820 *
821 * See also: emit_interpolation_setup_gfx4().
822 */
823 struct elk_reg delta_x = src[0];
824 struct elk_reg delta_y = offset(src[0], inst->exec_size / 8);
825 struct elk_reg interp = src[1];
826 elk_inst *i[2];
827
828 if (devinfo->has_pln) {
829 if (devinfo->ver <= 6 && (delta_x.nr & 1) != 0) {
830 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
831 *
832 * "[DevSNB]:<src1> must be even register aligned.
833 *
834 * This restriction is lifted on Ivy Bridge.
835 *
836 * This means that we need to split PLN into LINE+MAC on-the-fly.
837 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
838 * we have to split into SIMD8 pieces. For gfx4 (!has_pln), the
839 * coordinate registers are laid out differently so we leave it as a
840 * SIMD16 instruction.
841 */
842 assert(inst->exec_size == 8 || inst->exec_size == 16);
843 assert(inst->group % 16 == 0);
844
845 elk_push_insn_state(p);
846 elk_set_default_exec_size(p, ELK_EXECUTE_8);
847
848 /* Thanks to two accumulators, we can emit all the LINEs and then all
849 * the MACs. This improves parallelism a bit.
850 */
851 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
852 elk_inst *line = elk_LINE(p, elk_null_reg(), interp,
853 offset(delta_x, g * 2));
854 elk_inst_set_group(devinfo, line, inst->group + g * 8);
855
856 /* LINE writes the accumulator automatically on gfx4-5. On Sandy
857 * Bridge and later, we have to explicitly enable it.
858 */
859 if (devinfo->ver >= 6)
860 elk_inst_set_acc_wr_control(p->devinfo, line, true);
861
862 /* elk_set_default_saturate() is called before emitting
863 * instructions, so the saturate bit is set in each instruction,
864 * so we need to unset it on the LINE instructions.
865 */
866 elk_inst_set_saturate(p->devinfo, line, false);
867 }
868
869 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
870 elk_inst *mac = elk_MAC(p, offset(dst, g), suboffset(interp, 1),
871 offset(delta_x, g * 2 + 1));
872 elk_inst_set_group(devinfo, mac, inst->group + g * 8);
873 elk_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod);
874 }
875
876 elk_pop_insn_state(p);
877
878 return true;
879 } else {
880 elk_PLN(p, dst, interp, delta_x);
881
882 return false;
883 }
884 } else {
885 i[0] = elk_LINE(p, elk_null_reg(), interp, delta_x);
886 i[1] = elk_MAC(p, dst, suboffset(interp, 1), delta_y);
887
888 elk_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
889
890 /* elk_set_default_saturate() is called before emitting instructions, so
891 * the saturate bit is set in each instruction, so we need to unset it on
892 * the first instruction.
893 */
894 elk_inst_set_saturate(p->devinfo, i[0], false);
895
896 return true;
897 }
898 }
899
900 void
generate_tex(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg surface_index,struct elk_reg sampler_index)901 elk_fs_generator::generate_tex(elk_fs_inst *inst, struct elk_reg dst,
902 struct elk_reg surface_index,
903 struct elk_reg sampler_index)
904 {
905 assert(devinfo->ver < 7);
906 assert(inst->size_written % REG_SIZE == 0);
907 int msg_type = -1;
908 uint32_t simd_mode;
909 uint32_t return_format;
910
911 /* Sampler EOT message of less than the dispatch width would kill the
912 * thread prematurely.
913 */
914 assert(!inst->eot || inst->exec_size == dispatch_width);
915
916 switch (dst.type) {
917 case ELK_REGISTER_TYPE_D:
918 return_format = ELK_SAMPLER_RETURN_FORMAT_SINT32;
919 break;
920 case ELK_REGISTER_TYPE_UD:
921 return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32;
922 break;
923 default:
924 return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32;
925 break;
926 }
927
928 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
929 * is set as part of the message descriptor. On gfx4, the PRM seems to
930 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
931 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
932 * gone from the message descriptor entirely and you just get UINT32 all
933 * the time regasrdless. Since we can really only do non-UINT32 on gfx4,
934 * just stomp it to UINT32 all the time.
935 */
936 if (inst->opcode == ELK_SHADER_OPCODE_TXS)
937 return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32;
938
939 switch (inst->exec_size) {
940 case 8:
941 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8;
942 break;
943 case 16:
944 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
945 break;
946 default:
947 unreachable("Invalid width for texture instruction");
948 }
949
950 if (devinfo->ver >= 5) {
951 switch (inst->opcode) {
952 case ELK_SHADER_OPCODE_TEX:
953 if (inst->shadow_compare) {
954 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
955 } else {
956 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE;
957 }
958 break;
959 case ELK_FS_OPCODE_TXB:
960 if (inst->shadow_compare) {
961 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
962 } else {
963 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS;
964 }
965 break;
966 case ELK_SHADER_OPCODE_TXL:
967 if (inst->shadow_compare) {
968 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
969 } else {
970 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
971 }
972 break;
973 case ELK_SHADER_OPCODE_TXS:
974 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
975 break;
976 case ELK_SHADER_OPCODE_TXD:
977 assert(!inst->shadow_compare);
978 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
979 break;
980 case ELK_SHADER_OPCODE_TXF:
981 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
982 break;
983 case ELK_SHADER_OPCODE_TXF_CMS:
984 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
985 break;
986 case ELK_SHADER_OPCODE_LOD:
987 msg_type = GFX5_SAMPLER_MESSAGE_LOD;
988 break;
989 case ELK_SHADER_OPCODE_TG4:
990 assert(devinfo->ver == 6);
991 assert(!inst->shadow_compare);
992 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
993 break;
994 case ELK_SHADER_OPCODE_SAMPLEINFO:
995 msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
996 break;
997 default:
998 unreachable("not reached");
999 }
1000 } else {
1001 switch (inst->opcode) {
1002 case ELK_SHADER_OPCODE_TEX:
1003 /* Note that G45 and older determines shadow compare and dispatch width
1004 * from message length for most messages.
1005 */
1006 if (inst->exec_size == 8) {
1007 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE;
1008 if (inst->shadow_compare) {
1009 assert(inst->mlen == 6);
1010 } else {
1011 assert(inst->mlen <= 4);
1012 }
1013 } else {
1014 if (inst->shadow_compare) {
1015 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1016 assert(inst->mlen == 9);
1017 } else {
1018 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1019 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
1020 }
1021 }
1022 break;
1023 case ELK_FS_OPCODE_TXB:
1024 if (inst->shadow_compare) {
1025 assert(inst->exec_size == 8);
1026 assert(inst->mlen == 6);
1027 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
1028 } else {
1029 assert(inst->mlen == 9);
1030 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1031 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1032 }
1033 break;
1034 case ELK_SHADER_OPCODE_TXL:
1035 if (inst->shadow_compare) {
1036 assert(inst->exec_size == 8);
1037 assert(inst->mlen == 6);
1038 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
1039 } else {
1040 assert(inst->mlen == 9);
1041 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
1042 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1043 }
1044 break;
1045 case ELK_SHADER_OPCODE_TXD:
1046 /* There is no sample_d_c message; comparisons are done manually */
1047 assert(inst->exec_size == 8);
1048 assert(inst->mlen == 7 || inst->mlen == 10);
1049 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
1050 break;
1051 case ELK_SHADER_OPCODE_TXF:
1052 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
1053 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD;
1054 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1055 break;
1056 case ELK_SHADER_OPCODE_TXS:
1057 assert(inst->mlen == 3);
1058 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_RESINFO;
1059 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1060 break;
1061 default:
1062 unreachable("not reached");
1063 }
1064 }
1065 assert(msg_type != -1);
1066
1067 if (simd_mode == ELK_SAMPLER_SIMD_MODE_SIMD16) {
1068 dst = vec16(dst);
1069 }
1070
1071 assert(sampler_index.type == ELK_REGISTER_TYPE_UD);
1072
1073 /* Load the message header if present. If there's a texture offset,
1074 * we need to set it up explicitly and load the offset bitfield.
1075 * Otherwise, we can use an implied move from g0 to the first message reg.
1076 */
1077 struct elk_reg src = elk_null_reg();
1078 if (inst->header_size != 0) {
1079 if (devinfo->ver < 6 && !inst->offset) {
1080 /* Set up an implied move from g0 to the MRF. */
1081 src = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UW);
1082 } else {
1083 assert(inst->base_mrf != -1);
1084 struct elk_reg header_reg = elk_message_reg(inst->base_mrf);
1085
1086 elk_push_insn_state(p);
1087 elk_set_default_exec_size(p, ELK_EXECUTE_8);
1088 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
1089 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
1090 /* Explicitly set up the message header by copying g0 to the MRF. */
1091 elk_MOV(p, header_reg, elk_vec8_grf(0, 0));
1092
1093 elk_set_default_exec_size(p, ELK_EXECUTE_1);
1094 if (inst->offset) {
1095 /* Set the offset bits in DWord 2. */
1096 elk_MOV(p, get_element_ud(header_reg, 2),
1097 elk_imm_ud(inst->offset));
1098 }
1099
1100 elk_pop_insn_state(p);
1101 }
1102 }
1103
1104 assert(surface_index.file == ELK_IMMEDIATE_VALUE);
1105 assert(sampler_index.file == ELK_IMMEDIATE_VALUE);
1106
1107 elk_SAMPLE(p,
1108 retype(dst, ELK_REGISTER_TYPE_UW),
1109 inst->base_mrf,
1110 src,
1111 surface_index.ud,
1112 sampler_index.ud % 16,
1113 msg_type,
1114 inst->size_written / REG_SIZE,
1115 inst->mlen,
1116 inst->header_size != 0,
1117 simd_mode,
1118 return_format);
1119 }
1120
1121
1122 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1123 * looking like:
1124 *
1125 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1126 *
1127 * Ideally, we want to produce:
1128 *
1129 * DDX DDY
1130 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1131 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1132 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1133 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1134 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1135 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1136 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1137 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1138 *
1139 * and add another set of two more subspans if in 16-pixel dispatch mode.
1140 *
1141 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1142 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1143 * pair. But the ideal approximation may impose a huge performance cost on
1144 * sample_d. On at least Haswell, sample_d instruction does some
1145 * optimizations if the same LOD is used for all pixels in the subspan.
1146 *
1147 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1148 * appropriate swizzling.
1149 */
1150 void
generate_ddx(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src)1151 elk_fs_generator::generate_ddx(const elk_fs_inst *inst,
1152 struct elk_reg dst, struct elk_reg src)
1153 {
1154 unsigned vstride, width;
1155
1156 if (devinfo->ver >= 8) {
1157 if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) {
1158 /* produce accurate derivatives */
1159 vstride = ELK_VERTICAL_STRIDE_2;
1160 width = ELK_WIDTH_2;
1161 } else {
1162 /* replicate the derivative at the top-left pixel to other pixels */
1163 vstride = ELK_VERTICAL_STRIDE_4;
1164 width = ELK_WIDTH_4;
1165 }
1166
1167 struct elk_reg src0 = byte_offset(src, type_sz(src.type));;
1168 struct elk_reg src1 = src;
1169
1170 src0.vstride = vstride;
1171 src0.width = width;
1172 src0.hstride = ELK_HORIZONTAL_STRIDE_0;
1173 src1.vstride = vstride;
1174 src1.width = width;
1175 src1.hstride = ELK_HORIZONTAL_STRIDE_0;
1176
1177 elk_ADD(p, dst, src0, negate(src1));
1178 } else {
1179 /* On Haswell and earlier, the region used above appears to not work
1180 * correctly for compressed instructions. At least on Haswell and
1181 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1182 * would have to split to SIMD8 no matter which method we choose, we
1183 * may as well use ALIGN16 on all platforms gfx7 and earlier.
1184 */
1185 struct elk_reg src0 = stride(src, 4, 4, 1);
1186 struct elk_reg src1 = stride(src, 4, 4, 1);
1187 if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) {
1188 src0.swizzle = ELK_SWIZZLE_XXZZ;
1189 src1.swizzle = ELK_SWIZZLE_YYWW;
1190 } else {
1191 src0.swizzle = ELK_SWIZZLE_XXXX;
1192 src1.swizzle = ELK_SWIZZLE_YYYY;
1193 }
1194
1195 elk_push_insn_state(p);
1196 elk_set_default_access_mode(p, ELK_ALIGN_16);
1197 elk_ADD(p, dst, negate(src0), src1);
1198 elk_pop_insn_state(p);
1199 }
1200 }
1201
1202 /* The negate_value boolean is used to negate the derivative computation for
1203 * FBOs, since they place the origin at the upper left instead of the lower
1204 * left.
1205 */
1206 void
generate_ddy(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src)1207 elk_fs_generator::generate_ddy(const elk_fs_inst *inst,
1208 struct elk_reg dst, struct elk_reg src)
1209 {
1210 const uint32_t type_size = type_sz(src.type);
1211
1212 if (inst->opcode == ELK_FS_OPCODE_DDY_FINE) {
1213 /* produce accurate derivatives.
1214 *
1215 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1216 * "Register Region Restrictions", Section "1. Special Restrictions":
1217 *
1218 * "In Align16 mode, the channel selects and channel enables apply to
1219 * a pair of half-floats, because these parameters are defined for
1220 * DWord elements ONLY. This is applicable when both source and
1221 * destination are half-floats."
1222 *
1223 * So for half-float operations we use the Gfx11+ Align1 path. CHV
1224 * inherits its FP16 hardware from SKL, so it is not affected.
1225 */
1226 if (devinfo->platform == INTEL_PLATFORM_BDW && src.type == ELK_REGISTER_TYPE_HF) {
1227 src = stride(src, 0, 2, 1);
1228
1229 elk_push_insn_state(p);
1230 elk_set_default_exec_size(p, ELK_EXECUTE_4);
1231 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
1232 elk_set_default_group(p, inst->group + g);
1233 elk_ADD(p, byte_offset(dst, g * type_size),
1234 negate(byte_offset(src, g * type_size)),
1235 byte_offset(src, (g + 2) * type_size));
1236 }
1237 elk_pop_insn_state(p);
1238 } else {
1239 struct elk_reg src0 = stride(src, 4, 4, 1);
1240 struct elk_reg src1 = stride(src, 4, 4, 1);
1241 src0.swizzle = ELK_SWIZZLE_XYXY;
1242 src1.swizzle = ELK_SWIZZLE_ZWZW;
1243
1244 elk_push_insn_state(p);
1245 elk_set_default_access_mode(p, ELK_ALIGN_16);
1246 elk_ADD(p, dst, negate(src0), src1);
1247 elk_pop_insn_state(p);
1248 }
1249 } else {
1250 /* replicate the derivative at the top-left pixel to other pixels */
1251 if (devinfo->ver >= 8) {
1252 struct elk_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
1253 struct elk_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
1254
1255 elk_ADD(p, dst, negate(src0), src1);
1256 } else {
1257 /* On Haswell and earlier, the region used above appears to not work
1258 * correctly for compressed instructions. At least on Haswell and
1259 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1260 * would have to split to SIMD8 no matter which method we choose, we
1261 * may as well use ALIGN16 on all platforms gfx7 and earlier.
1262 */
1263 struct elk_reg src0 = stride(src, 4, 4, 1);
1264 struct elk_reg src1 = stride(src, 4, 4, 1);
1265 src0.swizzle = ELK_SWIZZLE_XXXX;
1266 src1.swizzle = ELK_SWIZZLE_ZZZZ;
1267
1268 elk_push_insn_state(p);
1269 elk_set_default_access_mode(p, ELK_ALIGN_16);
1270 elk_ADD(p, dst, negate(src0), src1);
1271 elk_pop_insn_state(p);
1272 }
1273 }
1274 }
1275
1276 void
generate_halt(elk_fs_inst *)1277 elk_fs_generator::generate_halt(elk_fs_inst *)
1278 {
1279 /* This HALT will be patched up at FB write time to point UIP at the end of
1280 * the program, and at elk_uip_jip() JIP will be set to the end of the
1281 * current block (or the program).
1282 */
1283 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1284 elk_HALT(p);
1285 }
1286
1287 void
generate_scratch_write(elk_fs_inst * inst,struct elk_reg src)1288 elk_fs_generator::generate_scratch_write(elk_fs_inst *inst, struct elk_reg src)
1289 {
1290 /* The 32-wide messages only respect the first 16-wide half of the channel
1291 * enable signals which are replicated identically for the second group of
1292 * 16 channels, so we cannot use them unless the write is marked
1293 * force_writemask_all.
1294 */
1295 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1296 MIN2(16, inst->exec_size);
1297 const unsigned block_size = 4 * lower_size / REG_SIZE;
1298 assert(inst->mlen != 0);
1299
1300 elk_push_insn_state(p);
1301 elk_set_default_exec_size(p, cvt(lower_size) - 1);
1302 elk_set_default_compression(p, lower_size > 8);
1303
1304 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1305 elk_set_default_group(p, inst->group + lower_size * i);
1306
1307 elk_MOV(p, elk_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1308 retype(offset(src, block_size * i), ELK_REGISTER_TYPE_UD));
1309
1310 elk_oword_block_write_scratch(p, elk_message_reg(inst->base_mrf),
1311 block_size,
1312 inst->offset + block_size * REG_SIZE * i);
1313 }
1314
1315 elk_pop_insn_state(p);
1316 }
1317
1318 void
generate_scratch_read(elk_fs_inst * inst,struct elk_reg dst)1319 elk_fs_generator::generate_scratch_read(elk_fs_inst *inst, struct elk_reg dst)
1320 {
1321 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1322 assert(inst->mlen != 0);
1323
1324 elk_oword_block_read_scratch(p, dst, elk_message_reg(inst->base_mrf),
1325 inst->exec_size / 8, inst->offset);
1326 }
1327
1328 void
generate_scratch_read_gfx7(elk_fs_inst * inst,struct elk_reg dst)1329 elk_fs_generator::generate_scratch_read_gfx7(elk_fs_inst *inst, struct elk_reg dst)
1330 {
1331 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1332
1333 elk_gfx7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1334 }
1335
1336 /* The A32 messages take a buffer base address in header.5:[31:0] (See
1337 * MH1_A32_PSM for typed messages or MH_A32_GO for byte/dword scattered
1338 * and OWord block messages in the SKL PRM Vol. 2d for more details.)
1339 * Unfortunately, there are a number of subtle differences:
1340 *
1341 * For the block read/write messages:
1342 *
1343 * - We always stomp header.2 to fill in the actual scratch address (in
1344 * units of OWORDs) so we don't care what's in there.
1345 *
1346 * - They rely on per-thread scratch space value in header.3[3:0] to do
1347 * bounds checking so that needs to be valid. The upper bits of
1348 * header.3 are ignored, though, so we can copy all of g0.3.
1349 *
1350 * - They ignore header.5[9:0] and assumes the address is 1KB aligned.
1351 *
1352 *
1353 * For the byte/dword scattered read/write messages:
1354 *
1355 * - We want header.2 to be zero because that gets added to the per-channel
1356 * offset in the non-header portion of the message.
1357 *
1358 * - Contrary to what the docs claim, they don't do any bounds checking so
1359 * the value of header.3[3:0] doesn't matter.
1360 *
1361 * - They consider all of header.5 for the base address and header.5[9:0]
1362 * are not ignored. This means that we can't copy g0.5 verbatim because
1363 * g0.5[9:0] contains the FFTID on most platforms. Instead, we have to
1364 * use an AND to mask off the bottom 10 bits.
1365 *
1366 *
1367 * For block messages, just copying g0 gives a valid header because all the
1368 * garbage gets ignored except for header.2 which we stomp as part of message
1369 * setup. For byte/dword scattered messages, we can just zero out the header
1370 * and copy over the bits we need from g0.5. This opcode, however, tries to
1371 * satisfy the requirements of both by starting with 0 and filling out the
1372 * information required by either set of opcodes.
1373 */
1374 void
generate_scratch_header(elk_fs_inst * inst,struct elk_reg dst)1375 elk_fs_generator::generate_scratch_header(elk_fs_inst *inst, struct elk_reg dst)
1376 {
1377 assert(inst->exec_size == 8 && inst->force_writemask_all);
1378 assert(dst.file == ELK_GENERAL_REGISTER_FILE);
1379
1380 dst.type = ELK_REGISTER_TYPE_UD;
1381
1382 elk_inst *insn = elk_MOV(p, dst, elk_imm_ud(0));
1383 elk_inst_set_no_dd_clear(p->devinfo, insn, true);
1384
1385 /* Copy the per-thread scratch space size from g0.3[3:0] */
1386 elk_set_default_exec_size(p, ELK_EXECUTE_1);
1387 insn = elk_AND(p, suboffset(dst, 3),
1388 retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD),
1389 elk_imm_ud(INTEL_MASK(3, 0)));
1390 elk_inst_set_no_dd_clear(p->devinfo, insn, true);
1391 elk_inst_set_no_dd_check(p->devinfo, insn, true);
1392
1393 /* Copy the scratch base address from g0.5[31:10] */
1394 insn = elk_AND(p, suboffset(dst, 5),
1395 retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD),
1396 elk_imm_ud(INTEL_MASK(31, 10)));
1397 elk_inst_set_no_dd_check(p->devinfo, insn, true);
1398 }
1399
1400 void
generate_uniform_pull_constant_load(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg index,struct elk_reg offset)1401 elk_fs_generator::generate_uniform_pull_constant_load(elk_fs_inst *inst,
1402 struct elk_reg dst,
1403 struct elk_reg index,
1404 struct elk_reg offset)
1405 {
1406 assert(type_sz(dst.type) == 4);
1407 assert(inst->mlen != 0);
1408
1409 assert(index.file == ELK_IMMEDIATE_VALUE &&
1410 index.type == ELK_REGISTER_TYPE_UD);
1411 uint32_t surf_index = index.ud;
1412
1413 assert(offset.file == ELK_IMMEDIATE_VALUE &&
1414 offset.type == ELK_REGISTER_TYPE_UD);
1415 uint32_t read_offset = offset.ud;
1416
1417 elk_oword_block_read(p, dst, elk_message_reg(inst->base_mrf),
1418 read_offset, surf_index);
1419 }
1420
1421 void
generate_varying_pull_constant_load_gfx4(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg index)1422 elk_fs_generator::generate_varying_pull_constant_load_gfx4(elk_fs_inst *inst,
1423 struct elk_reg dst,
1424 struct elk_reg index)
1425 {
1426 assert(devinfo->ver < 7); /* Should use the gfx7 variant. */
1427 assert(inst->header_size != 0);
1428 assert(inst->mlen);
1429
1430 assert(index.file == ELK_IMMEDIATE_VALUE &&
1431 index.type == ELK_REGISTER_TYPE_UD);
1432 uint32_t surf_index = index.ud;
1433
1434 uint32_t simd_mode, rlen, msg_type;
1435 if (inst->exec_size == 16) {
1436 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1437 rlen = 8;
1438 } else {
1439 assert(inst->exec_size == 8);
1440 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8;
1441 rlen = 4;
1442 }
1443
1444 if (devinfo->ver >= 5)
1445 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
1446 else {
1447 /* We always use the SIMD16 message so that we only have to load U, and
1448 * not V or R.
1449 */
1450 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD;
1451 assert(inst->mlen == 3);
1452 assert(inst->size_written == 8 * REG_SIZE);
1453 rlen = 8;
1454 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1455 }
1456
1457 struct elk_reg header = elk_vec8_grf(0, 0);
1458 elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf);
1459
1460 elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND);
1461 elk_inst_set_compression(devinfo, send, false);
1462 elk_inst_set_sfid(devinfo, send, ELK_SFID_SAMPLER);
1463 elk_set_dest(p, send, retype(dst, ELK_REGISTER_TYPE_UW));
1464 elk_set_src0(p, send, header);
1465 if (devinfo->ver < 6)
1466 elk_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1467
1468 /* Our surface is set up as floats, regardless of what actual data is
1469 * stored in it.
1470 */
1471 uint32_t return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32;
1472 elk_set_desc(p, send,
1473 elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size) |
1474 elk_sampler_desc(devinfo, surf_index,
1475 0, /* sampler (unused) */
1476 msg_type, simd_mode, return_format));
1477 }
1478
1479 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1480 * the ADD instruction.
1481 */
1482 void
generate_set_sample_id(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src0,struct elk_reg src1)1483 elk_fs_generator::generate_set_sample_id(elk_fs_inst *inst,
1484 struct elk_reg dst,
1485 struct elk_reg src0,
1486 struct elk_reg src1)
1487 {
1488 assert(dst.type == ELK_REGISTER_TYPE_D ||
1489 dst.type == ELK_REGISTER_TYPE_UD);
1490 assert(src0.type == ELK_REGISTER_TYPE_D ||
1491 src0.type == ELK_REGISTER_TYPE_UD);
1492
1493 const struct elk_reg reg = stride(src1, 1, 4, 0);
1494 const unsigned lower_size = MIN2(inst->exec_size,
1495 devinfo->ver >= 8 ? 16 : 8);
1496
1497 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1498 elk_inst *insn = elk_ADD(p, offset(dst, i * lower_size / 8),
1499 offset(src0, (src0.vstride == 0 ? 0 : (1 << (src0.vstride - 1)) *
1500 (i * lower_size / (1 << src0.width))) *
1501 type_sz(src0.type) / REG_SIZE),
1502 suboffset(reg, i * lower_size / 4));
1503 elk_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1);
1504 elk_inst_set_group(devinfo, insn, inst->group + lower_size * i);
1505 elk_inst_set_compression(devinfo, insn, lower_size > 8);
1506 }
1507 }
1508
1509 void
enable_debug(const char * shader_name)1510 elk_fs_generator::enable_debug(const char *shader_name)
1511 {
1512 debug_flag = true;
1513 this->shader_name = shader_name;
1514 }
1515
1516 int
generate_code(const elk_cfg_t * cfg,int dispatch_width,struct shader_stats shader_stats,const elk::performance & perf,struct elk_compile_stats * stats)1517 elk_fs_generator::generate_code(const elk_cfg_t *cfg, int dispatch_width,
1518 struct shader_stats shader_stats,
1519 const elk::performance &perf,
1520 struct elk_compile_stats *stats)
1521 {
1522 /* align to 64 byte boundary. */
1523 elk_realign(p, 64);
1524
1525 this->dispatch_width = dispatch_width;
1526
1527 int start_offset = p->next_insn_offset;
1528
1529 int loop_count = 0, send_count = 0, nop_count = 0, sync_nop_count = 0;
1530 bool is_accum_used = false;
1531
1532 struct elk_disasm_info *elk_disasm_info = elk_disasm_initialize(p->isa, cfg);
1533
1534 foreach_block_and_inst (block, elk_fs_inst, inst, cfg) {
1535 if (inst->opcode == ELK_SHADER_OPCODE_UNDEF)
1536 continue;
1537
1538 struct elk_reg src[4], dst;
1539 unsigned int last_insn_offset = p->next_insn_offset;
1540 bool multiple_instructions_emitted = false;
1541
1542 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1543 * "Register Region Restrictions" section: for BDW, SKL:
1544 *
1545 * "A POW/FDIV operation must not be followed by an instruction
1546 * that requires two destination registers."
1547 *
1548 * The documentation is often lacking annotations for Atom parts,
1549 * and empirically this affects CHV as well.
1550 */
1551 if (devinfo->ver >= 8 &&
1552 p->nr_insn > 1 &&
1553 elk_inst_opcode(p->isa, elk_last_inst) == ELK_OPCODE_MATH &&
1554 elk_inst_math_function(devinfo, elk_last_inst) == ELK_MATH_FUNCTION_POW &&
1555 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1556 elk_NOP(p);
1557 last_insn_offset = p->next_insn_offset;
1558
1559 /* In order to avoid spurious instruction count differences when the
1560 * instruction schedule changes, keep track of the number of inserted
1561 * NOPs.
1562 */
1563 nop_count++;
1564 }
1565
1566 /* Wa_14010017096:
1567 *
1568 * Clear accumulator register before end of thread.
1569 */
1570 if (inst->eot && is_accum_used &&
1571 intel_needs_workaround(devinfo, 14010017096)) {
1572 elk_set_default_exec_size(p, ELK_EXECUTE_16);
1573 elk_set_default_group(p, 0);
1574 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
1575 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
1576 elk_set_default_flag_reg(p, 0, 0);
1577 elk_MOV(p, elk_acc_reg(8), elk_imm_f(0.0f));
1578 last_insn_offset = p->next_insn_offset;
1579 }
1580
1581 if (!is_accum_used && !inst->eot) {
1582 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
1583 inst->dst.is_accumulator();
1584 }
1585
1586 if (unlikely(debug_flag))
1587 elk_disasm_annotate(elk_disasm_info, inst, p->next_insn_offset);
1588
1589 /* If the instruction writes to more than one register, it needs to be
1590 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1591 * hardware figures out by itself what the right compression mode is,
1592 * but we still need to know whether the instruction is compressed to
1593 * set up the source register regions appropriately.
1594 *
1595 * XXX - This is wrong for instructions that write a single register but
1596 * read more than one which should strictly speaking be treated as
1597 * compressed. For instructions that don't write any registers it
1598 * relies on the destination being a null register of the correct
1599 * type and regioning so the instruction is considered compressed
1600 * or not accordingly.
1601 */
1602 const bool compressed =
1603 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1604 elk_set_default_compression(p, compressed);
1605
1606 if (devinfo->ver < 7 && inst->group % 8 != 0) {
1607 assert(inst->force_writemask_all);
1608 assert(!inst->predicate && !inst->conditional_mod);
1609 assert(!inst->writes_accumulator_implicitly(devinfo) &&
1610 !inst->reads_accumulator_implicitly());
1611 assert(inst->opcode != ELK_SHADER_OPCODE_SEL_EXEC);
1612 elk_set_default_group(p, 0);
1613 } else {
1614 elk_set_default_group(p, inst->group);
1615 }
1616
1617 for (unsigned int i = 0; i < inst->sources; i++) {
1618 src[i] = elk_reg_from_fs_reg(devinfo, inst,
1619 &inst->src[i], compressed);
1620 /* The accumulator result appears to get used for the
1621 * conditional modifier generation. When negating a UD
1622 * value, there is a 33rd bit generated for the sign in the
1623 * accumulator value, so now you can't check, for example,
1624 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1625 */
1626 assert(!inst->conditional_mod ||
1627 inst->src[i].type != ELK_REGISTER_TYPE_UD ||
1628 !inst->src[i].negate);
1629 }
1630 dst = elk_reg_from_fs_reg(devinfo, inst,
1631 &inst->dst, compressed);
1632
1633 elk_set_default_access_mode(p, ELK_ALIGN_1);
1634 elk_set_default_predicate_control(p, inst->predicate);
1635 elk_set_default_predicate_inverse(p, inst->predicate_inverse);
1636 /* On gfx7 and above, hardware automatically adds the group onto the
1637 * flag subregister number. On Sandy Bridge and older, we have to do it
1638 * ourselves.
1639 */
1640 const unsigned flag_subreg = inst->flag_subreg +
1641 (devinfo->ver >= 7 ? 0 : inst->group / 16);
1642 elk_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
1643 elk_set_default_saturate(p, inst->saturate);
1644 elk_set_default_mask_control(p, inst->force_writemask_all);
1645 elk_set_default_acc_write_control(p, inst->writes_accumulator);
1646
1647 unsigned exec_size = inst->exec_size;
1648 if (devinfo->verx10 == 70 &&
1649 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
1650 exec_size *= 2;
1651 }
1652
1653 elk_set_default_exec_size(p, cvt(exec_size) - 1);
1654
1655 assert(inst->force_writemask_all || inst->exec_size >= 4);
1656 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1657 assert(inst->base_mrf + inst->mlen <= ELK_MAX_MRF(devinfo->ver));
1658 assert(inst->mlen <= ELK_MAX_MSG_LENGTH * reg_unit(devinfo));
1659
1660 switch (inst->opcode) {
1661 case ELK_OPCODE_MOV:
1662 elk_MOV(p, dst, src[0]);
1663 break;
1664 case ELK_OPCODE_ADD:
1665 elk_ADD(p, dst, src[0], src[1]);
1666 break;
1667 case ELK_OPCODE_MUL:
1668 elk_MUL(p, dst, src[0], src[1]);
1669 break;
1670 case ELK_OPCODE_AVG:
1671 elk_AVG(p, dst, src[0], src[1]);
1672 break;
1673 case ELK_OPCODE_MACH:
1674 elk_MACH(p, dst, src[0], src[1]);
1675 break;
1676
1677 case ELK_OPCODE_LINE:
1678 elk_LINE(p, dst, src[0], src[1]);
1679 break;
1680
1681 case ELK_OPCODE_MAD:
1682 assert(devinfo->ver >= 6);
1683 elk_set_default_access_mode(p, ELK_ALIGN_16);
1684 elk_MAD(p, dst, src[0], src[1], src[2]);
1685 break;
1686
1687 case ELK_OPCODE_LRP:
1688 assert(devinfo->ver >= 6);
1689 elk_set_default_access_mode(p, ELK_ALIGN_16);
1690 elk_LRP(p, dst, src[0], src[1], src[2]);
1691 break;
1692
1693 case ELK_OPCODE_FRC:
1694 elk_FRC(p, dst, src[0]);
1695 break;
1696 case ELK_OPCODE_RNDD:
1697 elk_RNDD(p, dst, src[0]);
1698 break;
1699 case ELK_OPCODE_RNDE:
1700 elk_RNDE(p, dst, src[0]);
1701 break;
1702 case ELK_OPCODE_RNDZ:
1703 elk_RNDZ(p, dst, src[0]);
1704 break;
1705
1706 case ELK_OPCODE_AND:
1707 elk_AND(p, dst, src[0], src[1]);
1708 break;
1709 case ELK_OPCODE_OR:
1710 elk_OR(p, dst, src[0], src[1]);
1711 break;
1712 case ELK_OPCODE_XOR:
1713 elk_XOR(p, dst, src[0], src[1]);
1714 break;
1715 case ELK_OPCODE_NOT:
1716 elk_NOT(p, dst, src[0]);
1717 break;
1718 case ELK_OPCODE_ASR:
1719 elk_ASR(p, dst, src[0], src[1]);
1720 break;
1721 case ELK_OPCODE_SHR:
1722 elk_SHR(p, dst, src[0], src[1]);
1723 break;
1724 case ELK_OPCODE_SHL:
1725 elk_SHL(p, dst, src[0], src[1]);
1726 break;
1727 case ELK_OPCODE_F32TO16:
1728 elk_F32TO16(p, dst, src[0]);
1729 break;
1730 case ELK_OPCODE_F16TO32:
1731 elk_F16TO32(p, dst, src[0]);
1732 break;
1733 case ELK_OPCODE_CMP:
1734 if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
1735 dst.file == ELK_ARCHITECTURE_REGISTER_FILE) {
1736 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1737 * implemented in the compiler is not sufficient. Overriding the
1738 * type when the destination is the null register is necessary but
1739 * not sufficient by itself.
1740 */
1741 dst.type = ELK_REGISTER_TYPE_D;
1742 }
1743 elk_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1744 break;
1745 case ELK_OPCODE_CMPN:
1746 if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
1747 dst.file == ELK_ARCHITECTURE_REGISTER_FILE) {
1748 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1749 * implemented in the compiler is not sufficient. Overriding the
1750 * type when the destination is the null register is necessary but
1751 * not sufficient by itself.
1752 */
1753 dst.type = ELK_REGISTER_TYPE_D;
1754 }
1755 elk_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
1756 break;
1757 case ELK_OPCODE_SEL:
1758 elk_SEL(p, dst, src[0], src[1]);
1759 break;
1760 case ELK_OPCODE_CSEL:
1761 assert(devinfo->ver >= 8);
1762 elk_set_default_access_mode(p, ELK_ALIGN_16);
1763 elk_CSEL(p, dst, src[0], src[1], src[2]);
1764 break;
1765 case ELK_OPCODE_BFREV:
1766 assert(devinfo->ver >= 7);
1767 elk_BFREV(p, retype(dst, ELK_REGISTER_TYPE_UD),
1768 retype(src[0], ELK_REGISTER_TYPE_UD));
1769 break;
1770 case ELK_OPCODE_FBH:
1771 assert(devinfo->ver >= 7);
1772 elk_FBH(p, retype(dst, src[0].type), src[0]);
1773 break;
1774 case ELK_OPCODE_FBL:
1775 assert(devinfo->ver >= 7);
1776 elk_FBL(p, retype(dst, ELK_REGISTER_TYPE_UD),
1777 retype(src[0], ELK_REGISTER_TYPE_UD));
1778 break;
1779 case ELK_OPCODE_LZD:
1780 elk_LZD(p, dst, src[0]);
1781 break;
1782 case ELK_OPCODE_CBIT:
1783 assert(devinfo->ver >= 7);
1784 elk_CBIT(p, retype(dst, ELK_REGISTER_TYPE_UD),
1785 retype(src[0], ELK_REGISTER_TYPE_UD));
1786 break;
1787 case ELK_OPCODE_ADDC:
1788 assert(devinfo->ver >= 7);
1789 elk_ADDC(p, dst, src[0], src[1]);
1790 break;
1791 case ELK_OPCODE_SUBB:
1792 assert(devinfo->ver >= 7);
1793 elk_SUBB(p, dst, src[0], src[1]);
1794 break;
1795 case ELK_OPCODE_MAC:
1796 elk_MAC(p, dst, src[0], src[1]);
1797 break;
1798
1799 case ELK_OPCODE_BFE:
1800 assert(devinfo->ver >= 7);
1801 elk_set_default_access_mode(p, ELK_ALIGN_16);
1802 elk_BFE(p, dst, src[0], src[1], src[2]);
1803 break;
1804
1805 case ELK_OPCODE_BFI1:
1806 assert(devinfo->ver >= 7);
1807 elk_BFI1(p, dst, src[0], src[1]);
1808 break;
1809 case ELK_OPCODE_BFI2:
1810 assert(devinfo->ver >= 7);
1811 elk_set_default_access_mode(p, ELK_ALIGN_16);
1812 elk_BFI2(p, dst, src[0], src[1], src[2]);
1813 break;
1814
1815 case ELK_OPCODE_IF:
1816 if (inst->src[0].file != BAD_FILE) {
1817 /* The instruction has an embedded compare (only allowed on gfx6) */
1818 assert(devinfo->ver == 6);
1819 elk_gfx6_IF(p, inst->conditional_mod, src[0], src[1]);
1820 } else {
1821 elk_IF(p, elk_get_default_exec_size(p));
1822 }
1823 break;
1824
1825 case ELK_OPCODE_ELSE:
1826 elk_ELSE(p);
1827 break;
1828 case ELK_OPCODE_ENDIF:
1829 elk_ENDIF(p);
1830 break;
1831
1832 case ELK_OPCODE_DO:
1833 elk_DO(p, elk_get_default_exec_size(p));
1834 break;
1835
1836 case ELK_OPCODE_BREAK:
1837 elk_BREAK(p);
1838 break;
1839 case ELK_OPCODE_CONTINUE:
1840 elk_CONT(p);
1841 break;
1842
1843 case ELK_OPCODE_WHILE:
1844 elk_WHILE(p);
1845 loop_count++;
1846 break;
1847
1848 case ELK_SHADER_OPCODE_RCP:
1849 case ELK_SHADER_OPCODE_RSQ:
1850 case ELK_SHADER_OPCODE_SQRT:
1851 case ELK_SHADER_OPCODE_EXP2:
1852 case ELK_SHADER_OPCODE_LOG2:
1853 case ELK_SHADER_OPCODE_SIN:
1854 case ELK_SHADER_OPCODE_COS:
1855 assert(inst->conditional_mod == ELK_CONDITIONAL_NONE);
1856 if (devinfo->ver >= 6) {
1857 assert(inst->mlen == 0);
1858 assert(devinfo->ver >= 7 || inst->exec_size == 8);
1859 elk_gfx6_math(p, dst, elk_math_function(inst->opcode),
1860 src[0], elk_null_reg());
1861 } else {
1862 assert(inst->mlen >= 1);
1863 assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8);
1864 elk_gfx4_math(p, dst,
1865 elk_math_function(inst->opcode),
1866 inst->base_mrf, src[0],
1867 ELK_MATH_PRECISION_FULL);
1868 send_count++;
1869 }
1870 break;
1871 case ELK_SHADER_OPCODE_INT_QUOTIENT:
1872 case ELK_SHADER_OPCODE_INT_REMAINDER:
1873 case ELK_SHADER_OPCODE_POW:
1874 assert(inst->conditional_mod == ELK_CONDITIONAL_NONE);
1875 if (devinfo->ver >= 6) {
1876 assert(inst->mlen == 0);
1877 assert((devinfo->ver >= 7 && inst->opcode == ELK_SHADER_OPCODE_POW) ||
1878 inst->exec_size == 8);
1879 elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src[0], src[1]);
1880 } else {
1881 assert(inst->mlen >= 1);
1882 assert(inst->exec_size == 8);
1883 elk_gfx4_math(p, dst, elk_math_function(inst->opcode),
1884 inst->base_mrf, src[0],
1885 ELK_MATH_PRECISION_FULL);
1886 send_count++;
1887 }
1888 break;
1889 case ELK_FS_OPCODE_LINTERP:
1890 multiple_instructions_emitted = generate_linterp(inst, dst, src);
1891 break;
1892 case ELK_FS_OPCODE_PIXEL_X:
1893 assert(src[0].type == ELK_REGISTER_TYPE_UW);
1894 assert(src[1].type == ELK_REGISTER_TYPE_UW);
1895 src[0].subnr = 0 * type_sz(src[0].type);
1896 if (src[1].file == ELK_IMMEDIATE_VALUE) {
1897 assert(src[1].ud == 0);
1898 elk_MOV(p, dst, stride(src[0], 8, 4, 1));
1899 } else {
1900 /* Coarse pixel case */
1901 elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1902 }
1903 break;
1904 case ELK_FS_OPCODE_PIXEL_Y:
1905 assert(src[0].type == ELK_REGISTER_TYPE_UW);
1906 assert(src[1].type == ELK_REGISTER_TYPE_UW);
1907 src[0].subnr = 4 * type_sz(src[0].type);
1908 if (src[1].file == ELK_IMMEDIATE_VALUE) {
1909 assert(src[1].ud == 0);
1910 elk_MOV(p, dst, stride(src[0], 8, 4, 1));
1911 } else {
1912 /* Coarse pixel case */
1913 elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
1914 }
1915 break;
1916
1917 case ELK_SHADER_OPCODE_SEND:
1918 generate_send(inst, dst, src[0], src[1]);
1919 send_count++;
1920 break;
1921
1922 case ELK_SHADER_OPCODE_TEX:
1923 case ELK_FS_OPCODE_TXB:
1924 case ELK_SHADER_OPCODE_TXD:
1925 case ELK_SHADER_OPCODE_TXF:
1926 case ELK_SHADER_OPCODE_TXF_CMS:
1927 case ELK_SHADER_OPCODE_TXL:
1928 case ELK_SHADER_OPCODE_TXS:
1929 case ELK_SHADER_OPCODE_LOD:
1930 case ELK_SHADER_OPCODE_TG4:
1931 case ELK_SHADER_OPCODE_SAMPLEINFO:
1932 assert(inst->src[0].file == BAD_FILE);
1933 generate_tex(inst, dst, src[1], src[2]);
1934 send_count++;
1935 break;
1936
1937 case ELK_FS_OPCODE_DDX_COARSE:
1938 case ELK_FS_OPCODE_DDX_FINE:
1939 generate_ddx(inst, dst, src[0]);
1940 break;
1941 case ELK_FS_OPCODE_DDY_COARSE:
1942 case ELK_FS_OPCODE_DDY_FINE:
1943 generate_ddy(inst, dst, src[0]);
1944 break;
1945
1946 case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE:
1947 generate_scratch_write(inst, src[0]);
1948 send_count++;
1949 break;
1950
1951 case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ:
1952 generate_scratch_read(inst, dst);
1953 send_count++;
1954 break;
1955
1956 case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ:
1957 generate_scratch_read_gfx7(inst, dst);
1958 send_count++;
1959 break;
1960
1961 case ELK_SHADER_OPCODE_SCRATCH_HEADER:
1962 generate_scratch_header(inst, dst);
1963 break;
1964
1965 case ELK_SHADER_OPCODE_MOV_INDIRECT:
1966 generate_mov_indirect(inst, dst, src[0], src[1]);
1967 break;
1968
1969 case ELK_SHADER_OPCODE_MOV_RELOC_IMM:
1970 assert(src[0].file == ELK_IMMEDIATE_VALUE);
1971 elk_MOV_reloc_imm(p, dst, dst.type, src[0].ud);
1972 break;
1973
1974 case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1975 assert(inst->force_writemask_all);
1976 generate_uniform_pull_constant_load(inst, dst,
1977 src[PULL_UNIFORM_CONSTANT_SRC_SURFACE],
1978 src[PULL_UNIFORM_CONSTANT_SRC_OFFSET]);
1979 send_count++;
1980 break;
1981
1982 case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
1983 generate_varying_pull_constant_load_gfx4(inst, dst, src[0]);
1984 send_count++;
1985 break;
1986
1987 case ELK_FS_OPCODE_REP_FB_WRITE:
1988 case ELK_FS_OPCODE_FB_WRITE:
1989 generate_fb_write(inst, src[0]);
1990 send_count++;
1991 break;
1992
1993 case ELK_OPCODE_HALT:
1994 generate_halt(inst);
1995 break;
1996
1997 case ELK_SHADER_OPCODE_INTERLOCK:
1998 case ELK_SHADER_OPCODE_MEMORY_FENCE: {
1999 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2000 assert(src[2].file == ELK_IMMEDIATE_VALUE);
2001
2002 const enum elk_opcode send_op = inst->opcode == ELK_SHADER_OPCODE_INTERLOCK ?
2003 ELK_OPCODE_SENDC : ELK_OPCODE_SEND;
2004
2005 elk_memory_fence(p, dst, src[0], send_op,
2006 elk_message_target(inst->sfid),
2007 inst->desc,
2008 /* commit_enable */ src[1].ud,
2009 /* bti */ src[2].ud);
2010 send_count++;
2011 break;
2012 }
2013
2014 case ELK_FS_OPCODE_SCHEDULING_FENCE:
2015 if (inst->sources == 0) {
2016 if (unlikely(debug_flag))
2017 elk_disasm_info->use_tail = true;
2018 break;
2019 }
2020
2021 for (unsigned i = 0; i < inst->sources; i++) {
2022 /* Emit a MOV to force a stall until the instruction producing the
2023 * registers finishes.
2024 */
2025 elk_MOV(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW),
2026 retype(src[i], ELK_REGISTER_TYPE_UW));
2027 }
2028
2029 if (inst->sources > 1)
2030 multiple_instructions_emitted = true;
2031
2032 break;
2033
2034 case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL:
2035 elk_find_live_channel(p, dst, false);
2036 break;
2037 case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
2038 elk_find_live_channel(p, dst, true);
2039 break;
2040
2041 case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: {
2042 assert(devinfo->ver >= 8);
2043 assert(inst->force_writemask_all && inst->group == 0);
2044 assert(inst->dst.file == BAD_FILE);
2045 elk_set_default_exec_size(p, ELK_EXECUTE_1);
2046 elk_MOV(p, retype(elk_flag_subreg(inst->flag_subreg),
2047 ELK_REGISTER_TYPE_UD),
2048 retype(elk_mask_reg(0), ELK_REGISTER_TYPE_UD));
2049 break;
2050 }
2051 case ELK_SHADER_OPCODE_BROADCAST:
2052 assert(inst->force_writemask_all);
2053 elk_broadcast(p, dst, src[0], src[1]);
2054 break;
2055
2056 case ELK_SHADER_OPCODE_SHUFFLE:
2057 generate_shuffle(inst, dst, src[0], src[1]);
2058 break;
2059
2060 case ELK_SHADER_OPCODE_SEL_EXEC:
2061 assert(inst->force_writemask_all);
2062 assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4);
2063 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
2064 elk_MOV(p, dst, src[1]);
2065 elk_set_default_mask_control(p, ELK_MASK_ENABLE);
2066 elk_MOV(p, dst, src[0]);
2067 break;
2068
2069 case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
2070 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2071 assert(src[1].type == ELK_REGISTER_TYPE_UD);
2072 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
2073 break;
2074
2075 case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: {
2076 assert((devinfo->platform != INTEL_PLATFORM_CHV &&
2077 devinfo->has_64bit_float) || type_sz(src[0].type) <= 4);
2078 assert(!src[0].negate && !src[0].abs);
2079 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2080 assert(src[1].type == ELK_REGISTER_TYPE_UD);
2081 assert(src[2].file == ELK_IMMEDIATE_VALUE);
2082 assert(src[2].type == ELK_REGISTER_TYPE_UD);
2083 const unsigned component = src[1].ud;
2084 const unsigned cluster_size = src[2].ud;
2085 assert(inst->src[0].file != ARF && inst->src[0].file != FIXED_GRF);
2086 const unsigned s = inst->src[0].stride;
2087 unsigned vstride = cluster_size * s;
2088 unsigned width = cluster_size;
2089
2090 /* The maximum exec_size is 32, but the maximum width is only 16. */
2091 if (inst->exec_size == width) {
2092 vstride = 0;
2093 width = 1;
2094 }
2095
2096 struct elk_reg strided = stride(suboffset(src[0], component * s),
2097 vstride, width, 0);
2098 elk_MOV(p, dst, strided);
2099 break;
2100 }
2101
2102 case ELK_FS_OPCODE_SET_SAMPLE_ID:
2103 generate_set_sample_id(inst, dst, src[0], src[1]);
2104 break;
2105
2106 case ELK_SHADER_OPCODE_HALT_TARGET:
2107 /* This is the place where the final HALT needs to be inserted if
2108 * we've emitted any discards. If not, this will emit no code.
2109 */
2110 if (!patch_halt_jumps()) {
2111 if (unlikely(debug_flag)) {
2112 elk_disasm_info->use_tail = true;
2113 }
2114 }
2115 break;
2116
2117 case ELK_CS_OPCODE_CS_TERMINATE:
2118 generate_cs_terminate(inst, src[0]);
2119 send_count++;
2120 break;
2121
2122 case ELK_SHADER_OPCODE_BARRIER:
2123 generate_barrier(inst, src[0]);
2124 send_count++;
2125 break;
2126
2127 case ELK_OPCODE_DIM:
2128 assert(devinfo->platform == INTEL_PLATFORM_HSW);
2129 assert(src[0].type == ELK_REGISTER_TYPE_DF);
2130 assert(dst.type == ELK_REGISTER_TYPE_DF);
2131 elk_DIM(p, dst, retype(src[0], ELK_REGISTER_TYPE_F));
2132 break;
2133
2134 case ELK_SHADER_OPCODE_RND_MODE: {
2135 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2136 /*
2137 * Changes the floating point rounding mode updating the control
2138 * register field defined at cr0.0[5-6] bits.
2139 */
2140 enum elk_rnd_mode mode =
2141 (enum elk_rnd_mode) (src[0].d << ELK_CR0_RND_MODE_SHIFT);
2142 elk_float_controls_mode(p, mode, ELK_CR0_RND_MODE_MASK);
2143 }
2144 break;
2145
2146 case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE:
2147 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2148 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2149 elk_float_controls_mode(p, src[0].d, src[1].d);
2150 break;
2151
2152 case ELK_SHADER_OPCODE_READ_SR_REG:
2153 elk_MOV(p, dst, elk_sr0_reg(src[0].ud));
2154 break;
2155
2156 default:
2157 unreachable("Unsupported opcode");
2158
2159 case ELK_SHADER_OPCODE_LOAD_PAYLOAD:
2160 unreachable("Should be lowered by lower_load_payload()");
2161 }
2162
2163 if (multiple_instructions_emitted)
2164 continue;
2165
2166 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2167 assert(p->next_insn_offset == last_insn_offset + 16 ||
2168 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2169 "emitting more than 1 instruction");
2170
2171 elk_inst *last = &p->store[last_insn_offset / 16];
2172
2173 if (inst->conditional_mod)
2174 elk_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2175 elk_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2176 elk_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2177 }
2178 }
2179
2180 elk_set_uip_jip(p, start_offset);
2181
2182 /* end of program sentinel */
2183 elk_disasm_new_inst_group(elk_disasm_info, p->next_insn_offset);
2184
2185 /* `send_count` explicitly does not include spills or fills, as we'd
2186 * like to use it as a metric for intentional memory access or other
2187 * shared function use. Otherwise, subtle changes to scheduling or
2188 * register allocation could cause it to fluctuate wildly - and that
2189 * effect is already counted in spill/fill counts.
2190 */
2191 send_count -= shader_stats.spill_count;
2192 send_count -= shader_stats.fill_count;
2193
2194 #ifndef NDEBUG
2195 bool validated =
2196 #else
2197 if (unlikely(debug_flag))
2198 #endif
2199 elk_validate_instructions(&compiler->isa, p->store,
2200 start_offset,
2201 p->next_insn_offset,
2202 elk_disasm_info);
2203
2204 int before_size = p->next_insn_offset - start_offset;
2205 elk_compact_instructions(p, start_offset, elk_disasm_info);
2206 int after_size = p->next_insn_offset - start_offset;
2207
2208 bool dump_shader_bin = elk_should_dump_shader_bin();
2209 unsigned char sha1[21];
2210 char sha1buf[41];
2211
2212 if (unlikely(debug_flag || dump_shader_bin)) {
2213 _mesa_sha1_compute(p->store + start_offset / sizeof(elk_inst),
2214 after_size, sha1);
2215 _mesa_sha1_format(sha1buf, sha1);
2216 }
2217
2218 if (unlikely(dump_shader_bin))
2219 elk_dump_shader_bin(p->store, start_offset, p->next_insn_offset,
2220 sha1buf);
2221
2222 if (unlikely(debug_flag)) {
2223 fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n"
2224 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2225 "%d:%d spills:fills, %u sends, "
2226 "scheduled with mode %s. "
2227 "Promoted %u constants. "
2228 "Compacted %d to %d bytes (%.0f%%)\n",
2229 shader_name, params->source_hash, sha1buf,
2230 dispatch_width, before_size / 16,
2231 loop_count, perf.latency,
2232 shader_stats.spill_count,
2233 shader_stats.fill_count,
2234 send_count,
2235 shader_stats.scheduler_mode,
2236 shader_stats.promoted_constants,
2237 before_size, after_size,
2238 100.0f * (before_size - after_size) / before_size);
2239
2240 /* overriding the shader makes elk_disasm_info invalid */
2241 if (!elk_try_override_assembly(p, start_offset, sha1buf)) {
2242 elk_dump_assembly(p->store, start_offset, p->next_insn_offset,
2243 elk_disasm_info, perf.block_latency);
2244 } else {
2245 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2246 }
2247 }
2248 ralloc_free(elk_disasm_info);
2249 #ifndef NDEBUG
2250 if (!validated && !debug_flag) {
2251 fprintf(stderr,
2252 "Validation failed. Rerun with INTEL_DEBUG=shaders to get more information.\n");
2253 }
2254 #endif
2255 assert(validated);
2256
2257 elk_shader_debug_log(compiler, params->log_data,
2258 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2259 "%d:%d spills:fills, %u sends, "
2260 "scheduled with mode %s, "
2261 "Promoted %u constants, "
2262 "compacted %d to %d bytes.\n",
2263 _mesa_shader_stage_to_abbrev(stage),
2264 dispatch_width,
2265 before_size / 16 - nop_count - sync_nop_count,
2266 loop_count, perf.latency,
2267 shader_stats.spill_count,
2268 shader_stats.fill_count,
2269 send_count,
2270 shader_stats.scheduler_mode,
2271 shader_stats.promoted_constants,
2272 before_size, after_size);
2273 if (stats) {
2274 stats->dispatch_width = dispatch_width;
2275 stats->max_dispatch_width = dispatch_width;
2276 stats->instructions = before_size / 16 - nop_count - sync_nop_count;
2277 stats->sends = send_count;
2278 stats->loops = loop_count;
2279 stats->cycles = perf.latency;
2280 stats->spills = shader_stats.spill_count;
2281 stats->fills = shader_stats.fill_count;
2282 stats->max_live_registers = shader_stats.max_register_pressure;
2283 }
2284
2285 return start_offset;
2286 }
2287
2288 void
add_const_data(void * data,unsigned size)2289 elk_fs_generator::add_const_data(void *data, unsigned size)
2290 {
2291 assert(prog_data->const_data_size == 0);
2292 if (size > 0) {
2293 prog_data->const_data_size = size;
2294 prog_data->const_data_offset = elk_append_data(p, data, size, 32);
2295 }
2296 }
2297
2298 const unsigned *
get_assembly()2299 elk_fs_generator::get_assembly()
2300 {
2301 prog_data->relocs = elk_get_shader_relocs(p, &prog_data->num_relocs);
2302
2303 return elk_get_program(p, &prog_data->program_size);
2304 }
2305