1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <types.h>
4 #include <cf9_reset.h>
5 #include <device/pci_ops.h>
6
7 #include "gm45.h"
8
gm45_early_reset(void)9 void gm45_early_reset(void/*const timings_t *const timings*/)
10 {
11 int ch, r;
12
13 /* Reset DRAM power-up settings in CLKCFG (they are not
14 affected by system reset but may disrupt raminit). */
15 mchbar_clrsetbits32(CLKCFG_MCHBAR, 3 << 21, 1 << 3);
16
17 /*\ Next settings are the real purpose of this function:
18 If these steps are not performed, reset results in power off. \*/
19
20 /* Initialize some DRAM settings to 1 populated rank of 128MB. */
21 FOR_EACH_CHANNEL(ch) {
22 /* Configure DRAM control mode. */
23 mchbar_clrsetbits32(CxDRC0_MCHBAR(ch), CxDRC0_RANKEN_MASK,
24 (ch ? 0 : CxDRC0_RANKEN(0)));
25 mchbar_write32(CxDRC1_MCHBAR(ch),
26 (mchbar_read32(CxDRC1_MCHBAR(ch)) | CxDRC1_NOTPOP_MASK) &
27 ~(ch ? 0 : CxDRC1_NOTPOP(0)));
28 mchbar_write32(CxDRC2_MCHBAR(ch),
29 (mchbar_read32(CxDRC2_MCHBAR(ch)) | CxDRC2_NOTPOP_MASK) &
30 ~(ch ? 0 : CxDRC2_NOTPOP(0)));
31 /*if (timings && (timings->mem_clock == MEM_CLOCK_1067MT))
32 mchbar_setbits32(CxDRC2_MCHBAR(ch), CxDRC2_CLK1067MT);*/
33
34 /* Program rank boundaries (CxDRBy). */
35 for (r = 0; r < RANKS_PER_CHANNEL; r += 2)
36 mchbar_write32(CxDRBy_MCHBAR(ch, r),
37 CxDRBy_BOUND_MB(r, 128) | CxDRBy_BOUND_MB(r + 1, 128));
38 }
39 /* Set DCC mode to no operation and do magic 0xf0 thing. */
40 mchbar_clrsetbits32(DCC_MCHBAR, DCC_CMD_MASK, DCC_CMD_NOP);
41
42 pci_and_config8(PCI_DEV(0, 0, 0), 0xf0, ~(1 << 2));
43
44 pci_or_config8(PCI_DEV(0, 0, 0), 0xf0, (1 << 2));
45
46 /* Normally, we would set this after successful raminit. */
47 mchbar_setbits32(DCC_MCHBAR, 1 << 19);
48
49 system_reset();
50 }
51