xref: /aosp_15_r20/external/coreboot/src/southbridge/intel/i82371eb/early_pm.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <stdint.h>
4 #include <device/pci_ops.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include "i82371eb.h"
8 
enable_pm(void)9 void enable_pm(void)
10 {
11 	u8 reg8;
12 	u16 reg16;
13 
14 	/* Get the SMBus/PM device of the 82371AB/EB/MB. */
15 	const pci_devfn_t dev = pci_locate_device(PCI_ID(PCI_VID_INTEL,
16 				PCI_DID_INTEL_82371AB_SMB_ACPI), 0);
17 
18 	/* Set the PM I/O base. */
19 	pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1);
20 
21 	/* Enable access to the PM I/O space. */
22 	reg16 = pci_read_config16(dev, PCI_COMMAND);
23 	reg16 |= PCI_COMMAND_IO;
24 	pci_write_config16(dev, PCI_COMMAND, reg16);
25 
26 	/* PM I/O Space Enable (PMIOSE). */
27 	reg8 = pci_read_config8(dev, PMREGMISC);
28 	reg8 |= PMIOSE;
29 	pci_write_config8(dev, PMREGMISC, reg8);
30 }
31