1 /* 2 * Copyright (c) 2023, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_RCC_H 8 #define STM32MP2_RCC_H 9 10 #include <lib/utils_def.h> 11 12 #define RCC_SECCFGR0 U(0x0) 13 #define RCC_SECCFGR1 U(0x4) 14 #define RCC_SECCFGR2 U(0x8) 15 #define RCC_SECCFGR3 U(0xC) 16 #define RCC_PRIVCFGR0 U(0x10) 17 #define RCC_PRIVCFGR1 U(0x14) 18 #define RCC_PRIVCFGR2 U(0x18) 19 #define RCC_PRIVCFGR3 U(0x1C) 20 #define RCC_RCFGLOCKR0 U(0x20) 21 #define RCC_RCFGLOCKR1 U(0x24) 22 #define RCC_RCFGLOCKR2 U(0x28) 23 #define RCC_RCFGLOCKR3 U(0x2C) 24 #define RCC_R0CIDCFGR U(0x30) 25 #define RCC_R0SEMCR U(0x34) 26 #define RCC_R1CIDCFGR U(0x38) 27 #define RCC_R1SEMCR U(0x3C) 28 #define RCC_R2CIDCFGR U(0x40) 29 #define RCC_R2SEMCR U(0x44) 30 #define RCC_R3CIDCFGR U(0x48) 31 #define RCC_R3SEMCR U(0x4C) 32 #define RCC_R4CIDCFGR U(0x50) 33 #define RCC_R4SEMCR U(0x54) 34 #define RCC_R5CIDCFGR U(0x58) 35 #define RCC_R5SEMCR U(0x5C) 36 #define RCC_R6CIDCFGR U(0x60) 37 #define RCC_R6SEMCR U(0x64) 38 #define RCC_R7CIDCFGR U(0x68) 39 #define RCC_R7SEMCR U(0x6C) 40 #define RCC_R8CIDCFGR U(0x70) 41 #define RCC_R8SEMCR U(0x74) 42 #define RCC_R9CIDCFGR U(0x78) 43 #define RCC_R9SEMCR U(0x7C) 44 #define RCC_R10CIDCFGR U(0x80) 45 #define RCC_R10SEMCR U(0x84) 46 #define RCC_R11CIDCFGR U(0x88) 47 #define RCC_R11SEMCR U(0x8C) 48 #define RCC_R12CIDCFGR U(0x90) 49 #define RCC_R12SEMCR U(0x94) 50 #define RCC_R13CIDCFGR U(0x98) 51 #define RCC_R13SEMCR U(0x9C) 52 #define RCC_R14CIDCFGR U(0xA0) 53 #define RCC_R14SEMCR U(0xA4) 54 #define RCC_R15CIDCFGR U(0xA8) 55 #define RCC_R15SEMCR U(0xAC) 56 #define RCC_R16CIDCFGR U(0xB0) 57 #define RCC_R16SEMCR U(0xB4) 58 #define RCC_R17CIDCFGR U(0xB8) 59 #define RCC_R17SEMCR U(0xBC) 60 #define RCC_R18CIDCFGR U(0xC0) 61 #define RCC_R18SEMCR U(0xC4) 62 #define RCC_R19CIDCFGR U(0xC8) 63 #define RCC_R19SEMCR U(0xCC) 64 #define RCC_R20CIDCFGR U(0xD0) 65 #define RCC_R20SEMCR U(0xD4) 66 #define RCC_R21CIDCFGR U(0xD8) 67 #define RCC_R21SEMCR U(0xDC) 68 #define RCC_R22CIDCFGR U(0xE0) 69 #define RCC_R22SEMCR U(0xE4) 70 #define RCC_R23CIDCFGR U(0xE8) 71 #define RCC_R23SEMCR U(0xEC) 72 #define RCC_R24CIDCFGR U(0xF0) 73 #define RCC_R24SEMCR U(0xF4) 74 #define RCC_R25CIDCFGR U(0xF8) 75 #define RCC_R25SEMCR U(0xFC) 76 #define RCC_R26CIDCFGR U(0x100) 77 #define RCC_R26SEMCR U(0x104) 78 #define RCC_R27CIDCFGR U(0x108) 79 #define RCC_R27SEMCR U(0x10C) 80 #define RCC_R28CIDCFGR U(0x110) 81 #define RCC_R28SEMCR U(0x114) 82 #define RCC_R29CIDCFGR U(0x118) 83 #define RCC_R29SEMCR U(0x11C) 84 #define RCC_R30CIDCFGR U(0x120) 85 #define RCC_R30SEMCR U(0x124) 86 #define RCC_R31CIDCFGR U(0x128) 87 #define RCC_R31SEMCR U(0x12C) 88 #define RCC_R32CIDCFGR U(0x130) 89 #define RCC_R32SEMCR U(0x134) 90 #define RCC_R33CIDCFGR U(0x138) 91 #define RCC_R33SEMCR U(0x13C) 92 #define RCC_R34CIDCFGR U(0x140) 93 #define RCC_R34SEMCR U(0x144) 94 #define RCC_R35CIDCFGR U(0x148) 95 #define RCC_R35SEMCR U(0x14C) 96 #define RCC_R36CIDCFGR U(0x150) 97 #define RCC_R36SEMCR U(0x154) 98 #define RCC_R37CIDCFGR U(0x158) 99 #define RCC_R37SEMCR U(0x15C) 100 #define RCC_R38CIDCFGR U(0x160) 101 #define RCC_R38SEMCR U(0x164) 102 #define RCC_R39CIDCFGR U(0x168) 103 #define RCC_R39SEMCR U(0x16C) 104 #define RCC_R40CIDCFGR U(0x170) 105 #define RCC_R40SEMCR U(0x174) 106 #define RCC_R41CIDCFGR U(0x178) 107 #define RCC_R41SEMCR U(0x17C) 108 #define RCC_R42CIDCFGR U(0x180) 109 #define RCC_R42SEMCR U(0x184) 110 #define RCC_R43CIDCFGR U(0x188) 111 #define RCC_R43SEMCR U(0x18C) 112 #define RCC_R44CIDCFGR U(0x190) 113 #define RCC_R44SEMCR U(0x194) 114 #define RCC_R45CIDCFGR U(0x198) 115 #define RCC_R45SEMCR U(0x19C) 116 #define RCC_R46CIDCFGR U(0x1A0) 117 #define RCC_R46SEMCR U(0x1A4) 118 #define RCC_R47CIDCFGR U(0x1A8) 119 #define RCC_R47SEMCR U(0x1AC) 120 #define RCC_R48CIDCFGR U(0x1B0) 121 #define RCC_R48SEMCR U(0x1B4) 122 #define RCC_R49CIDCFGR U(0x1B8) 123 #define RCC_R49SEMCR U(0x1BC) 124 #define RCC_R50CIDCFGR U(0x1C0) 125 #define RCC_R50SEMCR U(0x1C4) 126 #define RCC_R51CIDCFGR U(0x1C8) 127 #define RCC_R51SEMCR U(0x1CC) 128 #define RCC_R52CIDCFGR U(0x1D0) 129 #define RCC_R52SEMCR U(0x1D4) 130 #define RCC_R53CIDCFGR U(0x1D8) 131 #define RCC_R53SEMCR U(0x1DC) 132 #define RCC_R54CIDCFGR U(0x1E0) 133 #define RCC_R54SEMCR U(0x1E4) 134 #define RCC_R55CIDCFGR U(0x1E8) 135 #define RCC_R55SEMCR U(0x1EC) 136 #define RCC_R56CIDCFGR U(0x1F0) 137 #define RCC_R56SEMCR U(0x1F4) 138 #define RCC_R57CIDCFGR U(0x1F8) 139 #define RCC_R57SEMCR U(0x1FC) 140 #define RCC_R58CIDCFGR U(0x200) 141 #define RCC_R58SEMCR U(0x204) 142 #define RCC_R59CIDCFGR U(0x208) 143 #define RCC_R59SEMCR U(0x20C) 144 #define RCC_R60CIDCFGR U(0x210) 145 #define RCC_R60SEMCR U(0x214) 146 #define RCC_R61CIDCFGR U(0x218) 147 #define RCC_R61SEMCR U(0x21C) 148 #define RCC_R62CIDCFGR U(0x220) 149 #define RCC_R62SEMCR U(0x224) 150 #define RCC_R63CIDCFGR U(0x228) 151 #define RCC_R63SEMCR U(0x22C) 152 #define RCC_R64CIDCFGR U(0x230) 153 #define RCC_R64SEMCR U(0x234) 154 #define RCC_R65CIDCFGR U(0x238) 155 #define RCC_R65SEMCR U(0x23C) 156 #define RCC_R66CIDCFGR U(0x240) 157 #define RCC_R66SEMCR U(0x244) 158 #define RCC_R67CIDCFGR U(0x248) 159 #define RCC_R67SEMCR U(0x24C) 160 #define RCC_R68CIDCFGR U(0x250) 161 #define RCC_R68SEMCR U(0x254) 162 #define RCC_R69CIDCFGR U(0x258) 163 #define RCC_R69SEMCR U(0x25C) 164 #define RCC_R70CIDCFGR U(0x260) 165 #define RCC_R70SEMCR U(0x264) 166 #define RCC_R71CIDCFGR U(0x268) 167 #define RCC_R71SEMCR U(0x26C) 168 #define RCC_R72CIDCFGR U(0x270) 169 #define RCC_R72SEMCR U(0x274) 170 #define RCC_R73CIDCFGR U(0x278) 171 #define RCC_R73SEMCR U(0x27C) 172 #define RCC_R74CIDCFGR U(0x280) 173 #define RCC_R74SEMCR U(0x284) 174 #define RCC_R75CIDCFGR U(0x288) 175 #define RCC_R75SEMCR U(0x28C) 176 #define RCC_R76CIDCFGR U(0x290) 177 #define RCC_R76SEMCR U(0x294) 178 #define RCC_R77CIDCFGR U(0x298) 179 #define RCC_R77SEMCR U(0x29C) 180 #define RCC_R78CIDCFGR U(0x2A0) 181 #define RCC_R78SEMCR U(0x2A4) 182 #define RCC_R79CIDCFGR U(0x2A8) 183 #define RCC_R79SEMCR U(0x2AC) 184 #define RCC_R80CIDCFGR U(0x2B0) 185 #define RCC_R80SEMCR U(0x2B4) 186 #define RCC_R81CIDCFGR U(0x2B8) 187 #define RCC_R81SEMCR U(0x2BC) 188 #define RCC_R82CIDCFGR U(0x2C0) 189 #define RCC_R82SEMCR U(0x2C4) 190 #define RCC_R83CIDCFGR U(0x2C8) 191 #define RCC_R83SEMCR U(0x2CC) 192 #define RCC_R84CIDCFGR U(0x2D0) 193 #define RCC_R84SEMCR U(0x2D4) 194 #define RCC_R85CIDCFGR U(0x2D8) 195 #define RCC_R85SEMCR U(0x2DC) 196 #define RCC_R86CIDCFGR U(0x2E0) 197 #define RCC_R86SEMCR U(0x2E4) 198 #define RCC_R87CIDCFGR U(0x2E8) 199 #define RCC_R87SEMCR U(0x2EC) 200 #define RCC_R88CIDCFGR U(0x2F0) 201 #define RCC_R88SEMCR U(0x2F4) 202 #define RCC_R89CIDCFGR U(0x2F8) 203 #define RCC_R89SEMCR U(0x2FC) 204 #define RCC_R90CIDCFGR U(0x300) 205 #define RCC_R90SEMCR U(0x304) 206 #define RCC_R91CIDCFGR U(0x308) 207 #define RCC_R91SEMCR U(0x30C) 208 #define RCC_R92CIDCFGR U(0x310) 209 #define RCC_R92SEMCR U(0x314) 210 #define RCC_R93CIDCFGR U(0x318) 211 #define RCC_R93SEMCR U(0x31C) 212 #define RCC_R94CIDCFGR U(0x320) 213 #define RCC_R94SEMCR U(0x324) 214 #define RCC_R95CIDCFGR U(0x328) 215 #define RCC_R95SEMCR U(0x32C) 216 #define RCC_R96CIDCFGR U(0x330) 217 #define RCC_R96SEMCR U(0x334) 218 #define RCC_R97CIDCFGR U(0x338) 219 #define RCC_R97SEMCR U(0x33C) 220 #define RCC_R98CIDCFGR U(0x340) 221 #define RCC_R98SEMCR U(0x344) 222 #define RCC_R99CIDCFGR U(0x348) 223 #define RCC_R99SEMCR U(0x34C) 224 #define RCC_R100CIDCFGR U(0x350) 225 #define RCC_R100SEMCR U(0x354) 226 #define RCC_R101CIDCFGR U(0x358) 227 #define RCC_R101SEMCR U(0x35C) 228 #define RCC_R102CIDCFGR U(0x360) 229 #define RCC_R102SEMCR U(0x364) 230 #define RCC_R103CIDCFGR U(0x368) 231 #define RCC_R103SEMCR U(0x36C) 232 #define RCC_R104CIDCFGR U(0x370) 233 #define RCC_R104SEMCR U(0x374) 234 #define RCC_R105CIDCFGR U(0x378) 235 #define RCC_R105SEMCR U(0x37C) 236 #define RCC_R106CIDCFGR U(0x380) 237 #define RCC_R106SEMCR U(0x384) 238 #define RCC_R107CIDCFGR U(0x388) 239 #define RCC_R107SEMCR U(0x38C) 240 #define RCC_R108CIDCFGR U(0x390) 241 #define RCC_R108SEMCR U(0x394) 242 #define RCC_R109CIDCFGR U(0x398) 243 #define RCC_R109SEMCR U(0x39C) 244 #define RCC_R110CIDCFGR U(0x3A0) 245 #define RCC_R110SEMCR U(0x3A4) 246 #define RCC_R111CIDCFGR U(0x3A8) 247 #define RCC_R111SEMCR U(0x3AC) 248 #define RCC_R112CIDCFGR U(0x3B0) 249 #define RCC_R112SEMCR U(0x3B4) 250 #define RCC_R113CIDCFGR U(0x3B8) 251 #define RCC_R113SEMCR U(0x3BC) 252 #define RCC_GRSTCSETR U(0x400) 253 #define RCC_C1RSTCSETR U(0x404) 254 #define RCC_C1P1RSTCSETR U(0x408) 255 #define RCC_C2RSTCSETR U(0x40C) 256 #define RCC_HWRSTSCLRR U(0x410) 257 #define RCC_C1HWRSTSCLRR U(0x414) 258 #define RCC_C2HWRSTSCLRR U(0x418) 259 #define RCC_C1BOOTRSTSSETR U(0x41C) 260 #define RCC_C1BOOTRSTSCLRR U(0x420) 261 #define RCC_C2BOOTRSTSSETR U(0x424) 262 #define RCC_C2BOOTRSTSCLRR U(0x428) 263 #define RCC_C1SREQSETR U(0x42C) 264 #define RCC_C1SREQCLRR U(0x430) 265 #define RCC_CPUBOOTCR U(0x434) 266 #define RCC_STBYBOOTCR U(0x438) 267 #define RCC_LEGBOOTCR U(0x43C) 268 #define RCC_BDCR U(0x440) 269 #define RCC_D3DCR U(0x444) 270 #define RCC_D3DSR U(0x448) 271 #define RCC_RDCR U(0x44C) 272 #define RCC_C1MSRDCR U(0x450) 273 #define RCC_PWRLPDLYCR U(0x454) 274 #define RCC_C1CIESETR U(0x458) 275 #define RCC_C1CIFCLRR U(0x45C) 276 #define RCC_C2CIESETR U(0x460) 277 #define RCC_C2CIFCLRR U(0x464) 278 #define RCC_IWDGC1FZSETR U(0x468) 279 #define RCC_IWDGC1FZCLRR U(0x46C) 280 #define RCC_IWDGC1CFGSETR U(0x470) 281 #define RCC_IWDGC1CFGCLRR U(0x474) 282 #define RCC_IWDGC2FZSETR U(0x478) 283 #define RCC_IWDGC2FZCLRR U(0x47C) 284 #define RCC_IWDGC2CFGSETR U(0x480) 285 #define RCC_IWDGC2CFGCLRR U(0x484) 286 #define RCC_IWDGC3CFGSETR U(0x488) 287 #define RCC_IWDGC3CFGCLRR U(0x48C) 288 #define RCC_C3CFGR U(0x490) 289 #define RCC_MCO1CFGR U(0x494) 290 #define RCC_MCO2CFGR U(0x498) 291 #define RCC_OCENSETR U(0x49C) 292 #define RCC_OCENCLRR U(0x4A0) 293 #define RCC_OCRDYR U(0x4A4) 294 #define RCC_HSICFGR U(0x4A8) 295 #define RCC_CSICFGR U(0x4AC) 296 #define RCC_RTCDIVR U(0x4B0) 297 #define RCC_APB1DIVR U(0x4B4) 298 #define RCC_APB2DIVR U(0x4B8) 299 #define RCC_APB3DIVR U(0x4BC) 300 #define RCC_APB4DIVR U(0x4C0) 301 #define RCC_APBDBGDIVR U(0x4C4) 302 #define RCC_TIMG1PRER U(0x4C8) 303 #define RCC_TIMG2PRER U(0x4CC) 304 #define RCC_LSMCUDIVR U(0x4D0) 305 #define RCC_DDRCPCFGR U(0x4D4) 306 #define RCC_DDRCAPBCFGR U(0x4D8) 307 #define RCC_DDRPHYCAPBCFGR U(0x4DC) 308 #define RCC_DDRPHYCCFGR U(0x4E0) 309 #define RCC_DDRCFGR U(0x4E4) 310 #define RCC_DDRITFCFGR U(0x4E8) 311 #define RCC_SYSRAMCFGR U(0x4F0) 312 #define RCC_VDERAMCFGR U(0x4F4) 313 #define RCC_SRAM1CFGR U(0x4F8) 314 #define RCC_SRAM2CFGR U(0x4FC) 315 #define RCC_RETRAMCFGR U(0x500) 316 #define RCC_BKPSRAMCFGR U(0x504) 317 #define RCC_LPSRAM1CFGR U(0x508) 318 #define RCC_LPSRAM2CFGR U(0x50C) 319 #define RCC_LPSRAM3CFGR U(0x510) 320 #define RCC_OSPI1CFGR U(0x514) 321 #define RCC_OSPI2CFGR U(0x518) 322 #define RCC_FMCCFGR U(0x51C) 323 #define RCC_DBGCFGR U(0x520) 324 #define RCC_STM500CFGR U(0x524) 325 #define RCC_ETRCFGR U(0x528) 326 #define RCC_GPIOACFGR U(0x52C) 327 #define RCC_GPIOBCFGR U(0x530) 328 #define RCC_GPIOCCFGR U(0x534) 329 #define RCC_GPIODCFGR U(0x538) 330 #define RCC_GPIOECFGR U(0x53C) 331 #define RCC_GPIOFCFGR U(0x540) 332 #define RCC_GPIOGCFGR U(0x544) 333 #define RCC_GPIOHCFGR U(0x548) 334 #define RCC_GPIOICFGR U(0x54C) 335 #define RCC_GPIOJCFGR U(0x550) 336 #define RCC_GPIOKCFGR U(0x554) 337 #define RCC_GPIOZCFGR U(0x558) 338 #define RCC_HPDMA1CFGR U(0x55C) 339 #define RCC_HPDMA2CFGR U(0x560) 340 #define RCC_HPDMA3CFGR U(0x564) 341 #define RCC_LPDMACFGR U(0x568) 342 #define RCC_HSEMCFGR U(0x56C) 343 #define RCC_IPCC1CFGR U(0x570) 344 #define RCC_IPCC2CFGR U(0x574) 345 #define RCC_RTCCFGR U(0x578) 346 #define RCC_SYSCPU1CFGR U(0x580) 347 #define RCC_BSECCFGR U(0x584) 348 #define RCC_IS2MCFGR U(0x58C) 349 #define RCC_PLL2CFGR1 U(0x590) 350 #define RCC_PLL2CFGR2 U(0x594) 351 #define RCC_PLL2CFGR3 U(0x598) 352 #define RCC_PLL2CFGR4 U(0x59C) 353 #define RCC_PLL2CFGR5 U(0x5A0) 354 #define RCC_PLL2CFGR6 U(0x5A8) 355 #define RCC_PLL2CFGR7 U(0x5AC) 356 #define RCC_PLL3CFGR1 U(0x5B8) 357 #define RCC_PLL3CFGR2 U(0x5BC) 358 #define RCC_PLL3CFGR3 U(0x5C0) 359 #define RCC_PLL3CFGR4 U(0x5C4) 360 #define RCC_PLL3CFGR5 U(0x5C8) 361 #define RCC_PLL3CFGR6 U(0x5D0) 362 #define RCC_PLL3CFGR7 U(0x5D4) 363 #define RCC_HSIFMONCR U(0x5E0) 364 #define RCC_HSIFVALR U(0x5E4) 365 #define RCC_TIM1CFGR U(0x700) 366 #define RCC_TIM2CFGR U(0x704) 367 #define RCC_TIM3CFGR U(0x708) 368 #define RCC_TIM4CFGR U(0x70C) 369 #define RCC_TIM5CFGR U(0x710) 370 #define RCC_TIM6CFGR U(0x714) 371 #define RCC_TIM7CFGR U(0x718) 372 #define RCC_TIM8CFGR U(0x71C) 373 #define RCC_TIM10CFGR U(0x720) 374 #define RCC_TIM11CFGR U(0x724) 375 #define RCC_TIM12CFGR U(0x728) 376 #define RCC_TIM13CFGR U(0x72C) 377 #define RCC_TIM14CFGR U(0x730) 378 #define RCC_TIM15CFGR U(0x734) 379 #define RCC_TIM16CFGR U(0x738) 380 #define RCC_TIM17CFGR U(0x73C) 381 #define RCC_TIM20CFGR U(0x740) 382 #define RCC_LPTIM1CFGR U(0x744) 383 #define RCC_LPTIM2CFGR U(0x748) 384 #define RCC_LPTIM3CFGR U(0x74C) 385 #define RCC_LPTIM4CFGR U(0x750) 386 #define RCC_LPTIM5CFGR U(0x754) 387 #define RCC_SPI1CFGR U(0x758) 388 #define RCC_SPI2CFGR U(0x75C) 389 #define RCC_SPI3CFGR U(0x760) 390 #define RCC_SPI4CFGR U(0x764) 391 #define RCC_SPI5CFGR U(0x768) 392 #define RCC_SPI6CFGR U(0x76C) 393 #define RCC_SPI7CFGR U(0x770) 394 #define RCC_SPI8CFGR U(0x774) 395 #define RCC_SPDIFRXCFGR U(0x778) 396 #define RCC_USART1CFGR U(0x77C) 397 #define RCC_USART2CFGR U(0x780) 398 #define RCC_USART3CFGR U(0x784) 399 #define RCC_UART4CFGR U(0x788) 400 #define RCC_UART5CFGR U(0x78C) 401 #define RCC_USART6CFGR U(0x790) 402 #define RCC_UART7CFGR U(0x794) 403 #define RCC_UART8CFGR U(0x798) 404 #define RCC_UART9CFGR U(0x79C) 405 #define RCC_LPUART1CFGR U(0x7A0) 406 #define RCC_I2C1CFGR U(0x7A4) 407 #define RCC_I2C2CFGR U(0x7A8) 408 #define RCC_I2C3CFGR U(0x7AC) 409 #define RCC_I2C4CFGR U(0x7B0) 410 #define RCC_I2C5CFGR U(0x7B4) 411 #define RCC_I2C6CFGR U(0x7B8) 412 #define RCC_I2C7CFGR U(0x7BC) 413 #define RCC_I2C8CFGR U(0x7C0) 414 #define RCC_SAI1CFGR U(0x7C4) 415 #define RCC_SAI2CFGR U(0x7C8) 416 #define RCC_SAI3CFGR U(0x7CC) 417 #define RCC_SAI4CFGR U(0x7D0) 418 #define RCC_MDF1CFGR U(0x7D8) 419 #define RCC_ADF1CFGR U(0x7DC) 420 #define RCC_FDCANCFGR U(0x7E0) 421 #define RCC_HDPCFGR U(0x7E4) 422 #define RCC_ADC12CFGR U(0x7E8) 423 #define RCC_ADC3CFGR U(0x7EC) 424 #define RCC_ETH1CFGR U(0x7F0) 425 #define RCC_ETH2CFGR U(0x7F4) 426 #define RCC_USB2CFGR U(0x7FC) 427 #define RCC_USB2PHY1CFGR U(0x800) 428 #define RCC_USB2PHY2CFGR U(0x804) 429 #define RCC_USB3DRDCFGR U(0x808) 430 #define RCC_USB3PCIEPHYCFGR U(0x80C) 431 #define RCC_PCIECFGR U(0x810) 432 #define RCC_USBTCCFGR U(0x814) 433 #define RCC_ETHSWCFGR U(0x818) 434 #define RCC_ETHSWACMCFGR U(0x81C) 435 #define RCC_ETHSWACMMSGCFGR U(0x820) 436 #define RCC_STGENCFGR U(0x824) 437 #define RCC_SDMMC1CFGR U(0x830) 438 #define RCC_SDMMC2CFGR U(0x834) 439 #define RCC_SDMMC3CFGR U(0x838) 440 #define RCC_GPUCFGR U(0x83C) 441 #define RCC_LTDCCFGR U(0x840) 442 #define RCC_DSICFGR U(0x844) 443 #define RCC_LVDSCFGR U(0x850) 444 #define RCC_CSI2CFGR U(0x858) 445 #define RCC_DCMIPPCFGR U(0x85C) 446 #define RCC_CCICFGR U(0x860) 447 #define RCC_VDECCFGR U(0x864) 448 #define RCC_VENCCFGR U(0x868) 449 #define RCC_RNGCFGR U(0x870) 450 #define RCC_PKACFGR U(0x874) 451 #define RCC_SAESCFGR U(0x878) 452 #define RCC_HASHCFGR U(0x87C) 453 #define RCC_CRYP1CFGR U(0x880) 454 #define RCC_CRYP2CFGR U(0x884) 455 #define RCC_IWDG1CFGR U(0x888) 456 #define RCC_IWDG2CFGR U(0x88C) 457 #define RCC_IWDG3CFGR U(0x890) 458 #define RCC_IWDG4CFGR U(0x894) 459 #define RCC_IWDG5CFGR U(0x898) 460 #define RCC_WWDG1CFGR U(0x89C) 461 #define RCC_WWDG2CFGR U(0x8A0) 462 #define RCC_BUSPERFMCFGR U(0x8A4) 463 #define RCC_VREFCFGR U(0x8A8) 464 #define RCC_TMPSENSCFGR U(0x8AC) 465 #define RCC_CRCCFGR U(0x8B4) 466 #define RCC_SERCCFGR U(0x8B8) 467 #define RCC_OSPIIOMCFGR U(0x8BC) 468 #define RCC_GICV2MCFGR U(0x8C0) 469 #define RCC_I3C1CFGR U(0x8C8) 470 #define RCC_I3C2CFGR U(0x8CC) 471 #define RCC_I3C3CFGR U(0x8D0) 472 #define RCC_I3C4CFGR U(0x8D4) 473 #define RCC_MUXSELCFGR U(0x1000) 474 #define RCC_XBAR0CFGR U(0x1018) 475 #define RCC_XBAR1CFGR U(0x101C) 476 #define RCC_XBAR2CFGR U(0x1020) 477 #define RCC_XBAR3CFGR U(0x1024) 478 #define RCC_XBAR4CFGR U(0x1028) 479 #define RCC_XBAR5CFGR U(0x102C) 480 #define RCC_XBAR6CFGR U(0x1030) 481 #define RCC_XBAR7CFGR U(0x1034) 482 #define RCC_XBAR8CFGR U(0x1038) 483 #define RCC_XBAR9CFGR U(0x103C) 484 #define RCC_XBAR10CFGR U(0x1040) 485 #define RCC_XBAR11CFGR U(0x1044) 486 #define RCC_XBAR12CFGR U(0x1048) 487 #define RCC_XBAR13CFGR U(0x104C) 488 #define RCC_XBAR14CFGR U(0x1050) 489 #define RCC_XBAR15CFGR U(0x1054) 490 #define RCC_XBAR16CFGR U(0x1058) 491 #define RCC_XBAR17CFGR U(0x105C) 492 #define RCC_XBAR18CFGR U(0x1060) 493 #define RCC_XBAR19CFGR U(0x1064) 494 #define RCC_XBAR20CFGR U(0x1068) 495 #define RCC_XBAR21CFGR U(0x106C) 496 #define RCC_XBAR22CFGR U(0x1070) 497 #define RCC_XBAR23CFGR U(0x1074) 498 #define RCC_XBAR24CFGR U(0x1078) 499 #define RCC_XBAR25CFGR U(0x107C) 500 #define RCC_XBAR26CFGR U(0x1080) 501 #define RCC_XBAR27CFGR U(0x1084) 502 #define RCC_XBAR28CFGR U(0x1088) 503 #define RCC_XBAR29CFGR U(0x108C) 504 #define RCC_XBAR30CFGR U(0x1090) 505 #define RCC_XBAR31CFGR U(0x1094) 506 #define RCC_XBAR32CFGR U(0x1098) 507 #define RCC_XBAR33CFGR U(0x109C) 508 #define RCC_XBAR34CFGR U(0x10A0) 509 #define RCC_XBAR35CFGR U(0x10A4) 510 #define RCC_XBAR36CFGR U(0x10A8) 511 #define RCC_XBAR37CFGR U(0x10AC) 512 #define RCC_XBAR38CFGR U(0x10B0) 513 #define RCC_XBAR39CFGR U(0x10B4) 514 #define RCC_XBAR40CFGR U(0x10B8) 515 #define RCC_XBAR41CFGR U(0x10BC) 516 #define RCC_XBAR42CFGR U(0x10C0) 517 #define RCC_XBAR43CFGR U(0x10C4) 518 #define RCC_XBAR44CFGR U(0x10C8) 519 #define RCC_XBAR45CFGR U(0x10CC) 520 #define RCC_XBAR46CFGR U(0x10D0) 521 #define RCC_XBAR47CFGR U(0x10D4) 522 #define RCC_XBAR48CFGR U(0x10D8) 523 #define RCC_XBAR49CFGR U(0x10DC) 524 #define RCC_XBAR50CFGR U(0x10E0) 525 #define RCC_XBAR51CFGR U(0x10E4) 526 #define RCC_XBAR52CFGR U(0x10E8) 527 #define RCC_XBAR53CFGR U(0x10EC) 528 #define RCC_XBAR54CFGR U(0x10F0) 529 #define RCC_XBAR55CFGR U(0x10F4) 530 #define RCC_XBAR56CFGR U(0x10F8) 531 #define RCC_XBAR57CFGR U(0x10FC) 532 #define RCC_XBAR58CFGR U(0x1100) 533 #define RCC_XBAR59CFGR U(0x1104) 534 #define RCC_XBAR60CFGR U(0x1108) 535 #define RCC_XBAR61CFGR U(0x110C) 536 #define RCC_XBAR62CFGR U(0x1110) 537 #define RCC_XBAR63CFGR U(0x1114) 538 #define RCC_PREDIV0CFGR U(0x1118) 539 #define RCC_PREDIV1CFGR U(0x111C) 540 #define RCC_PREDIV2CFGR U(0x1120) 541 #define RCC_PREDIV3CFGR U(0x1124) 542 #define RCC_PREDIV4CFGR U(0x1128) 543 #define RCC_PREDIV5CFGR U(0x112C) 544 #define RCC_PREDIV6CFGR U(0x1130) 545 #define RCC_PREDIV7CFGR U(0x1134) 546 #define RCC_PREDIV8CFGR U(0x1138) 547 #define RCC_PREDIV9CFGR U(0x113C) 548 #define RCC_PREDIV10CFGR U(0x1140) 549 #define RCC_PREDIV11CFGR U(0x1144) 550 #define RCC_PREDIV12CFGR U(0x1148) 551 #define RCC_PREDIV13CFGR U(0x114C) 552 #define RCC_PREDIV14CFGR U(0x1150) 553 #define RCC_PREDIV15CFGR U(0x1154) 554 #define RCC_PREDIV16CFGR U(0x1158) 555 #define RCC_PREDIV17CFGR U(0x115C) 556 #define RCC_PREDIV18CFGR U(0x1160) 557 #define RCC_PREDIV19CFGR U(0x1164) 558 #define RCC_PREDIV20CFGR U(0x1168) 559 #define RCC_PREDIV21CFGR U(0x116C) 560 #define RCC_PREDIV22CFGR U(0x1170) 561 #define RCC_PREDIV23CFGR U(0x1174) 562 #define RCC_PREDIV24CFGR U(0x1178) 563 #define RCC_PREDIV25CFGR U(0x117C) 564 #define RCC_PREDIV26CFGR U(0x1180) 565 #define RCC_PREDIV27CFGR U(0x1184) 566 #define RCC_PREDIV28CFGR U(0x1188) 567 #define RCC_PREDIV29CFGR U(0x118C) 568 #define RCC_PREDIV30CFGR U(0x1190) 569 #define RCC_PREDIV31CFGR U(0x1194) 570 #define RCC_PREDIV32CFGR U(0x1198) 571 #define RCC_PREDIV33CFGR U(0x119C) 572 #define RCC_PREDIV34CFGR U(0x11A0) 573 #define RCC_PREDIV35CFGR U(0x11A4) 574 #define RCC_PREDIV36CFGR U(0x11A8) 575 #define RCC_PREDIV37CFGR U(0x11AC) 576 #define RCC_PREDIV38CFGR U(0x11B0) 577 #define RCC_PREDIV39CFGR U(0x11B4) 578 #define RCC_PREDIV40CFGR U(0x11B8) 579 #define RCC_PREDIV41CFGR U(0x11BC) 580 #define RCC_PREDIV42CFGR U(0x11C0) 581 #define RCC_PREDIV43CFGR U(0x11C4) 582 #define RCC_PREDIV44CFGR U(0x11C8) 583 #define RCC_PREDIV45CFGR U(0x11CC) 584 #define RCC_PREDIV46CFGR U(0x11D0) 585 #define RCC_PREDIV47CFGR U(0x11D4) 586 #define RCC_PREDIV48CFGR U(0x11D8) 587 #define RCC_PREDIV49CFGR U(0x11DC) 588 #define RCC_PREDIV50CFGR U(0x11E0) 589 #define RCC_PREDIV51CFGR U(0x11E4) 590 #define RCC_PREDIV52CFGR U(0x11E8) 591 #define RCC_PREDIV53CFGR U(0x11EC) 592 #define RCC_PREDIV54CFGR U(0x11F0) 593 #define RCC_PREDIV55CFGR U(0x11F4) 594 #define RCC_PREDIV56CFGR U(0x11F8) 595 #define RCC_PREDIV57CFGR U(0x11FC) 596 #define RCC_PREDIV58CFGR U(0x1200) 597 #define RCC_PREDIV59CFGR U(0x1204) 598 #define RCC_PREDIV60CFGR U(0x1208) 599 #define RCC_PREDIV61CFGR U(0x120C) 600 #define RCC_PREDIV62CFGR U(0x1210) 601 #define RCC_PREDIV63CFGR U(0x1214) 602 #define RCC_PREDIVSR1 U(0x1218) 603 #define RCC_PREDIVSR2 U(0x121C) 604 #define RCC_FINDIV0CFGR U(0x1224) 605 #define RCC_FINDIV1CFGR U(0x1228) 606 #define RCC_FINDIV2CFGR U(0x122C) 607 #define RCC_FINDIV3CFGR U(0x1230) 608 #define RCC_FINDIV4CFGR U(0x1234) 609 #define RCC_FINDIV5CFGR U(0x1238) 610 #define RCC_FINDIV6CFGR U(0x123C) 611 #define RCC_FINDIV7CFGR U(0x1240) 612 #define RCC_FINDIV8CFGR U(0x1244) 613 #define RCC_FINDIV9CFGR U(0x1248) 614 #define RCC_FINDIV10CFGR U(0x124C) 615 #define RCC_FINDIV11CFGR U(0x1250) 616 #define RCC_FINDIV12CFGR U(0x1254) 617 #define RCC_FINDIV13CFGR U(0x1258) 618 #define RCC_FINDIV14CFGR U(0x125C) 619 #define RCC_FINDIV15CFGR U(0x1260) 620 #define RCC_FINDIV16CFGR U(0x1264) 621 #define RCC_FINDIV17CFGR U(0x1268) 622 #define RCC_FINDIV18CFGR U(0x126C) 623 #define RCC_FINDIV19CFGR U(0x1270) 624 #define RCC_FINDIV20CFGR U(0x1274) 625 #define RCC_FINDIV21CFGR U(0x1278) 626 #define RCC_FINDIV22CFGR U(0x127C) 627 #define RCC_FINDIV23CFGR U(0x1280) 628 #define RCC_FINDIV24CFGR U(0x1284) 629 #define RCC_FINDIV25CFGR U(0x1288) 630 #define RCC_FINDIV26CFGR U(0x128C) 631 #define RCC_FINDIV27CFGR U(0x1290) 632 #define RCC_FINDIV28CFGR U(0x1294) 633 #define RCC_FINDIV29CFGR U(0x1298) 634 #define RCC_FINDIV30CFGR U(0x129C) 635 #define RCC_FINDIV31CFGR U(0x12A0) 636 #define RCC_FINDIV32CFGR U(0x12A4) 637 #define RCC_FINDIV33CFGR U(0x12A8) 638 #define RCC_FINDIV34CFGR U(0x12AC) 639 #define RCC_FINDIV35CFGR U(0x12B0) 640 #define RCC_FINDIV36CFGR U(0x12B4) 641 #define RCC_FINDIV37CFGR U(0x12B8) 642 #define RCC_FINDIV38CFGR U(0x12BC) 643 #define RCC_FINDIV39CFGR U(0x12C0) 644 #define RCC_FINDIV40CFGR U(0x12C4) 645 #define RCC_FINDIV41CFGR U(0x12C8) 646 #define RCC_FINDIV42CFGR U(0x12CC) 647 #define RCC_FINDIV43CFGR U(0x12D0) 648 #define RCC_FINDIV44CFGR U(0x12D4) 649 #define RCC_FINDIV45CFGR U(0x12D8) 650 #define RCC_FINDIV46CFGR U(0x12DC) 651 #define RCC_FINDIV47CFGR U(0x12E0) 652 #define RCC_FINDIV48CFGR U(0x12E4) 653 #define RCC_FINDIV49CFGR U(0x12E8) 654 #define RCC_FINDIV50CFGR U(0x12EC) 655 #define RCC_FINDIV51CFGR U(0x12F0) 656 #define RCC_FINDIV52CFGR U(0x12F4) 657 #define RCC_FINDIV53CFGR U(0x12F8) 658 #define RCC_FINDIV54CFGR U(0x12FC) 659 #define RCC_FINDIV55CFGR U(0x1300) 660 #define RCC_FINDIV56CFGR U(0x1304) 661 #define RCC_FINDIV57CFGR U(0x1308) 662 #define RCC_FINDIV58CFGR U(0x130C) 663 #define RCC_FINDIV59CFGR U(0x1310) 664 #define RCC_FINDIV60CFGR U(0x1314) 665 #define RCC_FINDIV61CFGR U(0x1318) 666 #define RCC_FINDIV62CFGR U(0x131C) 667 #define RCC_FINDIV63CFGR U(0x1320) 668 #define RCC_FINDIVSR1 U(0x1324) 669 #define RCC_FINDIVSR2 U(0x1328) 670 #define RCC_FCALCOBS0CFGR U(0x1340) 671 #define RCC_FCALCOBS1CFGR U(0x1344) 672 #define RCC_FCALCREFCFGR U(0x1348) 673 #define RCC_FCALCCR1 U(0x134C) 674 #define RCC_FCALCCR2 U(0x1354) 675 #define RCC_FCALCSR U(0x1358) 676 #define RCC_PLL4CFGR1 U(0x1360) 677 #define RCC_PLL4CFGR2 U(0x1364) 678 #define RCC_PLL4CFGR3 U(0x1368) 679 #define RCC_PLL4CFGR4 U(0x136C) 680 #define RCC_PLL4CFGR5 U(0x1370) 681 #define RCC_PLL4CFGR6 U(0x1378) 682 #define RCC_PLL4CFGR7 U(0x137C) 683 #define RCC_PLL5CFGR1 U(0x1388) 684 #define RCC_PLL5CFGR2 U(0x138C) 685 #define RCC_PLL5CFGR3 U(0x1390) 686 #define RCC_PLL5CFGR4 U(0x1394) 687 #define RCC_PLL5CFGR5 U(0x1398) 688 #define RCC_PLL5CFGR6 U(0x13A0) 689 #define RCC_PLL5CFGR7 U(0x13A4) 690 #define RCC_PLL6CFGR1 U(0x13B0) 691 #define RCC_PLL6CFGR2 U(0x13B4) 692 #define RCC_PLL6CFGR3 U(0x13B8) 693 #define RCC_PLL6CFGR4 U(0x13BC) 694 #define RCC_PLL6CFGR5 U(0x13C0) 695 #define RCC_PLL6CFGR6 U(0x13C8) 696 #define RCC_PLL6CFGR7 U(0x13CC) 697 #define RCC_PLL7CFGR1 U(0x13D8) 698 #define RCC_PLL7CFGR2 U(0x13DC) 699 #define RCC_PLL7CFGR3 U(0x13E0) 700 #define RCC_PLL7CFGR4 U(0x13E4) 701 #define RCC_PLL7CFGR5 U(0x13E8) 702 #define RCC_PLL7CFGR6 U(0x13F0) 703 #define RCC_PLL7CFGR7 U(0x13F4) 704 #define RCC_PLL8CFGR1 U(0x1400) 705 #define RCC_PLL8CFGR2 U(0x1404) 706 #define RCC_PLL8CFGR3 U(0x1408) 707 #define RCC_PLL8CFGR4 U(0x140C) 708 #define RCC_PLL8CFGR5 U(0x1410) 709 #define RCC_PLL8CFGR6 U(0x1418) 710 #define RCC_PLL8CFGR7 U(0x141C) 711 #define RCC_VERR U(0xFFF4) 712 #define RCC_IDR U(0xFFF8) 713 #define RCC_SIDR U(0xFFFC) 714 715 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 716 #define RCC_MP_ENCLRR_OFFSET U(4) 717 718 /* RCC_SECCFGR3 register fields */ 719 #define RCC_SECCFGR3_SEC_MASK GENMASK_32(17, 0) 720 #define RCC_SECCFGR3_SEC_SHIFT 0 721 722 /* RCC_PRIVCFGR3 register fields */ 723 #define RCC_PRIVCFGR3_PRIV_MASK GENMASK_32(17, 0) 724 #define RCC_PRIVCFGR3_PRIV_SHIFT 0 725 726 /* RCC_RCFGLOCKR3 register fields */ 727 #define RCC_RCFGLOCKR3_RLOCK_MASK GENMASK_32(17, 0) 728 #define RCC_RCFGLOCKR3_RLOCK_SHIFT 0 729 730 /* RCC_R0CIDCFGR register fields */ 731 #define RCC_R0CIDCFGR_CFEN BIT(0) 732 #define RCC_R0CIDCFGR_SEM_EN BIT(1) 733 #define RCC_R0CIDCFGR_SCID_MASK GENMASK_32(6, 4) 734 #define RCC_R0CIDCFGR_SCID_SHIFT 4 735 #define RCC_R0CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 736 #define RCC_R0CIDCFGR_SEMWLC_SHIFT 16 737 738 /* RCC_R0SEMCR register fields */ 739 #define RCC_R0SEMCR_SEM_MUTEX BIT(0) 740 #define RCC_R0SEMCR_SEMCID_MASK GENMASK_32(6, 4) 741 #define RCC_R0SEMCR_SEMCID_SHIFT 4 742 743 /* RCC_R1CIDCFGR register fields */ 744 #define RCC_R1CIDCFGR_CFEN BIT(0) 745 #define RCC_R1CIDCFGR_SEM_EN BIT(1) 746 #define RCC_R1CIDCFGR_SCID_MASK GENMASK_32(6, 4) 747 #define RCC_R1CIDCFGR_SCID_SHIFT 4 748 #define RCC_R1CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 749 #define RCC_R1CIDCFGR_SEMWLC_SHIFT 16 750 751 /* RCC_R1SEMCR register fields */ 752 #define RCC_R1SEMCR_SEM_MUTEX BIT(0) 753 #define RCC_R1SEMCR_SEMCID_MASK GENMASK_32(6, 4) 754 #define RCC_R1SEMCR_SEMCID_SHIFT 4 755 756 /* RCC_R2CIDCFGR register fields */ 757 #define RCC_R2CIDCFGR_CFEN BIT(0) 758 #define RCC_R2CIDCFGR_SEM_EN BIT(1) 759 #define RCC_R2CIDCFGR_SCID_MASK GENMASK_32(6, 4) 760 #define RCC_R2CIDCFGR_SCID_SHIFT 4 761 #define RCC_R2CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 762 #define RCC_R2CIDCFGR_SEMWLC_SHIFT 16 763 764 /* RCC_R2SEMCR register fields */ 765 #define RCC_R2SEMCR_SEM_MUTEX BIT(0) 766 #define RCC_R2SEMCR_SEMCID_MASK GENMASK_32(6, 4) 767 #define RCC_R2SEMCR_SEMCID_SHIFT 4 768 769 /* RCC_R3CIDCFGR register fields */ 770 #define RCC_R3CIDCFGR_CFEN BIT(0) 771 #define RCC_R3CIDCFGR_SEM_EN BIT(1) 772 #define RCC_R3CIDCFGR_SCID_MASK GENMASK_32(6, 4) 773 #define RCC_R3CIDCFGR_SCID_SHIFT 4 774 #define RCC_R3CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 775 #define RCC_R3CIDCFGR_SEMWLC_SHIFT 16 776 777 /* RCC_R3SEMCR register fields */ 778 #define RCC_R3SEMCR_SEM_MUTEX BIT(0) 779 #define RCC_R3SEMCR_SEMCID_MASK GENMASK_32(6, 4) 780 #define RCC_R3SEMCR_SEMCID_SHIFT 4 781 782 /* RCC_R4CIDCFGR register fields */ 783 #define RCC_R4CIDCFGR_CFEN BIT(0) 784 #define RCC_R4CIDCFGR_SEM_EN BIT(1) 785 #define RCC_R4CIDCFGR_SCID_MASK GENMASK_32(6, 4) 786 #define RCC_R4CIDCFGR_SCID_SHIFT 4 787 #define RCC_R4CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 788 #define RCC_R4CIDCFGR_SEMWLC_SHIFT 16 789 790 /* RCC_R4SEMCR register fields */ 791 #define RCC_R4SEMCR_SEM_MUTEX BIT(0) 792 #define RCC_R4SEMCR_SEMCID_MASK GENMASK_32(6, 4) 793 #define RCC_R4SEMCR_SEMCID_SHIFT 4 794 795 /* RCC_R5CIDCFGR register fields */ 796 #define RCC_R5CIDCFGR_CFEN BIT(0) 797 #define RCC_R5CIDCFGR_SEM_EN BIT(1) 798 #define RCC_R5CIDCFGR_SCID_MASK GENMASK_32(6, 4) 799 #define RCC_R5CIDCFGR_SCID_SHIFT 4 800 #define RCC_R5CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 801 #define RCC_R5CIDCFGR_SEMWLC_SHIFT 16 802 803 /* RCC_R5SEMCR register fields */ 804 #define RCC_R5SEMCR_SEM_MUTEX BIT(0) 805 #define RCC_R5SEMCR_SEMCID_MASK GENMASK_32(6, 4) 806 #define RCC_R5SEMCR_SEMCID_SHIFT 4 807 808 /* RCC_R6CIDCFGR register fields */ 809 #define RCC_R6CIDCFGR_CFEN BIT(0) 810 #define RCC_R6CIDCFGR_SEM_EN BIT(1) 811 #define RCC_R6CIDCFGR_SCID_MASK GENMASK_32(6, 4) 812 #define RCC_R6CIDCFGR_SCID_SHIFT 4 813 #define RCC_R6CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 814 #define RCC_R6CIDCFGR_SEMWLC_SHIFT 16 815 816 /* RCC_R6SEMCR register fields */ 817 #define RCC_R6SEMCR_SEM_MUTEX BIT(0) 818 #define RCC_R6SEMCR_SEMCID_MASK GENMASK_32(6, 4) 819 #define RCC_R6SEMCR_SEMCID_SHIFT 4 820 821 /* RCC_R7CIDCFGR register fields */ 822 #define RCC_R7CIDCFGR_CFEN BIT(0) 823 #define RCC_R7CIDCFGR_SEM_EN BIT(1) 824 #define RCC_R7CIDCFGR_SCID_MASK GENMASK_32(6, 4) 825 #define RCC_R7CIDCFGR_SCID_SHIFT 4 826 #define RCC_R7CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 827 #define RCC_R7CIDCFGR_SEMWLC_SHIFT 16 828 829 /* RCC_R7SEMCR register fields */ 830 #define RCC_R7SEMCR_SEM_MUTEX BIT(0) 831 #define RCC_R7SEMCR_SEMCID_MASK GENMASK_32(6, 4) 832 #define RCC_R7SEMCR_SEMCID_SHIFT 4 833 834 /* RCC_R8CIDCFGR register fields */ 835 #define RCC_R8CIDCFGR_CFEN BIT(0) 836 #define RCC_R8CIDCFGR_SEM_EN BIT(1) 837 #define RCC_R8CIDCFGR_SCID_MASK GENMASK_32(6, 4) 838 #define RCC_R8CIDCFGR_SCID_SHIFT 4 839 #define RCC_R8CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 840 #define RCC_R8CIDCFGR_SEMWLC_SHIFT 16 841 842 /* RCC_R8SEMCR register fields */ 843 #define RCC_R8SEMCR_SEM_MUTEX BIT(0) 844 #define RCC_R8SEMCR_SEMCID_MASK GENMASK_32(6, 4) 845 #define RCC_R8SEMCR_SEMCID_SHIFT 4 846 847 /* RCC_R9CIDCFGR register fields */ 848 #define RCC_R9CIDCFGR_CFEN BIT(0) 849 #define RCC_R9CIDCFGR_SEM_EN BIT(1) 850 #define RCC_R9CIDCFGR_SCID_MASK GENMASK_32(6, 4) 851 #define RCC_R9CIDCFGR_SCID_SHIFT 4 852 #define RCC_R9CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 853 #define RCC_R9CIDCFGR_SEMWLC_SHIFT 16 854 855 /* RCC_R9SEMCR register fields */ 856 #define RCC_R9SEMCR_SEM_MUTEX BIT(0) 857 #define RCC_R9SEMCR_SEMCID_MASK GENMASK_32(6, 4) 858 #define RCC_R9SEMCR_SEMCID_SHIFT 4 859 860 /* RCC_R10CIDCFGR register fields */ 861 #define RCC_R10CIDCFGR_CFEN BIT(0) 862 #define RCC_R10CIDCFGR_SEM_EN BIT(1) 863 #define RCC_R10CIDCFGR_SCID_MASK GENMASK_32(6, 4) 864 #define RCC_R10CIDCFGR_SCID_SHIFT 4 865 #define RCC_R10CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 866 #define RCC_R10CIDCFGR_SEMWLC_SHIFT 16 867 868 /* RCC_R10SEMCR register fields */ 869 #define RCC_R10SEMCR_SEM_MUTEX BIT(0) 870 #define RCC_R10SEMCR_SEMCID_MASK GENMASK_32(6, 4) 871 #define RCC_R10SEMCR_SEMCID_SHIFT 4 872 873 /* RCC_R11CIDCFGR register fields */ 874 #define RCC_R11CIDCFGR_CFEN BIT(0) 875 #define RCC_R11CIDCFGR_SEM_EN BIT(1) 876 #define RCC_R11CIDCFGR_SCID_MASK GENMASK_32(6, 4) 877 #define RCC_R11CIDCFGR_SCID_SHIFT 4 878 #define RCC_R11CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 879 #define RCC_R11CIDCFGR_SEMWLC_SHIFT 16 880 881 /* RCC_R11SEMCR register fields */ 882 #define RCC_R11SEMCR_SEM_MUTEX BIT(0) 883 #define RCC_R11SEMCR_SEMCID_MASK GENMASK_32(6, 4) 884 #define RCC_R11SEMCR_SEMCID_SHIFT 4 885 886 /* RCC_R12CIDCFGR register fields */ 887 #define RCC_R12CIDCFGR_CFEN BIT(0) 888 #define RCC_R12CIDCFGR_SEM_EN BIT(1) 889 #define RCC_R12CIDCFGR_SCID_MASK GENMASK_32(6, 4) 890 #define RCC_R12CIDCFGR_SCID_SHIFT 4 891 #define RCC_R12CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 892 #define RCC_R12CIDCFGR_SEMWLC_SHIFT 16 893 894 /* RCC_R12SEMCR register fields */ 895 #define RCC_R12SEMCR_SEM_MUTEX BIT(0) 896 #define RCC_R12SEMCR_SEMCID_MASK GENMASK_32(6, 4) 897 #define RCC_R12SEMCR_SEMCID_SHIFT 4 898 899 /* RCC_R13CIDCFGR register fields */ 900 #define RCC_R13CIDCFGR_CFEN BIT(0) 901 #define RCC_R13CIDCFGR_SEM_EN BIT(1) 902 #define RCC_R13CIDCFGR_SCID_MASK GENMASK_32(6, 4) 903 #define RCC_R13CIDCFGR_SCID_SHIFT 4 904 #define RCC_R13CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 905 #define RCC_R13CIDCFGR_SEMWLC_SHIFT 16 906 907 /* RCC_R13SEMCR register fields */ 908 #define RCC_R13SEMCR_SEM_MUTEX BIT(0) 909 #define RCC_R13SEMCR_SEMCID_MASK GENMASK_32(6, 4) 910 #define RCC_R13SEMCR_SEMCID_SHIFT 4 911 912 /* RCC_R14CIDCFGR register fields */ 913 #define RCC_R14CIDCFGR_CFEN BIT(0) 914 #define RCC_R14CIDCFGR_SEM_EN BIT(1) 915 #define RCC_R14CIDCFGR_SCID_MASK GENMASK_32(6, 4) 916 #define RCC_R14CIDCFGR_SCID_SHIFT 4 917 #define RCC_R14CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 918 #define RCC_R14CIDCFGR_SEMWLC_SHIFT 16 919 920 /* RCC_R14SEMCR register fields */ 921 #define RCC_R14SEMCR_SEM_MUTEX BIT(0) 922 #define RCC_R14SEMCR_SEMCID_MASK GENMASK_32(6, 4) 923 #define RCC_R14SEMCR_SEMCID_SHIFT 4 924 925 /* RCC_R15CIDCFGR register fields */ 926 #define RCC_R15CIDCFGR_CFEN BIT(0) 927 #define RCC_R15CIDCFGR_SEM_EN BIT(1) 928 #define RCC_R15CIDCFGR_SCID_MASK GENMASK_32(6, 4) 929 #define RCC_R15CIDCFGR_SCID_SHIFT 4 930 #define RCC_R15CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 931 #define RCC_R15CIDCFGR_SEMWLC_SHIFT 16 932 933 /* RCC_R15SEMCR register fields */ 934 #define RCC_R15SEMCR_SEM_MUTEX BIT(0) 935 #define RCC_R15SEMCR_SEMCID_MASK GENMASK_32(6, 4) 936 #define RCC_R15SEMCR_SEMCID_SHIFT 4 937 938 /* RCC_R16CIDCFGR register fields */ 939 #define RCC_R16CIDCFGR_CFEN BIT(0) 940 #define RCC_R16CIDCFGR_SEM_EN BIT(1) 941 #define RCC_R16CIDCFGR_SCID_MASK GENMASK_32(6, 4) 942 #define RCC_R16CIDCFGR_SCID_SHIFT 4 943 #define RCC_R16CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 944 #define RCC_R16CIDCFGR_SEMWLC_SHIFT 16 945 946 /* RCC_R16SEMCR register fields */ 947 #define RCC_R16SEMCR_SEM_MUTEX BIT(0) 948 #define RCC_R16SEMCR_SEMCID_MASK GENMASK_32(6, 4) 949 #define RCC_R16SEMCR_SEMCID_SHIFT 4 950 951 /* RCC_R17CIDCFGR register fields */ 952 #define RCC_R17CIDCFGR_CFEN BIT(0) 953 #define RCC_R17CIDCFGR_SEM_EN BIT(1) 954 #define RCC_R17CIDCFGR_SCID_MASK GENMASK_32(6, 4) 955 #define RCC_R17CIDCFGR_SCID_SHIFT 4 956 #define RCC_R17CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 957 #define RCC_R17CIDCFGR_SEMWLC_SHIFT 16 958 959 /* RCC_R17SEMCR register fields */ 960 #define RCC_R17SEMCR_SEM_MUTEX BIT(0) 961 #define RCC_R17SEMCR_SEMCID_MASK GENMASK_32(6, 4) 962 #define RCC_R17SEMCR_SEMCID_SHIFT 4 963 964 /* RCC_R18CIDCFGR register fields */ 965 #define RCC_R18CIDCFGR_CFEN BIT(0) 966 #define RCC_R18CIDCFGR_SEM_EN BIT(1) 967 #define RCC_R18CIDCFGR_SCID_MASK GENMASK_32(6, 4) 968 #define RCC_R18CIDCFGR_SCID_SHIFT 4 969 #define RCC_R18CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 970 #define RCC_R18CIDCFGR_SEMWLC_SHIFT 16 971 972 /* RCC_R18SEMCR register fields */ 973 #define RCC_R18SEMCR_SEM_MUTEX BIT(0) 974 #define RCC_R18SEMCR_SEMCID_MASK GENMASK_32(6, 4) 975 #define RCC_R18SEMCR_SEMCID_SHIFT 4 976 977 /* RCC_R19CIDCFGR register fields */ 978 #define RCC_R19CIDCFGR_CFEN BIT(0) 979 #define RCC_R19CIDCFGR_SEM_EN BIT(1) 980 #define RCC_R19CIDCFGR_SCID_MASK GENMASK_32(6, 4) 981 #define RCC_R19CIDCFGR_SCID_SHIFT 4 982 #define RCC_R19CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 983 #define RCC_R19CIDCFGR_SEMWLC_SHIFT 16 984 985 /* RCC_R19SEMCR register fields */ 986 #define RCC_R19SEMCR_SEM_MUTEX BIT(0) 987 #define RCC_R19SEMCR_SEMCID_MASK GENMASK_32(6, 4) 988 #define RCC_R19SEMCR_SEMCID_SHIFT 4 989 990 /* RCC_R20CIDCFGR register fields */ 991 #define RCC_R20CIDCFGR_CFEN BIT(0) 992 #define RCC_R20CIDCFGR_SEM_EN BIT(1) 993 #define RCC_R20CIDCFGR_SCID_MASK GENMASK_32(6, 4) 994 #define RCC_R20CIDCFGR_SCID_SHIFT 4 995 #define RCC_R20CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 996 #define RCC_R20CIDCFGR_SEMWLC_SHIFT 16 997 998 /* RCC_R20SEMCR register fields */ 999 #define RCC_R20SEMCR_SEM_MUTEX BIT(0) 1000 #define RCC_R20SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1001 #define RCC_R20SEMCR_SEMCID_SHIFT 4 1002 1003 /* RCC_R21CIDCFGR register fields */ 1004 #define RCC_R21CIDCFGR_CFEN BIT(0) 1005 #define RCC_R21CIDCFGR_SEM_EN BIT(1) 1006 #define RCC_R21CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1007 #define RCC_R21CIDCFGR_SCID_SHIFT 4 1008 #define RCC_R21CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1009 #define RCC_R21CIDCFGR_SEMWLC_SHIFT 16 1010 1011 /* RCC_R21SEMCR register fields */ 1012 #define RCC_R21SEMCR_SEM_MUTEX BIT(0) 1013 #define RCC_R21SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1014 #define RCC_R21SEMCR_SEMCID_SHIFT 4 1015 1016 /* RCC_R22CIDCFGR register fields */ 1017 #define RCC_R22CIDCFGR_CFEN BIT(0) 1018 #define RCC_R22CIDCFGR_SEM_EN BIT(1) 1019 #define RCC_R22CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1020 #define RCC_R22CIDCFGR_SCID_SHIFT 4 1021 #define RCC_R22CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1022 #define RCC_R22CIDCFGR_SEMWLC_SHIFT 16 1023 1024 /* RCC_R22SEMCR register fields */ 1025 #define RCC_R22SEMCR_SEM_MUTEX BIT(0) 1026 #define RCC_R22SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1027 #define RCC_R22SEMCR_SEMCID_SHIFT 4 1028 1029 /* RCC_R23CIDCFGR register fields */ 1030 #define RCC_R23CIDCFGR_CFEN BIT(0) 1031 #define RCC_R23CIDCFGR_SEM_EN BIT(1) 1032 #define RCC_R23CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1033 #define RCC_R23CIDCFGR_SCID_SHIFT 4 1034 #define RCC_R23CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1035 #define RCC_R23CIDCFGR_SEMWLC_SHIFT 16 1036 1037 /* RCC_R23SEMCR register fields */ 1038 #define RCC_R23SEMCR_SEM_MUTEX BIT(0) 1039 #define RCC_R23SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1040 #define RCC_R23SEMCR_SEMCID_SHIFT 4 1041 1042 /* RCC_R24CIDCFGR register fields */ 1043 #define RCC_R24CIDCFGR_CFEN BIT(0) 1044 #define RCC_R24CIDCFGR_SEM_EN BIT(1) 1045 #define RCC_R24CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1046 #define RCC_R24CIDCFGR_SCID_SHIFT 4 1047 #define RCC_R24CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1048 #define RCC_R24CIDCFGR_SEMWLC_SHIFT 16 1049 1050 /* RCC_R24SEMCR register fields */ 1051 #define RCC_R24SEMCR_SEM_MUTEX BIT(0) 1052 #define RCC_R24SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1053 #define RCC_R24SEMCR_SEMCID_SHIFT 4 1054 1055 /* RCC_R25CIDCFGR register fields */ 1056 #define RCC_R25CIDCFGR_CFEN BIT(0) 1057 #define RCC_R25CIDCFGR_SEM_EN BIT(1) 1058 #define RCC_R25CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1059 #define RCC_R25CIDCFGR_SCID_SHIFT 4 1060 #define RCC_R25CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1061 #define RCC_R25CIDCFGR_SEMWLC_SHIFT 16 1062 1063 /* RCC_R25SEMCR register fields */ 1064 #define RCC_R25SEMCR_SEM_MUTEX BIT(0) 1065 #define RCC_R25SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1066 #define RCC_R25SEMCR_SEMCID_SHIFT 4 1067 1068 /* RCC_R26CIDCFGR register fields */ 1069 #define RCC_R26CIDCFGR_CFEN BIT(0) 1070 #define RCC_R26CIDCFGR_SEM_EN BIT(1) 1071 #define RCC_R26CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1072 #define RCC_R26CIDCFGR_SCID_SHIFT 4 1073 #define RCC_R26CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1074 #define RCC_R26CIDCFGR_SEMWLC_SHIFT 16 1075 1076 /* RCC_R26SEMCR register fields */ 1077 #define RCC_R26SEMCR_SEM_MUTEX BIT(0) 1078 #define RCC_R26SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1079 #define RCC_R26SEMCR_SEMCID_SHIFT 4 1080 1081 /* RCC_R27CIDCFGR register fields */ 1082 #define RCC_R27CIDCFGR_CFEN BIT(0) 1083 #define RCC_R27CIDCFGR_SEM_EN BIT(1) 1084 #define RCC_R27CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1085 #define RCC_R27CIDCFGR_SCID_SHIFT 4 1086 #define RCC_R27CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1087 #define RCC_R27CIDCFGR_SEMWLC_SHIFT 16 1088 1089 /* RCC_R27SEMCR register fields */ 1090 #define RCC_R27SEMCR_SEM_MUTEX BIT(0) 1091 #define RCC_R27SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1092 #define RCC_R27SEMCR_SEMCID_SHIFT 4 1093 1094 /* RCC_R28CIDCFGR register fields */ 1095 #define RCC_R28CIDCFGR_CFEN BIT(0) 1096 #define RCC_R28CIDCFGR_SEM_EN BIT(1) 1097 #define RCC_R28CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1098 #define RCC_R28CIDCFGR_SCID_SHIFT 4 1099 #define RCC_R28CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1100 #define RCC_R28CIDCFGR_SEMWLC_SHIFT 16 1101 1102 /* RCC_R28SEMCR register fields */ 1103 #define RCC_R28SEMCR_SEM_MUTEX BIT(0) 1104 #define RCC_R28SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1105 #define RCC_R28SEMCR_SEMCID_SHIFT 4 1106 1107 /* RCC_R29CIDCFGR register fields */ 1108 #define RCC_R29CIDCFGR_CFEN BIT(0) 1109 #define RCC_R29CIDCFGR_SEM_EN BIT(1) 1110 #define RCC_R29CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1111 #define RCC_R29CIDCFGR_SCID_SHIFT 4 1112 #define RCC_R29CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1113 #define RCC_R29CIDCFGR_SEMWLC_SHIFT 16 1114 1115 /* RCC_R29SEMCR register fields */ 1116 #define RCC_R29SEMCR_SEM_MUTEX BIT(0) 1117 #define RCC_R29SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1118 #define RCC_R29SEMCR_SEMCID_SHIFT 4 1119 1120 /* RCC_R30CIDCFGR register fields */ 1121 #define RCC_R30CIDCFGR_CFEN BIT(0) 1122 #define RCC_R30CIDCFGR_SEM_EN BIT(1) 1123 #define RCC_R30CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1124 #define RCC_R30CIDCFGR_SCID_SHIFT 4 1125 #define RCC_R30CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1126 #define RCC_R30CIDCFGR_SEMWLC_SHIFT 16 1127 1128 /* RCC_R30SEMCR register fields */ 1129 #define RCC_R30SEMCR_SEM_MUTEX BIT(0) 1130 #define RCC_R30SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1131 #define RCC_R30SEMCR_SEMCID_SHIFT 4 1132 1133 /* RCC_R31CIDCFGR register fields */ 1134 #define RCC_R31CIDCFGR_CFEN BIT(0) 1135 #define RCC_R31CIDCFGR_SEM_EN BIT(1) 1136 #define RCC_R31CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1137 #define RCC_R31CIDCFGR_SCID_SHIFT 4 1138 #define RCC_R31CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1139 #define RCC_R31CIDCFGR_SEMWLC_SHIFT 16 1140 1141 /* RCC_R31SEMCR register fields */ 1142 #define RCC_R31SEMCR_SEM_MUTEX BIT(0) 1143 #define RCC_R31SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1144 #define RCC_R31SEMCR_SEMCID_SHIFT 4 1145 1146 /* RCC_R32CIDCFGR register fields */ 1147 #define RCC_R32CIDCFGR_CFEN BIT(0) 1148 #define RCC_R32CIDCFGR_SEM_EN BIT(1) 1149 #define RCC_R32CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1150 #define RCC_R32CIDCFGR_SCID_SHIFT 4 1151 #define RCC_R32CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1152 #define RCC_R32CIDCFGR_SEMWLC_SHIFT 16 1153 1154 /* RCC_R32SEMCR register fields */ 1155 #define RCC_R32SEMCR_SEM_MUTEX BIT(0) 1156 #define RCC_R32SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1157 #define RCC_R32SEMCR_SEMCID_SHIFT 4 1158 1159 /* RCC_R33CIDCFGR register fields */ 1160 #define RCC_R33CIDCFGR_CFEN BIT(0) 1161 #define RCC_R33CIDCFGR_SEM_EN BIT(1) 1162 #define RCC_R33CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1163 #define RCC_R33CIDCFGR_SCID_SHIFT 4 1164 #define RCC_R33CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1165 #define RCC_R33CIDCFGR_SEMWLC_SHIFT 16 1166 1167 /* RCC_R33SEMCR register fields */ 1168 #define RCC_R33SEMCR_SEM_MUTEX BIT(0) 1169 #define RCC_R33SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1170 #define RCC_R33SEMCR_SEMCID_SHIFT 4 1171 1172 /* RCC_R34CIDCFGR register fields */ 1173 #define RCC_R34CIDCFGR_CFEN BIT(0) 1174 #define RCC_R34CIDCFGR_SEM_EN BIT(1) 1175 #define RCC_R34CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1176 #define RCC_R34CIDCFGR_SCID_SHIFT 4 1177 #define RCC_R34CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1178 #define RCC_R34CIDCFGR_SEMWLC_SHIFT 16 1179 1180 /* RCC_R34SEMCR register fields */ 1181 #define RCC_R34SEMCR_SEM_MUTEX BIT(0) 1182 #define RCC_R34SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1183 #define RCC_R34SEMCR_SEMCID_SHIFT 4 1184 1185 /* RCC_R35CIDCFGR register fields */ 1186 #define RCC_R35CIDCFGR_CFEN BIT(0) 1187 #define RCC_R35CIDCFGR_SEM_EN BIT(1) 1188 #define RCC_R35CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1189 #define RCC_R35CIDCFGR_SCID_SHIFT 4 1190 #define RCC_R35CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1191 #define RCC_R35CIDCFGR_SEMWLC_SHIFT 16 1192 1193 /* RCC_R35SEMCR register fields */ 1194 #define RCC_R35SEMCR_SEM_MUTEX BIT(0) 1195 #define RCC_R35SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1196 #define RCC_R35SEMCR_SEMCID_SHIFT 4 1197 1198 /* RCC_R36CIDCFGR register fields */ 1199 #define RCC_R36CIDCFGR_CFEN BIT(0) 1200 #define RCC_R36CIDCFGR_SEM_EN BIT(1) 1201 #define RCC_R36CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1202 #define RCC_R36CIDCFGR_SCID_SHIFT 4 1203 #define RCC_R36CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1204 #define RCC_R36CIDCFGR_SEMWLC_SHIFT 16 1205 1206 /* RCC_R36SEMCR register fields */ 1207 #define RCC_R36SEMCR_SEM_MUTEX BIT(0) 1208 #define RCC_R36SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1209 #define RCC_R36SEMCR_SEMCID_SHIFT 4 1210 1211 /* RCC_R37CIDCFGR register fields */ 1212 #define RCC_R37CIDCFGR_CFEN BIT(0) 1213 #define RCC_R37CIDCFGR_SEM_EN BIT(1) 1214 #define RCC_R37CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1215 #define RCC_R37CIDCFGR_SCID_SHIFT 4 1216 #define RCC_R37CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1217 #define RCC_R37CIDCFGR_SEMWLC_SHIFT 16 1218 1219 /* RCC_R37SEMCR register fields */ 1220 #define RCC_R37SEMCR_SEM_MUTEX BIT(0) 1221 #define RCC_R37SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1222 #define RCC_R37SEMCR_SEMCID_SHIFT 4 1223 1224 /* RCC_R38CIDCFGR register fields */ 1225 #define RCC_R38CIDCFGR_CFEN BIT(0) 1226 #define RCC_R38CIDCFGR_SEM_EN BIT(1) 1227 #define RCC_R38CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1228 #define RCC_R38CIDCFGR_SCID_SHIFT 4 1229 #define RCC_R38CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1230 #define RCC_R38CIDCFGR_SEMWLC_SHIFT 16 1231 1232 /* RCC_R38SEMCR register fields */ 1233 #define RCC_R38SEMCR_SEM_MUTEX BIT(0) 1234 #define RCC_R38SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1235 #define RCC_R38SEMCR_SEMCID_SHIFT 4 1236 1237 /* RCC_R39CIDCFGR register fields */ 1238 #define RCC_R39CIDCFGR_CFEN BIT(0) 1239 #define RCC_R39CIDCFGR_SEM_EN BIT(1) 1240 #define RCC_R39CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1241 #define RCC_R39CIDCFGR_SCID_SHIFT 4 1242 #define RCC_R39CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1243 #define RCC_R39CIDCFGR_SEMWLC_SHIFT 16 1244 1245 /* RCC_R39SEMCR register fields */ 1246 #define RCC_R39SEMCR_SEM_MUTEX BIT(0) 1247 #define RCC_R39SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1248 #define RCC_R39SEMCR_SEMCID_SHIFT 4 1249 1250 /* RCC_R40CIDCFGR register fields */ 1251 #define RCC_R40CIDCFGR_CFEN BIT(0) 1252 #define RCC_R40CIDCFGR_SEM_EN BIT(1) 1253 #define RCC_R40CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1254 #define RCC_R40CIDCFGR_SCID_SHIFT 4 1255 #define RCC_R40CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1256 #define RCC_R40CIDCFGR_SEMWLC_SHIFT 16 1257 1258 /* RCC_R40SEMCR register fields */ 1259 #define RCC_R40SEMCR_SEM_MUTEX BIT(0) 1260 #define RCC_R40SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1261 #define RCC_R40SEMCR_SEMCID_SHIFT 4 1262 1263 /* RCC_R41CIDCFGR register fields */ 1264 #define RCC_R41CIDCFGR_CFEN BIT(0) 1265 #define RCC_R41CIDCFGR_SEM_EN BIT(1) 1266 #define RCC_R41CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1267 #define RCC_R41CIDCFGR_SCID_SHIFT 4 1268 #define RCC_R41CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1269 #define RCC_R41CIDCFGR_SEMWLC_SHIFT 16 1270 1271 /* RCC_R41SEMCR register fields */ 1272 #define RCC_R41SEMCR_SEM_MUTEX BIT(0) 1273 #define RCC_R41SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1274 #define RCC_R41SEMCR_SEMCID_SHIFT 4 1275 1276 /* RCC_R42CIDCFGR register fields */ 1277 #define RCC_R42CIDCFGR_CFEN BIT(0) 1278 #define RCC_R42CIDCFGR_SEM_EN BIT(1) 1279 #define RCC_R42CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1280 #define RCC_R42CIDCFGR_SCID_SHIFT 4 1281 #define RCC_R42CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1282 #define RCC_R42CIDCFGR_SEMWLC_SHIFT 16 1283 1284 /* RCC_R42SEMCR register fields */ 1285 #define RCC_R42SEMCR_SEM_MUTEX BIT(0) 1286 #define RCC_R42SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1287 #define RCC_R42SEMCR_SEMCID_SHIFT 4 1288 1289 /* RCC_R43CIDCFGR register fields */ 1290 #define RCC_R43CIDCFGR_CFEN BIT(0) 1291 #define RCC_R43CIDCFGR_SEM_EN BIT(1) 1292 #define RCC_R43CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1293 #define RCC_R43CIDCFGR_SCID_SHIFT 4 1294 #define RCC_R43CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1295 #define RCC_R43CIDCFGR_SEMWLC_SHIFT 16 1296 1297 /* RCC_R43SEMCR register fields */ 1298 #define RCC_R43SEMCR_SEM_MUTEX BIT(0) 1299 #define RCC_R43SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1300 #define RCC_R43SEMCR_SEMCID_SHIFT 4 1301 1302 /* RCC_R44CIDCFGR register fields */ 1303 #define RCC_R44CIDCFGR_CFEN BIT(0) 1304 #define RCC_R44CIDCFGR_SEM_EN BIT(1) 1305 #define RCC_R44CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1306 #define RCC_R44CIDCFGR_SCID_SHIFT 4 1307 #define RCC_R44CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1308 #define RCC_R44CIDCFGR_SEMWLC_SHIFT 16 1309 1310 /* RCC_R44SEMCR register fields */ 1311 #define RCC_R44SEMCR_SEM_MUTEX BIT(0) 1312 #define RCC_R44SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1313 #define RCC_R44SEMCR_SEMCID_SHIFT 4 1314 1315 /* RCC_R45CIDCFGR register fields */ 1316 #define RCC_R45CIDCFGR_CFEN BIT(0) 1317 #define RCC_R45CIDCFGR_SEM_EN BIT(1) 1318 #define RCC_R45CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1319 #define RCC_R45CIDCFGR_SCID_SHIFT 4 1320 #define RCC_R45CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1321 #define RCC_R45CIDCFGR_SEMWLC_SHIFT 16 1322 1323 /* RCC_R45SEMCR register fields */ 1324 #define RCC_R45SEMCR_SEM_MUTEX BIT(0) 1325 #define RCC_R45SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1326 #define RCC_R45SEMCR_SEMCID_SHIFT 4 1327 1328 /* RCC_R46CIDCFGR register fields */ 1329 #define RCC_R46CIDCFGR_CFEN BIT(0) 1330 #define RCC_R46CIDCFGR_SEM_EN BIT(1) 1331 #define RCC_R46CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1332 #define RCC_R46CIDCFGR_SCID_SHIFT 4 1333 #define RCC_R46CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1334 #define RCC_R46CIDCFGR_SEMWLC_SHIFT 16 1335 1336 /* RCC_R46SEMCR register fields */ 1337 #define RCC_R46SEMCR_SEM_MUTEX BIT(0) 1338 #define RCC_R46SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1339 #define RCC_R46SEMCR_SEMCID_SHIFT 4 1340 1341 /* RCC_R47CIDCFGR register fields */ 1342 #define RCC_R47CIDCFGR_CFEN BIT(0) 1343 #define RCC_R47CIDCFGR_SEM_EN BIT(1) 1344 #define RCC_R47CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1345 #define RCC_R47CIDCFGR_SCID_SHIFT 4 1346 #define RCC_R47CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1347 #define RCC_R47CIDCFGR_SEMWLC_SHIFT 16 1348 1349 /* RCC_R47SEMCR register fields */ 1350 #define RCC_R47SEMCR_SEM_MUTEX BIT(0) 1351 #define RCC_R47SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1352 #define RCC_R47SEMCR_SEMCID_SHIFT 4 1353 1354 /* RCC_R48CIDCFGR register fields */ 1355 #define RCC_R48CIDCFGR_CFEN BIT(0) 1356 #define RCC_R48CIDCFGR_SEM_EN BIT(1) 1357 #define RCC_R48CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1358 #define RCC_R48CIDCFGR_SCID_SHIFT 4 1359 #define RCC_R48CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1360 #define RCC_R48CIDCFGR_SEMWLC_SHIFT 16 1361 1362 /* RCC_R48SEMCR register fields */ 1363 #define RCC_R48SEMCR_SEM_MUTEX BIT(0) 1364 #define RCC_R48SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1365 #define RCC_R48SEMCR_SEMCID_SHIFT 4 1366 1367 /* RCC_R49CIDCFGR register fields */ 1368 #define RCC_R49CIDCFGR_CFEN BIT(0) 1369 #define RCC_R49CIDCFGR_SEM_EN BIT(1) 1370 #define RCC_R49CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1371 #define RCC_R49CIDCFGR_SCID_SHIFT 4 1372 #define RCC_R49CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1373 #define RCC_R49CIDCFGR_SEMWLC_SHIFT 16 1374 1375 /* RCC_R49SEMCR register fields */ 1376 #define RCC_R49SEMCR_SEM_MUTEX BIT(0) 1377 #define RCC_R49SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1378 #define RCC_R49SEMCR_SEMCID_SHIFT 4 1379 1380 /* RCC_R50CIDCFGR register fields */ 1381 #define RCC_R50CIDCFGR_CFEN BIT(0) 1382 #define RCC_R50CIDCFGR_SEM_EN BIT(1) 1383 #define RCC_R50CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1384 #define RCC_R50CIDCFGR_SCID_SHIFT 4 1385 #define RCC_R50CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1386 #define RCC_R50CIDCFGR_SEMWLC_SHIFT 16 1387 1388 /* RCC_R50SEMCR register fields */ 1389 #define RCC_R50SEMCR_SEM_MUTEX BIT(0) 1390 #define RCC_R50SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1391 #define RCC_R50SEMCR_SEMCID_SHIFT 4 1392 1393 /* RCC_R51CIDCFGR register fields */ 1394 #define RCC_R51CIDCFGR_CFEN BIT(0) 1395 #define RCC_R51CIDCFGR_SEM_EN BIT(1) 1396 #define RCC_R51CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1397 #define RCC_R51CIDCFGR_SCID_SHIFT 4 1398 #define RCC_R51CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1399 #define RCC_R51CIDCFGR_SEMWLC_SHIFT 16 1400 1401 /* RCC_R51SEMCR register fields */ 1402 #define RCC_R51SEMCR_SEM_MUTEX BIT(0) 1403 #define RCC_R51SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1404 #define RCC_R51SEMCR_SEMCID_SHIFT 4 1405 1406 /* RCC_R52CIDCFGR register fields */ 1407 #define RCC_R52CIDCFGR_CFEN BIT(0) 1408 #define RCC_R52CIDCFGR_SEM_EN BIT(1) 1409 #define RCC_R52CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1410 #define RCC_R52CIDCFGR_SCID_SHIFT 4 1411 #define RCC_R52CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1412 #define RCC_R52CIDCFGR_SEMWLC_SHIFT 16 1413 1414 /* RCC_R52SEMCR register fields */ 1415 #define RCC_R52SEMCR_SEM_MUTEX BIT(0) 1416 #define RCC_R52SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1417 #define RCC_R52SEMCR_SEMCID_SHIFT 4 1418 1419 /* RCC_R53CIDCFGR register fields */ 1420 #define RCC_R53CIDCFGR_CFEN BIT(0) 1421 #define RCC_R53CIDCFGR_SEM_EN BIT(1) 1422 #define RCC_R53CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1423 #define RCC_R53CIDCFGR_SCID_SHIFT 4 1424 #define RCC_R53CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1425 #define RCC_R53CIDCFGR_SEMWLC_SHIFT 16 1426 1427 /* RCC_R53SEMCR register fields */ 1428 #define RCC_R53SEMCR_SEM_MUTEX BIT(0) 1429 #define RCC_R53SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1430 #define RCC_R53SEMCR_SEMCID_SHIFT 4 1431 1432 /* RCC_R54CIDCFGR register fields */ 1433 #define RCC_R54CIDCFGR_CFEN BIT(0) 1434 #define RCC_R54CIDCFGR_SEM_EN BIT(1) 1435 #define RCC_R54CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1436 #define RCC_R54CIDCFGR_SCID_SHIFT 4 1437 #define RCC_R54CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1438 #define RCC_R54CIDCFGR_SEMWLC_SHIFT 16 1439 1440 /* RCC_R54SEMCR register fields */ 1441 #define RCC_R54SEMCR_SEM_MUTEX BIT(0) 1442 #define RCC_R54SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1443 #define RCC_R54SEMCR_SEMCID_SHIFT 4 1444 1445 /* RCC_R55CIDCFGR register fields */ 1446 #define RCC_R55CIDCFGR_CFEN BIT(0) 1447 #define RCC_R55CIDCFGR_SEM_EN BIT(1) 1448 #define RCC_R55CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1449 #define RCC_R55CIDCFGR_SCID_SHIFT 4 1450 #define RCC_R55CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1451 #define RCC_R55CIDCFGR_SEMWLC_SHIFT 16 1452 1453 /* RCC_R55SEMCR register fields */ 1454 #define RCC_R55SEMCR_SEM_MUTEX BIT(0) 1455 #define RCC_R55SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1456 #define RCC_R55SEMCR_SEMCID_SHIFT 4 1457 1458 /* RCC_R56CIDCFGR register fields */ 1459 #define RCC_R56CIDCFGR_CFEN BIT(0) 1460 #define RCC_R56CIDCFGR_SEM_EN BIT(1) 1461 #define RCC_R56CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1462 #define RCC_R56CIDCFGR_SCID_SHIFT 4 1463 #define RCC_R56CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1464 #define RCC_R56CIDCFGR_SEMWLC_SHIFT 16 1465 1466 /* RCC_R56SEMCR register fields */ 1467 #define RCC_R56SEMCR_SEM_MUTEX BIT(0) 1468 #define RCC_R56SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1469 #define RCC_R56SEMCR_SEMCID_SHIFT 4 1470 1471 /* RCC_R57CIDCFGR register fields */ 1472 #define RCC_R57CIDCFGR_CFEN BIT(0) 1473 #define RCC_R57CIDCFGR_SEM_EN BIT(1) 1474 #define RCC_R57CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1475 #define RCC_R57CIDCFGR_SCID_SHIFT 4 1476 #define RCC_R57CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1477 #define RCC_R57CIDCFGR_SEMWLC_SHIFT 16 1478 1479 /* RCC_R57SEMCR register fields */ 1480 #define RCC_R57SEMCR_SEM_MUTEX BIT(0) 1481 #define RCC_R57SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1482 #define RCC_R57SEMCR_SEMCID_SHIFT 4 1483 1484 /* RCC_R58CIDCFGR register fields */ 1485 #define RCC_R58CIDCFGR_CFEN BIT(0) 1486 #define RCC_R58CIDCFGR_SEM_EN BIT(1) 1487 #define RCC_R58CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1488 #define RCC_R58CIDCFGR_SCID_SHIFT 4 1489 #define RCC_R58CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1490 #define RCC_R58CIDCFGR_SEMWLC_SHIFT 16 1491 1492 /* RCC_R58SEMCR register fields */ 1493 #define RCC_R58SEMCR_SEM_MUTEX BIT(0) 1494 #define RCC_R58SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1495 #define RCC_R58SEMCR_SEMCID_SHIFT 4 1496 1497 /* RCC_R59CIDCFGR register fields */ 1498 #define RCC_R59CIDCFGR_CFEN BIT(0) 1499 #define RCC_R59CIDCFGR_SEM_EN BIT(1) 1500 #define RCC_R59CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1501 #define RCC_R59CIDCFGR_SCID_SHIFT 4 1502 #define RCC_R59CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1503 #define RCC_R59CIDCFGR_SEMWLC_SHIFT 16 1504 1505 /* RCC_R59SEMCR register fields */ 1506 #define RCC_R59SEMCR_SEM_MUTEX BIT(0) 1507 #define RCC_R59SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1508 #define RCC_R59SEMCR_SEMCID_SHIFT 4 1509 1510 /* RCC_R60CIDCFGR register fields */ 1511 #define RCC_R60CIDCFGR_CFEN BIT(0) 1512 #define RCC_R60CIDCFGR_SEM_EN BIT(1) 1513 #define RCC_R60CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1514 #define RCC_R60CIDCFGR_SCID_SHIFT 4 1515 #define RCC_R60CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1516 #define RCC_R60CIDCFGR_SEMWLC_SHIFT 16 1517 1518 /* RCC_R60SEMCR register fields */ 1519 #define RCC_R60SEMCR_SEM_MUTEX BIT(0) 1520 #define RCC_R60SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1521 #define RCC_R60SEMCR_SEMCID_SHIFT 4 1522 1523 /* RCC_R61CIDCFGR register fields */ 1524 #define RCC_R61CIDCFGR_CFEN BIT(0) 1525 #define RCC_R61CIDCFGR_SEM_EN BIT(1) 1526 #define RCC_R61CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1527 #define RCC_R61CIDCFGR_SCID_SHIFT 4 1528 #define RCC_R61CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1529 #define RCC_R61CIDCFGR_SEMWLC_SHIFT 16 1530 1531 /* RCC_R61SEMCR register fields */ 1532 #define RCC_R61SEMCR_SEM_MUTEX BIT(0) 1533 #define RCC_R61SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1534 #define RCC_R61SEMCR_SEMCID_SHIFT 4 1535 1536 /* RCC_R62CIDCFGR register fields */ 1537 #define RCC_R62CIDCFGR_CFEN BIT(0) 1538 #define RCC_R62CIDCFGR_SEM_EN BIT(1) 1539 #define RCC_R62CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1540 #define RCC_R62CIDCFGR_SCID_SHIFT 4 1541 #define RCC_R62CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1542 #define RCC_R62CIDCFGR_SEMWLC_SHIFT 16 1543 1544 /* RCC_R62SEMCR register fields */ 1545 #define RCC_R62SEMCR_SEM_MUTEX BIT(0) 1546 #define RCC_R62SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1547 #define RCC_R62SEMCR_SEMCID_SHIFT 4 1548 1549 /* RCC_R63CIDCFGR register fields */ 1550 #define RCC_R63CIDCFGR_CFEN BIT(0) 1551 #define RCC_R63CIDCFGR_SEM_EN BIT(1) 1552 #define RCC_R63CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1553 #define RCC_R63CIDCFGR_SCID_SHIFT 4 1554 #define RCC_R63CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1555 #define RCC_R63CIDCFGR_SEMWLC_SHIFT 16 1556 1557 /* RCC_R63SEMCR register fields */ 1558 #define RCC_R63SEMCR_SEM_MUTEX BIT(0) 1559 #define RCC_R63SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1560 #define RCC_R63SEMCR_SEMCID_SHIFT 4 1561 1562 /* RCC_R64CIDCFGR register fields */ 1563 #define RCC_R64CIDCFGR_CFEN BIT(0) 1564 #define RCC_R64CIDCFGR_SEM_EN BIT(1) 1565 #define RCC_R64CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1566 #define RCC_R64CIDCFGR_SCID_SHIFT 4 1567 #define RCC_R64CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1568 #define RCC_R64CIDCFGR_SEMWLC_SHIFT 16 1569 1570 /* RCC_R64SEMCR register fields */ 1571 #define RCC_R64SEMCR_SEM_MUTEX BIT(0) 1572 #define RCC_R64SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1573 #define RCC_R64SEMCR_SEMCID_SHIFT 4 1574 1575 /* RCC_R65CIDCFGR register fields */ 1576 #define RCC_R65CIDCFGR_CFEN BIT(0) 1577 #define RCC_R65CIDCFGR_SEM_EN BIT(1) 1578 #define RCC_R65CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1579 #define RCC_R65CIDCFGR_SCID_SHIFT 4 1580 #define RCC_R65CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1581 #define RCC_R65CIDCFGR_SEMWLC_SHIFT 16 1582 1583 /* RCC_R65SEMCR register fields */ 1584 #define RCC_R65SEMCR_SEM_MUTEX BIT(0) 1585 #define RCC_R65SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1586 #define RCC_R65SEMCR_SEMCID_SHIFT 4 1587 1588 /* RCC_R66CIDCFGR register fields */ 1589 #define RCC_R66CIDCFGR_CFEN BIT(0) 1590 #define RCC_R66CIDCFGR_SEM_EN BIT(1) 1591 #define RCC_R66CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1592 #define RCC_R66CIDCFGR_SCID_SHIFT 4 1593 #define RCC_R66CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1594 #define RCC_R66CIDCFGR_SEMWLC_SHIFT 16 1595 1596 /* RCC_R66SEMCR register fields */ 1597 #define RCC_R66SEMCR_SEM_MUTEX BIT(0) 1598 #define RCC_R66SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1599 #define RCC_R66SEMCR_SEMCID_SHIFT 4 1600 1601 /* RCC_R67CIDCFGR register fields */ 1602 #define RCC_R67CIDCFGR_CFEN BIT(0) 1603 #define RCC_R67CIDCFGR_SEM_EN BIT(1) 1604 #define RCC_R67CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1605 #define RCC_R67CIDCFGR_SCID_SHIFT 4 1606 #define RCC_R67CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1607 #define RCC_R67CIDCFGR_SEMWLC_SHIFT 16 1608 1609 /* RCC_R67SEMCR register fields */ 1610 #define RCC_R67SEMCR_SEM_MUTEX BIT(0) 1611 #define RCC_R67SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1612 #define RCC_R67SEMCR_SEMCID_SHIFT 4 1613 1614 /* RCC_R68CIDCFGR register fields */ 1615 #define RCC_R68CIDCFGR_CFEN BIT(0) 1616 #define RCC_R68CIDCFGR_SEM_EN BIT(1) 1617 #define RCC_R68CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1618 #define RCC_R68CIDCFGR_SCID_SHIFT 4 1619 #define RCC_R68CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1620 #define RCC_R68CIDCFGR_SEMWLC_SHIFT 16 1621 1622 /* RCC_R68SEMCR register fields */ 1623 #define RCC_R68SEMCR_SEM_MUTEX BIT(0) 1624 #define RCC_R68SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1625 #define RCC_R68SEMCR_SEMCID_SHIFT 4 1626 1627 /* RCC_R69CIDCFGR register fields */ 1628 #define RCC_R69CIDCFGR_CFEN BIT(0) 1629 #define RCC_R69CIDCFGR_SEM_EN BIT(1) 1630 #define RCC_R69CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1631 #define RCC_R69CIDCFGR_SCID_SHIFT 4 1632 #define RCC_R69CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1633 #define RCC_R69CIDCFGR_SEMWLC_SHIFT 16 1634 1635 /* RCC_R69SEMCR register fields */ 1636 #define RCC_R69SEMCR_SEM_MUTEX BIT(0) 1637 #define RCC_R69SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1638 #define RCC_R69SEMCR_SEMCID_SHIFT 4 1639 1640 /* RCC_R70CIDCFGR register fields */ 1641 #define RCC_R70CIDCFGR_CFEN BIT(0) 1642 #define RCC_R70CIDCFGR_SEM_EN BIT(1) 1643 #define RCC_R70CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1644 #define RCC_R70CIDCFGR_SCID_SHIFT 4 1645 #define RCC_R70CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1646 #define RCC_R70CIDCFGR_SEMWLC_SHIFT 16 1647 1648 /* RCC_R70SEMCR register fields */ 1649 #define RCC_R70SEMCR_SEM_MUTEX BIT(0) 1650 #define RCC_R70SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1651 #define RCC_R70SEMCR_SEMCID_SHIFT 4 1652 1653 /* RCC_R71CIDCFGR register fields */ 1654 #define RCC_R71CIDCFGR_CFEN BIT(0) 1655 #define RCC_R71CIDCFGR_SEM_EN BIT(1) 1656 #define RCC_R71CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1657 #define RCC_R71CIDCFGR_SCID_SHIFT 4 1658 #define RCC_R71CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1659 #define RCC_R71CIDCFGR_SEMWLC_SHIFT 16 1660 1661 /* RCC_R71SEMCR register fields */ 1662 #define RCC_R71SEMCR_SEM_MUTEX BIT(0) 1663 #define RCC_R71SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1664 #define RCC_R71SEMCR_SEMCID_SHIFT 4 1665 1666 /* RCC_R72CIDCFGR register fields */ 1667 #define RCC_R72CIDCFGR_CFEN BIT(0) 1668 #define RCC_R72CIDCFGR_SEM_EN BIT(1) 1669 #define RCC_R72CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1670 #define RCC_R72CIDCFGR_SCID_SHIFT 4 1671 #define RCC_R72CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1672 #define RCC_R72CIDCFGR_SEMWLC_SHIFT 16 1673 1674 /* RCC_R72SEMCR register fields */ 1675 #define RCC_R72SEMCR_SEM_MUTEX BIT(0) 1676 #define RCC_R72SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1677 #define RCC_R72SEMCR_SEMCID_SHIFT 4 1678 1679 /* RCC_R73CIDCFGR register fields */ 1680 #define RCC_R73CIDCFGR_CFEN BIT(0) 1681 #define RCC_R73CIDCFGR_SEM_EN BIT(1) 1682 #define RCC_R73CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1683 #define RCC_R73CIDCFGR_SCID_SHIFT 4 1684 #define RCC_R73CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1685 #define RCC_R73CIDCFGR_SEMWLC_SHIFT 16 1686 1687 /* RCC_R73SEMCR register fields */ 1688 #define RCC_R73SEMCR_SEM_MUTEX BIT(0) 1689 #define RCC_R73SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1690 #define RCC_R73SEMCR_SEMCID_SHIFT 4 1691 1692 /* RCC_R74CIDCFGR register fields */ 1693 #define RCC_R74CIDCFGR_CFEN BIT(0) 1694 #define RCC_R74CIDCFGR_SEM_EN BIT(1) 1695 #define RCC_R74CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1696 #define RCC_R74CIDCFGR_SCID_SHIFT 4 1697 #define RCC_R74CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1698 #define RCC_R74CIDCFGR_SEMWLC_SHIFT 16 1699 1700 /* RCC_R74SEMCR register fields */ 1701 #define RCC_R74SEMCR_SEM_MUTEX BIT(0) 1702 #define RCC_R74SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1703 #define RCC_R74SEMCR_SEMCID_SHIFT 4 1704 1705 /* RCC_R75CIDCFGR register fields */ 1706 #define RCC_R75CIDCFGR_CFEN BIT(0) 1707 #define RCC_R75CIDCFGR_SEM_EN BIT(1) 1708 #define RCC_R75CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1709 #define RCC_R75CIDCFGR_SCID_SHIFT 4 1710 #define RCC_R75CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1711 #define RCC_R75CIDCFGR_SEMWLC_SHIFT 16 1712 1713 /* RCC_R75SEMCR register fields */ 1714 #define RCC_R75SEMCR_SEM_MUTEX BIT(0) 1715 #define RCC_R75SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1716 #define RCC_R75SEMCR_SEMCID_SHIFT 4 1717 1718 /* RCC_R76CIDCFGR register fields */ 1719 #define RCC_R76CIDCFGR_CFEN BIT(0) 1720 #define RCC_R76CIDCFGR_SEM_EN BIT(1) 1721 #define RCC_R76CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1722 #define RCC_R76CIDCFGR_SCID_SHIFT 4 1723 #define RCC_R76CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1724 #define RCC_R76CIDCFGR_SEMWLC_SHIFT 16 1725 1726 /* RCC_R76SEMCR register fields */ 1727 #define RCC_R76SEMCR_SEM_MUTEX BIT(0) 1728 #define RCC_R76SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1729 #define RCC_R76SEMCR_SEMCID_SHIFT 4 1730 1731 /* RCC_R77CIDCFGR register fields */ 1732 #define RCC_R77CIDCFGR_CFEN BIT(0) 1733 #define RCC_R77CIDCFGR_SEM_EN BIT(1) 1734 #define RCC_R77CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1735 #define RCC_R77CIDCFGR_SCID_SHIFT 4 1736 #define RCC_R77CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1737 #define RCC_R77CIDCFGR_SEMWLC_SHIFT 16 1738 1739 /* RCC_R77SEMCR register fields */ 1740 #define RCC_R77SEMCR_SEM_MUTEX BIT(0) 1741 #define RCC_R77SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1742 #define RCC_R77SEMCR_SEMCID_SHIFT 4 1743 1744 /* RCC_R78CIDCFGR register fields */ 1745 #define RCC_R78CIDCFGR_CFEN BIT(0) 1746 #define RCC_R78CIDCFGR_SEM_EN BIT(1) 1747 #define RCC_R78CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1748 #define RCC_R78CIDCFGR_SCID_SHIFT 4 1749 #define RCC_R78CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1750 #define RCC_R78CIDCFGR_SEMWLC_SHIFT 16 1751 1752 /* RCC_R78SEMCR register fields */ 1753 #define RCC_R78SEMCR_SEM_MUTEX BIT(0) 1754 #define RCC_R78SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1755 #define RCC_R78SEMCR_SEMCID_SHIFT 4 1756 1757 /* RCC_R79CIDCFGR register fields */ 1758 #define RCC_R79CIDCFGR_CFEN BIT(0) 1759 #define RCC_R79CIDCFGR_SEM_EN BIT(1) 1760 #define RCC_R79CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1761 #define RCC_R79CIDCFGR_SCID_SHIFT 4 1762 #define RCC_R79CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1763 #define RCC_R79CIDCFGR_SEMWLC_SHIFT 16 1764 1765 /* RCC_R79SEMCR register fields */ 1766 #define RCC_R79SEMCR_SEM_MUTEX BIT(0) 1767 #define RCC_R79SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1768 #define RCC_R79SEMCR_SEMCID_SHIFT 4 1769 1770 /* RCC_R80CIDCFGR register fields */ 1771 #define RCC_R80CIDCFGR_CFEN BIT(0) 1772 #define RCC_R80CIDCFGR_SEM_EN BIT(1) 1773 #define RCC_R80CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1774 #define RCC_R80CIDCFGR_SCID_SHIFT 4 1775 #define RCC_R80CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1776 #define RCC_R80CIDCFGR_SEMWLC_SHIFT 16 1777 1778 /* RCC_R80SEMCR register fields */ 1779 #define RCC_R80SEMCR_SEM_MUTEX BIT(0) 1780 #define RCC_R80SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1781 #define RCC_R80SEMCR_SEMCID_SHIFT 4 1782 1783 /* RCC_R81CIDCFGR register fields */ 1784 #define RCC_R81CIDCFGR_CFEN BIT(0) 1785 #define RCC_R81CIDCFGR_SEM_EN BIT(1) 1786 #define RCC_R81CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1787 #define RCC_R81CIDCFGR_SCID_SHIFT 4 1788 #define RCC_R81CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1789 #define RCC_R81CIDCFGR_SEMWLC_SHIFT 16 1790 1791 /* RCC_R81SEMCR register fields */ 1792 #define RCC_R81SEMCR_SEM_MUTEX BIT(0) 1793 #define RCC_R81SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1794 #define RCC_R81SEMCR_SEMCID_SHIFT 4 1795 1796 /* RCC_R82CIDCFGR register fields */ 1797 #define RCC_R82CIDCFGR_CFEN BIT(0) 1798 #define RCC_R82CIDCFGR_SEM_EN BIT(1) 1799 #define RCC_R82CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1800 #define RCC_R82CIDCFGR_SCID_SHIFT 4 1801 #define RCC_R82CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1802 #define RCC_R82CIDCFGR_SEMWLC_SHIFT 16 1803 1804 /* RCC_R82SEMCR register fields */ 1805 #define RCC_R82SEMCR_SEM_MUTEX BIT(0) 1806 #define RCC_R82SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1807 #define RCC_R82SEMCR_SEMCID_SHIFT 4 1808 1809 /* RCC_R83CIDCFGR register fields */ 1810 #define RCC_R83CIDCFGR_CFEN BIT(0) 1811 #define RCC_R83CIDCFGR_SEM_EN BIT(1) 1812 #define RCC_R83CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1813 #define RCC_R83CIDCFGR_SCID_SHIFT 4 1814 #define RCC_R83CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1815 #define RCC_R83CIDCFGR_SEMWLC_SHIFT 16 1816 1817 /* RCC_R83SEMCR register fields */ 1818 #define RCC_R83SEMCR_SEM_MUTEX BIT(0) 1819 #define RCC_R83SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1820 #define RCC_R83SEMCR_SEMCID_SHIFT 4 1821 1822 /* RCC_R84CIDCFGR register fields */ 1823 #define RCC_R84CIDCFGR_CFEN BIT(0) 1824 #define RCC_R84CIDCFGR_SEM_EN BIT(1) 1825 #define RCC_R84CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1826 #define RCC_R84CIDCFGR_SCID_SHIFT 4 1827 #define RCC_R84CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1828 #define RCC_R84CIDCFGR_SEMWLC_SHIFT 16 1829 1830 /* RCC_R84SEMCR register fields */ 1831 #define RCC_R84SEMCR_SEM_MUTEX BIT(0) 1832 #define RCC_R84SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1833 #define RCC_R84SEMCR_SEMCID_SHIFT 4 1834 1835 /* RCC_R85CIDCFGR register fields */ 1836 #define RCC_R85CIDCFGR_CFEN BIT(0) 1837 #define RCC_R85CIDCFGR_SEM_EN BIT(1) 1838 #define RCC_R85CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1839 #define RCC_R85CIDCFGR_SCID_SHIFT 4 1840 #define RCC_R85CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1841 #define RCC_R85CIDCFGR_SEMWLC_SHIFT 16 1842 1843 /* RCC_R85SEMCR register fields */ 1844 #define RCC_R85SEMCR_SEM_MUTEX BIT(0) 1845 #define RCC_R85SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1846 #define RCC_R85SEMCR_SEMCID_SHIFT 4 1847 1848 /* RCC_R86CIDCFGR register fields */ 1849 #define RCC_R86CIDCFGR_CFEN BIT(0) 1850 #define RCC_R86CIDCFGR_SEM_EN BIT(1) 1851 #define RCC_R86CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1852 #define RCC_R86CIDCFGR_SCID_SHIFT 4 1853 #define RCC_R86CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1854 #define RCC_R86CIDCFGR_SEMWLC_SHIFT 16 1855 1856 /* RCC_R86SEMCR register fields */ 1857 #define RCC_R86SEMCR_SEM_MUTEX BIT(0) 1858 #define RCC_R86SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1859 #define RCC_R86SEMCR_SEMCID_SHIFT 4 1860 1861 /* RCC_R87CIDCFGR register fields */ 1862 #define RCC_R87CIDCFGR_CFEN BIT(0) 1863 #define RCC_R87CIDCFGR_SEM_EN BIT(1) 1864 #define RCC_R87CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1865 #define RCC_R87CIDCFGR_SCID_SHIFT 4 1866 #define RCC_R87CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1867 #define RCC_R87CIDCFGR_SEMWLC_SHIFT 16 1868 1869 /* RCC_R87SEMCR register fields */ 1870 #define RCC_R87SEMCR_SEM_MUTEX BIT(0) 1871 #define RCC_R87SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1872 #define RCC_R87SEMCR_SEMCID_SHIFT 4 1873 1874 /* RCC_R88CIDCFGR register fields */ 1875 #define RCC_R88CIDCFGR_CFEN BIT(0) 1876 #define RCC_R88CIDCFGR_SEM_EN BIT(1) 1877 #define RCC_R88CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1878 #define RCC_R88CIDCFGR_SCID_SHIFT 4 1879 #define RCC_R88CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1880 #define RCC_R88CIDCFGR_SEMWLC_SHIFT 16 1881 1882 /* RCC_R88SEMCR register fields */ 1883 #define RCC_R88SEMCR_SEM_MUTEX BIT(0) 1884 #define RCC_R88SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1885 #define RCC_R88SEMCR_SEMCID_SHIFT 4 1886 1887 /* RCC_R89CIDCFGR register fields */ 1888 #define RCC_R89CIDCFGR_CFEN BIT(0) 1889 #define RCC_R89CIDCFGR_SEM_EN BIT(1) 1890 #define RCC_R89CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1891 #define RCC_R89CIDCFGR_SCID_SHIFT 4 1892 #define RCC_R89CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1893 #define RCC_R89CIDCFGR_SEMWLC_SHIFT 16 1894 1895 /* RCC_R89SEMCR register fields */ 1896 #define RCC_R89SEMCR_SEM_MUTEX BIT(0) 1897 #define RCC_R89SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1898 #define RCC_R89SEMCR_SEMCID_SHIFT 4 1899 1900 /* RCC_R90CIDCFGR register fields */ 1901 #define RCC_R90CIDCFGR_CFEN BIT(0) 1902 #define RCC_R90CIDCFGR_SEM_EN BIT(1) 1903 #define RCC_R90CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1904 #define RCC_R90CIDCFGR_SCID_SHIFT 4 1905 #define RCC_R90CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1906 #define RCC_R90CIDCFGR_SEMWLC_SHIFT 16 1907 1908 /* RCC_R90SEMCR register fields */ 1909 #define RCC_R90SEMCR_SEM_MUTEX BIT(0) 1910 #define RCC_R90SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1911 #define RCC_R90SEMCR_SEMCID_SHIFT 4 1912 1913 /* RCC_R91CIDCFGR register fields */ 1914 #define RCC_R91CIDCFGR_CFEN BIT(0) 1915 #define RCC_R91CIDCFGR_SEM_EN BIT(1) 1916 #define RCC_R91CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1917 #define RCC_R91CIDCFGR_SCID_SHIFT 4 1918 #define RCC_R91CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1919 #define RCC_R91CIDCFGR_SEMWLC_SHIFT 16 1920 1921 /* RCC_R91SEMCR register fields */ 1922 #define RCC_R91SEMCR_SEM_MUTEX BIT(0) 1923 #define RCC_R91SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1924 #define RCC_R91SEMCR_SEMCID_SHIFT 4 1925 1926 /* RCC_R92CIDCFGR register fields */ 1927 #define RCC_R92CIDCFGR_CFEN BIT(0) 1928 #define RCC_R92CIDCFGR_SEM_EN BIT(1) 1929 #define RCC_R92CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1930 #define RCC_R92CIDCFGR_SCID_SHIFT 4 1931 #define RCC_R92CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1932 #define RCC_R92CIDCFGR_SEMWLC_SHIFT 16 1933 1934 /* RCC_R92SEMCR register fields */ 1935 #define RCC_R92SEMCR_SEM_MUTEX BIT(0) 1936 #define RCC_R92SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1937 #define RCC_R92SEMCR_SEMCID_SHIFT 4 1938 1939 /* RCC_R93CIDCFGR register fields */ 1940 #define RCC_R93CIDCFGR_CFEN BIT(0) 1941 #define RCC_R93CIDCFGR_SEM_EN BIT(1) 1942 #define RCC_R93CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1943 #define RCC_R93CIDCFGR_SCID_SHIFT 4 1944 #define RCC_R93CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1945 #define RCC_R93CIDCFGR_SEMWLC_SHIFT 16 1946 1947 /* RCC_R93SEMCR register fields */ 1948 #define RCC_R93SEMCR_SEM_MUTEX BIT(0) 1949 #define RCC_R93SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1950 #define RCC_R93SEMCR_SEMCID_SHIFT 4 1951 1952 /* RCC_R94CIDCFGR register fields */ 1953 #define RCC_R94CIDCFGR_CFEN BIT(0) 1954 #define RCC_R94CIDCFGR_SEM_EN BIT(1) 1955 #define RCC_R94CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1956 #define RCC_R94CIDCFGR_SCID_SHIFT 4 1957 #define RCC_R94CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1958 #define RCC_R94CIDCFGR_SEMWLC_SHIFT 16 1959 1960 /* RCC_R94SEMCR register fields */ 1961 #define RCC_R94SEMCR_SEM_MUTEX BIT(0) 1962 #define RCC_R94SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1963 #define RCC_R94SEMCR_SEMCID_SHIFT 4 1964 1965 /* RCC_R95CIDCFGR register fields */ 1966 #define RCC_R95CIDCFGR_CFEN BIT(0) 1967 #define RCC_R95CIDCFGR_SEM_EN BIT(1) 1968 #define RCC_R95CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1969 #define RCC_R95CIDCFGR_SCID_SHIFT 4 1970 #define RCC_R95CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1971 #define RCC_R95CIDCFGR_SEMWLC_SHIFT 16 1972 1973 /* RCC_R95SEMCR register fields */ 1974 #define RCC_R95SEMCR_SEM_MUTEX BIT(0) 1975 #define RCC_R95SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1976 #define RCC_R95SEMCR_SEMCID_SHIFT 4 1977 1978 /* RCC_R96CIDCFGR register fields */ 1979 #define RCC_R96CIDCFGR_CFEN BIT(0) 1980 #define RCC_R96CIDCFGR_SEM_EN BIT(1) 1981 #define RCC_R96CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1982 #define RCC_R96CIDCFGR_SCID_SHIFT 4 1983 #define RCC_R96CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1984 #define RCC_R96CIDCFGR_SEMWLC_SHIFT 16 1985 1986 /* RCC_R96SEMCR register fields */ 1987 #define RCC_R96SEMCR_SEM_MUTEX BIT(0) 1988 #define RCC_R96SEMCR_SEMCID_MASK GENMASK_32(6, 4) 1989 #define RCC_R96SEMCR_SEMCID_SHIFT 4 1990 1991 /* RCC_R97CIDCFGR register fields */ 1992 #define RCC_R97CIDCFGR_CFEN BIT(0) 1993 #define RCC_R97CIDCFGR_SEM_EN BIT(1) 1994 #define RCC_R97CIDCFGR_SCID_MASK GENMASK_32(6, 4) 1995 #define RCC_R97CIDCFGR_SCID_SHIFT 4 1996 #define RCC_R97CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 1997 #define RCC_R97CIDCFGR_SEMWLC_SHIFT 16 1998 1999 /* RCC_R97SEMCR register fields */ 2000 #define RCC_R97SEMCR_SEM_MUTEX BIT(0) 2001 #define RCC_R97SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2002 #define RCC_R97SEMCR_SEMCID_SHIFT 4 2003 2004 /* RCC_R98CIDCFGR register fields */ 2005 #define RCC_R98CIDCFGR_CFEN BIT(0) 2006 #define RCC_R98CIDCFGR_SEM_EN BIT(1) 2007 #define RCC_R98CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2008 #define RCC_R98CIDCFGR_SCID_SHIFT 4 2009 #define RCC_R98CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2010 #define RCC_R98CIDCFGR_SEMWLC_SHIFT 16 2011 2012 /* RCC_R98SEMCR register fields */ 2013 #define RCC_R98SEMCR_SEM_MUTEX BIT(0) 2014 #define RCC_R98SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2015 #define RCC_R98SEMCR_SEMCID_SHIFT 4 2016 2017 /* RCC_R99CIDCFGR register fields */ 2018 #define RCC_R99CIDCFGR_CFEN BIT(0) 2019 #define RCC_R99CIDCFGR_SEM_EN BIT(1) 2020 #define RCC_R99CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2021 #define RCC_R99CIDCFGR_SCID_SHIFT 4 2022 #define RCC_R99CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2023 #define RCC_R99CIDCFGR_SEMWLC_SHIFT 16 2024 2025 /* RCC_R99SEMCR register fields */ 2026 #define RCC_R99SEMCR_SEM_MUTEX BIT(0) 2027 #define RCC_R99SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2028 #define RCC_R99SEMCR_SEMCID_SHIFT 4 2029 2030 /* RCC_R100CIDCFGR register fields */ 2031 #define RCC_R100CIDCFGR_CFEN BIT(0) 2032 #define RCC_R100CIDCFGR_SEM_EN BIT(1) 2033 #define RCC_R100CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2034 #define RCC_R100CIDCFGR_SCID_SHIFT 4 2035 #define RCC_R100CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2036 #define RCC_R100CIDCFGR_SEMWLC_SHIFT 16 2037 2038 /* RCC_R100SEMCR register fields */ 2039 #define RCC_R100SEMCR_SEM_MUTEX BIT(0) 2040 #define RCC_R100SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2041 #define RCC_R100SEMCR_SEMCID_SHIFT 4 2042 2043 /* RCC_R101CIDCFGR register fields */ 2044 #define RCC_R101CIDCFGR_CFEN BIT(0) 2045 #define RCC_R101CIDCFGR_SEM_EN BIT(1) 2046 #define RCC_R101CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2047 #define RCC_R101CIDCFGR_SCID_SHIFT 4 2048 #define RCC_R101CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2049 #define RCC_R101CIDCFGR_SEMWLC_SHIFT 16 2050 2051 /* RCC_R101SEMCR register fields */ 2052 #define RCC_R101SEMCR_SEM_MUTEX BIT(0) 2053 #define RCC_R101SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2054 #define RCC_R101SEMCR_SEMCID_SHIFT 4 2055 2056 /* RCC_R102CIDCFGR register fields */ 2057 #define RCC_R102CIDCFGR_CFEN BIT(0) 2058 #define RCC_R102CIDCFGR_SEM_EN BIT(1) 2059 #define RCC_R102CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2060 #define RCC_R102CIDCFGR_SCID_SHIFT 4 2061 #define RCC_R102CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2062 #define RCC_R102CIDCFGR_SEMWLC_SHIFT 16 2063 2064 /* RCC_R102SEMCR register fields */ 2065 #define RCC_R102SEMCR_SEM_MUTEX BIT(0) 2066 #define RCC_R102SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2067 #define RCC_R102SEMCR_SEMCID_SHIFT 4 2068 2069 /* RCC_R103CIDCFGR register fields */ 2070 #define RCC_R103CIDCFGR_CFEN BIT(0) 2071 #define RCC_R103CIDCFGR_SEM_EN BIT(1) 2072 #define RCC_R103CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2073 #define RCC_R103CIDCFGR_SCID_SHIFT 4 2074 #define RCC_R103CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2075 #define RCC_R103CIDCFGR_SEMWLC_SHIFT 16 2076 2077 /* RCC_R103SEMCR register fields */ 2078 #define RCC_R103SEMCR_SEM_MUTEX BIT(0) 2079 #define RCC_R103SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2080 #define RCC_R103SEMCR_SEMCID_SHIFT 4 2081 2082 /* RCC_R104CIDCFGR register fields */ 2083 #define RCC_R104CIDCFGR_CFEN BIT(0) 2084 #define RCC_R104CIDCFGR_SEM_EN BIT(1) 2085 #define RCC_R104CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2086 #define RCC_R104CIDCFGR_SCID_SHIFT 4 2087 #define RCC_R104CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2088 #define RCC_R104CIDCFGR_SEMWLC_SHIFT 16 2089 2090 /* RCC_R104SEMCR register fields */ 2091 #define RCC_R104SEMCR_SEM_MUTEX BIT(0) 2092 #define RCC_R104SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2093 #define RCC_R104SEMCR_SEMCID_SHIFT 4 2094 2095 /* RCC_R105CIDCFGR register fields */ 2096 #define RCC_R105CIDCFGR_CFEN BIT(0) 2097 #define RCC_R105CIDCFGR_SEM_EN BIT(1) 2098 #define RCC_R105CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2099 #define RCC_R105CIDCFGR_SCID_SHIFT 4 2100 #define RCC_R105CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2101 #define RCC_R105CIDCFGR_SEMWLC_SHIFT 16 2102 2103 /* RCC_R105SEMCR register fields */ 2104 #define RCC_R105SEMCR_SEM_MUTEX BIT(0) 2105 #define RCC_R105SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2106 #define RCC_R105SEMCR_SEMCID_SHIFT 4 2107 2108 /* RCC_R106CIDCFGR register fields */ 2109 #define RCC_R106CIDCFGR_CFEN BIT(0) 2110 #define RCC_R106CIDCFGR_SEM_EN BIT(1) 2111 #define RCC_R106CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2112 #define RCC_R106CIDCFGR_SCID_SHIFT 4 2113 #define RCC_R106CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2114 #define RCC_R106CIDCFGR_SEMWLC_SHIFT 16 2115 2116 /* RCC_R106SEMCR register fields */ 2117 #define RCC_R106SEMCR_SEM_MUTEX BIT(0) 2118 #define RCC_R106SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2119 #define RCC_R106SEMCR_SEMCID_SHIFT 4 2120 2121 /* RCC_R107CIDCFGR register fields */ 2122 #define RCC_R107CIDCFGR_CFEN BIT(0) 2123 #define RCC_R107CIDCFGR_SEM_EN BIT(1) 2124 #define RCC_R107CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2125 #define RCC_R107CIDCFGR_SCID_SHIFT 4 2126 #define RCC_R107CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2127 #define RCC_R107CIDCFGR_SEMWLC_SHIFT 16 2128 2129 /* RCC_R107SEMCR register fields */ 2130 #define RCC_R107SEMCR_SEM_MUTEX BIT(0) 2131 #define RCC_R107SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2132 #define RCC_R107SEMCR_SEMCID_SHIFT 4 2133 2134 /* RCC_R108CIDCFGR register fields */ 2135 #define RCC_R108CIDCFGR_CFEN BIT(0) 2136 #define RCC_R108CIDCFGR_SEM_EN BIT(1) 2137 #define RCC_R108CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2138 #define RCC_R108CIDCFGR_SCID_SHIFT 4 2139 #define RCC_R108CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2140 #define RCC_R108CIDCFGR_SEMWLC_SHIFT 16 2141 2142 /* RCC_R108SEMCR register fields */ 2143 #define RCC_R108SEMCR_SEM_MUTEX BIT(0) 2144 #define RCC_R108SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2145 #define RCC_R108SEMCR_SEMCID_SHIFT 4 2146 2147 /* RCC_R109CIDCFGR register fields */ 2148 #define RCC_R109CIDCFGR_CFEN BIT(0) 2149 #define RCC_R109CIDCFGR_SEM_EN BIT(1) 2150 #define RCC_R109CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2151 #define RCC_R109CIDCFGR_SCID_SHIFT 4 2152 #define RCC_R109CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2153 #define RCC_R109CIDCFGR_SEMWLC_SHIFT 16 2154 2155 /* RCC_R109SEMCR register fields */ 2156 #define RCC_R109SEMCR_SEM_MUTEX BIT(0) 2157 #define RCC_R109SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2158 #define RCC_R109SEMCR_SEMCID_SHIFT 4 2159 2160 /* RCC_R110CIDCFGR register fields */ 2161 #define RCC_R110CIDCFGR_CFEN BIT(0) 2162 #define RCC_R110CIDCFGR_SEM_EN BIT(1) 2163 #define RCC_R110CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2164 #define RCC_R110CIDCFGR_SCID_SHIFT 4 2165 #define RCC_R110CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2166 #define RCC_R110CIDCFGR_SEMWLC_SHIFT 16 2167 2168 /* RCC_R110SEMCR register fields */ 2169 #define RCC_R110SEMCR_SEM_MUTEX BIT(0) 2170 #define RCC_R110SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2171 #define RCC_R110SEMCR_SEMCID_SHIFT 4 2172 2173 /* RCC_R111CIDCFGR register fields */ 2174 #define RCC_R111CIDCFGR_CFEN BIT(0) 2175 #define RCC_R111CIDCFGR_SEM_EN BIT(1) 2176 #define RCC_R111CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2177 #define RCC_R111CIDCFGR_SCID_SHIFT 4 2178 #define RCC_R111CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2179 #define RCC_R111CIDCFGR_SEMWLC_SHIFT 16 2180 2181 /* RCC_R111SEMCR register fields */ 2182 #define RCC_R111SEMCR_SEM_MUTEX BIT(0) 2183 #define RCC_R111SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2184 #define RCC_R111SEMCR_SEMCID_SHIFT 4 2185 2186 /* RCC_R112CIDCFGR register fields */ 2187 #define RCC_R112CIDCFGR_CFEN BIT(0) 2188 #define RCC_R112CIDCFGR_SEM_EN BIT(1) 2189 #define RCC_R112CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2190 #define RCC_R112CIDCFGR_SCID_SHIFT 4 2191 #define RCC_R112CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2192 #define RCC_R112CIDCFGR_SEMWLC_SHIFT 16 2193 2194 /* RCC_R112SEMCR register fields */ 2195 #define RCC_R112SEMCR_SEM_MUTEX BIT(0) 2196 #define RCC_R112SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2197 #define RCC_R112SEMCR_SEMCID_SHIFT 4 2198 2199 /* RCC_R113CIDCFGR register fields */ 2200 #define RCC_R113CIDCFGR_CFEN BIT(0) 2201 #define RCC_R113CIDCFGR_SEM_EN BIT(1) 2202 #define RCC_R113CIDCFGR_SCID_MASK GENMASK_32(6, 4) 2203 #define RCC_R113CIDCFGR_SCID_SHIFT 4 2204 #define RCC_R113CIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2205 #define RCC_R113CIDCFGR_SEMWLC_SHIFT 16 2206 2207 /* RCC_R113SEMCR register fields */ 2208 #define RCC_R113SEMCR_SEM_MUTEX BIT(0) 2209 #define RCC_R113SEMCR_SEMCID_MASK GENMASK_32(6, 4) 2210 #define RCC_R113SEMCR_SEMCID_SHIFT 4 2211 2212 /* RCC_RxCIDCFGR register fields */ 2213 #define RCC_RxCIDCFGR_CFEN BIT(0) 2214 #define RCC_RxCIDCFGR_SEM_EN BIT(1) 2215 #define RCC_RxCIDCFGR_SCID_MASK GENMASK_32(6, 4) 2216 #define RCC_RxCIDCFGR_SCID_SHIFT 4 2217 #define RCC_RxCIDCFGR_SEMWLC_MASK GENMASK_32(23, 16) 2218 #define RCC_RxCIDCFGR_SEMWLC_SHIFT 16 2219 2220 /* RCC_RxSEMCR register fields */ 2221 #define RCC_RxSEMCR_SEM_MUTEX BIT(0) 2222 #define RCC_RxSEMCR_SEMCID_MASK GENMASK_32(6, 4) 2223 #define RCC_RxSEMCR_SEMCID_SHIFT 4 2224 2225 /* RCC_GRSTCSETR register fields */ 2226 #define RCC_GRSTCSETR_SYSRST BIT(0) 2227 2228 /* RCC_C1RSTCSETR register fields */ 2229 #define RCC_C1RSTCSETR_C1RST BIT(0) 2230 2231 /* RCC_C1P1RSTCSETR register fields */ 2232 #define RCC_C1P1RSTCSETR_C1P1PORRST BIT(0) 2233 #define RCC_C1P1RSTCSETR_C1P1RST BIT(1) 2234 2235 /* RCC_C2RSTCSETR register fields */ 2236 #define RCC_C2RSTCSETR_C2RST BIT(0) 2237 2238 /* RCC_CxRSTCSETR register fields */ 2239 #define RCC_CxRSTCSETR_CxRST BIT(0) 2240 2241 /* RCC_HWRSTSCLRR register fields */ 2242 #define RCC_HWRSTSCLRR_PORRSTF BIT(0) 2243 #define RCC_HWRSTSCLRR_BORRSTF BIT(1) 2244 #define RCC_HWRSTSCLRR_PADRSTF BIT(2) 2245 #define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) 2246 #define RCC_HWRSTSCLRR_VCORERSTF BIT(4) 2247 #define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) 2248 #define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) 2249 #define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) 2250 #define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) 2251 #define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) 2252 #define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) 2253 #define RCC_HWRSTSCLRR_IWDG5SYSRSTF BIT(11) 2254 #define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) 2255 #define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) 2256 #define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) 2257 2258 /* RCC_C1HWRSTSCLRR register fields */ 2259 #define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) 2260 #define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) 2261 #define RCC_C1HWRSTSCLRR_C1P1RSTF BIT(2) 2262 2263 /* RCC_C2HWRSTSCLRR register fields */ 2264 #define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) 2265 2266 /* RCC_C1BOOTRSTSSETR register fields */ 2267 #define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) 2268 #define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) 2269 #define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) 2270 #define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) 2271 #define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) 2272 #define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) 2273 #define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) 2274 #define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) 2275 #define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 2276 #define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 2277 #define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 2278 #define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 2279 #define RCC_C1BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) 2280 #define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) 2281 #define RCC_C1BOOTRSTSSETR_C1P1RSTF BIT(16) 2282 #define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 2283 #define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 2284 #define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 2285 #define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) 2286 #define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) 2287 #define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) 2288 2289 /* RCC_C1BOOTRSTSCLRR register fields */ 2290 #define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) 2291 #define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) 2292 #define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) 2293 #define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) 2294 #define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) 2295 #define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) 2296 #define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) 2297 #define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) 2298 #define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 2299 #define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 2300 #define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 2301 #define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 2302 #define RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) 2303 #define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) 2304 #define RCC_C1BOOTRSTSCLRR_C1P1RSTF BIT(16) 2305 #define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 2306 #define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 2307 #define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 2308 #define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) 2309 #define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) 2310 #define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) 2311 2312 /* RCC_C2BOOTRSTSSETR register fields */ 2313 #define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) 2314 #define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) 2315 #define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) 2316 #define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) 2317 #define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) 2318 #define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) 2319 #define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) 2320 #define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 2321 #define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 2322 #define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 2323 #define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 2324 #define RCC_C2BOOTRSTSSETR_IWDG5SYSRSTF BIT(12) 2325 #define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) 2326 #define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 2327 #define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 2328 #define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 2329 #define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) 2330 #define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) 2331 2332 /* RCC_C2BOOTRSTSCLRR register fields */ 2333 #define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) 2334 #define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) 2335 #define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) 2336 #define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) 2337 #define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) 2338 #define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) 2339 #define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) 2340 #define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 2341 #define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 2342 #define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 2343 #define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 2344 #define RCC_C2BOOTRSTSCLRR_IWDG5SYSRSTF BIT(12) 2345 #define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) 2346 #define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 2347 #define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 2348 #define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 2349 #define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) 2350 #define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) 2351 2352 /* RCC_C1SREQSETR register fields */ 2353 #define RCC_C1SREQSETR_STPREQ_P0 BIT(0) 2354 #define RCC_C1SREQSETR_STPREQ_P1 BIT(1) 2355 #define RCC_C1SREQSETR_ESLPREQ BIT(16) 2356 2357 /* RCC_C1SREQCLRR register fields */ 2358 #define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) 2359 #define RCC_C1SREQCLRR_STPREQ_P1 BIT(1) 2360 #define RCC_C1SREQCLRR_ESLPREQ BIT(16) 2361 2362 /* RCC_CPUBOOTCR register fields */ 2363 #define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) 2364 #define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) 2365 2366 /* RCC_STBYBOOTCR register fields */ 2367 #define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) 2368 #define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) 2369 #define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) 2370 #define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) 2371 #define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) 2372 2373 /* RCC_LEGBOOTCR register fields */ 2374 #define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) 2375 2376 /* RCC_BDCR register fields */ 2377 #define RCC_BDCR_LSEON BIT(0) 2378 #define RCC_BDCR_LSEBYP BIT(1) 2379 #define RCC_BDCR_LSERDY BIT(2) 2380 #define RCC_BDCR_LSEDIGBYP BIT(3) 2381 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) 2382 #define RCC_BDCR_LSEDRV_SHIFT 4 2383 #define RCC_BDCR_LSECSSON BIT(6) 2384 #define RCC_BDCR_LSEGFON BIT(7) 2385 #define RCC_BDCR_LSECSSD BIT(8) 2386 #define RCC_BDCR_LSION BIT(9) 2387 #define RCC_BDCR_LSIRDY BIT(10) 2388 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) 2389 #define RCC_BDCR_RTCSRC_SHIFT 16 2390 #define RCC_BDCR_RTCCKEN BIT(20) 2391 #define RCC_BDCR_MSIFREQSEL BIT(24) 2392 #define RCC_BDCR_C3SYSTICKSEL BIT(25) 2393 #define RCC_BDCR_VSWRST BIT(31) 2394 #define RCC_BDCR_LSEBYP_BIT 1 2395 #define RCC_BDCR_LSEDIGBYP_BIT 3 2396 #define RCC_BDCR_LSECSSON_BIT 6 2397 #define RCC_BDCR_LSERDY_BIT 2 2398 #define RCC_BDCR_LSIRDY_BIT 10 2399 2400 #define RCC_BDCR_LSEDRV_SHIFT 4 2401 #define RCC_BDCR_LSEDRV_WIDTH 2 2402 2403 /* RCC_D3DCR register fields */ 2404 #define RCC_D3DCR_CSION BIT(0) 2405 #define RCC_D3DCR_CSIKERON BIT(1) 2406 #define RCC_D3DCR_CSIRDY BIT(2) 2407 #define RCC_D3DCR_D3PERCKSEL_MASK GENMASK_32(17, 16) 2408 #define RCC_D3DCR_D3PERCKSEL_SHIFT 16 2409 #define RCC_D3DCR_CSIRDY_BIT 2 2410 2411 /* RCC_D3DSR register fields */ 2412 #define RCC_D3DSR_D3STATE_MASK GENMASK_32(1, 0) 2413 #define RCC_D3DSR_D3STATE_SHIFT 0 2414 2415 /* RCC_RDCR register fields */ 2416 #define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) 2417 #define RCC_RDCR_MRD_SHIFT 16 2418 #define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) 2419 #define RCC_RDCR_EADLY_SHIFT 24 2420 2421 /* RCC_C1MSRDCR register fields */ 2422 #define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) 2423 #define RCC_C1MSRDCR_C1MSRD_SHIFT 0 2424 #define RCC_C1MSRDCR_C1MSRST BIT(8) 2425 2426 /* RCC_PWRLPDLYCR register fields */ 2427 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) 2428 #define RCC_PWRLPDLYCR_PWRLP_DLY_SHIFT 0 2429 #define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) 2430 2431 /* RCC_C1CIESETR register fields */ 2432 #define RCC_C1CIESETR_LSIRDYIE BIT(0) 2433 #define RCC_C1CIESETR_LSERDYIE BIT(1) 2434 #define RCC_C1CIESETR_HSIRDYIE BIT(2) 2435 #define RCC_C1CIESETR_HSERDYIE BIT(3) 2436 #define RCC_C1CIESETR_CSIRDYIE BIT(4) 2437 #define RCC_C1CIESETR_PLL1RDYIE BIT(5) 2438 #define RCC_C1CIESETR_PLL2RDYIE BIT(6) 2439 #define RCC_C1CIESETR_PLL3RDYIE BIT(7) 2440 #define RCC_C1CIESETR_PLL4RDYIE BIT(8) 2441 #define RCC_C1CIESETR_PLL5RDYIE BIT(9) 2442 #define RCC_C1CIESETR_PLL6RDYIE BIT(10) 2443 #define RCC_C1CIESETR_PLL7RDYIE BIT(11) 2444 #define RCC_C1CIESETR_PLL8RDYIE BIT(12) 2445 #define RCC_C1CIESETR_LSECSSIE BIT(16) 2446 #define RCC_C1CIESETR_WKUPIE BIT(20) 2447 2448 /* RCC_C1CIFCLRR register fields */ 2449 #define RCC_C1CIFCLRR_LSIRDYF BIT(0) 2450 #define RCC_C1CIFCLRR_LSERDYF BIT(1) 2451 #define RCC_C1CIFCLRR_HSIRDYF BIT(2) 2452 #define RCC_C1CIFCLRR_HSERDYF BIT(3) 2453 #define RCC_C1CIFCLRR_CSIRDYF BIT(4) 2454 #define RCC_C1CIFCLRR_PLL1RDYF BIT(5) 2455 #define RCC_C1CIFCLRR_PLL2RDYF BIT(6) 2456 #define RCC_C1CIFCLRR_PLL3RDYF BIT(7) 2457 #define RCC_C1CIFCLRR_PLL4RDYF BIT(8) 2458 #define RCC_C1CIFCLRR_PLL5RDYF BIT(9) 2459 #define RCC_C1CIFCLRR_PLL6RDYF BIT(10) 2460 #define RCC_C1CIFCLRR_PLL7RDYF BIT(11) 2461 #define RCC_C1CIFCLRR_PLL8RDYF BIT(12) 2462 #define RCC_C1CIFCLRR_LSECSSF BIT(16) 2463 #define RCC_C1CIFCLRR_WKUPF BIT(20) 2464 2465 /* RCC_C2CIESETR register fields */ 2466 #define RCC_C2CIESETR_LSIRDYIE BIT(0) 2467 #define RCC_C2CIESETR_LSERDYIE BIT(1) 2468 #define RCC_C2CIESETR_HSIRDYIE BIT(2) 2469 #define RCC_C2CIESETR_HSERDYIE BIT(3) 2470 #define RCC_C2CIESETR_CSIRDYIE BIT(4) 2471 #define RCC_C2CIESETR_PLL1RDYIE BIT(5) 2472 #define RCC_C2CIESETR_PLL2RDYIE BIT(6) 2473 #define RCC_C2CIESETR_PLL3RDYIE BIT(7) 2474 #define RCC_C2CIESETR_PLL4RDYIE BIT(8) 2475 #define RCC_C2CIESETR_PLL5RDYIE BIT(9) 2476 #define RCC_C2CIESETR_PLL6RDYIE BIT(10) 2477 #define RCC_C2CIESETR_PLL7RDYIE BIT(11) 2478 #define RCC_C2CIESETR_PLL8RDYIE BIT(12) 2479 #define RCC_C2CIESETR_LSECSSIE BIT(16) 2480 #define RCC_C2CIESETR_WKUPIE BIT(20) 2481 2482 /* RCC_C2CIFCLRR register fields */ 2483 #define RCC_C2CIFCLRR_LSIRDYF BIT(0) 2484 #define RCC_C2CIFCLRR_LSERDYF BIT(1) 2485 #define RCC_C2CIFCLRR_HSIRDYF BIT(2) 2486 #define RCC_C2CIFCLRR_HSERDYF BIT(3) 2487 #define RCC_C2CIFCLRR_CSIRDYF BIT(4) 2488 #define RCC_C2CIFCLRR_PLL1RDYF BIT(5) 2489 #define RCC_C2CIFCLRR_PLL2RDYF BIT(6) 2490 #define RCC_C2CIFCLRR_PLL3RDYF BIT(7) 2491 #define RCC_C2CIFCLRR_PLL4RDYF BIT(8) 2492 #define RCC_C2CIFCLRR_PLL5RDYF BIT(9) 2493 #define RCC_C2CIFCLRR_PLL6RDYF BIT(10) 2494 #define RCC_C2CIFCLRR_PLL7RDYF BIT(11) 2495 #define RCC_C2CIFCLRR_PLL8RDYF BIT(12) 2496 #define RCC_C2CIFCLRR_LSECSSF BIT(16) 2497 #define RCC_C2CIFCLRR_WKUPF BIT(20) 2498 2499 /* RCC_CxCIESETR register fields */ 2500 #define RCC_CxCIESETR_LSIRDYIE BIT(0) 2501 #define RCC_CxCIESETR_LSERDYIE BIT(1) 2502 #define RCC_CxCIESETR_HSIRDYIE BIT(2) 2503 #define RCC_CxCIESETR_HSERDYIE BIT(3) 2504 #define RCC_CxCIESETR_CSIRDYIE BIT(4) 2505 #define RCC_CxCIESETR_SHSIRDYIE BIT(5) 2506 #define RCC_CxCIESETR_PLL1RDYIE BIT(6) 2507 #define RCC_CxCIESETR_PLL2RDYIE BIT(7) 2508 #define RCC_CxCIESETR_PLL3RDYIE BIT(8) 2509 #define RCC_CxCIESETR_PLL4RDYIE BIT(9) 2510 #define RCC_CxCIESETR_PLL5RDYIE BIT(10) 2511 #define RCC_CxCIESETR_PLL6RDYIE BIT(11) 2512 #define RCC_CxCIESETR_PLL7RDYIE BIT(12) 2513 #define RCC_CxCIESETR_PLL8RDYIE BIT(13) 2514 #define RCC_CxCIESETR_LSECSSIE BIT(16) 2515 #define RCC_CxCIESETR_WKUPIE BIT(20) 2516 2517 /* RCC_CxCIFCLRR register fields */ 2518 #define RCC_CxCIFCLRR_LSIRDYF BIT(0) 2519 #define RCC_CxCIFCLRR_LSERDYF BIT(1) 2520 #define RCC_CxCIFCLRR_HSIRDYF BIT(2) 2521 #define RCC_CxCIFCLRR_HSERDYF BIT(3) 2522 #define RCC_CxCIFCLRR_CSIRDYF BIT(4) 2523 #define RCC_CxCIFCLRR_SHSIRDYF BIT(5) 2524 #define RCC_CxCIFCLRR_PLL1RDYF BIT(6) 2525 #define RCC_CxCIFCLRR_PLL2RDYF BIT(7) 2526 #define RCC_CxCIFCLRR_PLL3RDYF BIT(8) 2527 #define RCC_CxCIFCLRR_PLL4RDYF BIT(9) 2528 #define RCC_CxCIFCLRR_PLL5RDYF BIT(10) 2529 #define RCC_CxCIFCLRR_PLL6RDYF BIT(11) 2530 #define RCC_CxCIFCLRR_PLL7RDYF BIT(12) 2531 #define RCC_CxCIFCLRR_PLL8RDYF BIT(13) 2532 #define RCC_CxCIFCLRR_LSECSSF BIT(16) 2533 #define RCC_CxCIFCLRR_WKUPF BIT(20) 2534 2535 /* RCC_IWDGC1FZSETR register fields */ 2536 #define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) 2537 #define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) 2538 2539 /* RCC_IWDGC1FZCLRR register fields */ 2540 #define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) 2541 #define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) 2542 2543 /* RCC_IWDGC1CFGSETR register fields */ 2544 #define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) 2545 #define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) 2546 #define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) 2547 2548 /* RCC_IWDGC1CFGCLRR register fields */ 2549 #define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) 2550 #define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) 2551 #define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) 2552 2553 /* RCC_IWDGC2FZSETR register fields */ 2554 #define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) 2555 #define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) 2556 2557 /* RCC_IWDGC2FZCLRR register fields */ 2558 #define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) 2559 #define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) 2560 2561 /* RCC_IWDGC2CFGSETR register fields */ 2562 #define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) 2563 #define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) 2564 #define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) 2565 2566 /* RCC_IWDGC2CFGCLRR register fields */ 2567 #define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) 2568 #define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) 2569 #define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) 2570 2571 /* RCC_IWDGC3CFGSETR register fields */ 2572 #define RCC_IWDGC3CFGSETR_IWDG5_SYSRSTEN BIT(0) 2573 2574 /* RCC_IWDGC3CFGCLRR register fields */ 2575 #define RCC_IWDGC3CFGCLRR_IWDG5_SYSRSTEN BIT(0) 2576 2577 /* RCC_C3CFGR register fields */ 2578 #define RCC_C3CFGR_C3RST BIT(0) 2579 #define RCC_C3CFGR_C3EN BIT(1) 2580 #define RCC_C3CFGR_C3LPEN BIT(2) 2581 #define RCC_C3CFGR_C3AMEN BIT(3) 2582 #define RCC_C3CFGR_LPTIM3C3EN BIT(16) 2583 #define RCC_C3CFGR_LPTIM4C3EN BIT(17) 2584 #define RCC_C3CFGR_LPTIM5C3EN BIT(18) 2585 #define RCC_C3CFGR_SPI8C3EN BIT(19) 2586 #define RCC_C3CFGR_LPUART1C3EN BIT(20) 2587 #define RCC_C3CFGR_I2C8C3EN BIT(21) 2588 #define RCC_C3CFGR_ADF1C3EN BIT(23) 2589 #define RCC_C3CFGR_GPIOZC3EN BIT(24) 2590 #define RCC_C3CFGR_LPDMAC3EN BIT(25) 2591 #define RCC_C3CFGR_RTCC3EN BIT(26) 2592 #define RCC_C3CFGR_I3C4C3EN BIT(27) 2593 2594 /* RCC_MCO1CFGR register fields */ 2595 #define RCC_MCO1CFGR_MCO1SEL BIT(0) 2596 #define RCC_MCO1CFGR_MCO1ON BIT(8) 2597 2598 /* RCC_MCO2CFGR register fields */ 2599 #define RCC_MCO2CFGR_MCO2SEL BIT(0) 2600 #define RCC_MCO2CFGR_MCO2ON BIT(8) 2601 2602 /* RCC_MCOxCFGR register fields */ 2603 #define RCC_MCOxCFGR_MCOxSEL BIT(0) 2604 #define RCC_MCOxCFGR_MCOxON BIT(8) 2605 2606 /* RCC_OCENSETR register fields */ 2607 #define RCC_OCENSETR_HSION BIT(0) 2608 #define RCC_OCENSETR_HSIKERON BIT(1) 2609 #define RCC_OCENSETR_HSEDIV2ON BIT(5) 2610 #define RCC_OCENSETR_HSEDIV2BYP BIT(6) 2611 #define RCC_OCENSETR_HSEDIGBYP BIT(7) 2612 #define RCC_OCENSETR_HSEON BIT(8) 2613 #define RCC_OCENSETR_HSEKERON BIT(9) 2614 #define RCC_OCENSETR_HSEBYP BIT(10) 2615 #define RCC_OCENSETR_HSECSSON BIT(11) 2616 2617 /* RCC_OCENCLRR register fields */ 2618 #define RCC_OCENCLRR_HSION BIT(0) 2619 #define RCC_OCENCLRR_HSIKERON BIT(1) 2620 #define RCC_OCENCLRR_HSEDIV2ON BIT(5) 2621 #define RCC_OCENCLRR_HSEDIV2BYP BIT(6) 2622 #define RCC_OCENCLRR_HSEDIGBYP BIT(7) 2623 #define RCC_OCENCLRR_HSEON BIT(8) 2624 #define RCC_OCENCLRR_HSEKERON BIT(9) 2625 #define RCC_OCENCLRR_HSEBYP BIT(10) 2626 2627 /* RCC_OCRDYR register fields */ 2628 #define RCC_OCRDYR_HSIRDY BIT(0) 2629 #define RCC_OCRDYR_HSERDY BIT(8) 2630 #define RCC_OCRDYR_CKREST BIT(25) 2631 2632 #define RCC_OCRDYR_HSIRDY_BIT 0 2633 #define RCC_OCRDYR_HSERDY_BIT 8 2634 2635 /* RCC_HSICFGR register fields */ 2636 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) 2637 #define RCC_HSICFGR_HSITRIM_SHIFT 8 2638 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) 2639 #define RCC_HSICFGR_HSICAL_SHIFT 16 2640 2641 /* RCC_CSICFGR register fields */ 2642 #define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8) 2643 #define RCC_CSICFGR_CSITRIM_SHIFT 8 2644 #define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16) 2645 #define RCC_CSICFGR_CSICAL_SHIFT 16 2646 2647 /* RCC_RTCDIVR register fields */ 2648 #define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) 2649 #define RCC_RTCDIVR_RTCDIV_SHIFT 0 2650 2651 /* RCC_APB1DIVR register fields */ 2652 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) 2653 #define RCC_APB1DIVR_APB1DIV_SHIFT 0 2654 #define RCC_APB1DIVR_APB1DIVRDY BIT(31) 2655 2656 /* RCC_APB2DIVR register fields */ 2657 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) 2658 #define RCC_APB2DIVR_APB2DIV_SHIFT 0 2659 #define RCC_APB2DIVR_APB2DIVRDY BIT(31) 2660 2661 /* RCC_APB3DIVR register fields */ 2662 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) 2663 #define RCC_APB3DIVR_APB3DIV_SHIFT 0 2664 #define RCC_APB3DIVR_APB3DIVRDY BIT(31) 2665 2666 /* RCC_APB4DIVR register fields */ 2667 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) 2668 #define RCC_APB4DIVR_APB4DIV_SHIFT 0 2669 #define RCC_APB4DIVR_APB4DIVRDY BIT(31) 2670 2671 /* RCC_APBDBGDIVR register fields */ 2672 #define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) 2673 #define RCC_APBDBGDIVR_APBDBGDIV_SHIFT 0 2674 #define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) 2675 2676 /* RCC_APBxDIVR register fields */ 2677 #define RCC_APBxDIVR_APBxDIV_MASK GENMASK_32(2, 0) 2678 #define RCC_APBxDIVR_APBxDIV_SHIFT 0 2679 #define RCC_APBxDIVR_APBxDIVRDY BIT(31) 2680 2681 /* RCC_TIMG1PRER register fields */ 2682 #define RCC_TIMG1PRER_TIMG1PRE BIT(0) 2683 #define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) 2684 2685 /* RCC_TIMG2PRER register fields */ 2686 #define RCC_TIMG2PRER_TIMG2PRE BIT(0) 2687 #define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) 2688 2689 /* RCC_TIMGxPRER register fields */ 2690 #define RCC_TIMGxPRER_TIMGxPRE BIT(0) 2691 #define RCC_TIMGxPRER_TIMGxPRERDY BIT(31) 2692 2693 /* RCC_LSMCUDIVR register fields */ 2694 #define RCC_LSMCUDIVR_LSMCUDIV BIT(0) 2695 #define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) 2696 2697 /* RCC_DDRCPCFGR register fields */ 2698 #define RCC_DDRCPCFGR_DDRCPRST BIT(0) 2699 #define RCC_DDRCPCFGR_DDRCPEN BIT(1) 2700 #define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) 2701 2702 /* RCC_DDRCAPBCFGR register fields */ 2703 #define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) 2704 #define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) 2705 #define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) 2706 2707 /* RCC_DDRPHYCAPBCFGR register fields */ 2708 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) 2709 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) 2710 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) 2711 2712 /* RCC_DDRPHYCCFGR register fields */ 2713 #define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) 2714 2715 /* RCC_DDRCFGR register fields */ 2716 #define RCC_DDRCFGR_DDRCFGRST BIT(0) 2717 #define RCC_DDRCFGR_DDRCFGEN BIT(1) 2718 #define RCC_DDRCFGR_DDRCFGLPEN BIT(2) 2719 2720 /* RCC_DDRITFCFGR register fields */ 2721 #define RCC_DDRITFCFGR_DDRRST BIT(0) 2722 #define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) 2723 #define RCC_DDRITFCFGR_DDRCKMOD_SHIFT 4 2724 #define RCC_DDRITFCFGR_DDRCKMOD_HSR BIT(5) 2725 #define RCC_DDRITFCFGR_DDRSHR BIT(8) 2726 #define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) 2727 2728 /* RCC_SYSRAMCFGR register fields */ 2729 #define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) 2730 #define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) 2731 2732 /* RCC_VDERAMCFGR register fields */ 2733 #define RCC_VDERAMCFGR_VDERAMEN BIT(1) 2734 #define RCC_VDERAMCFGR_VDERAMLPEN BIT(2) 2735 2736 /* RCC_SRAM1CFGR register fields */ 2737 #define RCC_SRAM1CFGR_SRAM1EN BIT(1) 2738 #define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) 2739 2740 /* RCC_SRAM2CFGR register fields */ 2741 #define RCC_SRAM2CFGR_SRAM2EN BIT(1) 2742 #define RCC_SRAM2CFGR_SRAM2LPEN BIT(2) 2743 2744 /* RCC_RETRAMCFGR register fields */ 2745 #define RCC_RETRAMCFGR_RETRAMEN BIT(1) 2746 #define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) 2747 2748 /* RCC_BKPSRAMCFGR register fields */ 2749 #define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) 2750 #define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) 2751 2752 /* RCC_LPSRAM1CFGR register fields */ 2753 #define RCC_LPSRAM1CFGR_LPSRAM1EN BIT(1) 2754 #define RCC_LPSRAM1CFGR_LPSRAM1LPEN BIT(2) 2755 #define RCC_LPSRAM1CFGR_LPSRAM1AMEN BIT(3) 2756 2757 /* RCC_LPSRAM2CFGR register fields */ 2758 #define RCC_LPSRAM2CFGR_LPSRAM2EN BIT(1) 2759 #define RCC_LPSRAM2CFGR_LPSRAM2LPEN BIT(2) 2760 #define RCC_LPSRAM2CFGR_LPSRAM2AMEN BIT(3) 2761 2762 /* RCC_LPSRAM3CFGR register fields */ 2763 #define RCC_LPSRAM3CFGR_LPSRAM3EN BIT(1) 2764 #define RCC_LPSRAM3CFGR_LPSRAM3LPEN BIT(2) 2765 #define RCC_LPSRAM3CFGR_LPSRAM3AMEN BIT(3) 2766 2767 /* RCC_OSPI1CFGR register fields */ 2768 #define RCC_OSPI1CFGR_OSPI1RST BIT(0) 2769 #define RCC_OSPI1CFGR_OSPI1EN BIT(1) 2770 #define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) 2771 #define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) 2772 #define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) 2773 2774 /* RCC_OSPI2CFGR register fields */ 2775 #define RCC_OSPI2CFGR_OSPI2RST BIT(0) 2776 #define RCC_OSPI2CFGR_OSPI2EN BIT(1) 2777 #define RCC_OSPI2CFGR_OSPI2LPEN BIT(2) 2778 #define RCC_OSPI2CFGR_OTFDEC2RST BIT(8) 2779 #define RCC_OSPI2CFGR_OSPI2DLLRST BIT(16) 2780 2781 /* RCC_OSPIxCFGR register fields */ 2782 #define RCC_OSPIxCFGR_OSPIxRST BIT(0) 2783 #define RCC_OSPIxCFGR_OSPIxEN BIT(1) 2784 #define RCC_OSPIxCFGR_OSPIxLPEN BIT(2) 2785 #define RCC_OSPIxCFGR_OTFDECxRST BIT(8) 2786 #define RCC_OSPIxCFGR_OSPIxDLLRST BIT(16) 2787 2788 /* RCC_FMCCFGR register fields */ 2789 #define RCC_FMCCFGR_FMCRST BIT(0) 2790 #define RCC_FMCCFGR_FMCEN BIT(1) 2791 #define RCC_FMCCFGR_FMCLPEN BIT(2) 2792 2793 /* RCC_DBGCFGR register fields */ 2794 #define RCC_DBGCFGR_DBGEN BIT(8) 2795 #define RCC_DBGCFGR_TRACEEN BIT(9) 2796 #define RCC_DBGCFGR_DBGRST BIT(12) 2797 2798 /* RCC_STM500CFGR register fields */ 2799 #define RCC_STM500CFGR_STM500EN BIT(1) 2800 #define RCC_STM500CFGR_STM500LPEN BIT(2) 2801 2802 /* RCC_ETRCFGR register fields */ 2803 #define RCC_ETRCFGR_ETREN BIT(1) 2804 #define RCC_ETRCFGR_ETRLPEN BIT(2) 2805 2806 /* RCC_GPIOACFGR register fields */ 2807 #define RCC_GPIOACFGR_GPIOARST BIT(0) 2808 #define RCC_GPIOACFGR_GPIOAEN BIT(1) 2809 #define RCC_GPIOACFGR_GPIOALPEN BIT(2) 2810 2811 /* RCC_GPIOBCFGR register fields */ 2812 #define RCC_GPIOBCFGR_GPIOBRST BIT(0) 2813 #define RCC_GPIOBCFGR_GPIOBEN BIT(1) 2814 #define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) 2815 2816 /* RCC_GPIOCCFGR register fields */ 2817 #define RCC_GPIOCCFGR_GPIOCRST BIT(0) 2818 #define RCC_GPIOCCFGR_GPIOCEN BIT(1) 2819 #define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) 2820 2821 /* RCC_GPIODCFGR register fields */ 2822 #define RCC_GPIODCFGR_GPIODRST BIT(0) 2823 #define RCC_GPIODCFGR_GPIODEN BIT(1) 2824 #define RCC_GPIODCFGR_GPIODLPEN BIT(2) 2825 2826 /* RCC_GPIOECFGR register fields */ 2827 #define RCC_GPIOECFGR_GPIOERST BIT(0) 2828 #define RCC_GPIOECFGR_GPIOEEN BIT(1) 2829 #define RCC_GPIOECFGR_GPIOELPEN BIT(2) 2830 2831 /* RCC_GPIOFCFGR register fields */ 2832 #define RCC_GPIOFCFGR_GPIOFRST BIT(0) 2833 #define RCC_GPIOFCFGR_GPIOFEN BIT(1) 2834 #define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) 2835 2836 /* RCC_GPIOGCFGR register fields */ 2837 #define RCC_GPIOGCFGR_GPIOGRST BIT(0) 2838 #define RCC_GPIOGCFGR_GPIOGEN BIT(1) 2839 #define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) 2840 2841 /* RCC_GPIOHCFGR register fields */ 2842 #define RCC_GPIOHCFGR_GPIOHRST BIT(0) 2843 #define RCC_GPIOHCFGR_GPIOHEN BIT(1) 2844 #define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) 2845 2846 /* RCC_GPIOICFGR register fields */ 2847 #define RCC_GPIOICFGR_GPIOIRST BIT(0) 2848 #define RCC_GPIOICFGR_GPIOIEN BIT(1) 2849 #define RCC_GPIOICFGR_GPIOILPEN BIT(2) 2850 2851 /* RCC_GPIOJCFGR register fields */ 2852 #define RCC_GPIOJCFGR_GPIOJRST BIT(0) 2853 #define RCC_GPIOJCFGR_GPIOJEN BIT(1) 2854 #define RCC_GPIOJCFGR_GPIOJLPEN BIT(2) 2855 2856 /* RCC_GPIOKCFGR register fields */ 2857 #define RCC_GPIOKCFGR_GPIOKRST BIT(0) 2858 #define RCC_GPIOKCFGR_GPIOKEN BIT(1) 2859 #define RCC_GPIOKCFGR_GPIOKLPEN BIT(2) 2860 2861 /* RCC_GPIOZCFGR register fields */ 2862 #define RCC_GPIOZCFGR_GPIOZRST BIT(0) 2863 #define RCC_GPIOZCFGR_GPIOZEN BIT(1) 2864 #define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) 2865 #define RCC_GPIOZCFGR_GPIOZAMEN BIT(3) 2866 2867 /* RCC_GPIOxCFGR register fields */ 2868 #define RCC_GPIOxCFGR_GPIOxRST BIT(0) 2869 #define RCC_GPIOxCFGR_GPIOxEN BIT(1) 2870 #define RCC_GPIOxCFGR_GPIOxLPEN BIT(2) 2871 #define RCC_GPIOxCFGR_GPIOxAMEN BIT(3) 2872 2873 /* RCC_HPDMA1CFGR register fields */ 2874 #define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) 2875 #define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) 2876 #define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) 2877 2878 /* RCC_HPDMA2CFGR register fields */ 2879 #define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) 2880 #define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) 2881 #define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) 2882 2883 /* RCC_HPDMA3CFGR register fields */ 2884 #define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) 2885 #define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) 2886 #define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) 2887 2888 /* RCC_HPDMAxCFGR register fields */ 2889 #define RCC_HPDMAxCFGR_HPDMAxRST BIT(0) 2890 #define RCC_HPDMAxCFGR_HPDMAxEN BIT(1) 2891 #define RCC_HPDMAxCFGR_HPDMAxLPEN BIT(2) 2892 2893 /* RCC_LPDMACFGR register fields */ 2894 #define RCC_LPDMACFGR_LPDMARST BIT(0) 2895 #define RCC_LPDMACFGR_LPDMAEN BIT(1) 2896 #define RCC_LPDMACFGR_LPDMALPEN BIT(2) 2897 #define RCC_LPDMACFGR_LPDMAAMEN BIT(3) 2898 2899 /* RCC_HSEMCFGR register fields */ 2900 #define RCC_HSEMCFGR_HSEMRST BIT(0) 2901 #define RCC_HSEMCFGR_HSEMEN BIT(1) 2902 #define RCC_HSEMCFGR_HSEMLPEN BIT(2) 2903 #define RCC_HSEMCFGR_HSEMAMEN BIT(3) 2904 2905 /* RCC_IPCC1CFGR register fields */ 2906 #define RCC_IPCC1CFGR_IPCC1RST BIT(0) 2907 #define RCC_IPCC1CFGR_IPCC1EN BIT(1) 2908 #define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) 2909 2910 /* RCC_IPCC2CFGR register fields */ 2911 #define RCC_IPCC2CFGR_IPCC2RST BIT(0) 2912 #define RCC_IPCC2CFGR_IPCC2EN BIT(1) 2913 #define RCC_IPCC2CFGR_IPCC2LPEN BIT(2) 2914 #define RCC_IPCC2CFGR_IPCC2AMEN BIT(3) 2915 2916 /* RCC_RTCCFGR register fields */ 2917 #define RCC_RTCCFGR_RTCEN BIT(1) 2918 #define RCC_RTCCFGR_RTCLPEN BIT(2) 2919 #define RCC_RTCCFGR_RTCAMEN BIT(3) 2920 2921 /* RCC_SYSCPU1CFGR register fields */ 2922 #define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) 2923 #define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) 2924 2925 /* RCC_BSECCFGR register fields */ 2926 #define RCC_BSECCFGR_BSECEN BIT(1) 2927 #define RCC_BSECCFGR_BSECLPEN BIT(2) 2928 2929 /* RCC_IS2MCFGR register fields */ 2930 #define RCC_IS2MCFGR_IS2MRST BIT(0) 2931 #define RCC_IS2MCFGR_IS2MEN BIT(1) 2932 #define RCC_IS2MCFGR_IS2MLPEN BIT(2) 2933 2934 /* RCC_PLL2CFGR1 register fields */ 2935 #define RCC_PLL2CFGR1_SSMODRST BIT(0) 2936 #define RCC_PLL2CFGR1_PLLEN BIT(8) 2937 #define RCC_PLL2CFGR1_PLLRDY BIT(24) 2938 #define RCC_PLL2CFGR1_CKREFST BIT(28) 2939 2940 /* RCC_PLL2CFGR2 register fields */ 2941 #define RCC_PLL2CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 2942 #define RCC_PLL2CFGR2_FREFDIV_SHIFT 0 2943 #define RCC_PLL2CFGR2_FBDIV_MASK GENMASK_32(27, 16) 2944 #define RCC_PLL2CFGR2_FBDIV_SHIFT 16 2945 2946 /* RCC_PLL2CFGR3 register fields */ 2947 #define RCC_PLL2CFGR3_FRACIN_MASK GENMASK_32(23, 0) 2948 #define RCC_PLL2CFGR3_FRACIN_SHIFT 0 2949 #define RCC_PLL2CFGR3_DOWNSPREAD BIT(24) 2950 #define RCC_PLL2CFGR3_DACEN BIT(25) 2951 #define RCC_PLL2CFGR3_SSCGDIS BIT(26) 2952 2953 /* RCC_PLL2CFGR4 register fields */ 2954 #define RCC_PLL2CFGR4_DSMEN BIT(8) 2955 #define RCC_PLL2CFGR4_FOUTPOSTDIVEN BIT(9) 2956 #define RCC_PLL2CFGR4_BYPASS BIT(10) 2957 2958 /* RCC_PLL2CFGR5 register fields */ 2959 #define RCC_PLL2CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 2960 #define RCC_PLL2CFGR5_DIVVAL_SHIFT 0 2961 #define RCC_PLL2CFGR5_SPREAD_MASK GENMASK_32(20, 16) 2962 #define RCC_PLL2CFGR5_SPREAD_SHIFT 16 2963 2964 /* RCC_PLL2CFGR6 register fields */ 2965 #define RCC_PLL2CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 2966 #define RCC_PLL2CFGR6_POSTDIV1_SHIFT 0 2967 2968 /* RCC_PLL2CFGR7 register fields */ 2969 #define RCC_PLL2CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 2970 #define RCC_PLL2CFGR7_POSTDIV2_SHIFT 0 2971 2972 /* RCC_PLL3CFGR1 register fields */ 2973 #define RCC_PLL3CFGR1_SSMODRST BIT(0) 2974 #define RCC_PLL3CFGR1_PLLEN BIT(8) 2975 #define RCC_PLL3CFGR1_PLLRDY BIT(24) 2976 #define RCC_PLL3CFGR1_CKREFST BIT(28) 2977 2978 /* RCC_PLL3CFGR2 register fields */ 2979 #define RCC_PLL3CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 2980 #define RCC_PLL3CFGR2_FREFDIV_SHIFT 0 2981 #define RCC_PLL3CFGR2_FBDIV_MASK GENMASK_32(27, 16) 2982 #define RCC_PLL3CFGR2_FBDIV_SHIFT 16 2983 2984 /* RCC_PLL3CFGR3 register fields */ 2985 #define RCC_PLL3CFGR3_FRACIN_MASK GENMASK_32(23, 0) 2986 #define RCC_PLL3CFGR3_FRACIN_SHIFT 0 2987 #define RCC_PLL3CFGR3_DOWNSPREAD BIT(24) 2988 #define RCC_PLL3CFGR3_DACEN BIT(25) 2989 #define RCC_PLL3CFGR3_SSCGDIS BIT(26) 2990 2991 /* RCC_PLL3CFGR4 register fields */ 2992 #define RCC_PLL3CFGR4_DSMEN BIT(8) 2993 #define RCC_PLL3CFGR4_FOUTPOSTDIVEN BIT(9) 2994 #define RCC_PLL3CFGR4_BYPASS BIT(10) 2995 2996 /* RCC_PLL3CFGR5 register fields */ 2997 #define RCC_PLL3CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 2998 #define RCC_PLL3CFGR5_DIVVAL_SHIFT 0 2999 #define RCC_PLL3CFGR5_SPREAD_MASK GENMASK_32(20, 16) 3000 #define RCC_PLL3CFGR5_SPREAD_SHIFT 16 3001 3002 /* RCC_PLL3CFGR6 register fields */ 3003 #define RCC_PLL3CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 3004 #define RCC_PLL3CFGR6_POSTDIV1_SHIFT 0 3005 3006 /* RCC_PLL3CFGR7 register fields */ 3007 #define RCC_PLL3CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 3008 #define RCC_PLL3CFGR7_POSTDIV2_SHIFT 0 3009 3010 /* RCC_PLLxCFGR1 register fields */ 3011 #define RCC_PLLxCFGR1_SSMODRST BIT(0) 3012 #define RCC_PLLxCFGR1_PLLEN BIT(8) 3013 #define RCC_PLLxCFGR1_PLLRDY BIT(24) 3014 #define RCC_PLLxCFGR1_CKREFST BIT(28) 3015 3016 /* RCC_PLLxCFGR2 register fields */ 3017 #define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) 3018 #define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 3019 #define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) 3020 #define RCC_PLLxCFGR2_FBDIV_SHIFT 16 3021 3022 /* RCC_PLLxCFGR3 register fields */ 3023 #define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) 3024 #define RCC_PLLxCFGR3_FRACIN_SHIFT 0 3025 #define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) 3026 #define RCC_PLLxCFGR3_DACEN BIT(25) 3027 #define RCC_PLLxCFGR3_SSCGDIS BIT(26) 3028 3029 /* RCC_PLLxCFGR4 register fields */ 3030 #define RCC_PLLxCFGR4_DSMEN BIT(8) 3031 #define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) 3032 #define RCC_PLLxCFGR4_BYPASS BIT(10) 3033 3034 /* RCC_PLLxCFGR5 register fields */ 3035 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) 3036 #define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 3037 #define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) 3038 #define RCC_PLLxCFGR5_SPREAD_SHIFT 16 3039 3040 /* RCC_PLLxCFGR6 register fields */ 3041 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 3042 #define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 3043 3044 /* RCC_PLLxCFGR7 register fields */ 3045 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 3046 #define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 3047 3048 /* RCC_HSIFMONCR register fields */ 3049 #define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) 3050 #define RCC_HSIFMONCR_HSIREF_SHIFT 0 3051 #define RCC_HSIFMONCR_HSIMONEN BIT(15) 3052 #define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) 3053 #define RCC_HSIFMONCR_HSIDEV_SHIFT 16 3054 #define RCC_HSIFMONCR_HSIMONIE BIT(30) 3055 #define RCC_HSIFMONCR_HSIMONF BIT(31) 3056 3057 /* RCC_HSIFVALR register fields */ 3058 #define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) 3059 #define RCC_HSIFVALR_HSIVAL_SHIFT 0 3060 3061 /* RCC_TIM1CFGR register fields */ 3062 #define RCC_TIM1CFGR_TIM1RST BIT(0) 3063 #define RCC_TIM1CFGR_TIM1EN BIT(1) 3064 #define RCC_TIM1CFGR_TIM1LPEN BIT(2) 3065 3066 /* RCC_TIM2CFGR register fields */ 3067 #define RCC_TIM2CFGR_TIM2RST BIT(0) 3068 #define RCC_TIM2CFGR_TIM2EN BIT(1) 3069 #define RCC_TIM2CFGR_TIM2LPEN BIT(2) 3070 3071 /* RCC_TIM3CFGR register fields */ 3072 #define RCC_TIM3CFGR_TIM3RST BIT(0) 3073 #define RCC_TIM3CFGR_TIM3EN BIT(1) 3074 #define RCC_TIM3CFGR_TIM3LPEN BIT(2) 3075 3076 /* RCC_TIM4CFGR register fields */ 3077 #define RCC_TIM4CFGR_TIM4RST BIT(0) 3078 #define RCC_TIM4CFGR_TIM4EN BIT(1) 3079 #define RCC_TIM4CFGR_TIM4LPEN BIT(2) 3080 3081 /* RCC_TIM5CFGR register fields */ 3082 #define RCC_TIM5CFGR_TIM5RST BIT(0) 3083 #define RCC_TIM5CFGR_TIM5EN BIT(1) 3084 #define RCC_TIM5CFGR_TIM5LPEN BIT(2) 3085 3086 /* RCC_TIM6CFGR register fields */ 3087 #define RCC_TIM6CFGR_TIM6RST BIT(0) 3088 #define RCC_TIM6CFGR_TIM6EN BIT(1) 3089 #define RCC_TIM6CFGR_TIM6LPEN BIT(2) 3090 3091 /* RCC_TIM7CFGR register fields */ 3092 #define RCC_TIM7CFGR_TIM7RST BIT(0) 3093 #define RCC_TIM7CFGR_TIM7EN BIT(1) 3094 #define RCC_TIM7CFGR_TIM7LPEN BIT(2) 3095 3096 /* RCC_TIM8CFGR register fields */ 3097 #define RCC_TIM8CFGR_TIM8RST BIT(0) 3098 #define RCC_TIM8CFGR_TIM8EN BIT(1) 3099 #define RCC_TIM8CFGR_TIM8LPEN BIT(2) 3100 3101 /* RCC_TIM10CFGR register fields */ 3102 #define RCC_TIM10CFGR_TIM10RST BIT(0) 3103 #define RCC_TIM10CFGR_TIM10EN BIT(1) 3104 #define RCC_TIM10CFGR_TIM10LPEN BIT(2) 3105 3106 /* RCC_TIM11CFGR register fields */ 3107 #define RCC_TIM11CFGR_TIM11RST BIT(0) 3108 #define RCC_TIM11CFGR_TIM11EN BIT(1) 3109 #define RCC_TIM11CFGR_TIM11LPEN BIT(2) 3110 3111 /* RCC_TIM12CFGR register fields */ 3112 #define RCC_TIM12CFGR_TIM12RST BIT(0) 3113 #define RCC_TIM12CFGR_TIM12EN BIT(1) 3114 #define RCC_TIM12CFGR_TIM12LPEN BIT(2) 3115 3116 /* RCC_TIM13CFGR register fields */ 3117 #define RCC_TIM13CFGR_TIM13RST BIT(0) 3118 #define RCC_TIM13CFGR_TIM13EN BIT(1) 3119 #define RCC_TIM13CFGR_TIM13LPEN BIT(2) 3120 3121 /* RCC_TIM14CFGR register fields */ 3122 #define RCC_TIM14CFGR_TIM14RST BIT(0) 3123 #define RCC_TIM14CFGR_TIM14EN BIT(1) 3124 #define RCC_TIM14CFGR_TIM14LPEN BIT(2) 3125 3126 /* RCC_TIM15CFGR register fields */ 3127 #define RCC_TIM15CFGR_TIM15RST BIT(0) 3128 #define RCC_TIM15CFGR_TIM15EN BIT(1) 3129 #define RCC_TIM15CFGR_TIM15LPEN BIT(2) 3130 3131 /* RCC_TIM16CFGR register fields */ 3132 #define RCC_TIM16CFGR_TIM16RST BIT(0) 3133 #define RCC_TIM16CFGR_TIM16EN BIT(1) 3134 #define RCC_TIM16CFGR_TIM16LPEN BIT(2) 3135 3136 /* RCC_TIM17CFGR register fields */ 3137 #define RCC_TIM17CFGR_TIM17RST BIT(0) 3138 #define RCC_TIM17CFGR_TIM17EN BIT(1) 3139 #define RCC_TIM17CFGR_TIM17LPEN BIT(2) 3140 3141 /* RCC_TIM20CFGR register fields */ 3142 #define RCC_TIM20CFGR_TIM20RST BIT(0) 3143 #define RCC_TIM20CFGR_TIM20EN BIT(1) 3144 #define RCC_TIM20CFGR_TIM20LPEN BIT(2) 3145 3146 /* RCC_LPTIM1CFGR register fields */ 3147 #define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) 3148 #define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) 3149 #define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) 3150 3151 /* RCC_LPTIM2CFGR register fields */ 3152 #define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) 3153 #define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) 3154 #define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) 3155 3156 /* RCC_LPTIM3CFGR register fields */ 3157 #define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) 3158 #define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) 3159 #define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) 3160 #define RCC_LPTIM3CFGR_LPTIM3AMEN BIT(3) 3161 3162 /* RCC_LPTIM4CFGR register fields */ 3163 #define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) 3164 #define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) 3165 #define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) 3166 #define RCC_LPTIM4CFGR_LPTIM4AMEN BIT(3) 3167 3168 /* RCC_LPTIM5CFGR register fields */ 3169 #define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) 3170 #define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) 3171 #define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) 3172 #define RCC_LPTIM5CFGR_LPTIM5AMEN BIT(3) 3173 3174 /* RCC_LPTIMxCFGR register fields */ 3175 #define RCC_LPTIMxCFGR_LPTIMxRST BIT(0) 3176 #define RCC_LPTIMxCFGR_LPTIMxEN BIT(1) 3177 #define RCC_LPTIMxCFGR_LPTIMxLPEN BIT(2) 3178 #define RCC_LPTIMxCFGR_LPTIMxAMEN BIT(3) 3179 3180 /* RCC_SPI1CFGR register fields */ 3181 #define RCC_SPI1CFGR_SPI1RST BIT(0) 3182 #define RCC_SPI1CFGR_SPI1EN BIT(1) 3183 #define RCC_SPI1CFGR_SPI1LPEN BIT(2) 3184 3185 /* RCC_SPI2CFGR register fields */ 3186 #define RCC_SPI2CFGR_SPI2RST BIT(0) 3187 #define RCC_SPI2CFGR_SPI2EN BIT(1) 3188 #define RCC_SPI2CFGR_SPI2LPEN BIT(2) 3189 3190 /* RCC_SPI3CFGR register fields */ 3191 #define RCC_SPI3CFGR_SPI3RST BIT(0) 3192 #define RCC_SPI3CFGR_SPI3EN BIT(1) 3193 #define RCC_SPI3CFGR_SPI3LPEN BIT(2) 3194 3195 /* RCC_SPI4CFGR register fields */ 3196 #define RCC_SPI4CFGR_SPI4RST BIT(0) 3197 #define RCC_SPI4CFGR_SPI4EN BIT(1) 3198 #define RCC_SPI4CFGR_SPI4LPEN BIT(2) 3199 3200 /* RCC_SPI5CFGR register fields */ 3201 #define RCC_SPI5CFGR_SPI5RST BIT(0) 3202 #define RCC_SPI5CFGR_SPI5EN BIT(1) 3203 #define RCC_SPI5CFGR_SPI5LPEN BIT(2) 3204 3205 /* RCC_SPI6CFGR register fields */ 3206 #define RCC_SPI6CFGR_SPI6RST BIT(0) 3207 #define RCC_SPI6CFGR_SPI6EN BIT(1) 3208 #define RCC_SPI6CFGR_SPI6LPEN BIT(2) 3209 3210 /* RCC_SPI7CFGR register fields */ 3211 #define RCC_SPI7CFGR_SPI7RST BIT(0) 3212 #define RCC_SPI7CFGR_SPI7EN BIT(1) 3213 #define RCC_SPI7CFGR_SPI7LPEN BIT(2) 3214 3215 /* RCC_SPI8CFGR register fields */ 3216 #define RCC_SPI8CFGR_SPI8RST BIT(0) 3217 #define RCC_SPI8CFGR_SPI8EN BIT(1) 3218 #define RCC_SPI8CFGR_SPI8LPEN BIT(2) 3219 #define RCC_SPI8CFGR_SPI8AMEN BIT(3) 3220 3221 /* RCC_SPIxCFGR register fields */ 3222 #define RCC_SPIxCFGR_SPIxRST BIT(0) 3223 #define RCC_SPIxCFGR_SPIxEN BIT(1) 3224 #define RCC_SPIxCFGR_SPIxLPEN BIT(2) 3225 #define RCC_SPIxCFGR_SPIxAMEN BIT(3) 3226 3227 /* RCC_SPDIFRXCFGR register fields */ 3228 #define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) 3229 #define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) 3230 #define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) 3231 3232 /* RCC_USART1CFGR register fields */ 3233 #define RCC_USART1CFGR_USART1RST BIT(0) 3234 #define RCC_USART1CFGR_USART1EN BIT(1) 3235 #define RCC_USART1CFGR_USART1LPEN BIT(2) 3236 3237 /* RCC_USART2CFGR register fields */ 3238 #define RCC_USART2CFGR_USART2RST BIT(0) 3239 #define RCC_USART2CFGR_USART2EN BIT(1) 3240 #define RCC_USART2CFGR_USART2LPEN BIT(2) 3241 3242 /* RCC_USART3CFGR register fields */ 3243 #define RCC_USART3CFGR_USART3RST BIT(0) 3244 #define RCC_USART3CFGR_USART3EN BIT(1) 3245 #define RCC_USART3CFGR_USART3LPEN BIT(2) 3246 3247 /* RCC_UART4CFGR register fields */ 3248 #define RCC_UART4CFGR_UART4RST BIT(0) 3249 #define RCC_UART4CFGR_UART4EN BIT(1) 3250 #define RCC_UART4CFGR_UART4LPEN BIT(2) 3251 3252 /* RCC_UART5CFGR register fields */ 3253 #define RCC_UART5CFGR_UART5RST BIT(0) 3254 #define RCC_UART5CFGR_UART5EN BIT(1) 3255 #define RCC_UART5CFGR_UART5LPEN BIT(2) 3256 3257 /* RCC_USART6CFGR register fields */ 3258 #define RCC_USART6CFGR_USART6RST BIT(0) 3259 #define RCC_USART6CFGR_USART6EN BIT(1) 3260 #define RCC_USART6CFGR_USART6LPEN BIT(2) 3261 3262 /* RCC_UART7CFGR register fields */ 3263 #define RCC_UART7CFGR_UART7RST BIT(0) 3264 #define RCC_UART7CFGR_UART7EN BIT(1) 3265 #define RCC_UART7CFGR_UART7LPEN BIT(2) 3266 3267 /* RCC_UART8CFGR register fields */ 3268 #define RCC_UART8CFGR_UART8RST BIT(0) 3269 #define RCC_UART8CFGR_UART8EN BIT(1) 3270 #define RCC_UART8CFGR_UART8LPEN BIT(2) 3271 3272 /* RCC_UART9CFGR register fields */ 3273 #define RCC_UART9CFGR_UART9RST BIT(0) 3274 #define RCC_UART9CFGR_UART9EN BIT(1) 3275 #define RCC_UART9CFGR_UART9LPEN BIT(2) 3276 3277 /* RCC_USARTxCFGR register fields */ 3278 #define RCC_USARTxCFGR_USARTxRST BIT(0) 3279 #define RCC_USARTxCFGR_USARTxEN BIT(1) 3280 #define RCC_USARTxCFGR_USARTxLPEN BIT(2) 3281 3282 /* RCC_UARTxCFGR register fields */ 3283 #define RCC_UARTxCFGR_UARTxRST BIT(0) 3284 #define RCC_UARTxCFGR_UARTxEN BIT(1) 3285 #define RCC_UARTxCFGR_UARTxLPEN BIT(2) 3286 3287 /* RCC_LPUART1CFGR register fields */ 3288 #define RCC_LPUART1CFGR_LPUART1RST BIT(0) 3289 #define RCC_LPUART1CFGR_LPUART1EN BIT(1) 3290 #define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) 3291 #define RCC_LPUART1CFGR_LPUART1AMEN BIT(3) 3292 3293 /* RCC_I2C1CFGR register fields */ 3294 #define RCC_I2C1CFGR_I2C1RST BIT(0) 3295 #define RCC_I2C1CFGR_I2C1EN BIT(1) 3296 #define RCC_I2C1CFGR_I2C1LPEN BIT(2) 3297 3298 /* RCC_I2C2CFGR register fields */ 3299 #define RCC_I2C2CFGR_I2C2RST BIT(0) 3300 #define RCC_I2C2CFGR_I2C2EN BIT(1) 3301 #define RCC_I2C2CFGR_I2C2LPEN BIT(2) 3302 3303 /* RCC_I2C3CFGR register fields */ 3304 #define RCC_I2C3CFGR_I2C3RST BIT(0) 3305 #define RCC_I2C3CFGR_I2C3EN BIT(1) 3306 #define RCC_I2C3CFGR_I2C3LPEN BIT(2) 3307 3308 /* RCC_I2C4CFGR register fields */ 3309 #define RCC_I2C4CFGR_I2C4RST BIT(0) 3310 #define RCC_I2C4CFGR_I2C4EN BIT(1) 3311 #define RCC_I2C4CFGR_I2C4LPEN BIT(2) 3312 3313 /* RCC_I2C5CFGR register fields */ 3314 #define RCC_I2C5CFGR_I2C5RST BIT(0) 3315 #define RCC_I2C5CFGR_I2C5EN BIT(1) 3316 #define RCC_I2C5CFGR_I2C5LPEN BIT(2) 3317 3318 /* RCC_I2C6CFGR register fields */ 3319 #define RCC_I2C6CFGR_I2C6RST BIT(0) 3320 #define RCC_I2C6CFGR_I2C6EN BIT(1) 3321 #define RCC_I2C6CFGR_I2C6LPEN BIT(2) 3322 3323 /* RCC_I2C7CFGR register fields */ 3324 #define RCC_I2C7CFGR_I2C7RST BIT(0) 3325 #define RCC_I2C7CFGR_I2C7EN BIT(1) 3326 #define RCC_I2C7CFGR_I2C7LPEN BIT(2) 3327 3328 /* RCC_I2C8CFGR register fields */ 3329 #define RCC_I2C8CFGR_I2C8RST BIT(0) 3330 #define RCC_I2C8CFGR_I2C8EN BIT(1) 3331 #define RCC_I2C8CFGR_I2C8LPEN BIT(2) 3332 #define RCC_I2C8CFGR_I2C8AMEN BIT(3) 3333 3334 /* RCC_I2CxCFGR register fields */ 3335 #define RCC_I2CxCFGR_I2CxRST BIT(0) 3336 #define RCC_I2CxCFGR_I2CxEN BIT(1) 3337 #define RCC_I2CxCFGR_I2CxLPEN BIT(2) 3338 #define RCC_I2CxCFGR_I2CxAMEN BIT(3) 3339 3340 /* RCC_SAI1CFGR register fields */ 3341 #define RCC_SAI1CFGR_SAI1RST BIT(0) 3342 #define RCC_SAI1CFGR_SAI1EN BIT(1) 3343 #define RCC_SAI1CFGR_SAI1LPEN BIT(2) 3344 3345 /* RCC_SAI2CFGR register fields */ 3346 #define RCC_SAI2CFGR_SAI2RST BIT(0) 3347 #define RCC_SAI2CFGR_SAI2EN BIT(1) 3348 #define RCC_SAI2CFGR_SAI2LPEN BIT(2) 3349 3350 /* RCC_SAI3CFGR register fields */ 3351 #define RCC_SAI3CFGR_SAI3RST BIT(0) 3352 #define RCC_SAI3CFGR_SAI3EN BIT(1) 3353 #define RCC_SAI3CFGR_SAI3LPEN BIT(2) 3354 3355 /* RCC_SAI4CFGR register fields */ 3356 #define RCC_SAI4CFGR_SAI4RST BIT(0) 3357 #define RCC_SAI4CFGR_SAI4EN BIT(1) 3358 #define RCC_SAI4CFGR_SAI4LPEN BIT(2) 3359 3360 /* RCC_SAIxCFGR register fields */ 3361 #define RCC_SAIxCFGR_SAIxRST BIT(0) 3362 #define RCC_SAIxCFGR_SAIxEN BIT(1) 3363 #define RCC_SAIxCFGR_SAIxLPEN BIT(2) 3364 3365 /* RCC_MDF1CFGR register fields */ 3366 #define RCC_MDF1CFGR_MDF1RST BIT(0) 3367 #define RCC_MDF1CFGR_MDF1EN BIT(1) 3368 #define RCC_MDF1CFGR_MDF1LPEN BIT(2) 3369 3370 /* RCC_ADF1CFGR register fields */ 3371 #define RCC_ADF1CFGR_ADF1RST BIT(0) 3372 #define RCC_ADF1CFGR_ADF1EN BIT(1) 3373 #define RCC_ADF1CFGR_ADF1LPEN BIT(2) 3374 #define RCC_ADF1CFGR_ADF1AMEN BIT(3) 3375 3376 /* RCC_FDCANCFGR register fields */ 3377 #define RCC_FDCANCFGR_FDCANRST BIT(0) 3378 #define RCC_FDCANCFGR_FDCANEN BIT(1) 3379 #define RCC_FDCANCFGR_FDCANLPEN BIT(2) 3380 3381 /* RCC_HDPCFGR register fields */ 3382 #define RCC_HDPCFGR_HDPRST BIT(0) 3383 #define RCC_HDPCFGR_HDPEN BIT(1) 3384 3385 /* RCC_ADC12CFGR register fields */ 3386 #define RCC_ADC12CFGR_ADC12RST BIT(0) 3387 #define RCC_ADC12CFGR_ADC12EN BIT(1) 3388 #define RCC_ADC12CFGR_ADC12LPEN BIT(2) 3389 #define RCC_ADC12CFGR_ADC12KERSEL BIT(12) 3390 3391 /* RCC_ADC3CFGR register fields */ 3392 #define RCC_ADC3CFGR_ADC3RST BIT(0) 3393 #define RCC_ADC3CFGR_ADC3EN BIT(1) 3394 #define RCC_ADC3CFGR_ADC3LPEN BIT(2) 3395 #define RCC_ADC3CFGR_ADC3KERSEL_MASK GENMASK_32(13, 12) 3396 #define RCC_ADC3CFGR_ADC3KERSEL_SHIFT 12 3397 3398 /* RCC_ETH1CFGR register fields */ 3399 #define RCC_ETH1CFGR_ETH1RST BIT(0) 3400 #define RCC_ETH1CFGR_ETH1MACEN BIT(1) 3401 #define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) 3402 #define RCC_ETH1CFGR_ETH1STPEN BIT(4) 3403 #define RCC_ETH1CFGR_ETH1EN BIT(5) 3404 #define RCC_ETH1CFGR_ETH1LPEN BIT(6) 3405 #define RCC_ETH1CFGR_ETH1TXEN BIT(8) 3406 #define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) 3407 #define RCC_ETH1CFGR_ETH1RXEN BIT(10) 3408 #define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) 3409 3410 /* RCC_ETH2CFGR register fields */ 3411 #define RCC_ETH2CFGR_ETH2RST BIT(0) 3412 #define RCC_ETH2CFGR_ETH2MACEN BIT(1) 3413 #define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) 3414 #define RCC_ETH2CFGR_ETH2STPEN BIT(4) 3415 #define RCC_ETH2CFGR_ETH2EN BIT(5) 3416 #define RCC_ETH2CFGR_ETH2LPEN BIT(6) 3417 #define RCC_ETH2CFGR_ETH2TXEN BIT(8) 3418 #define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) 3419 #define RCC_ETH2CFGR_ETH2RXEN BIT(10) 3420 #define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) 3421 3422 /* RCC_ETHxCFGR register fields */ 3423 #define RCC_ETHxCFGR_ETHxRST BIT(0) 3424 #define RCC_ETHxCFGR_ETHxMACEN BIT(1) 3425 #define RCC_ETHxCFGR_ETHxMACLPEN BIT(2) 3426 #define RCC_ETHxCFGR_ETHxSTPEN BIT(4) 3427 #define RCC_ETHxCFGR_ETHxEN BIT(5) 3428 #define RCC_ETHxCFGR_ETHxLPEN BIT(6) 3429 #define RCC_ETHxCFGR_ETHxTXEN BIT(8) 3430 #define RCC_ETHxCFGR_ETHxTXLPEN BIT(9) 3431 #define RCC_ETHxCFGR_ETHxRXEN BIT(10) 3432 #define RCC_ETHxCFGR_ETHxRXLPEN BIT(11) 3433 3434 /* RCC_USB2CFGR register fields */ 3435 #define RCC_USB2CFGR_USB2RST BIT(0) 3436 #define RCC_USB2CFGR_USB2EN BIT(1) 3437 #define RCC_USB2CFGR_USB2LPEN BIT(2) 3438 #define RCC_USB2CFGR_USB2STPEN BIT(4) 3439 3440 /* RCC_USB2PHY1CFGR register fields */ 3441 #define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) 3442 #define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) 3443 #define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) 3444 #define RCC_USB2PHY1CFGR_USB2PHY1STPEN BIT(4) 3445 #define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) 3446 3447 /* RCC_USB2PHY2CFGR register fields */ 3448 #define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) 3449 #define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) 3450 #define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) 3451 #define RCC_USB2PHY2CFGR_USB2PHY2STPEN BIT(4) 3452 #define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) 3453 3454 /* RCC_USB2PHYxCFGR register fields */ 3455 #define RCC_USB2PHYxCFGR_USB2PHY1RST BIT(0) 3456 #define RCC_USB2PHYxCFGR_USB2PHY1EN BIT(1) 3457 #define RCC_USB2PHYxCFGR_USB2PHY1LPEN BIT(2) 3458 #define RCC_USB2PHYxCFGR_USB2PHY1STPEN BIT(4) 3459 #define RCC_USB2PHYxCFGR_USB2PHY1CKREFSEL BIT(15) 3460 3461 /* RCC_USB3DRDCFGR register fields */ 3462 #define RCC_USB3DRDCFGR_USB3DRDRST BIT(0) 3463 #define RCC_USB3DRDCFGR_USB3DRDEN BIT(1) 3464 #define RCC_USB3DRDCFGR_USB3DRDLPEN BIT(2) 3465 #define RCC_USB3DRDCFGR_USB3DRDSTPEN BIT(4) 3466 3467 /* RCC_USB3PCIEPHYCFGR register fields */ 3468 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYRST BIT(0) 3469 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYEN BIT(1) 3470 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYLPEN BIT(2) 3471 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYSTPEN BIT(4) 3472 #define RCC_USB3PCIEPHYCFGR_USB3PCIEPHYCKREFSEL BIT(15) 3473 3474 /* RCC_PCIECFGR register fields */ 3475 #define RCC_PCIECFGR_PCIERST BIT(0) 3476 #define RCC_PCIECFGR_PCIEEN BIT(1) 3477 #define RCC_PCIECFGR_PCIELPEN BIT(2) 3478 #define RCC_PCIECFGR_PCIESTPEN BIT(4) 3479 3480 /* RCC_USBTCCFGR register fields */ 3481 #define RCC_USBTCCFGR_USBTCRST BIT(0) 3482 #define RCC_USBTCCFGR_USBTCEN BIT(1) 3483 #define RCC_USBTCCFGR_USBTCLPEN BIT(2) 3484 3485 /* RCC_ETHSWCFGR register fields */ 3486 #define RCC_ETHSWCFGR_ETHSWRST BIT(0) 3487 #define RCC_ETHSWCFGR_ETHSWMACEN BIT(1) 3488 #define RCC_ETHSWCFGR_ETHSWMACLPEN BIT(2) 3489 #define RCC_ETHSWCFGR_ETHSWEN BIT(5) 3490 #define RCC_ETHSWCFGR_ETHSWLPEN BIT(6) 3491 #define RCC_ETHSWCFGR_ETHSWREFEN BIT(21) 3492 #define RCC_ETHSWCFGR_ETHSWREFLPEN BIT(22) 3493 3494 /* RCC_ETHSWACMCFGR register fields */ 3495 #define RCC_ETHSWACMCFGR_ETHSWACMEN BIT(1) 3496 #define RCC_ETHSWACMCFGR_ETHSWACMLPEN BIT(2) 3497 3498 /* RCC_ETHSWACMMSGCFGR register fields */ 3499 #define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGEN BIT(1) 3500 #define RCC_ETHSWACMMSGCFGR_ETHSWACMMSGLPEN BIT(2) 3501 3502 /* RCC_STGENCFGR register fields */ 3503 #define RCC_STGENCFGR_STGENEN BIT(1) 3504 #define RCC_STGENCFGR_STGENLPEN BIT(2) 3505 #define RCC_STGENCFGR_STGENSTPEN BIT(4) 3506 3507 /* RCC_SDMMC1CFGR register fields */ 3508 #define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) 3509 #define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) 3510 #define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) 3511 #define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) 3512 3513 /* RCC_SDMMC2CFGR register fields */ 3514 #define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) 3515 #define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) 3516 #define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) 3517 #define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) 3518 3519 /* RCC_SDMMC3CFGR register fields */ 3520 #define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) 3521 #define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) 3522 #define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) 3523 #define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) 3524 3525 /* RCC_SDMMCxCFGR register fields */ 3526 #define RCC_SDMMCxCFGR_SDMMC1RST BIT(0) 3527 #define RCC_SDMMCxCFGR_SDMMC1EN BIT(1) 3528 #define RCC_SDMMCxCFGR_SDMMC1LPEN BIT(2) 3529 #define RCC_SDMMCxCFGR_SDMMC1DLLRST BIT(16) 3530 3531 /* RCC_GPUCFGR register fields */ 3532 #define RCC_GPUCFGR_GPURST BIT(0) 3533 #define RCC_GPUCFGR_GPUEN BIT(1) 3534 #define RCC_GPUCFGR_GPULPEN BIT(2) 3535 3536 /* RCC_LTDCCFGR register fields */ 3537 #define RCC_LTDCCFGR_LTDCRST BIT(0) 3538 #define RCC_LTDCCFGR_LTDCEN BIT(1) 3539 #define RCC_LTDCCFGR_LTDCLPEN BIT(2) 3540 3541 /* RCC_DSICFGR register fields */ 3542 #define RCC_DSICFGR_DSIRST BIT(0) 3543 #define RCC_DSICFGR_DSIEN BIT(1) 3544 #define RCC_DSICFGR_DSILPEN BIT(2) 3545 #define RCC_DSICFGR_DSIBLSEL BIT(12) 3546 #define RCC_DSICFGR_DSIPHYCKREFSEL BIT(15) 3547 3548 /* RCC_LVDSCFGR register fields */ 3549 #define RCC_LVDSCFGR_LVDSRST BIT(0) 3550 #define RCC_LVDSCFGR_LVDSEN BIT(1) 3551 #define RCC_LVDSCFGR_LVDSLPEN BIT(2) 3552 #define RCC_LVDSCFGR_LVDSPHYCKREFSEL BIT(15) 3553 3554 /* RCC_CSI2CFGR register fields */ 3555 #define RCC_CSI2CFGR_CSI2RST BIT(0) 3556 #define RCC_CSI2CFGR_CSI2EN BIT(1) 3557 #define RCC_CSI2CFGR_CSI2LPEN BIT(2) 3558 3559 /* RCC_DCMIPPCFGR register fields */ 3560 #define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) 3561 #define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) 3562 #define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) 3563 3564 /* RCC_CCICFGR register fields */ 3565 #define RCC_CCICFGR_CCIRST BIT(0) 3566 #define RCC_CCICFGR_CCIEN BIT(1) 3567 #define RCC_CCICFGR_CCILPEN BIT(2) 3568 3569 /* RCC_VDECCFGR register fields */ 3570 #define RCC_VDECCFGR_VDECRST BIT(0) 3571 #define RCC_VDECCFGR_VDECEN BIT(1) 3572 #define RCC_VDECCFGR_VDECLPEN BIT(2) 3573 3574 /* RCC_VENCCFGR register fields */ 3575 #define RCC_VENCCFGR_VENCRST BIT(0) 3576 #define RCC_VENCCFGR_VENCEN BIT(1) 3577 #define RCC_VENCCFGR_VENCLPEN BIT(2) 3578 3579 /* RCC_RNGCFGR register fields */ 3580 #define RCC_RNGCFGR_RNGRST BIT(0) 3581 #define RCC_RNGCFGR_RNGEN BIT(1) 3582 #define RCC_RNGCFGR_RNGLPEN BIT(2) 3583 3584 /* RCC_PKACFGR register fields */ 3585 #define RCC_PKACFGR_PKARST BIT(0) 3586 #define RCC_PKACFGR_PKAEN BIT(1) 3587 #define RCC_PKACFGR_PKALPEN BIT(2) 3588 3589 /* RCC_SAESCFGR register fields */ 3590 #define RCC_SAESCFGR_SAESRST BIT(0) 3591 #define RCC_SAESCFGR_SAESEN BIT(1) 3592 #define RCC_SAESCFGR_SAESLPEN BIT(2) 3593 3594 /* RCC_HASHCFGR register fields */ 3595 #define RCC_HASHCFGR_HASHRST BIT(0) 3596 #define RCC_HASHCFGR_HASHEN BIT(1) 3597 #define RCC_HASHCFGR_HASHLPEN BIT(2) 3598 3599 /* RCC_CRYP1CFGR register fields */ 3600 #define RCC_CRYP1CFGR_CRYP1RST BIT(0) 3601 #define RCC_CRYP1CFGR_CRYP1EN BIT(1) 3602 #define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) 3603 3604 /* RCC_CRYP2CFGR register fields */ 3605 #define RCC_CRYP2CFGR_CRYP2RST BIT(0) 3606 #define RCC_CRYP2CFGR_CRYP2EN BIT(1) 3607 #define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) 3608 3609 /* RCC_CRYPxCFGR register fields */ 3610 #define RCC_CRYPxCFGR_CRYPxRST BIT(0) 3611 #define RCC_CRYPxCFGR_CRYPxEN BIT(1) 3612 #define RCC_CRYPxCFGR_CRYPxLPEN BIT(2) 3613 3614 /* RCC_IWDG1CFGR register fields */ 3615 #define RCC_IWDG1CFGR_IWDG1EN BIT(1) 3616 #define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) 3617 3618 /* RCC_IWDG2CFGR register fields */ 3619 #define RCC_IWDG2CFGR_IWDG2EN BIT(1) 3620 #define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) 3621 3622 /* RCC_IWDG3CFGR register fields */ 3623 #define RCC_IWDG3CFGR_IWDG3EN BIT(1) 3624 #define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) 3625 3626 /* RCC_IWDG4CFGR register fields */ 3627 #define RCC_IWDG4CFGR_IWDG4EN BIT(1) 3628 #define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) 3629 3630 /* RCC_IWDGxCFGR register fields */ 3631 #define RCC_IWDGxCFGR_IWDGxEN BIT(1) 3632 #define RCC_IWDGxCFGR_IWDGxLPEN BIT(2) 3633 3634 /* RCC_IWDG5CFGR register fields */ 3635 #define RCC_IWDG5CFGR_IWDG5EN BIT(1) 3636 #define RCC_IWDG5CFGR_IWDG5LPEN BIT(2) 3637 #define RCC_IWDG5CFGR_IWDG5AMEN BIT(3) 3638 3639 /* RCC_WWDG1CFGR register fields */ 3640 #define RCC_WWDG1CFGR_WWDG1RST BIT(0) 3641 #define RCC_WWDG1CFGR_WWDG1EN BIT(1) 3642 #define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) 3643 3644 /* RCC_WWDG2CFGR register fields */ 3645 #define RCC_WWDG2CFGR_WWDG2RST BIT(0) 3646 #define RCC_WWDG2CFGR_WWDG2EN BIT(1) 3647 #define RCC_WWDG2CFGR_WWDG2LPEN BIT(2) 3648 #define RCC_WWDG2CFGR_WWDG2AMEN BIT(3) 3649 3650 /* RCC_BUSPERFMCFGR register fields */ 3651 #define RCC_BUSPERFMCFGR_BUSPERFMRST BIT(0) 3652 #define RCC_BUSPERFMCFGR_BUSPERFMEN BIT(1) 3653 #define RCC_BUSPERFMCFGR_BUSPERFMLPEN BIT(2) 3654 3655 /* RCC_VREFCFGR register fields */ 3656 #define RCC_VREFCFGR_VREFRST BIT(0) 3657 #define RCC_VREFCFGR_VREFEN BIT(1) 3658 #define RCC_VREFCFGR_VREFLPEN BIT(2) 3659 3660 /* RCC_TMPSENSCFGR register fields */ 3661 #define RCC_TMPSENSCFGR_TMPSENSRST BIT(0) 3662 #define RCC_TMPSENSCFGR_TMPSENSEN BIT(1) 3663 #define RCC_TMPSENSCFGR_TMPSENSLPEN BIT(2) 3664 #define RCC_TMPSENSCFGR_TMPSENSKERSEL_MASK GENMASK_32(13, 12) 3665 #define RCC_TMPSENSCFGR_TMPSENSKERSEL_SHIFT 12 3666 3667 /* RCC_CRCCFGR register fields */ 3668 #define RCC_CRCCFGR_CRCRST BIT(0) 3669 #define RCC_CRCCFGR_CRCEN BIT(1) 3670 #define RCC_CRCCFGR_CRCLPEN BIT(2) 3671 3672 /* RCC_SERCCFGR register fields */ 3673 #define RCC_SERCCFGR_SERCRST BIT(0) 3674 #define RCC_SERCCFGR_SERCEN BIT(1) 3675 #define RCC_SERCCFGR_SERCLPEN BIT(2) 3676 3677 /* RCC_OSPIIOMCFGR register fields */ 3678 #define RCC_OSPIIOMCFGR_OSPIIOMRST BIT(0) 3679 #define RCC_OSPIIOMCFGR_OSPIIOMEN BIT(1) 3680 #define RCC_OSPIIOMCFGR_OSPIIOMLPEN BIT(2) 3681 3682 /* RCC_GICV2MCFGR register fields */ 3683 #define RCC_GICV2MCFGR_GICV2MEN BIT(1) 3684 #define RCC_GICV2MCFGR_GICV2MLPEN BIT(2) 3685 3686 /* RCC_I3C1CFGR register fields */ 3687 #define RCC_I3C1CFGR_I3C1RST BIT(0) 3688 #define RCC_I3C1CFGR_I3C1EN BIT(1) 3689 #define RCC_I3C1CFGR_I3C1LPEN BIT(2) 3690 3691 /* RCC_I3C2CFGR register fields */ 3692 #define RCC_I3C2CFGR_I3C2RST BIT(0) 3693 #define RCC_I3C2CFGR_I3C2EN BIT(1) 3694 #define RCC_I3C2CFGR_I3C2LPEN BIT(2) 3695 3696 /* RCC_I3C3CFGR register fields */ 3697 #define RCC_I3C3CFGR_I3C3RST BIT(0) 3698 #define RCC_I3C3CFGR_I3C3EN BIT(1) 3699 #define RCC_I3C3CFGR_I3C3LPEN BIT(2) 3700 3701 /* RCC_I3C4CFGR register fields */ 3702 #define RCC_I3C4CFGR_I3C4RST BIT(0) 3703 #define RCC_I3C4CFGR_I3C4EN BIT(1) 3704 #define RCC_I3C4CFGR_I3C4LPEN BIT(2) 3705 #define RCC_I3C4CFGR_I3C4AMEN BIT(3) 3706 3707 /* RCC_I3CxCFGR register fields */ 3708 #define RCC_I3CxCFGR_I3CxRST BIT(0) 3709 #define RCC_I3CxCFGR_I3CxEN BIT(1) 3710 #define RCC_I3CxCFGR_I3CxLPEN BIT(2) 3711 #define RCC_I3CxCFGR_I3CxAMEN BIT(3) 3712 3713 /* RCC_MUXSELCFGR register fields */ 3714 #define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(1, 0) 3715 #define RCC_MUXSELCFGR_MUXSEL0_SHIFT 0 3716 #define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(5, 4) 3717 #define RCC_MUXSELCFGR_MUXSEL1_SHIFT 4 3718 #define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(9, 8) 3719 #define RCC_MUXSELCFGR_MUXSEL2_SHIFT 8 3720 #define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(13, 12) 3721 #define RCC_MUXSELCFGR_MUXSEL3_SHIFT 12 3722 #define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(17, 16) 3723 #define RCC_MUXSELCFGR_MUXSEL4_SHIFT 16 3724 #define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) 3725 #define RCC_MUXSELCFGR_MUXSEL5_SHIFT 20 3726 #define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) 3727 #define RCC_MUXSELCFGR_MUXSEL6_SHIFT 24 3728 #define RCC_MUXSELCFGR_MUXSEL7_MASK GENMASK_32(29, 28) 3729 #define RCC_MUXSELCFGR_MUXSEL7_SHIFT 28 3730 3731 /* RCC_XBAR0CFGR register fields */ 3732 #define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) 3733 #define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 3734 #define RCC_XBAR0CFGR_XBAR0EN BIT(6) 3735 #define RCC_XBAR0CFGR_XBAR0STS BIT(7) 3736 3737 /* RCC_XBAR1CFGR register fields */ 3738 #define RCC_XBAR1CFGR_XBAR1SEL_MASK GENMASK_32(3, 0) 3739 #define RCC_XBAR1CFGR_XBAR1SEL_SHIFT 0 3740 #define RCC_XBAR1CFGR_XBAR1EN BIT(6) 3741 #define RCC_XBAR1CFGR_XBAR1STS BIT(7) 3742 3743 /* RCC_XBAR2CFGR register fields */ 3744 #define RCC_XBAR2CFGR_XBAR2SEL_MASK GENMASK_32(3, 0) 3745 #define RCC_XBAR2CFGR_XBAR2SEL_SHIFT 0 3746 #define RCC_XBAR2CFGR_XBAR2EN BIT(6) 3747 #define RCC_XBAR2CFGR_XBAR2STS BIT(7) 3748 3749 /* RCC_XBAR3CFGR register fields */ 3750 #define RCC_XBAR3CFGR_XBAR3SEL_MASK GENMASK_32(3, 0) 3751 #define RCC_XBAR3CFGR_XBAR3SEL_SHIFT 0 3752 #define RCC_XBAR3CFGR_XBAR3EN BIT(6) 3753 #define RCC_XBAR3CFGR_XBAR3STS BIT(7) 3754 3755 /* RCC_XBAR4CFGR register fields */ 3756 #define RCC_XBAR4CFGR_XBAR4SEL_MASK GENMASK_32(3, 0) 3757 #define RCC_XBAR4CFGR_XBAR4SEL_SHIFT 0 3758 #define RCC_XBAR4CFGR_XBAR4EN BIT(6) 3759 #define RCC_XBAR4CFGR_XBAR4STS BIT(7) 3760 3761 /* RCC_XBAR5CFGR register fields */ 3762 #define RCC_XBAR5CFGR_XBAR5SEL_MASK GENMASK_32(3, 0) 3763 #define RCC_XBAR5CFGR_XBAR5SEL_SHIFT 0 3764 #define RCC_XBAR5CFGR_XBAR5EN BIT(6) 3765 #define RCC_XBAR5CFGR_XBAR5STS BIT(7) 3766 3767 /* RCC_XBAR6CFGR register fields */ 3768 #define RCC_XBAR6CFGR_XBAR6SEL_MASK GENMASK_32(3, 0) 3769 #define RCC_XBAR6CFGR_XBAR6SEL_SHIFT 0 3770 #define RCC_XBAR6CFGR_XBAR6EN BIT(6) 3771 #define RCC_XBAR6CFGR_XBAR6STS BIT(7) 3772 3773 /* RCC_XBAR7CFGR register fields */ 3774 #define RCC_XBAR7CFGR_XBAR7SEL_MASK GENMASK_32(3, 0) 3775 #define RCC_XBAR7CFGR_XBAR7SEL_SHIFT 0 3776 #define RCC_XBAR7CFGR_XBAR7EN BIT(6) 3777 #define RCC_XBAR7CFGR_XBAR7STS BIT(7) 3778 3779 /* RCC_XBAR8CFGR register fields */ 3780 #define RCC_XBAR8CFGR_XBAR8SEL_MASK GENMASK_32(3, 0) 3781 #define RCC_XBAR8CFGR_XBAR8SEL_SHIFT 0 3782 #define RCC_XBAR8CFGR_XBAR8EN BIT(6) 3783 #define RCC_XBAR8CFGR_XBAR8STS BIT(7) 3784 3785 /* RCC_XBAR9CFGR register fields */ 3786 #define RCC_XBAR9CFGR_XBAR9SEL_MASK GENMASK_32(3, 0) 3787 #define RCC_XBAR9CFGR_XBAR9SEL_SHIFT 0 3788 #define RCC_XBAR9CFGR_XBAR9EN BIT(6) 3789 #define RCC_XBAR9CFGR_XBAR9STS BIT(7) 3790 3791 /* RCC_XBAR10CFGR register fields */ 3792 #define RCC_XBAR10CFGR_XBAR10SEL_MASK GENMASK_32(3, 0) 3793 #define RCC_XBAR10CFGR_XBAR10SEL_SHIFT 0 3794 #define RCC_XBAR10CFGR_XBAR10EN BIT(6) 3795 #define RCC_XBAR10CFGR_XBAR10STS BIT(7) 3796 3797 /* RCC_XBAR11CFGR register fields */ 3798 #define RCC_XBAR11CFGR_XBAR11SEL_MASK GENMASK_32(3, 0) 3799 #define RCC_XBAR11CFGR_XBAR11SEL_SHIFT 0 3800 #define RCC_XBAR11CFGR_XBAR11EN BIT(6) 3801 #define RCC_XBAR11CFGR_XBAR11STS BIT(7) 3802 3803 /* RCC_XBAR12CFGR register fields */ 3804 #define RCC_XBAR12CFGR_XBAR12SEL_MASK GENMASK_32(3, 0) 3805 #define RCC_XBAR12CFGR_XBAR12SEL_SHIFT 0 3806 #define RCC_XBAR12CFGR_XBAR12EN BIT(6) 3807 #define RCC_XBAR12CFGR_XBAR12STS BIT(7) 3808 3809 /* RCC_XBAR13CFGR register fields */ 3810 #define RCC_XBAR13CFGR_XBAR13SEL_MASK GENMASK_32(3, 0) 3811 #define RCC_XBAR13CFGR_XBAR13SEL_SHIFT 0 3812 #define RCC_XBAR13CFGR_XBAR13EN BIT(6) 3813 #define RCC_XBAR13CFGR_XBAR13STS BIT(7) 3814 3815 /* RCC_XBAR14CFGR register fields */ 3816 #define RCC_XBAR14CFGR_XBAR14SEL_MASK GENMASK_32(3, 0) 3817 #define RCC_XBAR14CFGR_XBAR14SEL_SHIFT 0 3818 #define RCC_XBAR14CFGR_XBAR14EN BIT(6) 3819 #define RCC_XBAR14CFGR_XBAR14STS BIT(7) 3820 3821 /* RCC_XBAR15CFGR register fields */ 3822 #define RCC_XBAR15CFGR_XBAR15SEL_MASK GENMASK_32(3, 0) 3823 #define RCC_XBAR15CFGR_XBAR15SEL_SHIFT 0 3824 #define RCC_XBAR15CFGR_XBAR15EN BIT(6) 3825 #define RCC_XBAR15CFGR_XBAR15STS BIT(7) 3826 3827 /* RCC_XBAR16CFGR register fields */ 3828 #define RCC_XBAR16CFGR_XBAR16SEL_MASK GENMASK_32(3, 0) 3829 #define RCC_XBAR16CFGR_XBAR16SEL_SHIFT 0 3830 #define RCC_XBAR16CFGR_XBAR16EN BIT(6) 3831 #define RCC_XBAR16CFGR_XBAR16STS BIT(7) 3832 3833 /* RCC_XBAR17CFGR register fields */ 3834 #define RCC_XBAR17CFGR_XBAR17SEL_MASK GENMASK_32(3, 0) 3835 #define RCC_XBAR17CFGR_XBAR17SEL_SHIFT 0 3836 #define RCC_XBAR17CFGR_XBAR17EN BIT(6) 3837 #define RCC_XBAR17CFGR_XBAR17STS BIT(7) 3838 3839 /* RCC_XBAR18CFGR register fields */ 3840 #define RCC_XBAR18CFGR_XBAR18SEL_MASK GENMASK_32(3, 0) 3841 #define RCC_XBAR18CFGR_XBAR18SEL_SHIFT 0 3842 #define RCC_XBAR18CFGR_XBAR18EN BIT(6) 3843 #define RCC_XBAR18CFGR_XBAR18STS BIT(7) 3844 3845 /* RCC_XBAR19CFGR register fields */ 3846 #define RCC_XBAR19CFGR_XBAR19SEL_MASK GENMASK_32(3, 0) 3847 #define RCC_XBAR19CFGR_XBAR19SEL_SHIFT 0 3848 #define RCC_XBAR19CFGR_XBAR19EN BIT(6) 3849 #define RCC_XBAR19CFGR_XBAR19STS BIT(7) 3850 3851 /* RCC_XBAR20CFGR register fields */ 3852 #define RCC_XBAR20CFGR_XBAR20SEL_MASK GENMASK_32(3, 0) 3853 #define RCC_XBAR20CFGR_XBAR20SEL_SHIFT 0 3854 #define RCC_XBAR20CFGR_XBAR20EN BIT(6) 3855 #define RCC_XBAR20CFGR_XBAR20STS BIT(7) 3856 3857 /* RCC_XBAR21CFGR register fields */ 3858 #define RCC_XBAR21CFGR_XBAR21SEL_MASK GENMASK_32(3, 0) 3859 #define RCC_XBAR21CFGR_XBAR21SEL_SHIFT 0 3860 #define RCC_XBAR21CFGR_XBAR21EN BIT(6) 3861 #define RCC_XBAR21CFGR_XBAR21STS BIT(7) 3862 3863 /* RCC_XBAR22CFGR register fields */ 3864 #define RCC_XBAR22CFGR_XBAR22SEL_MASK GENMASK_32(3, 0) 3865 #define RCC_XBAR22CFGR_XBAR22SEL_SHIFT 0 3866 #define RCC_XBAR22CFGR_XBAR22EN BIT(6) 3867 #define RCC_XBAR22CFGR_XBAR22STS BIT(7) 3868 3869 /* RCC_XBAR23CFGR register fields */ 3870 #define RCC_XBAR23CFGR_XBAR23SEL_MASK GENMASK_32(3, 0) 3871 #define RCC_XBAR23CFGR_XBAR23SEL_SHIFT 0 3872 #define RCC_XBAR23CFGR_XBAR23EN BIT(6) 3873 #define RCC_XBAR23CFGR_XBAR23STS BIT(7) 3874 3875 /* RCC_XBAR24CFGR register fields */ 3876 #define RCC_XBAR24CFGR_XBAR24SEL_MASK GENMASK_32(3, 0) 3877 #define RCC_XBAR24CFGR_XBAR24SEL_SHIFT 0 3878 #define RCC_XBAR24CFGR_XBAR24EN BIT(6) 3879 #define RCC_XBAR24CFGR_XBAR24STS BIT(7) 3880 3881 /* RCC_XBAR25CFGR register fields */ 3882 #define RCC_XBAR25CFGR_XBAR25SEL_MASK GENMASK_32(3, 0) 3883 #define RCC_XBAR25CFGR_XBAR25SEL_SHIFT 0 3884 #define RCC_XBAR25CFGR_XBAR25EN BIT(6) 3885 #define RCC_XBAR25CFGR_XBAR25STS BIT(7) 3886 3887 /* RCC_XBAR26CFGR register fields */ 3888 #define RCC_XBAR26CFGR_XBAR26SEL_MASK GENMASK_32(3, 0) 3889 #define RCC_XBAR26CFGR_XBAR26SEL_SHIFT 0 3890 #define RCC_XBAR26CFGR_XBAR26EN BIT(6) 3891 #define RCC_XBAR26CFGR_XBAR26STS BIT(7) 3892 3893 /* RCC_XBAR27CFGR register fields */ 3894 #define RCC_XBAR27CFGR_XBAR27SEL_MASK GENMASK_32(3, 0) 3895 #define RCC_XBAR27CFGR_XBAR27SEL_SHIFT 0 3896 #define RCC_XBAR27CFGR_XBAR27EN BIT(6) 3897 #define RCC_XBAR27CFGR_XBAR27STS BIT(7) 3898 3899 /* RCC_XBAR28CFGR register fields */ 3900 #define RCC_XBAR28CFGR_XBAR28SEL_MASK GENMASK_32(3, 0) 3901 #define RCC_XBAR28CFGR_XBAR28SEL_SHIFT 0 3902 #define RCC_XBAR28CFGR_XBAR28EN BIT(6) 3903 #define RCC_XBAR28CFGR_XBAR28STS BIT(7) 3904 3905 /* RCC_XBAR29CFGR register fields */ 3906 #define RCC_XBAR29CFGR_XBAR29SEL_MASK GENMASK_32(3, 0) 3907 #define RCC_XBAR29CFGR_XBAR29SEL_SHIFT 0 3908 #define RCC_XBAR29CFGR_XBAR29EN BIT(6) 3909 #define RCC_XBAR29CFGR_XBAR29STS BIT(7) 3910 3911 /* RCC_XBAR30CFGR register fields */ 3912 #define RCC_XBAR30CFGR_XBAR30SEL_MASK GENMASK_32(3, 0) 3913 #define RCC_XBAR30CFGR_XBAR30SEL_SHIFT 0 3914 #define RCC_XBAR30CFGR_XBAR30EN BIT(6) 3915 #define RCC_XBAR30CFGR_XBAR30STS BIT(7) 3916 3917 /* RCC_XBAR31CFGR register fields */ 3918 #define RCC_XBAR31CFGR_XBAR31SEL_MASK GENMASK_32(3, 0) 3919 #define RCC_XBAR31CFGR_XBAR31SEL_SHIFT 0 3920 #define RCC_XBAR31CFGR_XBAR31EN BIT(6) 3921 #define RCC_XBAR31CFGR_XBAR31STS BIT(7) 3922 3923 /* RCC_XBAR32CFGR register fields */ 3924 #define RCC_XBAR32CFGR_XBAR32SEL_MASK GENMASK_32(3, 0) 3925 #define RCC_XBAR32CFGR_XBAR32SEL_SHIFT 0 3926 #define RCC_XBAR32CFGR_XBAR32EN BIT(6) 3927 #define RCC_XBAR32CFGR_XBAR32STS BIT(7) 3928 3929 /* RCC_XBAR33CFGR register fields */ 3930 #define RCC_XBAR33CFGR_XBAR33SEL_MASK GENMASK_32(3, 0) 3931 #define RCC_XBAR33CFGR_XBAR33SEL_SHIFT 0 3932 #define RCC_XBAR33CFGR_XBAR33EN BIT(6) 3933 #define RCC_XBAR33CFGR_XBAR33STS BIT(7) 3934 3935 /* RCC_XBAR34CFGR register fields */ 3936 #define RCC_XBAR34CFGR_XBAR34SEL_MASK GENMASK_32(3, 0) 3937 #define RCC_XBAR34CFGR_XBAR34SEL_SHIFT 0 3938 #define RCC_XBAR34CFGR_XBAR34EN BIT(6) 3939 #define RCC_XBAR34CFGR_XBAR34STS BIT(7) 3940 3941 /* RCC_XBAR35CFGR register fields */ 3942 #define RCC_XBAR35CFGR_XBAR35SEL_MASK GENMASK_32(3, 0) 3943 #define RCC_XBAR35CFGR_XBAR35SEL_SHIFT 0 3944 #define RCC_XBAR35CFGR_XBAR35EN BIT(6) 3945 #define RCC_XBAR35CFGR_XBAR35STS BIT(7) 3946 3947 /* RCC_XBAR36CFGR register fields */ 3948 #define RCC_XBAR36CFGR_XBAR36SEL_MASK GENMASK_32(3, 0) 3949 #define RCC_XBAR36CFGR_XBAR36SEL_SHIFT 0 3950 #define RCC_XBAR36CFGR_XBAR36EN BIT(6) 3951 #define RCC_XBAR36CFGR_XBAR36STS BIT(7) 3952 3953 /* RCC_XBAR37CFGR register fields */ 3954 #define RCC_XBAR37CFGR_XBAR37SEL_MASK GENMASK_32(3, 0) 3955 #define RCC_XBAR37CFGR_XBAR37SEL_SHIFT 0 3956 #define RCC_XBAR37CFGR_XBAR37EN BIT(6) 3957 #define RCC_XBAR37CFGR_XBAR37STS BIT(7) 3958 3959 /* RCC_XBAR38CFGR register fields */ 3960 #define RCC_XBAR38CFGR_XBAR38SEL_MASK GENMASK_32(3, 0) 3961 #define RCC_XBAR38CFGR_XBAR38SEL_SHIFT 0 3962 #define RCC_XBAR38CFGR_XBAR38EN BIT(6) 3963 #define RCC_XBAR38CFGR_XBAR38STS BIT(7) 3964 3965 /* RCC_XBAR39CFGR register fields */ 3966 #define RCC_XBAR39CFGR_XBAR39SEL_MASK GENMASK_32(3, 0) 3967 #define RCC_XBAR39CFGR_XBAR39SEL_SHIFT 0 3968 #define RCC_XBAR39CFGR_XBAR39EN BIT(6) 3969 #define RCC_XBAR39CFGR_XBAR39STS BIT(7) 3970 3971 /* RCC_XBAR40CFGR register fields */ 3972 #define RCC_XBAR40CFGR_XBAR40SEL_MASK GENMASK_32(3, 0) 3973 #define RCC_XBAR40CFGR_XBAR40SEL_SHIFT 0 3974 #define RCC_XBAR40CFGR_XBAR40EN BIT(6) 3975 #define RCC_XBAR40CFGR_XBAR40STS BIT(7) 3976 3977 /* RCC_XBAR41CFGR register fields */ 3978 #define RCC_XBAR41CFGR_XBAR41SEL_MASK GENMASK_32(3, 0) 3979 #define RCC_XBAR41CFGR_XBAR41SEL_SHIFT 0 3980 #define RCC_XBAR41CFGR_XBAR41EN BIT(6) 3981 #define RCC_XBAR41CFGR_XBAR41STS BIT(7) 3982 3983 /* RCC_XBAR42CFGR register fields */ 3984 #define RCC_XBAR42CFGR_XBAR42SEL_MASK GENMASK_32(3, 0) 3985 #define RCC_XBAR42CFGR_XBAR42SEL_SHIFT 0 3986 #define RCC_XBAR42CFGR_XBAR42EN BIT(6) 3987 #define RCC_XBAR42CFGR_XBAR42STS BIT(7) 3988 3989 /* RCC_XBAR43CFGR register fields */ 3990 #define RCC_XBAR43CFGR_XBAR43SEL_MASK GENMASK_32(3, 0) 3991 #define RCC_XBAR43CFGR_XBAR43SEL_SHIFT 0 3992 #define RCC_XBAR43CFGR_XBAR43EN BIT(6) 3993 #define RCC_XBAR43CFGR_XBAR43STS BIT(7) 3994 3995 /* RCC_XBAR44CFGR register fields */ 3996 #define RCC_XBAR44CFGR_XBAR44SEL_MASK GENMASK_32(3, 0) 3997 #define RCC_XBAR44CFGR_XBAR44SEL_SHIFT 0 3998 #define RCC_XBAR44CFGR_XBAR44EN BIT(6) 3999 #define RCC_XBAR44CFGR_XBAR44STS BIT(7) 4000 4001 /* RCC_XBAR45CFGR register fields */ 4002 #define RCC_XBAR45CFGR_XBAR45SEL_MASK GENMASK_32(3, 0) 4003 #define RCC_XBAR45CFGR_XBAR45SEL_SHIFT 0 4004 #define RCC_XBAR45CFGR_XBAR45EN BIT(6) 4005 #define RCC_XBAR45CFGR_XBAR45STS BIT(7) 4006 4007 /* RCC_XBAR46CFGR register fields */ 4008 #define RCC_XBAR46CFGR_XBAR46SEL_MASK GENMASK_32(3, 0) 4009 #define RCC_XBAR46CFGR_XBAR46SEL_SHIFT 0 4010 #define RCC_XBAR46CFGR_XBAR46EN BIT(6) 4011 #define RCC_XBAR46CFGR_XBAR46STS BIT(7) 4012 4013 /* RCC_XBAR47CFGR register fields */ 4014 #define RCC_XBAR47CFGR_XBAR47SEL_MASK GENMASK_32(3, 0) 4015 #define RCC_XBAR47CFGR_XBAR47SEL_SHIFT 0 4016 #define RCC_XBAR47CFGR_XBAR47EN BIT(6) 4017 #define RCC_XBAR47CFGR_XBAR47STS BIT(7) 4018 4019 /* RCC_XBAR48CFGR register fields */ 4020 #define RCC_XBAR48CFGR_XBAR48SEL_MASK GENMASK_32(3, 0) 4021 #define RCC_XBAR48CFGR_XBAR48SEL_SHIFT 0 4022 #define RCC_XBAR48CFGR_XBAR48EN BIT(6) 4023 #define RCC_XBAR48CFGR_XBAR48STS BIT(7) 4024 4025 /* RCC_XBAR49CFGR register fields */ 4026 #define RCC_XBAR49CFGR_XBAR49SEL_MASK GENMASK_32(3, 0) 4027 #define RCC_XBAR49CFGR_XBAR49SEL_SHIFT 0 4028 #define RCC_XBAR49CFGR_XBAR49EN BIT(6) 4029 #define RCC_XBAR49CFGR_XBAR49STS BIT(7) 4030 4031 /* RCC_XBAR50CFGR register fields */ 4032 #define RCC_XBAR50CFGR_XBAR50SEL_MASK GENMASK_32(3, 0) 4033 #define RCC_XBAR50CFGR_XBAR50SEL_SHIFT 0 4034 #define RCC_XBAR50CFGR_XBAR50EN BIT(6) 4035 #define RCC_XBAR50CFGR_XBAR50STS BIT(7) 4036 4037 /* RCC_XBAR51CFGR register fields */ 4038 #define RCC_XBAR51CFGR_XBAR51SEL_MASK GENMASK_32(3, 0) 4039 #define RCC_XBAR51CFGR_XBAR51SEL_SHIFT 0 4040 #define RCC_XBAR51CFGR_XBAR51EN BIT(6) 4041 #define RCC_XBAR51CFGR_XBAR51STS BIT(7) 4042 4043 /* RCC_XBAR52CFGR register fields */ 4044 #define RCC_XBAR52CFGR_XBAR52SEL_MASK GENMASK_32(3, 0) 4045 #define RCC_XBAR52CFGR_XBAR52SEL_SHIFT 0 4046 #define RCC_XBAR52CFGR_XBAR52EN BIT(6) 4047 #define RCC_XBAR52CFGR_XBAR52STS BIT(7) 4048 4049 /* RCC_XBAR53CFGR register fields */ 4050 #define RCC_XBAR53CFGR_XBAR53SEL_MASK GENMASK_32(3, 0) 4051 #define RCC_XBAR53CFGR_XBAR53SEL_SHIFT 0 4052 #define RCC_XBAR53CFGR_XBAR53EN BIT(6) 4053 #define RCC_XBAR53CFGR_XBAR53STS BIT(7) 4054 4055 /* RCC_XBAR54CFGR register fields */ 4056 #define RCC_XBAR54CFGR_XBAR54SEL_MASK GENMASK_32(3, 0) 4057 #define RCC_XBAR54CFGR_XBAR54SEL_SHIFT 0 4058 #define RCC_XBAR54CFGR_XBAR54EN BIT(6) 4059 #define RCC_XBAR54CFGR_XBAR54STS BIT(7) 4060 4061 /* RCC_XBAR55CFGR register fields */ 4062 #define RCC_XBAR55CFGR_XBAR55SEL_MASK GENMASK_32(3, 0) 4063 #define RCC_XBAR55CFGR_XBAR55SEL_SHIFT 0 4064 #define RCC_XBAR55CFGR_XBAR55EN BIT(6) 4065 #define RCC_XBAR55CFGR_XBAR55STS BIT(7) 4066 4067 /* RCC_XBAR56CFGR register fields */ 4068 #define RCC_XBAR56CFGR_XBAR56SEL_MASK GENMASK_32(3, 0) 4069 #define RCC_XBAR56CFGR_XBAR56SEL_SHIFT 0 4070 #define RCC_XBAR56CFGR_XBAR56EN BIT(6) 4071 #define RCC_XBAR56CFGR_XBAR56STS BIT(7) 4072 4073 /* RCC_XBAR57CFGR register fields */ 4074 #define RCC_XBAR57CFGR_XBAR57SEL_MASK GENMASK_32(3, 0) 4075 #define RCC_XBAR57CFGR_XBAR57SEL_SHIFT 0 4076 #define RCC_XBAR57CFGR_XBAR57EN BIT(6) 4077 #define RCC_XBAR57CFGR_XBAR57STS BIT(7) 4078 4079 /* RCC_XBAR58CFGR register fields */ 4080 #define RCC_XBAR58CFGR_XBAR58SEL_MASK GENMASK_32(3, 0) 4081 #define RCC_XBAR58CFGR_XBAR58SEL_SHIFT 0 4082 #define RCC_XBAR58CFGR_XBAR58EN BIT(6) 4083 #define RCC_XBAR58CFGR_XBAR58STS BIT(7) 4084 4085 /* RCC_XBAR59CFGR register fields */ 4086 #define RCC_XBAR59CFGR_XBAR59SEL_MASK GENMASK_32(3, 0) 4087 #define RCC_XBAR59CFGR_XBAR59SEL_SHIFT 0 4088 #define RCC_XBAR59CFGR_XBAR59EN BIT(6) 4089 #define RCC_XBAR59CFGR_XBAR59STS BIT(7) 4090 4091 /* RCC_XBAR60CFGR register fields */ 4092 #define RCC_XBAR60CFGR_XBAR60SEL_MASK GENMASK_32(3, 0) 4093 #define RCC_XBAR60CFGR_XBAR60SEL_SHIFT 0 4094 #define RCC_XBAR60CFGR_XBAR60EN BIT(6) 4095 #define RCC_XBAR60CFGR_XBAR60STS BIT(7) 4096 4097 /* RCC_XBAR61CFGR register fields */ 4098 #define RCC_XBAR61CFGR_XBAR61SEL_MASK GENMASK_32(3, 0) 4099 #define RCC_XBAR61CFGR_XBAR61SEL_SHIFT 0 4100 #define RCC_XBAR61CFGR_XBAR61EN BIT(6) 4101 #define RCC_XBAR61CFGR_XBAR61STS BIT(7) 4102 4103 /* RCC_XBAR62CFGR register fields */ 4104 #define RCC_XBAR62CFGR_XBAR62SEL_MASK GENMASK_32(3, 0) 4105 #define RCC_XBAR62CFGR_XBAR62SEL_SHIFT 0 4106 #define RCC_XBAR62CFGR_XBAR62EN BIT(6) 4107 #define RCC_XBAR62CFGR_XBAR62STS BIT(7) 4108 4109 /* RCC_XBAR63CFGR register fields */ 4110 #define RCC_XBAR63CFGR_XBAR63SEL_MASK GENMASK_32(3, 0) 4111 #define RCC_XBAR63CFGR_XBAR63SEL_SHIFT 0 4112 #define RCC_XBAR63CFGR_XBAR63EN BIT(6) 4113 #define RCC_XBAR63CFGR_XBAR63STS BIT(7) 4114 4115 /* RCC_XBARxCFGR register fields */ 4116 #define RCC_XBARxCFGR_XBARxSEL_MASK GENMASK_32(3, 0) 4117 #define RCC_XBARxCFGR_XBARxSEL_SHIFT 0 4118 #define RCC_XBARxCFGR_XBARxEN BIT(6) 4119 #define RCC_XBARxCFGR_XBARxSTS BIT(7) 4120 4121 /* RCC_PREDIV0CFGR register fields */ 4122 #define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) 4123 #define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 4124 4125 /* RCC_PREDIV1CFGR register fields */ 4126 #define RCC_PREDIV1CFGR_PREDIV1_MASK GENMASK_32(9, 0) 4127 #define RCC_PREDIV1CFGR_PREDIV1_SHIFT 0 4128 4129 /* RCC_PREDIV2CFGR register fields */ 4130 #define RCC_PREDIV2CFGR_PREDIV2_MASK GENMASK_32(9, 0) 4131 #define RCC_PREDIV2CFGR_PREDIV2_SHIFT 0 4132 4133 /* RCC_PREDIV3CFGR register fields */ 4134 #define RCC_PREDIV3CFGR_PREDIV3_MASK GENMASK_32(9, 0) 4135 #define RCC_PREDIV3CFGR_PREDIV3_SHIFT 0 4136 4137 /* RCC_PREDIV4CFGR register fields */ 4138 #define RCC_PREDIV4CFGR_PREDIV4_MASK GENMASK_32(9, 0) 4139 #define RCC_PREDIV4CFGR_PREDIV4_SHIFT 0 4140 4141 /* RCC_PREDIV5CFGR register fields */ 4142 #define RCC_PREDIV5CFGR_PREDIV5_MASK GENMASK_32(9, 0) 4143 #define RCC_PREDIV5CFGR_PREDIV5_SHIFT 0 4144 4145 /* RCC_PREDIV6CFGR register fields */ 4146 #define RCC_PREDIV6CFGR_PREDIV6_MASK GENMASK_32(9, 0) 4147 #define RCC_PREDIV6CFGR_PREDIV6_SHIFT 0 4148 4149 /* RCC_PREDIV7CFGR register fields */ 4150 #define RCC_PREDIV7CFGR_PREDIV7_MASK GENMASK_32(9, 0) 4151 #define RCC_PREDIV7CFGR_PREDIV7_SHIFT 0 4152 4153 /* RCC_PREDIV8CFGR register fields */ 4154 #define RCC_PREDIV8CFGR_PREDIV8_MASK GENMASK_32(9, 0) 4155 #define RCC_PREDIV8CFGR_PREDIV8_SHIFT 0 4156 4157 /* RCC_PREDIV9CFGR register fields */ 4158 #define RCC_PREDIV9CFGR_PREDIV9_MASK GENMASK_32(9, 0) 4159 #define RCC_PREDIV9CFGR_PREDIV9_SHIFT 0 4160 4161 /* RCC_PREDIV10CFGR register fields */ 4162 #define RCC_PREDIV10CFGR_PREDIV10_MASK GENMASK_32(9, 0) 4163 #define RCC_PREDIV10CFGR_PREDIV10_SHIFT 0 4164 4165 /* RCC_PREDIV11CFGR register fields */ 4166 #define RCC_PREDIV11CFGR_PREDIV11_MASK GENMASK_32(9, 0) 4167 #define RCC_PREDIV11CFGR_PREDIV11_SHIFT 0 4168 4169 /* RCC_PREDIV12CFGR register fields */ 4170 #define RCC_PREDIV12CFGR_PREDIV12_MASK GENMASK_32(9, 0) 4171 #define RCC_PREDIV12CFGR_PREDIV12_SHIFT 0 4172 4173 /* RCC_PREDIV13CFGR register fields */ 4174 #define RCC_PREDIV13CFGR_PREDIV13_MASK GENMASK_32(9, 0) 4175 #define RCC_PREDIV13CFGR_PREDIV13_SHIFT 0 4176 4177 /* RCC_PREDIV14CFGR register fields */ 4178 #define RCC_PREDIV14CFGR_PREDIV14_MASK GENMASK_32(9, 0) 4179 #define RCC_PREDIV14CFGR_PREDIV14_SHIFT 0 4180 4181 /* RCC_PREDIV15CFGR register fields */ 4182 #define RCC_PREDIV15CFGR_PREDIV15_MASK GENMASK_32(9, 0) 4183 #define RCC_PREDIV15CFGR_PREDIV15_SHIFT 0 4184 4185 /* RCC_PREDIV16CFGR register fields */ 4186 #define RCC_PREDIV16CFGR_PREDIV16_MASK GENMASK_32(9, 0) 4187 #define RCC_PREDIV16CFGR_PREDIV16_SHIFT 0 4188 4189 /* RCC_PREDIV17CFGR register fields */ 4190 #define RCC_PREDIV17CFGR_PREDIV17_MASK GENMASK_32(9, 0) 4191 #define RCC_PREDIV17CFGR_PREDIV17_SHIFT 0 4192 4193 /* RCC_PREDIV18CFGR register fields */ 4194 #define RCC_PREDIV18CFGR_PREDIV18_MASK GENMASK_32(9, 0) 4195 #define RCC_PREDIV18CFGR_PREDIV18_SHIFT 0 4196 4197 /* RCC_PREDIV19CFGR register fields */ 4198 #define RCC_PREDIV19CFGR_PREDIV19_MASK GENMASK_32(9, 0) 4199 #define RCC_PREDIV19CFGR_PREDIV19_SHIFT 0 4200 4201 /* RCC_PREDIV20CFGR register fields */ 4202 #define RCC_PREDIV20CFGR_PREDIV20_MASK GENMASK_32(9, 0) 4203 #define RCC_PREDIV20CFGR_PREDIV20_SHIFT 0 4204 4205 /* RCC_PREDIV21CFGR register fields */ 4206 #define RCC_PREDIV21CFGR_PREDIV21_MASK GENMASK_32(9, 0) 4207 #define RCC_PREDIV21CFGR_PREDIV21_SHIFT 0 4208 4209 /* RCC_PREDIV22CFGR register fields */ 4210 #define RCC_PREDIV22CFGR_PREDIV22_MASK GENMASK_32(9, 0) 4211 #define RCC_PREDIV22CFGR_PREDIV22_SHIFT 0 4212 4213 /* RCC_PREDIV23CFGR register fields */ 4214 #define RCC_PREDIV23CFGR_PREDIV23_MASK GENMASK_32(9, 0) 4215 #define RCC_PREDIV23CFGR_PREDIV23_SHIFT 0 4216 4217 /* RCC_PREDIV24CFGR register fields */ 4218 #define RCC_PREDIV24CFGR_PREDIV24_MASK GENMASK_32(9, 0) 4219 #define RCC_PREDIV24CFGR_PREDIV24_SHIFT 0 4220 4221 /* RCC_PREDIV25CFGR register fields */ 4222 #define RCC_PREDIV25CFGR_PREDIV25_MASK GENMASK_32(9, 0) 4223 #define RCC_PREDIV25CFGR_PREDIV25_SHIFT 0 4224 4225 /* RCC_PREDIV26CFGR register fields */ 4226 #define RCC_PREDIV26CFGR_PREDIV26_MASK GENMASK_32(9, 0) 4227 #define RCC_PREDIV26CFGR_PREDIV26_SHIFT 0 4228 4229 /* RCC_PREDIV27CFGR register fields */ 4230 #define RCC_PREDIV27CFGR_PREDIV27_MASK GENMASK_32(9, 0) 4231 #define RCC_PREDIV27CFGR_PREDIV27_SHIFT 0 4232 4233 /* RCC_PREDIV28CFGR register fields */ 4234 #define RCC_PREDIV28CFGR_PREDIV28_MASK GENMASK_32(9, 0) 4235 #define RCC_PREDIV28CFGR_PREDIV28_SHIFT 0 4236 4237 /* RCC_PREDIV29CFGR register fields */ 4238 #define RCC_PREDIV29CFGR_PREDIV29_MASK GENMASK_32(9, 0) 4239 #define RCC_PREDIV29CFGR_PREDIV29_SHIFT 0 4240 4241 /* RCC_PREDIV30CFGR register fields */ 4242 #define RCC_PREDIV30CFGR_PREDIV30_MASK GENMASK_32(9, 0) 4243 #define RCC_PREDIV30CFGR_PREDIV30_SHIFT 0 4244 4245 /* RCC_PREDIV31CFGR register fields */ 4246 #define RCC_PREDIV31CFGR_PREDIV31_MASK GENMASK_32(9, 0) 4247 #define RCC_PREDIV31CFGR_PREDIV31_SHIFT 0 4248 4249 /* RCC_PREDIV32CFGR register fields */ 4250 #define RCC_PREDIV32CFGR_PREDIV32_MASK GENMASK_32(9, 0) 4251 #define RCC_PREDIV32CFGR_PREDIV32_SHIFT 0 4252 4253 /* RCC_PREDIV33CFGR register fields */ 4254 #define RCC_PREDIV33CFGR_PREDIV33_MASK GENMASK_32(9, 0) 4255 #define RCC_PREDIV33CFGR_PREDIV33_SHIFT 0 4256 4257 /* RCC_PREDIV34CFGR register fields */ 4258 #define RCC_PREDIV34CFGR_PREDIV34_MASK GENMASK_32(9, 0) 4259 #define RCC_PREDIV34CFGR_PREDIV34_SHIFT 0 4260 4261 /* RCC_PREDIV35CFGR register fields */ 4262 #define RCC_PREDIV35CFGR_PREDIV35_MASK GENMASK_32(9, 0) 4263 #define RCC_PREDIV35CFGR_PREDIV35_SHIFT 0 4264 4265 /* RCC_PREDIV36CFGR register fields */ 4266 #define RCC_PREDIV36CFGR_PREDIV36_MASK GENMASK_32(9, 0) 4267 #define RCC_PREDIV36CFGR_PREDIV36_SHIFT 0 4268 4269 /* RCC_PREDIV37CFGR register fields */ 4270 #define RCC_PREDIV37CFGR_PREDIV37_MASK GENMASK_32(9, 0) 4271 #define RCC_PREDIV37CFGR_PREDIV37_SHIFT 0 4272 4273 /* RCC_PREDIV38CFGR register fields */ 4274 #define RCC_PREDIV38CFGR_PREDIV38_MASK GENMASK_32(9, 0) 4275 #define RCC_PREDIV38CFGR_PREDIV38_SHIFT 0 4276 4277 /* RCC_PREDIV39CFGR register fields */ 4278 #define RCC_PREDIV39CFGR_PREDIV39_MASK GENMASK_32(9, 0) 4279 #define RCC_PREDIV39CFGR_PREDIV39_SHIFT 0 4280 4281 /* RCC_PREDIV40CFGR register fields */ 4282 #define RCC_PREDIV40CFGR_PREDIV40_MASK GENMASK_32(9, 0) 4283 #define RCC_PREDIV40CFGR_PREDIV40_SHIFT 0 4284 4285 /* RCC_PREDIV41CFGR register fields */ 4286 #define RCC_PREDIV41CFGR_PREDIV41_MASK GENMASK_32(9, 0) 4287 #define RCC_PREDIV41CFGR_PREDIV41_SHIFT 0 4288 4289 /* RCC_PREDIV42CFGR register fields */ 4290 #define RCC_PREDIV42CFGR_PREDIV42_MASK GENMASK_32(9, 0) 4291 #define RCC_PREDIV42CFGR_PREDIV42_SHIFT 0 4292 4293 /* RCC_PREDIV43CFGR register fields */ 4294 #define RCC_PREDIV43CFGR_PREDIV43_MASK GENMASK_32(9, 0) 4295 #define RCC_PREDIV43CFGR_PREDIV43_SHIFT 0 4296 4297 /* RCC_PREDIV44CFGR register fields */ 4298 #define RCC_PREDIV44CFGR_PREDIV44_MASK GENMASK_32(9, 0) 4299 #define RCC_PREDIV44CFGR_PREDIV44_SHIFT 0 4300 4301 /* RCC_PREDIV45CFGR register fields */ 4302 #define RCC_PREDIV45CFGR_PREDIV45_MASK GENMASK_32(9, 0) 4303 #define RCC_PREDIV45CFGR_PREDIV45_SHIFT 0 4304 4305 /* RCC_PREDIV46CFGR register fields */ 4306 #define RCC_PREDIV46CFGR_PREDIV46_MASK GENMASK_32(9, 0) 4307 #define RCC_PREDIV46CFGR_PREDIV46_SHIFT 0 4308 4309 /* RCC_PREDIV47CFGR register fields */ 4310 #define RCC_PREDIV47CFGR_PREDIV47_MASK GENMASK_32(9, 0) 4311 #define RCC_PREDIV47CFGR_PREDIV47_SHIFT 0 4312 4313 /* RCC_PREDIV48CFGR register fields */ 4314 #define RCC_PREDIV48CFGR_PREDIV48_MASK GENMASK_32(9, 0) 4315 #define RCC_PREDIV48CFGR_PREDIV48_SHIFT 0 4316 4317 /* RCC_PREDIV49CFGR register fields */ 4318 #define RCC_PREDIV49CFGR_PREDIV49_MASK GENMASK_32(9, 0) 4319 #define RCC_PREDIV49CFGR_PREDIV49_SHIFT 0 4320 4321 /* RCC_PREDIV50CFGR register fields */ 4322 #define RCC_PREDIV50CFGR_PREDIV50_MASK GENMASK_32(9, 0) 4323 #define RCC_PREDIV50CFGR_PREDIV50_SHIFT 0 4324 4325 /* RCC_PREDIV51CFGR register fields */ 4326 #define RCC_PREDIV51CFGR_PREDIV51_MASK GENMASK_32(9, 0) 4327 #define RCC_PREDIV51CFGR_PREDIV51_SHIFT 0 4328 4329 /* RCC_PREDIV52CFGR register fields */ 4330 #define RCC_PREDIV52CFGR_PREDIV52_MASK GENMASK_32(9, 0) 4331 #define RCC_PREDIV52CFGR_PREDIV52_SHIFT 0 4332 4333 /* RCC_PREDIV53CFGR register fields */ 4334 #define RCC_PREDIV53CFGR_PREDIV53_MASK GENMASK_32(9, 0) 4335 #define RCC_PREDIV53CFGR_PREDIV53_SHIFT 0 4336 4337 /* RCC_PREDIV54CFGR register fields */ 4338 #define RCC_PREDIV54CFGR_PREDIV54_MASK GENMASK_32(9, 0) 4339 #define RCC_PREDIV54CFGR_PREDIV54_SHIFT 0 4340 4341 /* RCC_PREDIV55CFGR register fields */ 4342 #define RCC_PREDIV55CFGR_PREDIV55_MASK GENMASK_32(9, 0) 4343 #define RCC_PREDIV55CFGR_PREDIV55_SHIFT 0 4344 4345 /* RCC_PREDIV56CFGR register fields */ 4346 #define RCC_PREDIV56CFGR_PREDIV56_MASK GENMASK_32(9, 0) 4347 #define RCC_PREDIV56CFGR_PREDIV56_SHIFT 0 4348 4349 /* RCC_PREDIV57CFGR register fields */ 4350 #define RCC_PREDIV57CFGR_PREDIV57_MASK GENMASK_32(9, 0) 4351 #define RCC_PREDIV57CFGR_PREDIV57_SHIFT 0 4352 4353 /* RCC_PREDIV58CFGR register fields */ 4354 #define RCC_PREDIV58CFGR_PREDIV58_MASK GENMASK_32(9, 0) 4355 #define RCC_PREDIV58CFGR_PREDIV58_SHIFT 0 4356 4357 /* RCC_PREDIV59CFGR register fields */ 4358 #define RCC_PREDIV59CFGR_PREDIV59_MASK GENMASK_32(9, 0) 4359 #define RCC_PREDIV59CFGR_PREDIV59_SHIFT 0 4360 4361 /* RCC_PREDIV60CFGR register fields */ 4362 #define RCC_PREDIV60CFGR_PREDIV60_MASK GENMASK_32(9, 0) 4363 #define RCC_PREDIV60CFGR_PREDIV60_SHIFT 0 4364 4365 /* RCC_PREDIV61CFGR register fields */ 4366 #define RCC_PREDIV61CFGR_PREDIV61_MASK GENMASK_32(9, 0) 4367 #define RCC_PREDIV61CFGR_PREDIV61_SHIFT 0 4368 4369 /* RCC_PREDIV62CFGR register fields */ 4370 #define RCC_PREDIV62CFGR_PREDIV62_MASK GENMASK_32(9, 0) 4371 #define RCC_PREDIV62CFGR_PREDIV62_SHIFT 0 4372 4373 /* RCC_PREDIV63CFGR register fields */ 4374 #define RCC_PREDIV63CFGR_PREDIV63_MASK GENMASK_32(9, 0) 4375 #define RCC_PREDIV63CFGR_PREDIV63_SHIFT 0 4376 4377 /* RCC_PREDIVxCFGR register fields */ 4378 #define RCC_PREDIVxCFGR_PREDIVx_MASK GENMASK_32(9, 0) 4379 #define RCC_PREDIVxCFGR_PREDIVx_SHIFT 0 4380 4381 /* RCC_FINDIV0CFGR register fields */ 4382 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) 4383 #define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 4384 #define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) 4385 4386 /* RCC_FINDIV1CFGR register fields */ 4387 #define RCC_FINDIV1CFGR_FINDIV1_MASK GENMASK_32(5, 0) 4388 #define RCC_FINDIV1CFGR_FINDIV1_SHIFT 0 4389 #define RCC_FINDIV1CFGR_FINDIV1EN BIT(6) 4390 4391 /* RCC_FINDIV2CFGR register fields */ 4392 #define RCC_FINDIV2CFGR_FINDIV2_MASK GENMASK_32(5, 0) 4393 #define RCC_FINDIV2CFGR_FINDIV2_SHIFT 0 4394 #define RCC_FINDIV2CFGR_FINDIV2EN BIT(6) 4395 4396 /* RCC_FINDIV3CFGR register fields */ 4397 #define RCC_FINDIV3CFGR_FINDIV3_MASK GENMASK_32(5, 0) 4398 #define RCC_FINDIV3CFGR_FINDIV3_SHIFT 0 4399 #define RCC_FINDIV3CFGR_FINDIV3EN BIT(6) 4400 4401 /* RCC_FINDIV4CFGR register fields */ 4402 #define RCC_FINDIV4CFGR_FINDIV4_MASK GENMASK_32(5, 0) 4403 #define RCC_FINDIV4CFGR_FINDIV4_SHIFT 0 4404 #define RCC_FINDIV4CFGR_FINDIV4EN BIT(6) 4405 4406 /* RCC_FINDIV5CFGR register fields */ 4407 #define RCC_FINDIV5CFGR_FINDIV5_MASK GENMASK_32(5, 0) 4408 #define RCC_FINDIV5CFGR_FINDIV5_SHIFT 0 4409 #define RCC_FINDIV5CFGR_FINDIV5EN BIT(6) 4410 4411 /* RCC_FINDIV6CFGR register fields */ 4412 #define RCC_FINDIV6CFGR_FINDIV6_MASK GENMASK_32(5, 0) 4413 #define RCC_FINDIV6CFGR_FINDIV6_SHIFT 0 4414 #define RCC_FINDIV6CFGR_FINDIV6EN BIT(6) 4415 4416 /* RCC_FINDIV7CFGR register fields */ 4417 #define RCC_FINDIV7CFGR_FINDIV7_MASK GENMASK_32(5, 0) 4418 #define RCC_FINDIV7CFGR_FINDIV7_SHIFT 0 4419 #define RCC_FINDIV7CFGR_FINDIV7EN BIT(6) 4420 4421 /* RCC_FINDIV8CFGR register fields */ 4422 #define RCC_FINDIV8CFGR_FINDIV8_MASK GENMASK_32(5, 0) 4423 #define RCC_FINDIV8CFGR_FINDIV8_SHIFT 0 4424 #define RCC_FINDIV8CFGR_FINDIV8EN BIT(6) 4425 4426 /* RCC_FINDIV9CFGR register fields */ 4427 #define RCC_FINDIV9CFGR_FINDIV9_MASK GENMASK_32(5, 0) 4428 #define RCC_FINDIV9CFGR_FINDIV9_SHIFT 0 4429 #define RCC_FINDIV9CFGR_FINDIV9EN BIT(6) 4430 4431 /* RCC_FINDIV10CFGR register fields */ 4432 #define RCC_FINDIV10CFGR_FINDIV10_MASK GENMASK_32(5, 0) 4433 #define RCC_FINDIV10CFGR_FINDIV10_SHIFT 0 4434 #define RCC_FINDIV10CFGR_FINDIV10EN BIT(6) 4435 4436 /* RCC_FINDIV11CFGR register fields */ 4437 #define RCC_FINDIV11CFGR_FINDIV11_MASK GENMASK_32(5, 0) 4438 #define RCC_FINDIV11CFGR_FINDIV11_SHIFT 0 4439 #define RCC_FINDIV11CFGR_FINDIV11EN BIT(6) 4440 4441 /* RCC_FINDIV12CFGR register fields */ 4442 #define RCC_FINDIV12CFGR_FINDIV12_MASK GENMASK_32(5, 0) 4443 #define RCC_FINDIV12CFGR_FINDIV12_SHIFT 0 4444 #define RCC_FINDIV12CFGR_FINDIV12EN BIT(6) 4445 4446 /* RCC_FINDIV13CFGR register fields */ 4447 #define RCC_FINDIV13CFGR_FINDIV13_MASK GENMASK_32(5, 0) 4448 #define RCC_FINDIV13CFGR_FINDIV13_SHIFT 0 4449 #define RCC_FINDIV13CFGR_FINDIV13EN BIT(6) 4450 4451 /* RCC_FINDIV14CFGR register fields */ 4452 #define RCC_FINDIV14CFGR_FINDIV14_MASK GENMASK_32(5, 0) 4453 #define RCC_FINDIV14CFGR_FINDIV14_SHIFT 0 4454 #define RCC_FINDIV14CFGR_FINDIV14EN BIT(6) 4455 4456 /* RCC_FINDIV15CFGR register fields */ 4457 #define RCC_FINDIV15CFGR_FINDIV15_MASK GENMASK_32(5, 0) 4458 #define RCC_FINDIV15CFGR_FINDIV15_SHIFT 0 4459 #define RCC_FINDIV15CFGR_FINDIV15EN BIT(6) 4460 4461 /* RCC_FINDIV16CFGR register fields */ 4462 #define RCC_FINDIV16CFGR_FINDIV16_MASK GENMASK_32(5, 0) 4463 #define RCC_FINDIV16CFGR_FINDIV16_SHIFT 0 4464 #define RCC_FINDIV16CFGR_FINDIV16EN BIT(6) 4465 4466 /* RCC_FINDIV17CFGR register fields */ 4467 #define RCC_FINDIV17CFGR_FINDIV17_MASK GENMASK_32(5, 0) 4468 #define RCC_FINDIV17CFGR_FINDIV17_SHIFT 0 4469 #define RCC_FINDIV17CFGR_FINDIV17EN BIT(6) 4470 4471 /* RCC_FINDIV18CFGR register fields */ 4472 #define RCC_FINDIV18CFGR_FINDIV18_MASK GENMASK_32(5, 0) 4473 #define RCC_FINDIV18CFGR_FINDIV18_SHIFT 0 4474 #define RCC_FINDIV18CFGR_FINDIV18EN BIT(6) 4475 4476 /* RCC_FINDIV19CFGR register fields */ 4477 #define RCC_FINDIV19CFGR_FINDIV19_MASK GENMASK_32(5, 0) 4478 #define RCC_FINDIV19CFGR_FINDIV19_SHIFT 0 4479 #define RCC_FINDIV19CFGR_FINDIV19EN BIT(6) 4480 4481 /* RCC_FINDIV20CFGR register fields */ 4482 #define RCC_FINDIV20CFGR_FINDIV20_MASK GENMASK_32(5, 0) 4483 #define RCC_FINDIV20CFGR_FINDIV20_SHIFT 0 4484 #define RCC_FINDIV20CFGR_FINDIV20EN BIT(6) 4485 4486 /* RCC_FINDIV21CFGR register fields */ 4487 #define RCC_FINDIV21CFGR_FINDIV21_MASK GENMASK_32(5, 0) 4488 #define RCC_FINDIV21CFGR_FINDIV21_SHIFT 0 4489 #define RCC_FINDIV21CFGR_FINDIV21EN BIT(6) 4490 4491 /* RCC_FINDIV22CFGR register fields */ 4492 #define RCC_FINDIV22CFGR_FINDIV22_MASK GENMASK_32(5, 0) 4493 #define RCC_FINDIV22CFGR_FINDIV22_SHIFT 0 4494 #define RCC_FINDIV22CFGR_FINDIV22EN BIT(6) 4495 4496 /* RCC_FINDIV23CFGR register fields */ 4497 #define RCC_FINDIV23CFGR_FINDIV23_MASK GENMASK_32(5, 0) 4498 #define RCC_FINDIV23CFGR_FINDIV23_SHIFT 0 4499 #define RCC_FINDIV23CFGR_FINDIV23EN BIT(6) 4500 4501 /* RCC_FINDIV24CFGR register fields */ 4502 #define RCC_FINDIV24CFGR_FINDIV24_MASK GENMASK_32(5, 0) 4503 #define RCC_FINDIV24CFGR_FINDIV24_SHIFT 0 4504 #define RCC_FINDIV24CFGR_FINDIV24EN BIT(6) 4505 4506 /* RCC_FINDIV25CFGR register fields */ 4507 #define RCC_FINDIV25CFGR_FINDIV25_MASK GENMASK_32(5, 0) 4508 #define RCC_FINDIV25CFGR_FINDIV25_SHIFT 0 4509 #define RCC_FINDIV25CFGR_FINDIV25EN BIT(6) 4510 4511 /* RCC_FINDIV26CFGR register fields */ 4512 #define RCC_FINDIV26CFGR_FINDIV26_MASK GENMASK_32(5, 0) 4513 #define RCC_FINDIV26CFGR_FINDIV26_SHIFT 0 4514 #define RCC_FINDIV26CFGR_FINDIV26EN BIT(6) 4515 4516 /* RCC_FINDIV27CFGR register fields */ 4517 #define RCC_FINDIV27CFGR_FINDIV27_MASK GENMASK_32(5, 0) 4518 #define RCC_FINDIV27CFGR_FINDIV27_SHIFT 0 4519 #define RCC_FINDIV27CFGR_FINDIV27EN BIT(6) 4520 4521 /* RCC_FINDIV28CFGR register fields */ 4522 #define RCC_FINDIV28CFGR_FINDIV28_MASK GENMASK_32(5, 0) 4523 #define RCC_FINDIV28CFGR_FINDIV28_SHIFT 0 4524 #define RCC_FINDIV28CFGR_FINDIV28EN BIT(6) 4525 4526 /* RCC_FINDIV29CFGR register fields */ 4527 #define RCC_FINDIV29CFGR_FINDIV29_MASK GENMASK_32(5, 0) 4528 #define RCC_FINDIV29CFGR_FINDIV29_SHIFT 0 4529 #define RCC_FINDIV29CFGR_FINDIV29EN BIT(6) 4530 4531 /* RCC_FINDIV30CFGR register fields */ 4532 #define RCC_FINDIV30CFGR_FINDIV30_MASK GENMASK_32(5, 0) 4533 #define RCC_FINDIV30CFGR_FINDIV30_SHIFT 0 4534 #define RCC_FINDIV30CFGR_FINDIV30EN BIT(6) 4535 4536 /* RCC_FINDIV31CFGR register fields */ 4537 #define RCC_FINDIV31CFGR_FINDIV31_MASK GENMASK_32(5, 0) 4538 #define RCC_FINDIV31CFGR_FINDIV31_SHIFT 0 4539 #define RCC_FINDIV31CFGR_FINDIV31EN BIT(6) 4540 4541 /* RCC_FINDIV32CFGR register fields */ 4542 #define RCC_FINDIV32CFGR_FINDIV32_MASK GENMASK_32(5, 0) 4543 #define RCC_FINDIV32CFGR_FINDIV32_SHIFT 0 4544 #define RCC_FINDIV32CFGR_FINDIV32EN BIT(6) 4545 4546 /* RCC_FINDIV33CFGR register fields */ 4547 #define RCC_FINDIV33CFGR_FINDIV33_MASK GENMASK_32(5, 0) 4548 #define RCC_FINDIV33CFGR_FINDIV33_SHIFT 0 4549 #define RCC_FINDIV33CFGR_FINDIV33EN BIT(6) 4550 4551 /* RCC_FINDIV34CFGR register fields */ 4552 #define RCC_FINDIV34CFGR_FINDIV34_MASK GENMASK_32(5, 0) 4553 #define RCC_FINDIV34CFGR_FINDIV34_SHIFT 0 4554 #define RCC_FINDIV34CFGR_FINDIV34EN BIT(6) 4555 4556 /* RCC_FINDIV35CFGR register fields */ 4557 #define RCC_FINDIV35CFGR_FINDIV35_MASK GENMASK_32(5, 0) 4558 #define RCC_FINDIV35CFGR_FINDIV35_SHIFT 0 4559 #define RCC_FINDIV35CFGR_FINDIV35EN BIT(6) 4560 4561 /* RCC_FINDIV36CFGR register fields */ 4562 #define RCC_FINDIV36CFGR_FINDIV36_MASK GENMASK_32(5, 0) 4563 #define RCC_FINDIV36CFGR_FINDIV36_SHIFT 0 4564 #define RCC_FINDIV36CFGR_FINDIV36EN BIT(6) 4565 4566 /* RCC_FINDIV37CFGR register fields */ 4567 #define RCC_FINDIV37CFGR_FINDIV37_MASK GENMASK_32(5, 0) 4568 #define RCC_FINDIV37CFGR_FINDIV37_SHIFT 0 4569 #define RCC_FINDIV37CFGR_FINDIV37EN BIT(6) 4570 4571 /* RCC_FINDIV38CFGR register fields */ 4572 #define RCC_FINDIV38CFGR_FINDIV38_MASK GENMASK_32(5, 0) 4573 #define RCC_FINDIV38CFGR_FINDIV38_SHIFT 0 4574 #define RCC_FINDIV38CFGR_FINDIV38EN BIT(6) 4575 4576 /* RCC_FINDIV39CFGR register fields */ 4577 #define RCC_FINDIV39CFGR_FINDIV39_MASK GENMASK_32(5, 0) 4578 #define RCC_FINDIV39CFGR_FINDIV39_SHIFT 0 4579 #define RCC_FINDIV39CFGR_FINDIV39EN BIT(6) 4580 4581 /* RCC_FINDIV40CFGR register fields */ 4582 #define RCC_FINDIV40CFGR_FINDIV40_MASK GENMASK_32(5, 0) 4583 #define RCC_FINDIV40CFGR_FINDIV40_SHIFT 0 4584 #define RCC_FINDIV40CFGR_FINDIV40EN BIT(6) 4585 4586 /* RCC_FINDIV41CFGR register fields */ 4587 #define RCC_FINDIV41CFGR_FINDIV41_MASK GENMASK_32(5, 0) 4588 #define RCC_FINDIV41CFGR_FINDIV41_SHIFT 0 4589 #define RCC_FINDIV41CFGR_FINDIV41EN BIT(6) 4590 4591 /* RCC_FINDIV42CFGR register fields */ 4592 #define RCC_FINDIV42CFGR_FINDIV42_MASK GENMASK_32(5, 0) 4593 #define RCC_FINDIV42CFGR_FINDIV42_SHIFT 0 4594 #define RCC_FINDIV42CFGR_FINDIV42EN BIT(6) 4595 4596 /* RCC_FINDIV43CFGR register fields */ 4597 #define RCC_FINDIV43CFGR_FINDIV43_MASK GENMASK_32(5, 0) 4598 #define RCC_FINDIV43CFGR_FINDIV43_SHIFT 0 4599 #define RCC_FINDIV43CFGR_FINDIV43EN BIT(6) 4600 4601 /* RCC_FINDIV44CFGR register fields */ 4602 #define RCC_FINDIV44CFGR_FINDIV44_MASK GENMASK_32(5, 0) 4603 #define RCC_FINDIV44CFGR_FINDIV44_SHIFT 0 4604 #define RCC_FINDIV44CFGR_FINDIV44EN BIT(6) 4605 4606 /* RCC_FINDIV45CFGR register fields */ 4607 #define RCC_FINDIV45CFGR_FINDIV45_MASK GENMASK_32(5, 0) 4608 #define RCC_FINDIV45CFGR_FINDIV45_SHIFT 0 4609 #define RCC_FINDIV45CFGR_FINDIV45EN BIT(6) 4610 4611 /* RCC_FINDIV46CFGR register fields */ 4612 #define RCC_FINDIV46CFGR_FINDIV46_MASK GENMASK_32(5, 0) 4613 #define RCC_FINDIV46CFGR_FINDIV46_SHIFT 0 4614 #define RCC_FINDIV46CFGR_FINDIV46EN BIT(6) 4615 4616 /* RCC_FINDIV47CFGR register fields */ 4617 #define RCC_FINDIV47CFGR_FINDIV47_MASK GENMASK_32(5, 0) 4618 #define RCC_FINDIV47CFGR_FINDIV47_SHIFT 0 4619 #define RCC_FINDIV47CFGR_FINDIV47EN BIT(6) 4620 4621 /* RCC_FINDIV48CFGR register fields */ 4622 #define RCC_FINDIV48CFGR_FINDIV48_MASK GENMASK_32(5, 0) 4623 #define RCC_FINDIV48CFGR_FINDIV48_SHIFT 0 4624 #define RCC_FINDIV48CFGR_FINDIV48EN BIT(6) 4625 4626 /* RCC_FINDIV49CFGR register fields */ 4627 #define RCC_FINDIV49CFGR_FINDIV49_MASK GENMASK_32(5, 0) 4628 #define RCC_FINDIV49CFGR_FINDIV49_SHIFT 0 4629 #define RCC_FINDIV49CFGR_FINDIV49EN BIT(6) 4630 4631 /* RCC_FINDIV50CFGR register fields */ 4632 #define RCC_FINDIV50CFGR_FINDIV50_MASK GENMASK_32(5, 0) 4633 #define RCC_FINDIV50CFGR_FINDIV50_SHIFT 0 4634 #define RCC_FINDIV50CFGR_FINDIV50EN BIT(6) 4635 4636 /* RCC_FINDIV51CFGR register fields */ 4637 #define RCC_FINDIV51CFGR_FINDIV51_MASK GENMASK_32(5, 0) 4638 #define RCC_FINDIV51CFGR_FINDIV51_SHIFT 0 4639 #define RCC_FINDIV51CFGR_FINDIV51EN BIT(6) 4640 4641 /* RCC_FINDIV52CFGR register fields */ 4642 #define RCC_FINDIV52CFGR_FINDIV52_MASK GENMASK_32(5, 0) 4643 #define RCC_FINDIV52CFGR_FINDIV52_SHIFT 0 4644 #define RCC_FINDIV52CFGR_FINDIV52EN BIT(6) 4645 4646 /* RCC_FINDIV53CFGR register fields */ 4647 #define RCC_FINDIV53CFGR_FINDIV53_MASK GENMASK_32(5, 0) 4648 #define RCC_FINDIV53CFGR_FINDIV53_SHIFT 0 4649 #define RCC_FINDIV53CFGR_FINDIV53EN BIT(6) 4650 4651 /* RCC_FINDIV54CFGR register fields */ 4652 #define RCC_FINDIV54CFGR_FINDIV54_MASK GENMASK_32(5, 0) 4653 #define RCC_FINDIV54CFGR_FINDIV54_SHIFT 0 4654 #define RCC_FINDIV54CFGR_FINDIV54EN BIT(6) 4655 4656 /* RCC_FINDIV55CFGR register fields */ 4657 #define RCC_FINDIV55CFGR_FINDIV55_MASK GENMASK_32(5, 0) 4658 #define RCC_FINDIV55CFGR_FINDIV55_SHIFT 0 4659 #define RCC_FINDIV55CFGR_FINDIV55EN BIT(6) 4660 4661 /* RCC_FINDIV56CFGR register fields */ 4662 #define RCC_FINDIV56CFGR_FINDIV56_MASK GENMASK_32(5, 0) 4663 #define RCC_FINDIV56CFGR_FINDIV56_SHIFT 0 4664 #define RCC_FINDIV56CFGR_FINDIV56EN BIT(6) 4665 4666 /* RCC_FINDIV57CFGR register fields */ 4667 #define RCC_FINDIV57CFGR_FINDIV57_MASK GENMASK_32(5, 0) 4668 #define RCC_FINDIV57CFGR_FINDIV57_SHIFT 0 4669 #define RCC_FINDIV57CFGR_FINDIV57EN BIT(6) 4670 4671 /* RCC_FINDIV58CFGR register fields */ 4672 #define RCC_FINDIV58CFGR_FINDIV58_MASK GENMASK_32(5, 0) 4673 #define RCC_FINDIV58CFGR_FINDIV58_SHIFT 0 4674 #define RCC_FINDIV58CFGR_FINDIV58EN BIT(6) 4675 4676 /* RCC_FINDIV59CFGR register fields */ 4677 #define RCC_FINDIV59CFGR_FINDIV59_MASK GENMASK_32(5, 0) 4678 #define RCC_FINDIV59CFGR_FINDIV59_SHIFT 0 4679 #define RCC_FINDIV59CFGR_FINDIV59EN BIT(6) 4680 4681 /* RCC_FINDIV60CFGR register fields */ 4682 #define RCC_FINDIV60CFGR_FINDIV60_MASK GENMASK_32(5, 0) 4683 #define RCC_FINDIV60CFGR_FINDIV60_SHIFT 0 4684 #define RCC_FINDIV60CFGR_FINDIV60EN BIT(6) 4685 4686 /* RCC_FINDIV61CFGR register fields */ 4687 #define RCC_FINDIV61CFGR_FINDIV61_MASK GENMASK_32(5, 0) 4688 #define RCC_FINDIV61CFGR_FINDIV61_SHIFT 0 4689 #define RCC_FINDIV61CFGR_FINDIV61EN BIT(6) 4690 4691 /* RCC_FINDIV62CFGR register fields */ 4692 #define RCC_FINDIV62CFGR_FINDIV62_MASK GENMASK_32(5, 0) 4693 #define RCC_FINDIV62CFGR_FINDIV62_SHIFT 0 4694 #define RCC_FINDIV62CFGR_FINDIV62EN BIT(6) 4695 4696 /* RCC_FINDIV63CFGR register fields */ 4697 #define RCC_FINDIV63CFGR_FINDIV63_MASK GENMASK_32(5, 0) 4698 #define RCC_FINDIV63CFGR_FINDIV63_SHIFT 0 4699 #define RCC_FINDIV63CFGR_FINDIV63EN BIT(6) 4700 4701 /* RCC_FINDIVxCFGR register fields */ 4702 #define RCC_FINDIVxCFGR_FINDIVx_MASK GENMASK_32(5, 0) 4703 #define RCC_FINDIVxCFGR_FINDIVx_SHIFT 0 4704 #define RCC_FINDIVxCFGR_FINDIVxEN BIT(6) 4705 4706 /* RCC_FCALCOBS0CFGR register fields */ 4707 #define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 4708 #define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 4709 #define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 4710 #define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 4711 #define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) 4712 #define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) 4713 #define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) 4714 #define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) 4715 #define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 4716 #define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 4717 #define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) 4718 #define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) 4719 4720 /* RCC_FCALCOBS1CFGR register fields */ 4721 #define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 4722 #define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 4723 #define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 4724 #define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 4725 #define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) 4726 #define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) 4727 #define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 4728 #define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 4729 #define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) 4730 #define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) 4731 4732 /* RCC_FCALCREFCFGR register fields */ 4733 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) 4734 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_SHIFT 0 4735 4736 /* RCC_FCALCCR1 register fields */ 4737 #define RCC_FCALCCR1_FCALCRUN BIT(0) 4738 4739 /* RCC_FCALCCR2 register fields */ 4740 #define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) 4741 #define RCC_FCALCCR2_FCALCMD_SHIFT 3 4742 #define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) 4743 #define RCC_FCALCCR2_FCALCTWC_SHIFT 11 4744 #define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) 4745 #define RCC_FCALCCR2_FCALCTYP_SHIFT 17 4746 4747 /* RCC_FCALCSR register fields */ 4748 #define RCC_FCALCSR_FVAL_MASK GENMASK_32(16, 0) 4749 #define RCC_FCALCSR_FVAL_SHIFT 0 4750 #define RCC_FCALCSR_FCALCSTS BIT(19) 4751 4752 /* RCC_PLL4CFGR1 register fields */ 4753 #define RCC_PLL4CFGR1_SSMODRST BIT(0) 4754 #define RCC_PLL4CFGR1_PLLEN BIT(8) 4755 #define RCC_PLL4CFGR1_PLLRDY BIT(24) 4756 #define RCC_PLL4CFGR1_CKREFST BIT(28) 4757 4758 /* RCC_PLL4CFGR2 register fields */ 4759 #define RCC_PLL4CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4760 #define RCC_PLL4CFGR2_FREFDIV_SHIFT 0 4761 #define RCC_PLL4CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4762 #define RCC_PLL4CFGR2_FBDIV_SHIFT 16 4763 4764 /* RCC_PLL4CFGR3 register fields */ 4765 #define RCC_PLL4CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4766 #define RCC_PLL4CFGR3_FRACIN_SHIFT 0 4767 #define RCC_PLL4CFGR3_DOWNSPREAD BIT(24) 4768 #define RCC_PLL4CFGR3_DACEN BIT(25) 4769 #define RCC_PLL4CFGR3_SSCGDIS BIT(26) 4770 4771 /* RCC_PLL4CFGR4 register fields */ 4772 #define RCC_PLL4CFGR4_DSMEN BIT(8) 4773 #define RCC_PLL4CFGR4_FOUTPOSTDIVEN BIT(9) 4774 #define RCC_PLL4CFGR4_BYPASS BIT(10) 4775 4776 /* RCC_PLL4CFGR5 register fields */ 4777 #define RCC_PLL4CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4778 #define RCC_PLL4CFGR5_DIVVAL_SHIFT 0 4779 #define RCC_PLL4CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4780 #define RCC_PLL4CFGR5_SPREAD_SHIFT 16 4781 4782 /* RCC_PLL4CFGR6 register fields */ 4783 #define RCC_PLL4CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4784 #define RCC_PLL4CFGR6_POSTDIV1_SHIFT 0 4785 4786 /* RCC_PLL4CFGR7 register fields */ 4787 #define RCC_PLL4CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4788 #define RCC_PLL4CFGR7_POSTDIV2_SHIFT 0 4789 4790 /* RCC_PLL5CFGR1 register fields */ 4791 #define RCC_PLL5CFGR1_SSMODRST BIT(0) 4792 #define RCC_PLL5CFGR1_PLLEN BIT(8) 4793 #define RCC_PLL5CFGR1_PLLRDY BIT(24) 4794 #define RCC_PLL5CFGR1_CKREFST BIT(28) 4795 4796 /* RCC_PLL5CFGR2 register fields */ 4797 #define RCC_PLL5CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4798 #define RCC_PLL5CFGR2_FREFDIV_SHIFT 0 4799 #define RCC_PLL5CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4800 #define RCC_PLL5CFGR2_FBDIV_SHIFT 16 4801 4802 /* RCC_PLL5CFGR3 register fields */ 4803 #define RCC_PLL5CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4804 #define RCC_PLL5CFGR3_FRACIN_SHIFT 0 4805 #define RCC_PLL5CFGR3_DOWNSPREAD BIT(24) 4806 #define RCC_PLL5CFGR3_DACEN BIT(25) 4807 #define RCC_PLL5CFGR3_SSCGDIS BIT(26) 4808 4809 /* RCC_PLL5CFGR4 register fields */ 4810 #define RCC_PLL5CFGR4_DSMEN BIT(8) 4811 #define RCC_PLL5CFGR4_FOUTPOSTDIVEN BIT(9) 4812 #define RCC_PLL5CFGR4_BYPASS BIT(10) 4813 4814 /* RCC_PLL5CFGR5 register fields */ 4815 #define RCC_PLL5CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4816 #define RCC_PLL5CFGR5_DIVVAL_SHIFT 0 4817 #define RCC_PLL5CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4818 #define RCC_PLL5CFGR5_SPREAD_SHIFT 16 4819 4820 /* RCC_PLL5CFGR6 register fields */ 4821 #define RCC_PLL5CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4822 #define RCC_PLL5CFGR6_POSTDIV1_SHIFT 0 4823 4824 /* RCC_PLL5CFGR7 register fields */ 4825 #define RCC_PLL5CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4826 #define RCC_PLL5CFGR7_POSTDIV2_SHIFT 0 4827 4828 /* RCC_PLL6CFGR1 register fields */ 4829 #define RCC_PLL6CFGR1_SSMODRST BIT(0) 4830 #define RCC_PLL6CFGR1_PLLEN BIT(8) 4831 #define RCC_PLL6CFGR1_PLLRDY BIT(24) 4832 #define RCC_PLL6CFGR1_CKREFST BIT(28) 4833 4834 /* RCC_PLL6CFGR2 register fields */ 4835 #define RCC_PLL6CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4836 #define RCC_PLL6CFGR2_FREFDIV_SHIFT 0 4837 #define RCC_PLL6CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4838 #define RCC_PLL6CFGR2_FBDIV_SHIFT 16 4839 4840 /* RCC_PLL6CFGR3 register fields */ 4841 #define RCC_PLL6CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4842 #define RCC_PLL6CFGR3_FRACIN_SHIFT 0 4843 #define RCC_PLL6CFGR3_DOWNSPREAD BIT(24) 4844 #define RCC_PLL6CFGR3_DACEN BIT(25) 4845 #define RCC_PLL6CFGR3_SSCGDIS BIT(26) 4846 4847 /* RCC_PLL6CFGR4 register fields */ 4848 #define RCC_PLL6CFGR4_DSMEN BIT(8) 4849 #define RCC_PLL6CFGR4_FOUTPOSTDIVEN BIT(9) 4850 #define RCC_PLL6CFGR4_BYPASS BIT(10) 4851 4852 /* RCC_PLL6CFGR5 register fields */ 4853 #define RCC_PLL6CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4854 #define RCC_PLL6CFGR5_DIVVAL_SHIFT 0 4855 #define RCC_PLL6CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4856 #define RCC_PLL6CFGR5_SPREAD_SHIFT 16 4857 4858 /* RCC_PLL6CFGR6 register fields */ 4859 #define RCC_PLL6CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4860 #define RCC_PLL6CFGR6_POSTDIV1_SHIFT 0 4861 4862 /* RCC_PLL6CFGR7 register fields */ 4863 #define RCC_PLL6CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4864 #define RCC_PLL6CFGR7_POSTDIV2_SHIFT 0 4865 4866 /* RCC_PLL7CFGR1 register fields */ 4867 #define RCC_PLL7CFGR1_SSMODRST BIT(0) 4868 #define RCC_PLL7CFGR1_PLLEN BIT(8) 4869 #define RCC_PLL7CFGR1_PLLRDY BIT(24) 4870 #define RCC_PLL7CFGR1_CKREFST BIT(28) 4871 4872 /* RCC_PLL7CFGR2 register fields */ 4873 #define RCC_PLL7CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4874 #define RCC_PLL7CFGR2_FREFDIV_SHIFT 0 4875 #define RCC_PLL7CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4876 #define RCC_PLL7CFGR2_FBDIV_SHIFT 16 4877 4878 /* RCC_PLL7CFGR3 register fields */ 4879 #define RCC_PLL7CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4880 #define RCC_PLL7CFGR3_FRACIN_SHIFT 0 4881 #define RCC_PLL7CFGR3_DOWNSPREAD BIT(24) 4882 #define RCC_PLL7CFGR3_DACEN BIT(25) 4883 #define RCC_PLL7CFGR3_SSCGDIS BIT(26) 4884 4885 /* RCC_PLL7CFGR4 register fields */ 4886 #define RCC_PLL7CFGR4_DSMEN BIT(8) 4887 #define RCC_PLL7CFGR4_FOUTPOSTDIVEN BIT(9) 4888 #define RCC_PLL7CFGR4_BYPASS BIT(10) 4889 4890 /* RCC_PLL7CFGR5 register fields */ 4891 #define RCC_PLL7CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4892 #define RCC_PLL7CFGR5_DIVVAL_SHIFT 0 4893 #define RCC_PLL7CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4894 #define RCC_PLL7CFGR5_SPREAD_SHIFT 16 4895 4896 /* RCC_PLL7CFGR6 register fields */ 4897 #define RCC_PLL7CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4898 #define RCC_PLL7CFGR6_POSTDIV1_SHIFT 0 4899 4900 /* RCC_PLL7CFGR7 register fields */ 4901 #define RCC_PLL7CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4902 #define RCC_PLL7CFGR7_POSTDIV2_SHIFT 0 4903 4904 /* RCC_PLL8CFGR1 register fields */ 4905 #define RCC_PLL8CFGR1_SSMODRST BIT(0) 4906 #define RCC_PLL8CFGR1_PLLEN BIT(8) 4907 #define RCC_PLL8CFGR1_PLLRDY BIT(24) 4908 #define RCC_PLL8CFGR1_CKREFST BIT(28) 4909 4910 /* RCC_PLL8CFGR2 register fields */ 4911 #define RCC_PLL8CFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4912 #define RCC_PLL8CFGR2_FREFDIV_SHIFT 0 4913 #define RCC_PLL8CFGR2_FBDIV_MASK GENMASK_32(27, 16) 4914 #define RCC_PLL8CFGR2_FBDIV_SHIFT 16 4915 4916 /* RCC_PLL8CFGR3 register fields */ 4917 #define RCC_PLL8CFGR3_FRACIN_MASK GENMASK_32(23, 0) 4918 #define RCC_PLL8CFGR3_FRACIN_SHIFT 0 4919 #define RCC_PLL8CFGR3_DOWNSPREAD BIT(24) 4920 #define RCC_PLL8CFGR3_DACEN BIT(25) 4921 #define RCC_PLL8CFGR3_SSCGDIS BIT(26) 4922 4923 /* RCC_PLL8CFGR4 register fields */ 4924 #define RCC_PLL8CFGR4_DSMEN BIT(8) 4925 #define RCC_PLL8CFGR4_FOUTPOSTDIVEN BIT(9) 4926 #define RCC_PLL8CFGR4_BYPASS BIT(10) 4927 4928 /* RCC_PLL8CFGR5 register fields */ 4929 #define RCC_PLL8CFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4930 #define RCC_PLL8CFGR5_DIVVAL_SHIFT 0 4931 #define RCC_PLL8CFGR5_SPREAD_MASK GENMASK_32(20, 16) 4932 #define RCC_PLL8CFGR5_SPREAD_SHIFT 16 4933 4934 /* RCC_PLL8CFGR6 register fields */ 4935 #define RCC_PLL8CFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4936 #define RCC_PLL8CFGR6_POSTDIV1_SHIFT 0 4937 4938 /* RCC_PLL8CFGR7 register fields */ 4939 #define RCC_PLL8CFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4940 #define RCC_PLL8CFGR7_POSTDIV2_SHIFT 0 4941 4942 /* RCC_PLLxCFGR1 register fields */ 4943 #define RCC_PLLxCFGR1_SSMODRST BIT(0) 4944 #define RCC_PLLxCFGR1_PLLEN BIT(8) 4945 #define RCC_PLLxCFGR1_PLLRDY BIT(24) 4946 #define RCC_PLLxCFGR1_CKREFST BIT(28) 4947 4948 /* RCC_PLLxCFGR2 register fields */ 4949 #define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) 4950 #define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 4951 #define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) 4952 #define RCC_PLLxCFGR2_FBDIV_SHIFT 16 4953 4954 /* RCC_PLLxCFGR3 register fields */ 4955 #define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) 4956 #define RCC_PLLxCFGR3_FRACIN_SHIFT 0 4957 #define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) 4958 #define RCC_PLLxCFGR3_DACEN BIT(25) 4959 #define RCC_PLLxCFGR3_SSCGDIS BIT(26) 4960 4961 /* RCC_PLLxCFGR4 register fields */ 4962 #define RCC_PLLxCFGR4_DSMEN BIT(8) 4963 #define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) 4964 #define RCC_PLLxCFGR4_BYPASS BIT(10) 4965 4966 /* RCC_PLLxCFGR5 register fields */ 4967 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) 4968 #define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 4969 #define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) 4970 #define RCC_PLLxCFGR5_SPREAD_SHIFT 16 4971 4972 /* RCC_PLLxCFGR6 register fields */ 4973 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 4974 #define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 4975 4976 /* RCC_PLLxCFGR7 register fields */ 4977 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 4978 #define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 4979 4980 /* RCC_VERR register fields */ 4981 #define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) 4982 #define RCC_VERR_MINREV_SHIFT 0 4983 #define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) 4984 #define RCC_VERR_MAJREV_SHIFT 4 4985 4986 #endif /* STM32MP2_RCC_H */ 4987