1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * GPIO driver for AMD
4 *
5 * Copyright (c) 2014,2015 AMD Corporation.
6 * Authors: Ken Xue <[email protected]>
7 * Wu, Jeff <[email protected]>
8 *
9 */
10
11 #include <linux/err.h>
12 #include <linux/bug.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/compiler.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/log2.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/slab.h>
23 #include <linux/platform_device.h>
24 #include <linux/mutex.h>
25 #include <linux/acpi.h>
26 #include <linux/seq_file.h>
27 #include <linux/interrupt.h>
28 #include <linux/list.h>
29 #include <linux/bitops.h>
30 #include <linux/pinctrl/pinconf.h>
31 #include <linux/pinctrl/pinconf-generic.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/string_choices.h>
34 #include <linux/suspend.h>
35
36 #include "core.h"
37 #include "pinctrl-utils.h"
38 #include "pinctrl-amd.h"
39
amd_gpio_get_direction(struct gpio_chip * gc,unsigned offset)40 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
41 {
42 unsigned long flags;
43 u32 pin_reg;
44 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
45
46 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
47 pin_reg = readl(gpio_dev->base + offset * 4);
48 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
51 return GPIO_LINE_DIRECTION_OUT;
52
53 return GPIO_LINE_DIRECTION_IN;
54 }
55
amd_gpio_direction_input(struct gpio_chip * gc,unsigned offset)56 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
57 {
58 unsigned long flags;
59 u32 pin_reg;
60 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
61
62 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
63 pin_reg = readl(gpio_dev->base + offset * 4);
64 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
65 writel(pin_reg, gpio_dev->base + offset * 4);
66 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
67
68 return 0;
69 }
70
amd_gpio_direction_output(struct gpio_chip * gc,unsigned offset,int value)71 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
72 int value)
73 {
74 u32 pin_reg;
75 unsigned long flags;
76 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
77
78 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
79 pin_reg = readl(gpio_dev->base + offset * 4);
80 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 if (value)
82 pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 else
84 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
85 writel(pin_reg, gpio_dev->base + offset * 4);
86 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
87
88 return 0;
89 }
90
amd_gpio_get_value(struct gpio_chip * gc,unsigned offset)91 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
92 {
93 u32 pin_reg;
94 unsigned long flags;
95 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
96
97 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
98 pin_reg = readl(gpio_dev->base + offset * 4);
99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
100
101 return !!(pin_reg & BIT(PIN_STS_OFF));
102 }
103
amd_gpio_set_value(struct gpio_chip * gc,unsigned offset,int value)104 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
105 {
106 u32 pin_reg;
107 unsigned long flags;
108 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
109
110 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
111 pin_reg = readl(gpio_dev->base + offset * 4);
112 if (value)
113 pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 else
115 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
116 writel(pin_reg, gpio_dev->base + offset * 4);
117 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
118 }
119
amd_gpio_set_debounce(struct amd_gpio * gpio_dev,unsigned int offset,unsigned int debounce)120 static int amd_gpio_set_debounce(struct amd_gpio *gpio_dev, unsigned int offset,
121 unsigned int debounce)
122 {
123 u32 time;
124 u32 pin_reg;
125 int ret = 0;
126
127 /* Use special handling for Pin0 debounce */
128 if (offset == 0) {
129 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
130 if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
131 debounce = 0;
132 }
133
134 pin_reg = readl(gpio_dev->base + offset * 4);
135
136 if (debounce) {
137 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
138 pin_reg &= ~DB_TMR_OUT_MASK;
139 /*
140 Debounce Debounce Timer Max
141 TmrLarge TmrOutUnit Unit Debounce
142 Time
143 0 0 61 usec (2 RtcClk) 976 usec
144 0 1 244 usec (8 RtcClk) 3.9 msec
145 1 0 15.6 msec (512 RtcClk) 250 msec
146 1 1 62.5 msec (2048 RtcClk) 1 sec
147 */
148
149 if (debounce < 61) {
150 pin_reg |= 1;
151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
153 } else if (debounce < 976) {
154 time = debounce / 61;
155 pin_reg |= time & DB_TMR_OUT_MASK;
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 } else if (debounce < 3900) {
159 time = debounce / 244;
160 pin_reg |= time & DB_TMR_OUT_MASK;
161 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
162 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
163 } else if (debounce < 250000) {
164 time = debounce / 15625;
165 pin_reg |= time & DB_TMR_OUT_MASK;
166 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
167 pin_reg |= BIT(DB_TMR_LARGE_OFF);
168 } else if (debounce < 1000000) {
169 time = debounce / 62500;
170 pin_reg |= time & DB_TMR_OUT_MASK;
171 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
172 pin_reg |= BIT(DB_TMR_LARGE_OFF);
173 } else {
174 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
175 ret = -EINVAL;
176 }
177 } else {
178 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
179 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
180 pin_reg &= ~DB_TMR_OUT_MASK;
181 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
182 }
183 writel(pin_reg, gpio_dev->base + offset * 4);
184
185 return ret;
186 }
187
188 #ifdef CONFIG_DEBUG_FS
amd_gpio_dbg_show(struct seq_file * s,struct gpio_chip * gc)189 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
190 {
191 u32 pin_reg;
192 u32 db_cntrl;
193 unsigned long flags;
194 unsigned int bank, i, pin_num;
195 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
196
197 bool tmr_out_unit;
198 bool tmr_large;
199
200 char *level_trig;
201 char *active_level;
202 char *interrupt_mask;
203 char *wake_cntrl0;
204 char *wake_cntrl1;
205 char *wake_cntrl2;
206 char *pin_sts;
207 char *interrupt_sts;
208 char *wake_sts;
209 char *orientation;
210 char debounce_value[40];
211 char *debounce_enable;
212 char *wake_cntrlz;
213
214 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG));
215 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
216 unsigned int time = 0;
217 unsigned int unit = 0;
218
219 switch (bank) {
220 case 0:
221 i = 0;
222 pin_num = AMD_GPIO_PINS_BANK0;
223 break;
224 case 1:
225 i = 64;
226 pin_num = AMD_GPIO_PINS_BANK1 + i;
227 break;
228 case 2:
229 i = 128;
230 pin_num = AMD_GPIO_PINS_BANK2 + i;
231 break;
232 case 3:
233 i = 192;
234 pin_num = AMD_GPIO_PINS_BANK3 + i;
235 break;
236 default:
237 /* Illegal bank number, ignore */
238 continue;
239 }
240 seq_printf(s, "GPIO bank%d\n", bank);
241 seq_puts(s, "gpio\t int|active|trigger|S0i3| S3|S4/S5| Z|wake|pull| orient| debounce|reg\n");
242 for (; i < pin_num; i++) {
243 seq_printf(s, "#%d\t", i);
244 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
245 pin_reg = readl(gpio_dev->base + i * 4);
246 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
247
248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
250 ACTIVE_LEVEL_MASK;
251
252 if (level == ACTIVE_LEVEL_HIGH)
253 active_level = "↑";
254 else if (level == ACTIVE_LEVEL_LOW)
255 active_level = "↓";
256 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
257 level == ACTIVE_LEVEL_BOTH)
258 active_level = "b";
259 else
260 active_level = "?";
261
262 if (pin_reg & BIT(LEVEL_TRIG_OFF))
263 level_trig = "level";
264 else
265 level_trig = " edge";
266
267 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
268 interrupt_mask = "��";
269 else
270 interrupt_mask = "��";
271
272 if (pin_reg & BIT(INTERRUPT_STS_OFF))
273 interrupt_sts = "��";
274 else
275 interrupt_sts = " ";
276
277 seq_printf(s, "%s %s| %s| %s|",
278 interrupt_sts,
279 interrupt_mask,
280 active_level,
281 level_trig);
282 } else
283 seq_puts(s, " ∅| | |");
284
285 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
286 wake_cntrl0 = "⏰";
287 else
288 wake_cntrl0 = " ";
289 seq_printf(s, " %s| ", wake_cntrl0);
290
291 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
292 wake_cntrl1 = "⏰";
293 else
294 wake_cntrl1 = " ";
295 seq_printf(s, "%s|", wake_cntrl1);
296
297 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
298 wake_cntrl2 = "⏰";
299 else
300 wake_cntrl2 = " ";
301 seq_printf(s, " %s|", wake_cntrl2);
302
303 if (pin_reg & BIT(WAKECNTRL_Z_OFF))
304 wake_cntrlz = "⏰";
305 else
306 wake_cntrlz = " ";
307 seq_printf(s, "%s|", wake_cntrlz);
308
309 if (pin_reg & BIT(WAKE_STS_OFF))
310 wake_sts = "��";
311 else
312 wake_sts = " ";
313 seq_printf(s, " %s|", wake_sts);
314
315 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
316 seq_puts(s, " ↑ |");
317 } else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
318 seq_puts(s, " ↓ |");
319 } else {
320 seq_puts(s, " |");
321 }
322
323 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
324 pin_sts = "output";
325 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
326 orientation = "↑";
327 else
328 orientation = "↓";
329 } else {
330 pin_sts = "input ";
331 if (pin_reg & BIT(PIN_STS_OFF))
332 orientation = "↑";
333 else
334 orientation = "↓";
335 }
336 seq_printf(s, "%s %s|", pin_sts, orientation);
337
338 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
339 if (db_cntrl) {
340 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
341 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
342 time = pin_reg & DB_TMR_OUT_MASK;
343 if (tmr_large) {
344 if (tmr_out_unit)
345 unit = 62500;
346 else
347 unit = 15625;
348 } else {
349 if (tmr_out_unit)
350 unit = 244;
351 else
352 unit = 61;
353 }
354 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
355 debounce_enable = "b";
356 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
357 debounce_enable = "↓";
358 else
359 debounce_enable = "↑";
360 snprintf(debounce_value, sizeof(debounce_value), "%06u", time * unit);
361 seq_printf(s, "%s (�� %sus)|", debounce_enable, debounce_value);
362 } else {
363 seq_puts(s, " |");
364 }
365 seq_printf(s, "0x%x\n", pin_reg);
366 }
367 }
368 }
369 #else
370 #define amd_gpio_dbg_show NULL
371 #endif
372
amd_gpio_irq_enable(struct irq_data * d)373 static void amd_gpio_irq_enable(struct irq_data *d)
374 {
375 u32 pin_reg;
376 unsigned long flags;
377 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
378 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
379
380 gpiochip_enable_irq(gc, d->hwirq);
381
382 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
383 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
384 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
385 pin_reg |= BIT(INTERRUPT_MASK_OFF);
386 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
387 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
388 }
389
amd_gpio_irq_disable(struct irq_data * d)390 static void amd_gpio_irq_disable(struct irq_data *d)
391 {
392 u32 pin_reg;
393 unsigned long flags;
394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
395 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
396
397 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
398 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
399 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
400 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
401 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
402 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
403
404 gpiochip_disable_irq(gc, d->hwirq);
405 }
406
amd_gpio_irq_mask(struct irq_data * d)407 static void amd_gpio_irq_mask(struct irq_data *d)
408 {
409 u32 pin_reg;
410 unsigned long flags;
411 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
412 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
413
414 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
415 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
416 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
417 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
418 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
419 }
420
amd_gpio_irq_unmask(struct irq_data * d)421 static void amd_gpio_irq_unmask(struct irq_data *d)
422 {
423 u32 pin_reg;
424 unsigned long flags;
425 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
426 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
427
428 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
429 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
430 pin_reg |= BIT(INTERRUPT_MASK_OFF);
431 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
432 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
433 }
434
amd_gpio_irq_set_wake(struct irq_data * d,unsigned int on)435 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
436 {
437 u32 pin_reg;
438 unsigned long flags;
439 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
440 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
441 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
442 int err;
443
444 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
445 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
446
447 if (on)
448 pin_reg |= wake_mask;
449 else
450 pin_reg &= ~wake_mask;
451
452 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
453 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
454
455 if (on)
456 err = enable_irq_wake(gpio_dev->irq);
457 else
458 err = disable_irq_wake(gpio_dev->irq);
459
460 if (err)
461 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
462 str_enable_disable(on));
463
464 return 0;
465 }
466
amd_gpio_irq_eoi(struct irq_data * d)467 static void amd_gpio_irq_eoi(struct irq_data *d)
468 {
469 u32 reg;
470 unsigned long flags;
471 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
472 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
473
474 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
475 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
476 reg |= EOI_MASK;
477 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
478 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
479 }
480
amd_gpio_irq_set_type(struct irq_data * d,unsigned int type)481 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
482 {
483 int ret = 0;
484 u32 pin_reg, pin_reg_irq_en, mask;
485 unsigned long flags;
486 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
487 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
488
489 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
490 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
491
492 switch (type & IRQ_TYPE_SENSE_MASK) {
493 case IRQ_TYPE_EDGE_RISING:
494 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
495 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
496 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
497 irq_set_handler_locked(d, handle_edge_irq);
498 break;
499
500 case IRQ_TYPE_EDGE_FALLING:
501 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
502 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
503 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
504 irq_set_handler_locked(d, handle_edge_irq);
505 break;
506
507 case IRQ_TYPE_EDGE_BOTH:
508 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
509 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
510 pin_reg |= BOTH_EDGES << ACTIVE_LEVEL_OFF;
511 irq_set_handler_locked(d, handle_edge_irq);
512 break;
513
514 case IRQ_TYPE_LEVEL_HIGH:
515 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
516 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
517 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
518 irq_set_handler_locked(d, handle_level_irq);
519 break;
520
521 case IRQ_TYPE_LEVEL_LOW:
522 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
523 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
524 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
525 irq_set_handler_locked(d, handle_level_irq);
526 break;
527
528 case IRQ_TYPE_NONE:
529 break;
530
531 default:
532 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
533 ret = -EINVAL;
534 }
535
536 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
537 /*
538 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
539 * debounce registers of any GPIO will block wake/interrupt status
540 * generation for *all* GPIOs for a length of time that depends on
541 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
542 * INTERRUPT_ENABLE bit will read as 0.
543 *
544 * We temporarily enable irq for the GPIO whose configuration is
545 * changing, and then wait for it to read back as 1 to know when
546 * debounce has settled and then disable the irq again.
547 * We do this polling with the spinlock held to ensure other GPIO
548 * access routines do not read an incorrect value for the irq enable
549 * bit of other GPIOs. We keep the GPIO masked while polling to avoid
550 * spurious irqs, and disable the irq again after polling.
551 */
552 mask = BIT(INTERRUPT_ENABLE_OFF);
553 pin_reg_irq_en = pin_reg;
554 pin_reg_irq_en |= mask;
555 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
556 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
557 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
558 continue;
559 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
560 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
561
562 return ret;
563 }
564
amd_irq_ack(struct irq_data * d)565 static void amd_irq_ack(struct irq_data *d)
566 {
567 /*
568 * based on HW design,there is no need to ack HW
569 * before handle current irq. But this routine is
570 * necessary for handle_edge_irq
571 */
572 }
573
574 static const struct irq_chip amd_gpio_irqchip = {
575 .name = "amd_gpio",
576 .irq_ack = amd_irq_ack,
577 .irq_enable = amd_gpio_irq_enable,
578 .irq_disable = amd_gpio_irq_disable,
579 .irq_mask = amd_gpio_irq_mask,
580 .irq_unmask = amd_gpio_irq_unmask,
581 .irq_set_wake = amd_gpio_irq_set_wake,
582 .irq_eoi = amd_gpio_irq_eoi,
583 .irq_set_type = amd_gpio_irq_set_type,
584 /*
585 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
586 * also generates an IRQ. We need the IRQ so the irq_handler can clear
587 * the wake event. Otherwise the wake event will never clear and
588 * prevent the system from suspending.
589 */
590 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE,
591 GPIOCHIP_IRQ_RESOURCE_HELPERS,
592 };
593
594 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
595
do_amd_gpio_irq_handler(int irq,void * dev_id)596 static bool do_amd_gpio_irq_handler(int irq, void *dev_id)
597 {
598 struct amd_gpio *gpio_dev = dev_id;
599 struct gpio_chip *gc = &gpio_dev->gc;
600 unsigned int i, irqnr;
601 unsigned long flags;
602 u32 __iomem *regs;
603 bool ret = false;
604 u32 regval;
605 u64 status, mask;
606
607 /* Read the wake status */
608 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
609 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
610 status <<= 32;
611 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
612 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
613
614 /* Bit 0-45 contain the relevant status bits */
615 status &= (1ULL << 46) - 1;
616 regs = gpio_dev->base;
617 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
618 if (!(status & mask))
619 continue;
620 status &= ~mask;
621
622 /* Each status bit covers four pins */
623 for (i = 0; i < 4; i++) {
624 regval = readl(regs + i);
625
626 if (regval & PIN_IRQ_PENDING)
627 pm_pr_dbg("GPIO %d is active: 0x%x",
628 irqnr + i, regval);
629
630 /* caused wake on resume context for shared IRQ */
631 if (irq < 0 && (regval & BIT(WAKE_STS_OFF)))
632 return true;
633
634 if (!(regval & PIN_IRQ_PENDING) ||
635 !(regval & BIT(INTERRUPT_MASK_OFF)))
636 continue;
637 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i);
638
639 /* Clear interrupt.
640 * We must read the pin register again, in case the
641 * value was changed while executing
642 * generic_handle_domain_irq() above.
643 * If the line is not an irq, disable it in order to
644 * avoid a system hang caused by an interrupt storm.
645 */
646 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
647 regval = readl(regs + i);
648 if (!gpiochip_line_is_irq(gc, irqnr + i)) {
649 regval &= ~BIT(INTERRUPT_MASK_OFF);
650 dev_dbg(&gpio_dev->pdev->dev,
651 "Disabling spurious GPIO IRQ %d\n",
652 irqnr + i);
653 } else {
654 ret = true;
655 }
656 writel(regval, regs + i);
657 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
658 }
659 }
660 /* did not cause wake on resume context for shared IRQ */
661 if (irq < 0)
662 return false;
663
664 /* Signal EOI to the GPIO unit */
665 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
666 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
667 regval |= EOI_MASK;
668 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
669 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
670
671 return ret;
672 }
673
amd_gpio_irq_handler(int irq,void * dev_id)674 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
675 {
676 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id));
677 }
678
amd_gpio_check_wake(void * dev_id)679 static bool __maybe_unused amd_gpio_check_wake(void *dev_id)
680 {
681 return do_amd_gpio_irq_handler(-1, dev_id);
682 }
683
amd_get_groups_count(struct pinctrl_dev * pctldev)684 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
685 {
686 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
687
688 return gpio_dev->ngroups;
689 }
690
amd_get_group_name(struct pinctrl_dev * pctldev,unsigned group)691 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
692 unsigned group)
693 {
694 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
695
696 return gpio_dev->groups[group].name;
697 }
698
amd_get_group_pins(struct pinctrl_dev * pctldev,unsigned group,const unsigned ** pins,unsigned * num_pins)699 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
700 unsigned group,
701 const unsigned **pins,
702 unsigned *num_pins)
703 {
704 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
705
706 *pins = gpio_dev->groups[group].pins;
707 *num_pins = gpio_dev->groups[group].npins;
708 return 0;
709 }
710
711 static const struct pinctrl_ops amd_pinctrl_ops = {
712 .get_groups_count = amd_get_groups_count,
713 .get_group_name = amd_get_group_name,
714 .get_group_pins = amd_get_group_pins,
715 #ifdef CONFIG_OF
716 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
717 .dt_free_map = pinctrl_utils_free_map,
718 #endif
719 };
720
amd_pinconf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)721 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
722 unsigned int pin,
723 unsigned long *config)
724 {
725 u32 pin_reg;
726 unsigned arg;
727 unsigned long flags;
728 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
729 enum pin_config_param param = pinconf_to_config_param(*config);
730
731 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
732 pin_reg = readl(gpio_dev->base + pin*4);
733 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
734 switch (param) {
735 case PIN_CONFIG_INPUT_DEBOUNCE:
736 arg = pin_reg & DB_TMR_OUT_MASK;
737 break;
738
739 case PIN_CONFIG_BIAS_PULL_DOWN:
740 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
741 break;
742
743 case PIN_CONFIG_BIAS_PULL_UP:
744 arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
745 break;
746
747 case PIN_CONFIG_DRIVE_STRENGTH:
748 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
749 break;
750
751 default:
752 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
753 param);
754 return -ENOTSUPP;
755 }
756
757 *config = pinconf_to_config_packed(param, arg);
758
759 return 0;
760 }
761
amd_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)762 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
763 unsigned long *configs, unsigned int num_configs)
764 {
765 int i;
766 u32 arg;
767 int ret = 0;
768 u32 pin_reg;
769 unsigned long flags;
770 enum pin_config_param param;
771 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
772
773 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
774 for (i = 0; i < num_configs; i++) {
775 param = pinconf_to_config_param(configs[i]);
776 arg = pinconf_to_config_argument(configs[i]);
777 pin_reg = readl(gpio_dev->base + pin*4);
778
779 switch (param) {
780 case PIN_CONFIG_INPUT_DEBOUNCE:
781 ret = amd_gpio_set_debounce(gpio_dev, pin, arg);
782 goto out_unlock;
783
784 case PIN_CONFIG_BIAS_PULL_DOWN:
785 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
786 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
787 break;
788
789 case PIN_CONFIG_BIAS_PULL_UP:
790 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
791 pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
792 break;
793
794 case PIN_CONFIG_DRIVE_STRENGTH:
795 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
796 << DRV_STRENGTH_SEL_OFF);
797 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
798 << DRV_STRENGTH_SEL_OFF;
799 break;
800
801 default:
802 dev_dbg(&gpio_dev->pdev->dev,
803 "Invalid config param %04x\n", param);
804 ret = -ENOTSUPP;
805 }
806
807 writel(pin_reg, gpio_dev->base + pin*4);
808 }
809 out_unlock:
810 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
811
812 return ret;
813 }
814
amd_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)815 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
816 unsigned int group,
817 unsigned long *config)
818 {
819 const unsigned *pins;
820 unsigned npins;
821 int ret;
822
823 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
824 if (ret)
825 return ret;
826
827 if (amd_pinconf_get(pctldev, pins[0], config))
828 return -ENOTSUPP;
829
830 return 0;
831 }
832
amd_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned group,unsigned long * configs,unsigned num_configs)833 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
834 unsigned group, unsigned long *configs,
835 unsigned num_configs)
836 {
837 const unsigned *pins;
838 unsigned npins;
839 int i, ret;
840
841 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
842 if (ret)
843 return ret;
844 for (i = 0; i < npins; i++) {
845 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
846 return -ENOTSUPP;
847 }
848 return 0;
849 }
850
amd_gpio_set_config(struct gpio_chip * gc,unsigned int pin,unsigned long config)851 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin,
852 unsigned long config)
853 {
854 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
855
856 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1);
857 }
858
859 static const struct pinconf_ops amd_pinconf_ops = {
860 .pin_config_get = amd_pinconf_get,
861 .pin_config_set = amd_pinconf_set,
862 .pin_config_group_get = amd_pinconf_group_get,
863 .pin_config_group_set = amd_pinconf_group_set,
864 };
865
amd_gpio_irq_init(struct amd_gpio * gpio_dev)866 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev)
867 {
868 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
869 unsigned long flags;
870 u32 pin_reg, mask;
871 int i;
872
873 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
874 BIT(WAKE_CNTRL_OFF_S4);
875
876 for (i = 0; i < desc->npins; i++) {
877 int pin = desc->pins[i].number;
878 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
879
880 if (!pd)
881 continue;
882
883 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
884
885 pin_reg = readl(gpio_dev->base + pin * 4);
886 pin_reg &= ~mask;
887 writel(pin_reg, gpio_dev->base + pin * 4);
888
889 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
890 }
891 }
892
893 #ifdef CONFIG_PM_SLEEP
amd_gpio_should_save(struct amd_gpio * gpio_dev,unsigned int pin)894 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
895 {
896 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
897
898 if (!pd)
899 return false;
900
901 /*
902 * Only restore the pin if it is actually in use by the kernel (or
903 * by userspace).
904 */
905 if (pd->mux_owner || pd->gpio_owner ||
906 gpiochip_line_is_irq(&gpio_dev->gc, pin))
907 return true;
908
909 return false;
910 }
911
amd_gpio_suspend_hibernate_common(struct device * dev,bool is_suspend)912 static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
913 {
914 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
915 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
916 unsigned long flags;
917 int i;
918 u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
919
920 for (i = 0; i < desc->npins; i++) {
921 int pin = desc->pins[i].number;
922
923 if (!amd_gpio_should_save(gpio_dev, pin))
924 continue;
925
926 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
927 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
928
929 /* mask any interrupts not intended to be a wake source */
930 if (!(gpio_dev->saved_regs[i] & wake_mask)) {
931 writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
932 gpio_dev->base + pin * 4);
933 pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n",
934 pin, is_suspend ? "suspend" : "hibernate");
935 }
936
937 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
938 }
939
940 return 0;
941 }
942
amd_gpio_suspend(struct device * dev)943 static int amd_gpio_suspend(struct device *dev)
944 {
945 return amd_gpio_suspend_hibernate_common(dev, true);
946 }
947
amd_gpio_hibernate(struct device * dev)948 static int amd_gpio_hibernate(struct device *dev)
949 {
950 return amd_gpio_suspend_hibernate_common(dev, false);
951 }
952
amd_gpio_resume(struct device * dev)953 static int amd_gpio_resume(struct device *dev)
954 {
955 struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
956 struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
957 unsigned long flags;
958 int i;
959
960 for (i = 0; i < desc->npins; i++) {
961 int pin = desc->pins[i].number;
962
963 if (!amd_gpio_should_save(gpio_dev, pin))
964 continue;
965
966 raw_spin_lock_irqsave(&gpio_dev->lock, flags);
967 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING;
968 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4);
969 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
970 }
971
972 return 0;
973 }
974
975 static const struct dev_pm_ops amd_gpio_pm_ops = {
976 .suspend_late = amd_gpio_suspend,
977 .resume_early = amd_gpio_resume,
978 .freeze_late = amd_gpio_hibernate,
979 .thaw_early = amd_gpio_resume,
980 .poweroff_late = amd_gpio_hibernate,
981 .restore_early = amd_gpio_resume,
982 };
983 #endif
984
amd_get_functions_count(struct pinctrl_dev * pctldev)985 static int amd_get_functions_count(struct pinctrl_dev *pctldev)
986 {
987 return ARRAY_SIZE(pmx_functions);
988 }
989
amd_get_fname(struct pinctrl_dev * pctrldev,unsigned int selector)990 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector)
991 {
992 return pmx_functions[selector].name;
993 }
994
amd_get_groups(struct pinctrl_dev * pctrldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)995 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector,
996 const char * const **groups,
997 unsigned int * const num_groups)
998 {
999 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1000
1001 if (!gpio_dev->iomux_base) {
1002 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector);
1003 return -EINVAL;
1004 }
1005
1006 *groups = pmx_functions[selector].groups;
1007 *num_groups = pmx_functions[selector].ngroups;
1008 return 0;
1009 }
1010
amd_set_mux(struct pinctrl_dev * pctrldev,unsigned int function,unsigned int group)1011 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group)
1012 {
1013 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev);
1014 struct device *dev = &gpio_dev->pdev->dev;
1015 struct pin_desc *pd;
1016 int ind, index;
1017
1018 if (!gpio_dev->iomux_base)
1019 return -EINVAL;
1020
1021 for (index = 0; index < NSELECTS; index++) {
1022 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index]))
1023 continue;
1024
1025 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) ==
1026 FUNCTION_INVALID) {
1027 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1028 pmx_functions[function].index);
1029 return -EINVAL;
1030 }
1031
1032 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index);
1033
1034 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) &
1035 FUNCTION_MASK)) {
1036 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n",
1037 pmx_functions[function].index);
1038 return -EINVAL;
1039 }
1040
1041 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) {
1042 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F")))
1043 continue;
1044
1045 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]);
1046 pd->mux_owner = gpio_dev->groups[group].name;
1047 }
1048 break;
1049 }
1050
1051 return 0;
1052 }
1053
1054 static const struct pinmux_ops amd_pmxops = {
1055 .get_functions_count = amd_get_functions_count,
1056 .get_function_name = amd_get_fname,
1057 .get_function_groups = amd_get_groups,
1058 .set_mux = amd_set_mux,
1059 };
1060
1061 static struct pinctrl_desc amd_pinctrl_desc = {
1062 .pins = kerncz_pins,
1063 .npins = ARRAY_SIZE(kerncz_pins),
1064 .pctlops = &amd_pinctrl_ops,
1065 .pmxops = &amd_pmxops,
1066 .confops = &amd_pinconf_ops,
1067 .owner = THIS_MODULE,
1068 };
1069
amd_get_iomux_res(struct amd_gpio * gpio_dev)1070 static void amd_get_iomux_res(struct amd_gpio *gpio_dev)
1071 {
1072 struct pinctrl_desc *desc = &amd_pinctrl_desc;
1073 struct device *dev = &gpio_dev->pdev->dev;
1074 int index;
1075
1076 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux");
1077 if (index < 0) {
1078 dev_dbg(dev, "iomux not supported\n");
1079 goto out_no_pinmux;
1080 }
1081
1082 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index);
1083 if (IS_ERR(gpio_dev->iomux_base)) {
1084 dev_dbg(dev, "iomux not supported %d io resource\n", index);
1085 goto out_no_pinmux;
1086 }
1087
1088 return;
1089
1090 out_no_pinmux:
1091 desc->pmxops = NULL;
1092 }
1093
amd_gpio_probe(struct platform_device * pdev)1094 static int amd_gpio_probe(struct platform_device *pdev)
1095 {
1096 int ret = 0;
1097 struct resource *res;
1098 struct amd_gpio *gpio_dev;
1099 struct gpio_irq_chip *girq;
1100
1101 gpio_dev = devm_kzalloc(&pdev->dev,
1102 sizeof(struct amd_gpio), GFP_KERNEL);
1103 if (!gpio_dev)
1104 return -ENOMEM;
1105
1106 raw_spin_lock_init(&gpio_dev->lock);
1107
1108 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1109 if (IS_ERR(gpio_dev->base)) {
1110 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
1111 return PTR_ERR(gpio_dev->base);
1112 }
1113
1114 gpio_dev->irq = platform_get_irq(pdev, 0);
1115 if (gpio_dev->irq < 0)
1116 return gpio_dev->irq;
1117
1118 #ifdef CONFIG_PM_SLEEP
1119 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
1120 sizeof(*gpio_dev->saved_regs),
1121 GFP_KERNEL);
1122 if (!gpio_dev->saved_regs)
1123 return -ENOMEM;
1124 #endif
1125
1126 gpio_dev->pdev = pdev;
1127 gpio_dev->gc.get_direction = amd_gpio_get_direction;
1128 gpio_dev->gc.direction_input = amd_gpio_direction_input;
1129 gpio_dev->gc.direction_output = amd_gpio_direction_output;
1130 gpio_dev->gc.get = amd_gpio_get_value;
1131 gpio_dev->gc.set = amd_gpio_set_value;
1132 gpio_dev->gc.set_config = amd_gpio_set_config;
1133 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
1134
1135 gpio_dev->gc.base = -1;
1136 gpio_dev->gc.label = pdev->name;
1137 gpio_dev->gc.owner = THIS_MODULE;
1138 gpio_dev->gc.parent = &pdev->dev;
1139 gpio_dev->gc.ngpio = resource_size(res) / 4;
1140
1141 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
1142 gpio_dev->groups = kerncz_groups;
1143 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
1144
1145 amd_pinctrl_desc.name = dev_name(&pdev->dev);
1146 amd_get_iomux_res(gpio_dev);
1147 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
1148 gpio_dev);
1149 if (IS_ERR(gpio_dev->pctrl)) {
1150 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1151 return PTR_ERR(gpio_dev->pctrl);
1152 }
1153
1154 /* Disable and mask interrupts */
1155 amd_gpio_irq_init(gpio_dev);
1156
1157 girq = &gpio_dev->gc.irq;
1158 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip);
1159 /* This will let us handle the parent IRQ in the driver */
1160 girq->parent_handler = NULL;
1161 girq->num_parents = 0;
1162 girq->parents = NULL;
1163 girq->default_type = IRQ_TYPE_NONE;
1164 girq->handler = handle_simple_irq;
1165
1166 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
1167 if (ret)
1168 return ret;
1169
1170 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
1171 0, 0, gpio_dev->gc.ngpio);
1172 if (ret) {
1173 dev_err(&pdev->dev, "Failed to add pin range\n");
1174 goto out2;
1175 }
1176
1177 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler,
1178 IRQF_SHARED | IRQF_COND_ONESHOT, KBUILD_MODNAME, gpio_dev);
1179 if (ret)
1180 goto out2;
1181
1182 platform_set_drvdata(pdev, gpio_dev);
1183 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev);
1184
1185 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
1186 return ret;
1187
1188 out2:
1189 gpiochip_remove(&gpio_dev->gc);
1190
1191 return ret;
1192 }
1193
amd_gpio_remove(struct platform_device * pdev)1194 static void amd_gpio_remove(struct platform_device *pdev)
1195 {
1196 struct amd_gpio *gpio_dev;
1197
1198 gpio_dev = platform_get_drvdata(pdev);
1199
1200 gpiochip_remove(&gpio_dev->gc);
1201 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev);
1202 }
1203
1204 #ifdef CONFIG_ACPI
1205 static const struct acpi_device_id amd_gpio_acpi_match[] = {
1206 { "AMD0030", 0 },
1207 { "AMDI0030", 0},
1208 { "AMDI0031", 0},
1209 { },
1210 };
1211 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
1212 #endif
1213
1214 static struct platform_driver amd_gpio_driver = {
1215 .driver = {
1216 .name = "amd_gpio",
1217 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
1218 #ifdef CONFIG_PM_SLEEP
1219 .pm = &amd_gpio_pm_ops,
1220 #endif
1221 },
1222 .probe = amd_gpio_probe,
1223 .remove = amd_gpio_remove,
1224 };
1225
1226 module_platform_driver(amd_gpio_driver);
1227
1228 MODULE_AUTHOR("Ken Xue <[email protected]>, Jeff Wu <[email protected]>");
1229 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
1230