1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * PCI Express Downstream Port Containment services driver
4  * Author: Keith Busch <[email protected]>
5  *
6  * Copyright (C) 2016 Intel Corp.
7  */
8 
9 #define dev_fmt(fmt) "DPC: " fmt
10 
11 #include <linux/aer.h>
12 #include <linux/bitfield.h>
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 
18 #include "portdrv.h"
19 #include "../pci.h"
20 
21 #define PCI_EXP_DPC_CTL_EN_MASK	(PCI_EXP_DPC_CTL_EN_FATAL | \
22 				 PCI_EXP_DPC_CTL_EN_NONFATAL)
23 
24 static const char * const rp_pio_error_string[] = {
25 	"Configuration Request received UR Completion",	 /* Bit Position 0  */
26 	"Configuration Request received CA Completion",	 /* Bit Position 1  */
27 	"Configuration Request Completion Timeout",	 /* Bit Position 2  */
28 	NULL,
29 	NULL,
30 	NULL,
31 	NULL,
32 	NULL,
33 	"I/O Request received UR Completion",		 /* Bit Position 8  */
34 	"I/O Request received CA Completion",		 /* Bit Position 9  */
35 	"I/O Request Completion Timeout",		 /* Bit Position 10 */
36 	NULL,
37 	NULL,
38 	NULL,
39 	NULL,
40 	NULL,
41 	"Memory Request received UR Completion",	 /* Bit Position 16 */
42 	"Memory Request received CA Completion",	 /* Bit Position 17 */
43 	"Memory Request Completion Timeout",		 /* Bit Position 18 */
44 };
45 
pci_save_dpc_state(struct pci_dev * dev)46 void pci_save_dpc_state(struct pci_dev *dev)
47 {
48 	struct pci_cap_saved_state *save_state;
49 	u16 *cap;
50 
51 	if (!pci_is_pcie(dev))
52 		return;
53 
54 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
55 	if (!save_state)
56 		return;
57 
58 	cap = (u16 *)&save_state->cap.data[0];
59 	pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
60 }
61 
pci_restore_dpc_state(struct pci_dev * dev)62 void pci_restore_dpc_state(struct pci_dev *dev)
63 {
64 	struct pci_cap_saved_state *save_state;
65 	u16 *cap;
66 
67 	if (!pci_is_pcie(dev))
68 		return;
69 
70 	save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
71 	if (!save_state)
72 		return;
73 
74 	cap = (u16 *)&save_state->cap.data[0];
75 	pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
76 }
77 
78 static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
79 
80 #ifdef CONFIG_HOTPLUG_PCI_PCIE
dpc_completed(struct pci_dev * pdev)81 static bool dpc_completed(struct pci_dev *pdev)
82 {
83 	u16 status;
84 
85 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
86 	if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
87 		return false;
88 
89 	if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
90 		return false;
91 
92 	return true;
93 }
94 
95 /**
96  * pci_dpc_recovered - whether DPC triggered and has recovered successfully
97  * @pdev: PCI device
98  *
99  * Return true if DPC was triggered for @pdev and has recovered successfully.
100  * Wait for recovery if it hasn't completed yet.  Called from the PCIe hotplug
101  * driver to recognize and ignore Link Down/Up events caused by DPC.
102  */
pci_dpc_recovered(struct pci_dev * pdev)103 bool pci_dpc_recovered(struct pci_dev *pdev)
104 {
105 	struct pci_host_bridge *host;
106 
107 	if (!pdev->dpc_cap)
108 		return false;
109 
110 	/*
111 	 * Synchronization between hotplug and DPC is not supported
112 	 * if DPC is owned by firmware and EDR is not enabled.
113 	 */
114 	host = pci_find_host_bridge(pdev->bus);
115 	if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
116 		return false;
117 
118 	/*
119 	 * Need a timeout in case DPC never completes due to failure of
120 	 * dpc_wait_rp_inactive().  The spec doesn't mandate a time limit,
121 	 * but reports indicate that DPC completes within 4 seconds.
122 	 */
123 	wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
124 			   msecs_to_jiffies(4000));
125 
126 	return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
127 }
128 #endif /* CONFIG_HOTPLUG_PCI_PCIE */
129 
dpc_wait_rp_inactive(struct pci_dev * pdev)130 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
131 {
132 	unsigned long timeout = jiffies + HZ;
133 	u16 cap = pdev->dpc_cap, status;
134 
135 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
136 	while (status & PCI_EXP_DPC_RP_BUSY &&
137 					!time_after(jiffies, timeout)) {
138 		msleep(10);
139 		pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
140 	}
141 	if (status & PCI_EXP_DPC_RP_BUSY) {
142 		pci_warn(pdev, "root port still busy\n");
143 		return -EBUSY;
144 	}
145 	return 0;
146 }
147 
dpc_reset_link(struct pci_dev * pdev)148 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
149 {
150 	pci_ers_result_t ret;
151 	u16 cap;
152 
153 	set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
154 
155 	/*
156 	 * DPC disables the Link automatically in hardware, so it has
157 	 * already been reset by the time we get here.
158 	 */
159 	cap = pdev->dpc_cap;
160 
161 	/*
162 	 * Wait until the Link is inactive, then clear DPC Trigger Status
163 	 * to allow the Port to leave DPC.
164 	 */
165 	if (!pcie_wait_for_link(pdev, false))
166 		pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
167 
168 	if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
169 		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
170 		ret = PCI_ERS_RESULT_DISCONNECT;
171 		goto out;
172 	}
173 
174 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
175 			      PCI_EXP_DPC_STATUS_TRIGGER);
176 
177 	if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
178 		clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
179 		ret = PCI_ERS_RESULT_DISCONNECT;
180 	} else {
181 		set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
182 		ret = PCI_ERS_RESULT_RECOVERED;
183 	}
184 out:
185 	clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
186 	wake_up_all(&dpc_completed_waitqueue);
187 	return ret;
188 }
189 
dpc_process_rp_pio_error(struct pci_dev * pdev)190 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
191 {
192 	u16 cap = pdev->dpc_cap, dpc_status, first_error;
193 	u32 status, mask, sev, syserr, exc, log;
194 	struct pcie_tlp_log tlp_log;
195 	int i;
196 
197 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
198 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
199 	pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
200 		status, mask);
201 
202 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
203 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
204 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
205 	pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
206 		sev, syserr, exc);
207 
208 	/* Get First Error Pointer */
209 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
210 	first_error = FIELD_GET(PCI_EXP_DPC_RP_PIO_FEP, dpc_status);
211 
212 	for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
213 		if ((status & ~mask) & (1 << i))
214 			pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
215 				first_error == i ? " (First)" : "");
216 	}
217 
218 	if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG)
219 		goto clear_status;
220 	pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
221 			  cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
222 			  dpc_tlp_log_len(pdev), &tlp_log);
223 	pcie_print_tlp_log(pdev, &tlp_log, dev_fmt(""));
224 
225 	if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG + 1)
226 		goto clear_status;
227 	pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
228 	pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
229 
230  clear_status:
231 	pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
232 }
233 
dpc_get_aer_uncorrect_severity(struct pci_dev * dev,struct aer_err_info * info)234 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
235 					  struct aer_err_info *info)
236 {
237 	int pos = dev->aer_cap;
238 	u32 status, mask, sev;
239 
240 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
241 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
242 	status &= ~mask;
243 	if (!status)
244 		return 0;
245 
246 	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
247 	status &= sev;
248 	if (status)
249 		info->severity = AER_FATAL;
250 	else
251 		info->severity = AER_NONFATAL;
252 
253 	return 1;
254 }
255 
dpc_process_error(struct pci_dev * pdev)256 void dpc_process_error(struct pci_dev *pdev)
257 {
258 	u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
259 	struct aer_err_info info;
260 
261 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
262 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
263 
264 	pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
265 		 status, source);
266 
267 	reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN;
268 	ext_reason = status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT;
269 	pci_warn(pdev, "%s detected\n",
270 		 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR) ?
271 		 "unmasked uncorrectable error" :
272 		 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE) ?
273 		 "ERR_NONFATAL" :
274 		 (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE) ?
275 		 "ERR_FATAL" :
276 		 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO) ?
277 		 "RP PIO error" :
278 		 (ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER) ?
279 		 "software trigger" :
280 		 "reserved error");
281 
282 	/* show RP PIO error detail information */
283 	if (pdev->dpc_rp_extensions &&
284 	    reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT &&
285 	    ext_reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO)
286 		dpc_process_rp_pio_error(pdev);
287 	else if (reason == PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR &&
288 		 dpc_get_aer_uncorrect_severity(pdev, &info) &&
289 		 aer_get_device_error_info(pdev, &info)) {
290 		aer_print_error(pdev, &info);
291 		pci_aer_clear_nonfatal_status(pdev);
292 		pci_aer_clear_fatal_status(pdev);
293 	}
294 }
295 
pci_clear_surpdn_errors(struct pci_dev * pdev)296 static void pci_clear_surpdn_errors(struct pci_dev *pdev)
297 {
298 	if (pdev->dpc_rp_extensions)
299 		pci_write_config_dword(pdev, pdev->dpc_cap +
300 				       PCI_EXP_DPC_RP_PIO_STATUS, ~0);
301 
302 	/*
303 	 * In practice, Surprise Down errors have been observed to also set
304 	 * error bits in the Status Register as well as the Fatal Error
305 	 * Detected bit in the Device Status Register.
306 	 */
307 	pci_write_config_word(pdev, PCI_STATUS, 0xffff);
308 
309 	pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_FED);
310 }
311 
dpc_handle_surprise_removal(struct pci_dev * pdev)312 static void dpc_handle_surprise_removal(struct pci_dev *pdev)
313 {
314 	if (!pcie_wait_for_link(pdev, false)) {
315 		pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
316 		goto out;
317 	}
318 
319 	if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
320 		goto out;
321 
322 	pci_aer_raw_clear_status(pdev);
323 	pci_clear_surpdn_errors(pdev);
324 
325 	pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS,
326 			      PCI_EXP_DPC_STATUS_TRIGGER);
327 
328 out:
329 	clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
330 	wake_up_all(&dpc_completed_waitqueue);
331 }
332 
dpc_is_surprise_removal(struct pci_dev * pdev)333 static bool dpc_is_surprise_removal(struct pci_dev *pdev)
334 {
335 	u16 status;
336 
337 	if (!pdev->is_hotplug_bridge)
338 		return false;
339 
340 	if (pci_read_config_word(pdev, pdev->aer_cap + PCI_ERR_UNCOR_STATUS,
341 				 &status))
342 		return false;
343 
344 	return status & PCI_ERR_UNC_SURPDN;
345 }
346 
dpc_handler(int irq,void * context)347 static irqreturn_t dpc_handler(int irq, void *context)
348 {
349 	struct pci_dev *pdev = context;
350 
351 	/*
352 	 * According to PCIe r6.0 sec 6.7.6, errors are an expected side effect
353 	 * of async removal and should be ignored by software.
354 	 */
355 	if (dpc_is_surprise_removal(pdev)) {
356 		dpc_handle_surprise_removal(pdev);
357 		return IRQ_HANDLED;
358 	}
359 
360 	dpc_process_error(pdev);
361 
362 	/* We configure DPC so it only triggers on ERR_FATAL */
363 	pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
364 
365 	return IRQ_HANDLED;
366 }
367 
dpc_irq(int irq,void * context)368 static irqreturn_t dpc_irq(int irq, void *context)
369 {
370 	struct pci_dev *pdev = context;
371 	u16 cap = pdev->dpc_cap, status;
372 
373 	pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
374 
375 	if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status))
376 		return IRQ_NONE;
377 
378 	pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
379 			      PCI_EXP_DPC_STATUS_INTERRUPT);
380 	if (status & PCI_EXP_DPC_STATUS_TRIGGER)
381 		return IRQ_WAKE_THREAD;
382 	return IRQ_HANDLED;
383 }
384 
pci_dpc_init(struct pci_dev * pdev)385 void pci_dpc_init(struct pci_dev *pdev)
386 {
387 	u16 cap;
388 
389 	pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
390 	if (!pdev->dpc_cap)
391 		return;
392 
393 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
394 	if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
395 		return;
396 
397 	pdev->dpc_rp_extensions = true;
398 
399 	/* Quirks may set dpc_rp_log_size if device or firmware is buggy */
400 	if (!pdev->dpc_rp_log_size) {
401 		pdev->dpc_rp_log_size =
402 				FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, cap);
403 		if (pdev->dpc_rp_log_size < PCIE_STD_NUM_TLP_HEADERLOG ||
404 		    pdev->dpc_rp_log_size > PCIE_STD_NUM_TLP_HEADERLOG + 1 +
405 					    PCIE_STD_MAX_TLP_PREFIXLOG) {
406 			pci_err(pdev, "RP PIO log size %u is invalid\n",
407 				pdev->dpc_rp_log_size);
408 			pdev->dpc_rp_log_size = 0;
409 		}
410 	}
411 }
412 
dpc_enable(struct pcie_device * dev)413 static void dpc_enable(struct pcie_device *dev)
414 {
415 	struct pci_dev *pdev = dev->port;
416 	int dpc = pdev->dpc_cap;
417 	u16 ctl;
418 
419 	/*
420 	 * Clear DPC Interrupt Status so we don't get an interrupt for an
421 	 * old event when setting DPC Interrupt Enable.
422 	 */
423 	pci_write_config_word(pdev, dpc + PCI_EXP_DPC_STATUS,
424 			      PCI_EXP_DPC_STATUS_INTERRUPT);
425 
426 	pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
427 	ctl &= ~PCI_EXP_DPC_CTL_EN_MASK;
428 	ctl |= PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
429 	pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
430 }
431 
dpc_disable(struct pcie_device * dev)432 static void dpc_disable(struct pcie_device *dev)
433 {
434 	struct pci_dev *pdev = dev->port;
435 	int dpc = pdev->dpc_cap;
436 	u16 ctl;
437 
438 	/* Disable DPC triggering and DPC interrupts */
439 	pci_read_config_word(pdev, dpc + PCI_EXP_DPC_CTL, &ctl);
440 	ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
441 	pci_write_config_word(pdev, dpc + PCI_EXP_DPC_CTL, ctl);
442 }
443 
444 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
dpc_probe(struct pcie_device * dev)445 static int dpc_probe(struct pcie_device *dev)
446 {
447 	struct pci_dev *pdev = dev->port;
448 	struct device *device = &dev->device;
449 	int status;
450 	u16 cap;
451 
452 	if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
453 		return -ENOTSUPP;
454 
455 	status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
456 					   dpc_handler, IRQF_SHARED,
457 					   "pcie-dpc", pdev);
458 	if (status) {
459 		pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
460 			 status);
461 		return status;
462 	}
463 
464 	pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
465 	dpc_enable(dev);
466 
467 	pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
468 	pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
469 		 cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
470 		 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
471 		 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
472 		 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
473 
474 	pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
475 	return status;
476 }
477 
dpc_suspend(struct pcie_device * dev)478 static int dpc_suspend(struct pcie_device *dev)
479 {
480 	dpc_disable(dev);
481 	return 0;
482 }
483 
dpc_resume(struct pcie_device * dev)484 static int dpc_resume(struct pcie_device *dev)
485 {
486 	dpc_enable(dev);
487 	return 0;
488 }
489 
dpc_remove(struct pcie_device * dev)490 static void dpc_remove(struct pcie_device *dev)
491 {
492 	dpc_disable(dev);
493 }
494 
495 static struct pcie_port_service_driver dpcdriver = {
496 	.name		= "dpc",
497 	.port_type	= PCIE_ANY_PORT,
498 	.service	= PCIE_PORT_SERVICE_DPC,
499 	.probe		= dpc_probe,
500 	.suspend	= dpc_suspend,
501 	.resume		= dpc_resume,
502 	.remove		= dpc_remove,
503 };
504 
pcie_dpc_init(void)505 int __init pcie_dpc_init(void)
506 {
507 	return pcie_port_service_register(&dpcdriver);
508 }
509