1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * pci-j721e - PCIe controller driver for TI's J721E SoCs
4 *
5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <[email protected]>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/container_of.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/io.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/of.h>
19 #include <linux/pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23
24 #include "../../pci.h"
25 #include "pcie-cadence.h"
26
27 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)
28
29 #define ENABLE_REG_SYS_2 0x108
30 #define STATUS_REG_SYS_2 0x508
31 #define STATUS_CLR_REG_SYS_2 0x708
32 #define LINK_DOWN BIT(1)
33 #define J7200_LINK_DOWN BIT(10)
34
35 #define J721E_PCIE_USER_CMD_STATUS 0x4
36 #define LINK_TRAINING_ENABLE BIT(0)
37
38 #define J721E_PCIE_USER_LINKSTATUS 0x14
39 #define LINK_STATUS GENMASK(1, 0)
40
41 enum link_status {
42 NO_RECEIVERS_DETECTED,
43 LINK_TRAINING_IN_PROGRESS,
44 LINK_UP_DL_IN_PROGRESS,
45 LINK_UP_DL_COMPLETED,
46 };
47
48 #define J721E_MODE_RC BIT(7)
49 #define LANE_COUNT(n) ((n) << 8)
50
51 #define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0)
52 #define GENERATION_SEL_MASK GENMASK(1, 0)
53
54 struct j721e_pcie {
55 struct cdns_pcie *cdns_pcie;
56 struct clk *refclk;
57 u32 mode;
58 u32 num_lanes;
59 u32 max_lanes;
60 struct gpio_desc *reset_gpio;
61 void __iomem *user_cfg_base;
62 void __iomem *intd_cfg_base;
63 u32 linkdown_irq_regfield;
64 };
65
66 enum j721e_pcie_mode {
67 PCI_MODE_RC,
68 PCI_MODE_EP,
69 };
70
71 struct j721e_pcie_data {
72 enum j721e_pcie_mode mode;
73 unsigned int quirk_retrain_flag:1;
74 unsigned int quirk_detect_quiet_flag:1;
75 unsigned int quirk_disable_flr:1;
76 u32 linkdown_irq_regfield;
77 unsigned int byte_access_allowed:1;
78 unsigned int max_lanes;
79 };
80
j721e_pcie_user_readl(struct j721e_pcie * pcie,u32 offset)81 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
82 {
83 return readl(pcie->user_cfg_base + offset);
84 }
85
j721e_pcie_user_writel(struct j721e_pcie * pcie,u32 offset,u32 value)86 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
87 u32 value)
88 {
89 writel(value, pcie->user_cfg_base + offset);
90 }
91
j721e_pcie_intd_readl(struct j721e_pcie * pcie,u32 offset)92 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
93 {
94 return readl(pcie->intd_cfg_base + offset);
95 }
96
j721e_pcie_intd_writel(struct j721e_pcie * pcie,u32 offset,u32 value)97 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
98 u32 value)
99 {
100 writel(value, pcie->intd_cfg_base + offset);
101 }
102
j721e_pcie_link_irq_handler(int irq,void * priv)103 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)
104 {
105 struct j721e_pcie *pcie = priv;
106 struct device *dev = pcie->cdns_pcie->dev;
107 u32 reg;
108
109 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
110 if (!(reg & pcie->linkdown_irq_regfield))
111 return IRQ_NONE;
112
113 dev_err(dev, "LINK DOWN!\n");
114
115 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
116 return IRQ_HANDLED;
117 }
118
j721e_pcie_config_link_irq(struct j721e_pcie * pcie)119 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
120 {
121 u32 reg;
122
123 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
124 reg |= pcie->linkdown_irq_regfield;
125 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
126 }
127
j721e_pcie_start_link(struct cdns_pcie * cdns_pcie)128 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)
129 {
130 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
131 u32 reg;
132
133 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
134 reg |= LINK_TRAINING_ENABLE;
135 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
136
137 return 0;
138 }
139
j721e_pcie_stop_link(struct cdns_pcie * cdns_pcie)140 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)
141 {
142 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
143 u32 reg;
144
145 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
146 reg &= ~LINK_TRAINING_ENABLE;
147 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
148 }
149
j721e_pcie_link_up(struct cdns_pcie * cdns_pcie)150 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)
151 {
152 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
153 u32 reg;
154
155 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
156 reg &= LINK_STATUS;
157 if (reg == LINK_UP_DL_COMPLETED)
158 return true;
159
160 return false;
161 }
162
163 static const struct cdns_pcie_ops j721e_pcie_ops = {
164 .start_link = j721e_pcie_start_link,
165 .stop_link = j721e_pcie_stop_link,
166 .link_up = j721e_pcie_link_up,
167 };
168
j721e_pcie_set_mode(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)169 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
170 unsigned int offset)
171 {
172 struct device *dev = pcie->cdns_pcie->dev;
173 u32 mask = J721E_MODE_RC;
174 u32 mode = pcie->mode;
175 u32 val = 0;
176 int ret = 0;
177
178 if (mode == PCI_MODE_RC)
179 val = J721E_MODE_RC;
180
181 ret = regmap_update_bits(syscon, offset, mask, val);
182 if (ret)
183 dev_err(dev, "failed to set pcie mode\n");
184
185 return ret;
186 }
187
j721e_pcie_set_link_speed(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)188 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
189 struct regmap *syscon, unsigned int offset)
190 {
191 struct device *dev = pcie->cdns_pcie->dev;
192 struct device_node *np = dev->of_node;
193 int link_speed;
194 u32 val = 0;
195 int ret;
196
197 link_speed = of_pci_get_max_link_speed(np);
198 if (link_speed < 2)
199 link_speed = 2;
200
201 val = link_speed - 1;
202 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);
203 if (ret)
204 dev_err(dev, "failed to set link speed\n");
205
206 return ret;
207 }
208
j721e_pcie_set_lane_count(struct j721e_pcie * pcie,struct regmap * syscon,unsigned int offset)209 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
210 struct regmap *syscon, unsigned int offset)
211 {
212 struct device *dev = pcie->cdns_pcie->dev;
213 u32 lanes = pcie->num_lanes;
214 u32 mask = BIT(8);
215 u32 val = 0;
216 int ret;
217
218 if (pcie->max_lanes == 4)
219 mask = GENMASK(9, 8);
220
221 val = LANE_COUNT(lanes - 1);
222 ret = regmap_update_bits(syscon, offset, mask, val);
223 if (ret)
224 dev_err(dev, "failed to set link count\n");
225
226 return ret;
227 }
228
j721e_enable_acspcie_refclk(struct j721e_pcie * pcie,struct regmap * syscon)229 static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie,
230 struct regmap *syscon)
231 {
232 struct device *dev = pcie->cdns_pcie->dev;
233 struct device_node *node = dev->of_node;
234 u32 mask = ACSPCIE_PAD_DISABLE_MASK;
235 struct of_phandle_args args;
236 u32 val;
237 int ret;
238
239 ret = of_parse_phandle_with_fixed_args(node,
240 "ti,syscon-acspcie-proxy-ctrl",
241 1, 0, &args);
242 if (ret) {
243 dev_err(dev,
244 "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n");
245 return ret;
246 }
247
248 /* Clear PAD IO disable bits to enable refclk output */
249 val = ~(args.args[0]);
250 ret = regmap_update_bits(syscon, 0, mask, val);
251 if (ret) {
252 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret);
253 return ret;
254 }
255
256 return 0;
257 }
258
j721e_pcie_ctrl_init(struct j721e_pcie * pcie)259 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
260 {
261 struct device *dev = pcie->cdns_pcie->dev;
262 struct device_node *node = dev->of_node;
263 struct of_phandle_args args;
264 unsigned int offset = 0;
265 struct regmap *syscon;
266 int ret;
267
268 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
269 if (IS_ERR(syscon)) {
270 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
271 return PTR_ERR(syscon);
272 }
273
274 /* Do not error out to maintain old DT compatibility */
275 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
276 0, &args);
277 if (!ret)
278 offset = args.args[0];
279
280 ret = j721e_pcie_set_mode(pcie, syscon, offset);
281 if (ret < 0) {
282 dev_err(dev, "Failed to set pci mode\n");
283 return ret;
284 }
285
286 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
287 if (ret < 0) {
288 dev_err(dev, "Failed to set link speed\n");
289 return ret;
290 }
291
292 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
293 if (ret < 0) {
294 dev_err(dev, "Failed to set num-lanes\n");
295 return ret;
296 }
297
298 /* Enable ACSPCIE refclk output if the optional property exists */
299 syscon = syscon_regmap_lookup_by_phandle_optional(node,
300 "ti,syscon-acspcie-proxy-ctrl");
301 if (!syscon)
302 return 0;
303
304 return j721e_enable_acspcie_refclk(pcie, syscon);
305 }
306
cdns_ti_pcie_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)307 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
308 int where, int size, u32 *value)
309 {
310 if (pci_is_root_bus(bus))
311 return pci_generic_config_read32(bus, devfn, where, size,
312 value);
313
314 return pci_generic_config_read(bus, devfn, where, size, value);
315 }
316
cdns_ti_pcie_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)317 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
318 int where, int size, u32 value)
319 {
320 if (pci_is_root_bus(bus))
321 return pci_generic_config_write32(bus, devfn, where, size,
322 value);
323
324 return pci_generic_config_write(bus, devfn, where, size, value);
325 }
326
327 static struct pci_ops cdns_ti_pcie_host_ops = {
328 .map_bus = cdns_pci_map_bus,
329 .read = cdns_ti_pcie_config_read,
330 .write = cdns_ti_pcie_config_write,
331 };
332
333 static const struct j721e_pcie_data j721e_pcie_rc_data = {
334 .mode = PCI_MODE_RC,
335 .quirk_retrain_flag = true,
336 .byte_access_allowed = false,
337 .linkdown_irq_regfield = LINK_DOWN,
338 .max_lanes = 2,
339 };
340
341 static const struct j721e_pcie_data j721e_pcie_ep_data = {
342 .mode = PCI_MODE_EP,
343 .linkdown_irq_regfield = LINK_DOWN,
344 .max_lanes = 2,
345 };
346
347 static const struct j721e_pcie_data j7200_pcie_rc_data = {
348 .mode = PCI_MODE_RC,
349 .quirk_detect_quiet_flag = true,
350 .linkdown_irq_regfield = J7200_LINK_DOWN,
351 .byte_access_allowed = true,
352 .max_lanes = 2,
353 };
354
355 static const struct j721e_pcie_data j7200_pcie_ep_data = {
356 .mode = PCI_MODE_EP,
357 .quirk_detect_quiet_flag = true,
358 .linkdown_irq_regfield = J7200_LINK_DOWN,
359 .quirk_disable_flr = true,
360 .max_lanes = 2,
361 };
362
363 static const struct j721e_pcie_data am64_pcie_rc_data = {
364 .mode = PCI_MODE_RC,
365 .linkdown_irq_regfield = J7200_LINK_DOWN,
366 .byte_access_allowed = true,
367 .max_lanes = 1,
368 };
369
370 static const struct j721e_pcie_data am64_pcie_ep_data = {
371 .mode = PCI_MODE_EP,
372 .linkdown_irq_regfield = J7200_LINK_DOWN,
373 .max_lanes = 1,
374 };
375
376 static const struct j721e_pcie_data j784s4_pcie_rc_data = {
377 .mode = PCI_MODE_RC,
378 .quirk_retrain_flag = true,
379 .byte_access_allowed = false,
380 .linkdown_irq_regfield = J7200_LINK_DOWN,
381 .max_lanes = 4,
382 };
383
384 static const struct j721e_pcie_data j784s4_pcie_ep_data = {
385 .mode = PCI_MODE_EP,
386 .linkdown_irq_regfield = J7200_LINK_DOWN,
387 .max_lanes = 4,
388 };
389
390 static const struct j721e_pcie_data j722s_pcie_rc_data = {
391 .mode = PCI_MODE_RC,
392 .linkdown_irq_regfield = J7200_LINK_DOWN,
393 .byte_access_allowed = true,
394 .max_lanes = 1,
395 };
396
397 static const struct of_device_id of_j721e_pcie_match[] = {
398 {
399 .compatible = "ti,j721e-pcie-host",
400 .data = &j721e_pcie_rc_data,
401 },
402 {
403 .compatible = "ti,j721e-pcie-ep",
404 .data = &j721e_pcie_ep_data,
405 },
406 {
407 .compatible = "ti,j7200-pcie-host",
408 .data = &j7200_pcie_rc_data,
409 },
410 {
411 .compatible = "ti,j7200-pcie-ep",
412 .data = &j7200_pcie_ep_data,
413 },
414 {
415 .compatible = "ti,am64-pcie-host",
416 .data = &am64_pcie_rc_data,
417 },
418 {
419 .compatible = "ti,am64-pcie-ep",
420 .data = &am64_pcie_ep_data,
421 },
422 {
423 .compatible = "ti,j784s4-pcie-host",
424 .data = &j784s4_pcie_rc_data,
425 },
426 {
427 .compatible = "ti,j784s4-pcie-ep",
428 .data = &j784s4_pcie_ep_data,
429 },
430 {
431 .compatible = "ti,j722s-pcie-host",
432 .data = &j722s_pcie_rc_data,
433 },
434 {},
435 };
436
j721e_pcie_probe(struct platform_device * pdev)437 static int j721e_pcie_probe(struct platform_device *pdev)
438 {
439 struct device *dev = &pdev->dev;
440 struct device_node *node = dev->of_node;
441 struct pci_host_bridge *bridge;
442 const struct j721e_pcie_data *data;
443 struct cdns_pcie *cdns_pcie;
444 struct j721e_pcie *pcie;
445 struct cdns_pcie_rc *rc = NULL;
446 struct cdns_pcie_ep *ep = NULL;
447 struct gpio_desc *gpiod;
448 void __iomem *base;
449 struct clk *clk;
450 u32 num_lanes;
451 u32 mode;
452 int ret;
453 int irq;
454
455 data = of_device_get_match_data(dev);
456 if (!data)
457 return -EINVAL;
458
459 mode = (u32)data->mode;
460
461 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
462 if (!pcie)
463 return -ENOMEM;
464
465 switch (mode) {
466 case PCI_MODE_RC:
467 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))
468 return -ENODEV;
469
470 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
471 if (!bridge)
472 return -ENOMEM;
473
474 if (!data->byte_access_allowed)
475 bridge->ops = &cdns_ti_pcie_host_ops;
476 rc = pci_host_bridge_priv(bridge);
477 rc->quirk_retrain_flag = data->quirk_retrain_flag;
478 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
479
480 cdns_pcie = &rc->pcie;
481 cdns_pcie->dev = dev;
482 cdns_pcie->ops = &j721e_pcie_ops;
483 pcie->cdns_pcie = cdns_pcie;
484 break;
485 case PCI_MODE_EP:
486 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))
487 return -ENODEV;
488
489 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
490 if (!ep)
491 return -ENOMEM;
492
493 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;
494 ep->quirk_disable_flr = data->quirk_disable_flr;
495
496 cdns_pcie = &ep->pcie;
497 cdns_pcie->dev = dev;
498 cdns_pcie->ops = &j721e_pcie_ops;
499 pcie->cdns_pcie = cdns_pcie;
500 break;
501 default:
502 dev_err(dev, "INVALID device type %d\n", mode);
503 return 0;
504 }
505
506 pcie->mode = mode;
507 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
508
509 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");
510 if (IS_ERR(base))
511 return PTR_ERR(base);
512 pcie->intd_cfg_base = base;
513
514 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");
515 if (IS_ERR(base))
516 return PTR_ERR(base);
517 pcie->user_cfg_base = base;
518
519 ret = of_property_read_u32(node, "num-lanes", &num_lanes);
520 if (ret || num_lanes > data->max_lanes) {
521 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");
522 num_lanes = 1;
523 }
524
525 pcie->num_lanes = num_lanes;
526 pcie->max_lanes = data->max_lanes;
527
528 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))
529 return -EINVAL;
530
531 irq = platform_get_irq_byname(pdev, "link_state");
532 if (irq < 0)
533 return irq;
534
535 dev_set_drvdata(dev, pcie);
536 pm_runtime_enable(dev);
537 ret = pm_runtime_get_sync(dev);
538 if (ret < 0) {
539 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");
540 goto err_get_sync;
541 }
542
543 ret = j721e_pcie_ctrl_init(pcie);
544 if (ret < 0) {
545 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");
546 goto err_get_sync;
547 }
548
549 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,
550 "j721e-pcie-link-down-irq", pcie);
551 if (ret < 0) {
552 dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq);
553 goto err_get_sync;
554 }
555
556 j721e_pcie_config_link_irq(pcie);
557
558 switch (mode) {
559 case PCI_MODE_RC:
560 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
561 if (IS_ERR(gpiod)) {
562 ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");
563 goto err_get_sync;
564 }
565 pcie->reset_gpio = gpiod;
566
567 ret = cdns_pcie_init_phy(dev, cdns_pcie);
568 if (ret) {
569 dev_err_probe(dev, ret, "Failed to init phy\n");
570 goto err_get_sync;
571 }
572
573 clk = devm_clk_get_optional(dev, "pcie_refclk");
574 if (IS_ERR(clk)) {
575 ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");
576 goto err_pcie_setup;
577 }
578
579 ret = clk_prepare_enable(clk);
580 if (ret) {
581 dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");
582 goto err_pcie_setup;
583 }
584 pcie->refclk = clk;
585
586 /*
587 * Section 2.2 of the PCI Express Card Electromechanical
588 * Specification (Revision 5.1) mandates that the deassertion
589 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
590 * This shall ensure that the power and the reference clock
591 * are stable.
592 */
593 if (gpiod) {
594 msleep(PCIE_T_PVPERL_MS);
595 gpiod_set_value_cansleep(gpiod, 1);
596 }
597
598 ret = cdns_pcie_host_setup(rc);
599 if (ret < 0) {
600 clk_disable_unprepare(pcie->refclk);
601 goto err_pcie_setup;
602 }
603
604 break;
605 case PCI_MODE_EP:
606 ret = cdns_pcie_init_phy(dev, cdns_pcie);
607 if (ret) {
608 dev_err_probe(dev, ret, "Failed to init phy\n");
609 goto err_get_sync;
610 }
611
612 ret = cdns_pcie_ep_setup(ep);
613 if (ret < 0)
614 goto err_pcie_setup;
615
616 break;
617 }
618
619 return 0;
620
621 err_pcie_setup:
622 cdns_pcie_disable_phy(cdns_pcie);
623
624 err_get_sync:
625 pm_runtime_put(dev);
626 pm_runtime_disable(dev);
627
628 return ret;
629 }
630
j721e_pcie_remove(struct platform_device * pdev)631 static void j721e_pcie_remove(struct platform_device *pdev)
632 {
633 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
634 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
635 struct device *dev = &pdev->dev;
636
637 clk_disable_unprepare(pcie->refclk);
638 cdns_pcie_disable_phy(cdns_pcie);
639 pm_runtime_put(dev);
640 pm_runtime_disable(dev);
641 }
642
j721e_pcie_suspend_noirq(struct device * dev)643 static int j721e_pcie_suspend_noirq(struct device *dev)
644 {
645 struct j721e_pcie *pcie = dev_get_drvdata(dev);
646
647 if (pcie->mode == PCI_MODE_RC) {
648 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
649 clk_disable_unprepare(pcie->refclk);
650 }
651
652 cdns_pcie_disable_phy(pcie->cdns_pcie);
653
654 return 0;
655 }
656
j721e_pcie_resume_noirq(struct device * dev)657 static int j721e_pcie_resume_noirq(struct device *dev)
658 {
659 struct j721e_pcie *pcie = dev_get_drvdata(dev);
660 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
661 int ret;
662
663 ret = j721e_pcie_ctrl_init(pcie);
664 if (ret < 0)
665 return ret;
666
667 j721e_pcie_config_link_irq(pcie);
668
669 /*
670 * This is not called explicitly in the probe, it is called by
671 * cdns_pcie_init_phy().
672 */
673 ret = cdns_pcie_enable_phy(pcie->cdns_pcie);
674 if (ret < 0)
675 return ret;
676
677 if (pcie->mode == PCI_MODE_RC) {
678 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);
679
680 ret = clk_prepare_enable(pcie->refclk);
681 if (ret < 0)
682 return ret;
683
684 /*
685 * Section 2.2 of the PCI Express Card Electromechanical
686 * Specification (Revision 5.1) mandates that the deassertion
687 * of the PERST# signal should be delayed by 100 ms (TPVPERL).
688 * This shall ensure that the power and the reference clock
689 * are stable.
690 */
691 if (pcie->reset_gpio) {
692 msleep(PCIE_T_PVPERL_MS);
693 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
694 }
695
696 ret = cdns_pcie_host_link_setup(rc);
697 if (ret < 0) {
698 clk_disable_unprepare(pcie->refclk);
699 return ret;
700 }
701
702 /*
703 * Reset internal status of BARs to force reinitialization in
704 * cdns_pcie_host_init().
705 */
706 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)
707 rc->avail_ib_bar[bar] = true;
708
709 ret = cdns_pcie_host_init(rc);
710 if (ret) {
711 clk_disable_unprepare(pcie->refclk);
712 return ret;
713 }
714 }
715
716 return 0;
717 }
718
719 static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,
720 j721e_pcie_suspend_noirq,
721 j721e_pcie_resume_noirq);
722
723 static struct platform_driver j721e_pcie_driver = {
724 .probe = j721e_pcie_probe,
725 .remove = j721e_pcie_remove,
726 .driver = {
727 .name = "j721e-pcie",
728 .of_match_table = of_j721e_pcie_match,
729 .suppress_bind_attrs = true,
730 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops),
731 },
732 };
733 builtin_platform_driver(j721e_pcie_driver);
734