1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Microchip Technology
3
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/delay.h>
7 #include <linux/mii.h>
8 #include <linux/phy.h>
9 #include <linux/sort.h>
10 #include <linux/ethtool.h>
11 #include <linux/ethtool_netlink.h>
12 #include <linux/bitfield.h>
13 #include "microchip_rds_ptp.h"
14
15 #define PHY_ID_LAN87XX 0x0007c150
16 #define PHY_ID_LAN937X 0x0007c180
17 #define PHY_ID_LAN887X 0x0007c1f0
18
19 #define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000
20 #define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)
21
22 /* External Register Control Register */
23 #define LAN87XX_EXT_REG_CTL (0x14)
24 #define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
25 #define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
26 #define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)
27 #define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
28
29 /* External Register Read Data Register */
30 #define LAN87XX_EXT_REG_RD_DATA (0x15)
31
32 /* External Register Write Data Register */
33 #define LAN87XX_EXT_REG_WR_DATA (0x16)
34
35 /* Interrupt Source Register */
36 #define LAN87XX_INTERRUPT_SOURCE (0x18)
37 #define LAN87XX_INTERRUPT_SOURCE_2 (0x08)
38
39 /* Interrupt Mask Register */
40 #define LAN87XX_INTERRUPT_MASK (0x19)
41 #define LAN87XX_MASK_LINK_UP (0x0004)
42 #define LAN87XX_MASK_LINK_DOWN (0x0002)
43
44 #define LAN87XX_INTERRUPT_MASK_2 (0x09)
45 #define LAN87XX_MASK_COMM_RDY BIT(10)
46
47 /* MISC Control 1 Register */
48 #define LAN87XX_CTRL_1 (0x11)
49 #define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)
50 #define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)
51
52 /* phyaccess nested types */
53 #define PHYACC_ATTR_MODE_READ 0
54 #define PHYACC_ATTR_MODE_WRITE 1
55 #define PHYACC_ATTR_MODE_MODIFY 2
56 #define PHYACC_ATTR_MODE_POLL 3
57
58 #define PHYACC_ATTR_BANK_SMI 0
59 #define PHYACC_ATTR_BANK_MISC 1
60 #define PHYACC_ATTR_BANK_PCS 2
61 #define PHYACC_ATTR_BANK_AFE 3
62 #define PHYACC_ATTR_BANK_DSP 4
63 #define PHYACC_ATTR_BANK_MAX 7
64
65 /* measurement defines */
66 #define LAN87XX_CABLE_TEST_OK 0
67 #define LAN87XX_CABLE_TEST_OPEN 1
68 #define LAN87XX_CABLE_TEST_SAME_SHORT 2
69
70 /* T1 Registers */
71 #define T1_AFE_PORT_CFG1_REG 0x0B
72 #define T1_POWER_DOWN_CONTROL_REG 0x1A
73 #define T1_SLV_FD_MULT_CFG_REG 0x18
74 #define T1_CDR_CFG_PRE_LOCK_REG 0x05
75 #define T1_CDR_CFG_POST_LOCK_REG 0x06
76 #define T1_LCK_STG2_MUFACT_CFG_REG 0x1A
77 #define T1_LCK_STG3_MUFACT_CFG_REG 0x1B
78 #define T1_POST_LCK_MUFACT_CFG_REG 0x1C
79 #define T1_TX_RX_FIFO_CFG_REG 0x02
80 #define T1_TX_LPF_FIR_CFG_REG 0x55
81 #define T1_COEF_CLK_PWR_DN_CFG 0x04
82 #define T1_COEF_RW_CTL_CFG 0x0D
83 #define T1_SQI_CONFIG_REG 0x2E
84 #define T1_SQI_CONFIG2_REG 0x4A
85 #define T1_DCQ_SQI_REG 0xC3
86 #define T1_DCQ_SQI_MSK GENMASK(3, 1)
87 #define T1_MDIO_CONTROL2_REG 0x10
88 #define T1_INTERRUPT_SOURCE_REG 0x18
89 #define T1_INTERRUPT2_SOURCE_REG 0x08
90 #define T1_EQ_FD_STG1_FRZ_CFG 0x69
91 #define T1_EQ_FD_STG2_FRZ_CFG 0x6A
92 #define T1_EQ_FD_STG3_FRZ_CFG 0x6B
93 #define T1_EQ_FD_STG4_FRZ_CFG 0x6C
94 #define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D
95 #define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
96
97 #define T1_MODE_STAT_REG 0x11
98 #define T1_LINK_UP_MSK BIT(0)
99
100 /* SQI defines */
101 #define LAN87XX_MAX_SQI 0x07
102
103 /* Chiptop registers */
104 #define LAN887X_PMA_EXT_ABILITY_2 0x12
105 #define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)
106 #define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)
107
108 /* DSP 100M registers */
109 #define LAN887x_CDR_CONFIG1_100 0x0405
110 #define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411
111 #define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417
112 #define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c
113 #define LAN887x_PROT_DISABLE_100 0x0425
114 #define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454
115
116 /* DSP 1000M registers */
117 #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811
118 #define LAN887X_LOCK3_EQLSR_CONFIG 0x0813
119 #define LAN887X_PROT_DISABLE 0x0825
120 #define LAN887X_FFE_GAIN6 0x0843
121 #define LAN887X_FFE_GAIN7 0x0844
122 #define LAN887X_FFE_GAIN8 0x0845
123 #define LAN887X_FFE_GAIN9 0x0846
124 #define LAN887X_ECHO_DELAY_CONFIG 0x08ec
125 #define LAN887X_FFE_MAX_CONFIG 0x08ee
126
127 /* PCS 1000M registers */
128 #define LAN887X_SCR_CONFIG_3 0x8043
129 #define LAN887X_INFO_FLD_CONFIG_5 0x8048
130
131 /* T1 afe registers */
132 #define LAN887X_ZQCAL_CONTROL_1 0x8080
133 #define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089
134 #define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b
135 #define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d
136 #define LAN887X_TX_AMPLT_1000T1_REG 0x80b0
137 #define LAN887X_INIT_COEFF_DFE1_100 0x0422
138
139 /* PMA registers */
140 #define LAN887X_DSP_PMA_CONTROL 0x810e
141 #define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)
142
143 /* PCS 100M registers */
144 #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204
145 #define LAN887X_IDLE_ERR_CNT_THRESH 0x8213
146
147 /* Misc registers */
148 #define LAN887X_REG_REG26 0x001a
149 #define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)
150
151 /* Mis registers */
152 #define LAN887X_MIS_CFG_REG0 0xa00
153 #define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)
154 #define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)
155
156 #define LAN887X_MAC_MODE_RGMII 0x01
157 #define LAN887X_MAC_MODE_SGMII 0x03
158
159 #define LAN887X_MIS_DLL_CFG_REG0 0xa01
160 #define LAN887X_MIS_DLL_CFG_REG1 0xa02
161
162 #define LAN887X_MIS_DLL_DELAY_EN BIT(15)
163 #define LAN887X_MIS_DLL_EN BIT(0)
164 #define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\
165 LAN887X_MIS_DLL_EN)
166
167 #define LAN887X_MIS_CFG_REG2 0xa03
168 #define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)
169
170 #define LAN887X_MIS_PKT_STAT_REG0 0xa06
171 #define LAN887X_MIS_PKT_STAT_REG1 0xa07
172 #define LAN887X_MIS_PKT_STAT_REG3 0xa09
173 #define LAN887X_MIS_PKT_STAT_REG4 0xa0a
174 #define LAN887X_MIS_PKT_STAT_REG5 0xa0b
175 #define LAN887X_MIS_PKT_STAT_REG6 0xa0c
176
177 /* Chiptop common registers */
178 #define LAN887X_COMMON_LED3_LED2 0xc05
179 #define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)
180 #define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0
181
182 /* MX chip top registers */
183 #define LAN887X_CHIP_HARD_RST 0xf03e
184 #define LAN887X_CHIP_HARD_RST_RESET BIT(0)
185
186 #define LAN887X_CHIP_SOFT_RST 0xf03f
187 #define LAN887X_CHIP_SOFT_RST_RESET BIT(0)
188
189 #define LAN887X_SGMII_CTL 0xf01a
190 #define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)
191
192 #define LAN887X_SGMII_PCS_CFG 0xf034
193 #define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)
194
195 #define LAN887X_EFUSE_READ_DAT9 0xf209
196 #define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)
197 #define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)
198
199 #define LAN887X_CALIB_CONFIG_100 0x437
200 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5)
201 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4)
202 #define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3)
203 #define LAN887X_CALIB_CONFIG_100_VAL \
204 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\
205 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\
206 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL)
207
208 #define LAN887X_MAX_PGA_GAIN_100 0x44f
209 #define LAN887X_MIN_PGA_GAIN_100 0x450
210 #define LAN887X_START_CBL_DIAG_100 0x45a
211 #define LAN887X_CBL_DIAG_DONE BIT(1)
212 #define LAN887X_CBL_DIAG_START BIT(0)
213 #define LAN887X_CBL_DIAG_STOP 0x0
214
215 #define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b
216 #define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c
217 #define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d
218 #define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e
219 #define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f
220 #define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460
221 #define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462
222 #define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497
223 #define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499
224 #define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a
225 #define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c
226 #define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d
227
228 #define MICROCHIP_CABLE_NOISE_MARGIN 20
229 #define MICROCHIP_CABLE_TIME_MARGIN 89
230 #define MICROCHIP_CABLE_MIN_TIME_DIFF 96
231 #define MICROCHIP_CABLE_MAX_TIME_DIFF \
232 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN)
233
234 #define LAN887X_INT_STS 0xf000
235 #define LAN887X_INT_MSK 0xf001
236 #define LAN887X_INT_MSK_P1588_MOD_INT_MSK BIT(3)
237 #define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2)
238 #define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)
239 #define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
240
241 #define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002
242 #define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8)
243
244 #define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\
245 LAN887X_INT_MSK_LINK_DOWN_MSK)
246
247 #define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\
248 LAN887X_MX_CHIP_TOP_LINK_MSK)
249
250 #define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404
251 #define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6
252 #define LAN887X_SQI_CONFIG_100 0x042e
253 #define LAN887X_SQI_CONFIG_100_V 0x9572
254 #define LAN887X_SQI_MSE_100 0x483
255
256 #define LAN887X_POKE_PEEK_100 0x040d
257 #define LAN887X_POKE_PEEK_100_EN BIT(0)
258
259 #define LAN887X_COEFF_MOD_CONFIG 0x080d
260 #define LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN BIT(8)
261
262 #define LAN887X_DCQ_SQI_STATUS 0x08b2
263
264 /* SQI raw samples count */
265 #define SQI_SAMPLES 200
266
267 /* Samples percentage considered for SQI calculation */
268 #define SQI_INLINERS_PERCENT 60
269
270 /* Samples count considered for SQI calculation */
271 #define SQI_INLIERS_NUM (SQI_SAMPLES * SQI_INLINERS_PERCENT / 100)
272
273 /* Start offset of samples */
274 #define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2)
275
276 /* End offset of samples */
277 #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM)
278
279 #define DRIVER_AUTHOR "Nisar Sayed <[email protected]>"
280 #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver"
281
282 /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)
283 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault
284 */
285 enum cable_diag_mode {
286 TEST_MODE_NORMAL,
287 TEST_MODE_HYBRID
288 };
289
290 /* CD_TEST_INIT: Cable test is initated
291 * CD_TEST_DONE: Cable test is done
292 */
293 enum cable_diag_state {
294 CD_TEST_INIT,
295 CD_TEST_DONE
296 };
297
298 struct access_ereg_val {
299 u8 mode;
300 u8 bank;
301 u8 offset;
302 u16 val;
303 u16 mask;
304 };
305
306 struct lan887x_hw_stat {
307 const char *string;
308 u8 mmd;
309 u16 reg;
310 u8 bits;
311 };
312
313 static const struct lan887x_hw_stat lan887x_hw_stats[] = {
314 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
315 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
316 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
317 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
318 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
319 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
320 };
321
322 struct lan887x_regwr_map {
323 u8 mmd;
324 u16 reg;
325 u16 val;
326 };
327
328 struct lan887x_priv {
329 u64 stats[ARRAY_SIZE(lan887x_hw_stats)];
330 struct mchp_rds_ptp_clock *clock;
331 bool init_done;
332 };
333
lan937x_dsp_workaround(struct phy_device * phydev,u16 ereg,u8 bank)334 static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
335 {
336 u8 prev_bank;
337 int rc = 0;
338 u16 val;
339
340 mutex_lock(&phydev->lock);
341 /* Read previous selected bank */
342 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
343 if (rc < 0)
344 goto out_unlock;
345
346 /* store the prev_bank */
347 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);
348
349 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
350 val = ereg & ~LAN87XX_REG_ADDR_MASK;
351
352 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;
353 val |= LAN87XX_EXT_REG_CTL_RD_CTL;
354
355 /* access twice for DSP bank change,dummy access */
356 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
357 }
358
359 out_unlock:
360 mutex_unlock(&phydev->lock);
361
362 return rc;
363 }
364
access_ereg(struct phy_device * phydev,u8 mode,u8 bank,u8 offset,u16 val)365 static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
366 u8 offset, u16 val)
367 {
368 u16 ereg = 0;
369 int rc = 0;
370
371 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)
372 return -EINVAL;
373
374 if (bank == PHYACC_ATTR_BANK_SMI) {
375 if (mode == PHYACC_ATTR_MODE_WRITE)
376 rc = phy_write(phydev, offset, val);
377 else
378 rc = phy_read(phydev, offset);
379 return rc;
380 }
381
382 if (mode == PHYACC_ATTR_MODE_WRITE) {
383 ereg = LAN87XX_EXT_REG_CTL_WR_CTL;
384 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
385 if (rc < 0)
386 return rc;
387 } else {
388 ereg = LAN87XX_EXT_REG_CTL_RD_CTL;
389 }
390
391 ereg |= (bank << 8) | offset;
392
393 /* DSP bank access workaround for lan937x */
394 if (phydev->phy_id == PHY_ID_LAN937X) {
395 rc = lan937x_dsp_workaround(phydev, ereg, bank);
396 if (rc < 0)
397 return rc;
398 }
399
400 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
401 if (rc < 0)
402 return rc;
403
404 if (mode == PHYACC_ATTR_MODE_READ)
405 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);
406
407 return rc;
408 }
409
access_ereg_modify_changed(struct phy_device * phydev,u8 bank,u8 offset,u16 val,u16 mask)410 static int access_ereg_modify_changed(struct phy_device *phydev,
411 u8 bank, u8 offset, u16 val, u16 mask)
412 {
413 int new = 0, rc = 0;
414
415 if (bank > PHYACC_ATTR_BANK_MAX)
416 return -EINVAL;
417
418 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
419 if (rc < 0)
420 return rc;
421
422 new = val | (rc & (mask ^ 0xFFFF));
423 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
424
425 return rc;
426 }
427
access_smi_poll_timeout(struct phy_device * phydev,u8 offset,u16 mask,u16 clr)428 static int access_smi_poll_timeout(struct phy_device *phydev,
429 u8 offset, u16 mask, u16 clr)
430 {
431 int val;
432
433 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
434 150, 30000, true);
435 }
436
lan87xx_config_rgmii_delay(struct phy_device * phydev)437 static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
438 {
439 int rc;
440
441 if (!phy_interface_is_rgmii(phydev))
442 return 0;
443
444 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
445 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0);
446 if (rc < 0)
447 return rc;
448
449 switch (phydev->interface) {
450 case PHY_INTERFACE_MODE_RGMII:
451 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
452 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
453 break;
454 case PHY_INTERFACE_MODE_RGMII_ID:
455 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
456 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
457 break;
458 case PHY_INTERFACE_MODE_RGMII_RXID:
459 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
460 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
461 break;
462 case PHY_INTERFACE_MODE_RGMII_TXID:
463 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
464 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
465 break;
466 default:
467 return 0;
468 }
469
470 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
471 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc);
472 }
473
lan87xx_phy_init_cmd(struct phy_device * phydev,const struct access_ereg_val * cmd_seq,int cnt)474 static int lan87xx_phy_init_cmd(struct phy_device *phydev,
475 const struct access_ereg_val *cmd_seq, int cnt)
476 {
477 int ret, i;
478
479 for (i = 0; i < cnt; i++) {
480 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL &&
481 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) {
482 ret = access_smi_poll_timeout(phydev,
483 cmd_seq[i].offset,
484 cmd_seq[i].val,
485 cmd_seq[i].mask);
486 } else {
487 ret = access_ereg(phydev, cmd_seq[i].mode,
488 cmd_seq[i].bank, cmd_seq[i].offset,
489 cmd_seq[i].val);
490 }
491 if (ret < 0)
492 return ret;
493 }
494
495 return ret;
496 }
497
lan87xx_phy_init(struct phy_device * phydev)498 static int lan87xx_phy_init(struct phy_device *phydev)
499 {
500 static const struct access_ereg_val hw_init[] = {
501 /* TXPD/TXAMP6 Configs */
502 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
503 T1_AFE_PORT_CFG1_REG, 0x002D, 0 },
504 /* HW_Init Hi and Force_ED */
505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
506 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },
507 };
508
509 static const struct access_ereg_val slave_init[] = {
510 /* Equalizer Full Duplex Freeze - T1 Slave */
511 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
512 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },
513 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
514 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },
515 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
516 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },
517 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
518 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },
519 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
520 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },
521 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
522 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },
523 };
524
525 static const struct access_ereg_val phy_init[] = {
526 /* Slave Full Duplex Multi Configs */
527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
528 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },
529 /* CDR Pre and Post Lock Configs */
530 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
531 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },
532 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
533 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },
534 /* Lock Stage 2-3 Multi Factor Config */
535 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
536 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },
537 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
538 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },
539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
540 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },
541 /* Pointer delay */
542 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
543 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
544 /* Tx iir edits */
545 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
546 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
548 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
549 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
550 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
551 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
552 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
553 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
554 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
555 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
556 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
557 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
558 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
559 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
560 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
561 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
562 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
563 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
564 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
565 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
566 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
567 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
568 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
569 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
570 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
571 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
572 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
573 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
574 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
575 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
576 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
577 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
578 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
579 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
580 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
581 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
582 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
583 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
584 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
585 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
586 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
587 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
588 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
589 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
590 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
591 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
592 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
593 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
594 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
595 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
596 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
597 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
598 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
599 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
600 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
601 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
602 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
603 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
604 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
605 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
606 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
607 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
608 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
609 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
610 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
611 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
612 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
613 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
614 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
615 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
616 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
617 /* Setup SQI measurement */
618 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
619 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },
620 /* SQI enable */
621 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
622 T1_SQI_CONFIG_REG, 0x9572, 0 },
623 /* SQI select mode 5 */
624 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
625 T1_SQI_CONFIG2_REG, 0x0001, 0 },
626 /* Throws the first SQI reading */
627 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
628 T1_COEF_RW_CTL_CFG, 0x0301, 0 },
629 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
630 T1_DCQ_SQI_REG, 0, 0 },
631 /* Flag LPS and WUR as idle errors */
632 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
633 T1_MDIO_CONTROL2_REG, 0x0014, 0 },
634 /* HW_Init toggle, undo force ED, TXPD off */
635 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
636 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },
637 /* Reset PCS to trigger hardware initialization */
638 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
639 T1_MDIO_CONTROL2_REG, 0x0094, 0 },
640 /* Poll till Hardware is initialized */
641 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,
642 T1_MDIO_CONTROL2_REG, 0x0080, 0 },
643 /* Tx AMP - 0x06 */
644 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
645 T1_AFE_PORT_CFG1_REG, 0x000C, 0 },
646 /* Read INTERRUPT_SOURCE Register */
647 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
648 T1_INTERRUPT_SOURCE_REG, 0, 0 },
649 /* Read INTERRUPT_SOURCE Register */
650 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,
651 T1_INTERRUPT2_SOURCE_REG, 0, 0 },
652 /* HW_Init Hi */
653 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
654 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },
655 };
656 int rc;
657
658 /* phy Soft reset */
659 rc = genphy_soft_reset(phydev);
660 if (rc < 0)
661 return rc;
662
663 /* PHY Initialization */
664 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init));
665 if (rc < 0)
666 return rc;
667
668 rc = genphy_read_master_slave(phydev);
669 if (rc)
670 return rc;
671
672 /* The following squence needs to run only if phydev is in
673 * slave mode.
674 */
675 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) {
676 rc = lan87xx_phy_init_cmd(phydev, slave_init,
677 ARRAY_SIZE(slave_init));
678 if (rc < 0)
679 return rc;
680 }
681
682 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init));
683 if (rc < 0)
684 return rc;
685
686 return lan87xx_config_rgmii_delay(phydev);
687 }
688
lan87xx_phy_config_intr(struct phy_device * phydev)689 static int lan87xx_phy_config_intr(struct phy_device *phydev)
690 {
691 int rc, val = 0;
692
693 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
694 /* clear all interrupt */
695 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
696 if (rc < 0)
697 return rc;
698
699 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
700 if (rc < 0)
701 return rc;
702
703 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
704 PHYACC_ATTR_BANK_MISC,
705 LAN87XX_INTERRUPT_MASK_2, val);
706 if (rc < 0)
707 return rc;
708
709 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
710 PHYACC_ATTR_BANK_MISC,
711 LAN87XX_INTERRUPT_SOURCE_2, 0);
712 if (rc < 0)
713 return rc;
714
715 /* enable link down and comm ready interrupt */
716 val = LAN87XX_MASK_LINK_DOWN;
717 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
718 if (rc < 0)
719 return rc;
720
721 val = LAN87XX_MASK_COMM_RDY;
722 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
723 PHYACC_ATTR_BANK_MISC,
724 LAN87XX_INTERRUPT_MASK_2, val);
725 } else {
726 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
727 if (rc < 0)
728 return rc;
729
730 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
731 if (rc < 0)
732 return rc;
733
734 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
735 PHYACC_ATTR_BANK_MISC,
736 LAN87XX_INTERRUPT_MASK_2, val);
737 if (rc < 0)
738 return rc;
739
740 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
741 PHYACC_ATTR_BANK_MISC,
742 LAN87XX_INTERRUPT_SOURCE_2, 0);
743 }
744
745 return rc < 0 ? rc : 0;
746 }
747
lan87xx_handle_interrupt(struct phy_device * phydev)748 static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)
749 {
750 int irq_status;
751
752 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
753 PHYACC_ATTR_BANK_MISC,
754 LAN87XX_INTERRUPT_SOURCE_2, 0);
755 if (irq_status < 0) {
756 phy_error(phydev);
757 return IRQ_NONE;
758 }
759
760 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
761 if (irq_status < 0) {
762 phy_error(phydev);
763 return IRQ_NONE;
764 }
765
766 if (irq_status == 0)
767 return IRQ_NONE;
768
769 phy_trigger_machine(phydev);
770
771 return IRQ_HANDLED;
772 }
773
lan87xx_config_init(struct phy_device * phydev)774 static int lan87xx_config_init(struct phy_device *phydev)
775 {
776 int rc = lan87xx_phy_init(phydev);
777
778 return rc < 0 ? rc : 0;
779 }
780
microchip_cable_test_start_common(struct phy_device * phydev)781 static int microchip_cable_test_start_common(struct phy_device *phydev)
782 {
783 int bmcr, bmsr, ret;
784
785 /* If auto-negotiation is enabled, but not complete, the cable
786 * test never completes. So disable auto-neg.
787 */
788 bmcr = phy_read(phydev, MII_BMCR);
789 if (bmcr < 0)
790 return bmcr;
791
792 bmsr = phy_read(phydev, MII_BMSR);
793
794 if (bmsr < 0)
795 return bmsr;
796
797 if (bmcr & BMCR_ANENABLE) {
798 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
799 if (ret < 0)
800 return ret;
801 ret = genphy_soft_reset(phydev);
802 if (ret < 0)
803 return ret;
804 }
805
806 /* If the link is up, allow it some time to go down */
807 if (bmsr & BMSR_LSTATUS)
808 msleep(1500);
809
810 return 0;
811 }
812
lan87xx_cable_test_start(struct phy_device * phydev)813 static int lan87xx_cable_test_start(struct phy_device *phydev)
814 {
815 static const struct access_ereg_val cable_test[] = {
816 /* min wait */
817 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,
818 0, 0},
819 /* max wait */
820 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
821 10, 0},
822 /* pulse cycle */
823 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,
824 90, 0},
825 /* cable diag thresh */
826 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,
827 60, 0},
828 /* max gain */
829 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,
830 31, 0},
831 /* clock align for each iteration */
832 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,
833 0, 0x0038},
834 /* max cycle wait config */
835 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
836 70, 0},
837 /* start cable diag*/
838 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,
839 1, 0},
840 };
841 int rc, i;
842
843 rc = microchip_cable_test_start_common(phydev);
844 if (rc < 0)
845 return rc;
846
847 /* start cable diag */
848 /* check if part is alive - if not, return diagnostic error */
849 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
850 0x00, 0);
851 if (rc < 0)
852 return rc;
853
854 /* master/slave specific configs */
855 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
856 0x0A, 0);
857 if (rc < 0)
858 return rc;
859
860 if ((rc & 0x4000) != 0x4000) {
861 /* DUT is Slave */
862 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE,
863 0x0E, 0x5, 0x7);
864 if (rc < 0)
865 return rc;
866 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
867 0x1A, 0x8, 0x8);
868 if (rc < 0)
869 return rc;
870 } else {
871 /* DUT is Master */
872 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
873 0x10, 0x8, 0x40);
874 if (rc < 0)
875 return rc;
876 }
877
878 for (i = 0; i < ARRAY_SIZE(cable_test); i++) {
879 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) {
880 rc = access_ereg_modify_changed(phydev,
881 cable_test[i].bank,
882 cable_test[i].offset,
883 cable_test[i].val,
884 cable_test[i].mask);
885 /* wait 50ms */
886 msleep(50);
887 } else {
888 rc = access_ereg(phydev, cable_test[i].mode,
889 cable_test[i].bank,
890 cable_test[i].offset,
891 cable_test[i].val);
892 }
893 if (rc < 0)
894 return rc;
895 }
896 /* cable diag started */
897
898 return 0;
899 }
900
lan87xx_cable_test_report_trans(u32 result)901 static int lan87xx_cable_test_report_trans(u32 result)
902 {
903 switch (result) {
904 case LAN87XX_CABLE_TEST_OK:
905 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
906 case LAN87XX_CABLE_TEST_OPEN:
907 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
908 case LAN87XX_CABLE_TEST_SAME_SHORT:
909 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
910 default:
911 /* DIAGNOSTIC_ERROR */
912 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
913 }
914 }
915
lan87xx_cable_test_report(struct phy_device * phydev)916 static int lan87xx_cable_test_report(struct phy_device *phydev)
917 {
918 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;
919 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;
920 int noise_margin = 20, time_margin = 89, jitter_var = 30;
921 int min_time_diff = 96, max_time_diff = 96 + time_margin;
922 bool fault = false, check_a = false, check_b = false;
923 int gain_idx = 0, pos_peak = 0, neg_peak = 0;
924 int pos_peak_time = 0, neg_peak_time = 0;
925 int pos_peak_in_phases_hybrid = 0;
926 int detect = -1;
927
928 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
929 PHYACC_ATTR_BANK_DSP, 151, 0);
930 /* read non-hybrid results */
931 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
932 PHYACC_ATTR_BANK_DSP, 153, 0);
933 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
934 PHYACC_ATTR_BANK_DSP, 154, 0);
935 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
936 PHYACC_ATTR_BANK_DSP, 156, 0);
937 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
938 PHYACC_ATTR_BANK_DSP, 157, 0);
939
940 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F;
941 /* calculate non-hybrid values */
942 pos_peak_phase = pos_peak_time & 0x7F;
943 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase;
944 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F;
945 neg_peak_phase = neg_peak_time & 0x7F;
946 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase;
947
948 /* process values */
949 check_a =
950 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) &&
951 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) &&
952 pos_peak_in_phases_hybrid < pos_peak_in_phases &&
953 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var));
954 check_b =
955 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) &&
956 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) &&
957 pos_peak_in_phases_hybrid < neg_peak_in_phases &&
958 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var));
959
960 if (pos_peak_in_phases > neg_peak_in_phases && check_a)
961 detect = 2;
962 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b)
963 detect = 1;
964
965 if (pos_peak > noise_margin && neg_peak > noise_margin &&
966 gain_idx >= 0) {
967 if (detect == 1 || detect == 2)
968 fault = true;
969 }
970
971 if (!fault)
972 detect = 0;
973
974 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
975 lan87xx_cable_test_report_trans(detect));
976
977 return phy_init_hw(phydev);
978 }
979
lan87xx_cable_test_get_status(struct phy_device * phydev,bool * finished)980 static int lan87xx_cable_test_get_status(struct phy_device *phydev,
981 bool *finished)
982 {
983 int rc = 0;
984
985 *finished = false;
986
987 /* check if cable diag was finished */
988 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
989 90, 0);
990 if (rc < 0)
991 return rc;
992
993 if ((rc & 2) == 2) {
994 /* stop cable diag*/
995 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
996 PHYACC_ATTR_BANK_DSP,
997 90, 0);
998 if (rc < 0)
999 return rc;
1000
1001 *finished = true;
1002
1003 return lan87xx_cable_test_report(phydev);
1004 }
1005
1006 return 0;
1007 }
1008
lan87xx_read_status(struct phy_device * phydev)1009 static int lan87xx_read_status(struct phy_device *phydev)
1010 {
1011 int rc = 0;
1012
1013 rc = phy_read(phydev, T1_MODE_STAT_REG);
1014 if (rc < 0)
1015 return rc;
1016
1017 if (rc & T1_LINK_UP_MSK)
1018 phydev->link = 1;
1019 else
1020 phydev->link = 0;
1021
1022 phydev->speed = SPEED_UNKNOWN;
1023 phydev->duplex = DUPLEX_UNKNOWN;
1024 phydev->pause = 0;
1025 phydev->asym_pause = 0;
1026
1027 rc = genphy_read_master_slave(phydev);
1028 if (rc < 0)
1029 return rc;
1030
1031 rc = genphy_read_status_fixed(phydev);
1032 if (rc < 0)
1033 return rc;
1034
1035 return rc;
1036 }
1037
lan87xx_config_aneg(struct phy_device * phydev)1038 static int lan87xx_config_aneg(struct phy_device *phydev)
1039 {
1040 u16 ctl = 0;
1041 int ret;
1042
1043 switch (phydev->master_slave_set) {
1044 case MASTER_SLAVE_CFG_MASTER_FORCE:
1045 ctl |= CTL1000_AS_MASTER;
1046 break;
1047 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1048 break;
1049 case MASTER_SLAVE_CFG_UNKNOWN:
1050 case MASTER_SLAVE_CFG_UNSUPPORTED:
1051 return 0;
1052 default:
1053 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1054 return -EOPNOTSUPP;
1055 }
1056
1057 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1058 if (ret == 1)
1059 return phy_init_hw(phydev);
1060
1061 return ret;
1062 }
1063
lan87xx_get_sqi(struct phy_device * phydev)1064 static int lan87xx_get_sqi(struct phy_device *phydev)
1065 {
1066 u8 sqi_value = 0;
1067 int rc;
1068
1069 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
1070 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
1071 if (rc < 0)
1072 return rc;
1073
1074 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
1075 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
1076 if (rc < 0)
1077 return rc;
1078
1079 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);
1080
1081 return sqi_value;
1082 }
1083
lan87xx_get_sqi_max(struct phy_device * phydev)1084 static int lan87xx_get_sqi_max(struct phy_device *phydev)
1085 {
1086 return LAN87XX_MAX_SQI;
1087 }
1088
lan887x_rgmii_init(struct phy_device * phydev)1089 static int lan887x_rgmii_init(struct phy_device *phydev)
1090 {
1091 int ret;
1092
1093 /* SGMII mux disable */
1094 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1095 LAN887X_SGMII_CTL,
1096 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1097 if (ret < 0)
1098 return ret;
1099
1100 /* Select MAC_MODE as RGMII */
1101 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1102 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1103 LAN887X_MAC_MODE_RGMII);
1104 if (ret < 0)
1105 return ret;
1106
1107 /* Disable PCS */
1108 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1109 LAN887X_SGMII_PCS_CFG,
1110 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1111 if (ret < 0)
1112 return ret;
1113
1114 /* LAN887x Errata: RGMII rx clock active in SGMII mode
1115 * Disabled it for SGMII mode
1116 * Re-enabling it for RGMII mode
1117 */
1118 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1119 LAN887X_MIS_CFG_REG0,
1120 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1121 }
1122
lan887x_sgmii_init(struct phy_device * phydev)1123 static int lan887x_sgmii_init(struct phy_device *phydev)
1124 {
1125 int ret;
1126
1127 /* SGMII mux enable */
1128 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1129 LAN887X_SGMII_CTL,
1130 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1131 if (ret < 0)
1132 return ret;
1133
1134 /* Select MAC_MODE as SGMII */
1135 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1136 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1137 LAN887X_MAC_MODE_SGMII);
1138 if (ret < 0)
1139 return ret;
1140
1141 /* LAN887x Errata: RGMII rx clock active in SGMII mode.
1142 * So disabling it for SGMII mode
1143 */
1144 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1145 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1146 if (ret < 0)
1147 return ret;
1148
1149 /* Enable PCS */
1150 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
1151 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1152 }
1153
lan887x_config_rgmii_en(struct phy_device * phydev)1154 static int lan887x_config_rgmii_en(struct phy_device *phydev)
1155 {
1156 int txc;
1157 int rxc;
1158 int ret;
1159
1160 ret = lan887x_rgmii_init(phydev);
1161 if (ret < 0)
1162 return ret;
1163
1164 /* Control bit to enable/disable TX DLL delay line in signal path */
1165 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
1166 if (txc < 0)
1167 return txc;
1168
1169 /* Control bit to enable/disable RX DLL delay line in signal path */
1170 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
1171 if (rxc < 0)
1172 return rxc;
1173
1174 /* Configures the phy to enable RX/TX delay
1175 * RGMII - TX & RX delays are either added by MAC or not needed,
1176 * phy should not add
1177 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add
1178 * RGMII_RX_ID - Configures the PHY to enable the RX delay.
1179 * The MAC shouldn't add the RX delay
1180 * RGMII_TX_ID - Configures the PHY to enable the TX delay.
1181 * The MAC shouldn't add the TX delay in this case
1182 */
1183 switch (phydev->interface) {
1184 case PHY_INTERFACE_MODE_RGMII:
1185 txc &= ~LAN887X_MIS_DLL_CONF;
1186 rxc &= ~LAN887X_MIS_DLL_CONF;
1187 break;
1188 case PHY_INTERFACE_MODE_RGMII_ID:
1189 txc |= LAN887X_MIS_DLL_CONF;
1190 rxc |= LAN887X_MIS_DLL_CONF;
1191 break;
1192 case PHY_INTERFACE_MODE_RGMII_RXID:
1193 txc &= ~LAN887X_MIS_DLL_CONF;
1194 rxc |= LAN887X_MIS_DLL_CONF;
1195 break;
1196 case PHY_INTERFACE_MODE_RGMII_TXID:
1197 txc |= LAN887X_MIS_DLL_CONF;
1198 rxc &= ~LAN887X_MIS_DLL_CONF;
1199 break;
1200 default:
1201 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface);
1202 return 0;
1203 }
1204
1205 /* Configures the PHY to enable/disable RX delay in signal path */
1206 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
1207 LAN887X_MIS_DLL_CONF, rxc);
1208 if (ret < 0)
1209 return ret;
1210
1211 /* Configures the PHY to enable/disable the TX delay in signal path */
1212 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
1213 LAN887X_MIS_DLL_CONF, txc);
1214 }
1215
lan887x_config_phy_interface(struct phy_device * phydev)1216 static int lan887x_config_phy_interface(struct phy_device *phydev)
1217 {
1218 int interface_mode;
1219 int sgmii_dis;
1220 int ret;
1221
1222 /* Read sku efuse data for interfaces supported by sku */
1223 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
1224 if (ret < 0)
1225 return ret;
1226
1227 /* If interface_mode is 1 then efuse sets RGMII operations.
1228 * If interface mode is 3 then efuse sets SGMII operations.
1229 */
1230 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE;
1231 /* SGMII disable is set for RGMII operations */
1232 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS;
1233
1234 switch (phydev->interface) {
1235 case PHY_INTERFACE_MODE_RGMII:
1236 case PHY_INTERFACE_MODE_RGMII_ID:
1237 case PHY_INTERFACE_MODE_RGMII_RXID:
1238 case PHY_INTERFACE_MODE_RGMII_TXID:
1239 /* Reject RGMII settings for SGMII only sku */
1240 ret = -EOPNOTSUPP;
1241
1242 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==
1243 LAN887X_MAC_MODE_SGMII))
1244 ret = lan887x_config_rgmii_en(phydev);
1245 break;
1246 case PHY_INTERFACE_MODE_SGMII:
1247 /* Reject SGMII setting for RGMII only sku */
1248 ret = -EOPNOTSUPP;
1249
1250 if (!sgmii_dis)
1251 ret = lan887x_sgmii_init(phydev);
1252 break;
1253 default:
1254 /* Reject setting for unsupported interfaces */
1255 ret = -EOPNOTSUPP;
1256 }
1257
1258 return ret;
1259 }
1260
lan887x_get_features(struct phy_device * phydev)1261 static int lan887x_get_features(struct phy_device *phydev)
1262 {
1263 int ret;
1264
1265 ret = genphy_c45_pma_read_abilities(phydev);
1266 if (ret < 0)
1267 return ret;
1268
1269 /* Enable twisted pair */
1270 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1271
1272 /* First patch only supports 100Mbps and 1000Mbps force-mode.
1273 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later.
1274 */
1275 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1276
1277 return 0;
1278 }
1279
lan887x_phy_init(struct phy_device * phydev)1280 static int lan887x_phy_init(struct phy_device *phydev)
1281 {
1282 struct lan887x_priv *priv = phydev->priv;
1283 int ret;
1284
1285 if (!priv->init_done && phy_interrupt_is_valid(phydev)) {
1286 priv->clock = mchp_rds_ptp_probe(phydev, MDIO_MMD_VEND1,
1287 MCHP_RDS_PTP_LTC_BASE_ADDR,
1288 MCHP_RDS_PTP_PORT_BASE_ADDR);
1289 if (IS_ERR(priv->clock))
1290 return PTR_ERR(priv->clock);
1291
1292 /* Enable pin mux for EVT */
1293 phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1294 LAN887X_MX_CHIP_TOP_REG_CONTROL1,
1295 LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN,
1296 LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN);
1297
1298 /* Initialize pin numbers specific to PEROUT */
1299 priv->clock->event_pin = 3;
1300
1301 priv->init_done = true;
1302 }
1303
1304 /* Clear loopback */
1305 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1306 LAN887X_MIS_CFG_REG2,
1307 LAN887X_MIS_CFG_REG2_FE_LPBK_EN);
1308 if (ret < 0)
1309 return ret;
1310
1311 /* Configure default behavior of led to link and activity for any
1312 * speed
1313 */
1314 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1315 LAN887X_COMMON_LED3_LED2,
1316 LAN887X_COMMON_LED2_MODE_SEL_MASK,
1317 LAN887X_LED_LINK_ACT_ANY_SPEED);
1318 if (ret < 0)
1319 return ret;
1320
1321 /* PHY interface setup */
1322 return lan887x_config_phy_interface(phydev);
1323 }
1324
lan887x_phy_config(struct phy_device * phydev,const struct lan887x_regwr_map * reg_map,int cnt)1325 static int lan887x_phy_config(struct phy_device *phydev,
1326 const struct lan887x_regwr_map *reg_map, int cnt)
1327 {
1328 int ret;
1329
1330 for (int i = 0; i < cnt; i++) {
1331 ret = phy_write_mmd(phydev, reg_map[i].mmd,
1332 reg_map[i].reg, reg_map[i].val);
1333 if (ret < 0)
1334 return ret;
1335 }
1336
1337 return 0;
1338 }
1339
lan887x_phy_setup(struct phy_device * phydev)1340 static int lan887x_phy_setup(struct phy_device *phydev)
1341 {
1342 static const struct lan887x_regwr_map phy_cfg[] = {
1343 /* PORT_AFE writes */
1344 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},
1345 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},
1346 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},
1347 /* 100T1_PCS_VENDOR writes */
1348 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},
1349 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},
1350 /* 100T1 DSP writes */
1351 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
1352 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
1353 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
1354 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
1355 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
1356 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
1357 /* 1000T1 DSP writes */
1358 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
1359 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
1360 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
1361 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
1362 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
1363 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
1364 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
1365 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
1366 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
1367 /* 1000T1 PCS writes */
1368 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},
1369 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},
1370 };
1371
1372 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1373 }
1374
lan887x_100M_setup(struct phy_device * phydev)1375 static int lan887x_100M_setup(struct phy_device *phydev)
1376 {
1377 int ret;
1378
1379 /* (Re)configure the speed/mode dependent T1 settings */
1380 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||
1381 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){
1382 static const struct lan887x_regwr_map phy_cfg[] = {
1383 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1384 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},
1385 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
1386 };
1387
1388 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1389 } else {
1390 static const struct lan887x_regwr_map phy_cfg[] = {
1391 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},
1392 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
1393 };
1394
1395 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1396 }
1397 if (ret < 0)
1398 return ret;
1399
1400 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1401 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1402 }
1403
lan887x_1000M_setup(struct phy_device * phydev)1404 static int lan887x_1000M_setup(struct phy_device *phydev)
1405 {
1406 static const struct lan887x_regwr_map phy_cfg[] = {
1407 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},
1408 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1409 };
1410 int ret;
1411
1412 /* (Re)configure the speed/mode dependent T1 settings */
1413 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1414 if (ret < 0)
1415 return ret;
1416
1417 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1418 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1419 }
1420
lan887x_link_setup(struct phy_device * phydev)1421 static int lan887x_link_setup(struct phy_device *phydev)
1422 {
1423 int ret = -EINVAL;
1424
1425 if (phydev->speed == SPEED_1000)
1426 ret = lan887x_1000M_setup(phydev);
1427 else if (phydev->speed == SPEED_100)
1428 ret = lan887x_100M_setup(phydev);
1429
1430 return ret;
1431 }
1432
1433 /* LAN887x Errata: speed configuration changes require soft reset
1434 * and chip soft reset
1435 */
lan887x_phy_reset(struct phy_device * phydev)1436 static int lan887x_phy_reset(struct phy_device *phydev)
1437 {
1438 int ret, val;
1439
1440 /* Clear 1000M link sync */
1441 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1442 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1443 if (ret < 0)
1444 return ret;
1445
1446 /* Clear 100M link sync */
1447 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1448 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1449 if (ret < 0)
1450 return ret;
1451
1452 /* Chiptop soft-reset to allow the speed/mode change */
1453 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
1454 LAN887X_CHIP_SOFT_RST_RESET);
1455 if (ret < 0)
1456 return ret;
1457
1458 /* CL22 soft-reset to let the link re-train */
1459 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);
1460 if (ret < 0)
1461 return ret;
1462
1463 /* Wait for reset complete or timeout if > 10ms */
1464 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1465 5000, 10000, true);
1466 }
1467
lan887x_phy_reconfig(struct phy_device * phydev)1468 static int lan887x_phy_reconfig(struct phy_device *phydev)
1469 {
1470 int ret;
1471
1472 linkmode_zero(phydev->advertising);
1473
1474 ret = genphy_c45_pma_setup_forced(phydev);
1475 if (ret < 0)
1476 return ret;
1477
1478 return lan887x_link_setup(phydev);
1479 }
1480
lan887x_config_aneg(struct phy_device * phydev)1481 static int lan887x_config_aneg(struct phy_device *phydev)
1482 {
1483 int ret;
1484
1485 /* LAN887x Errata: speed configuration changes require soft reset
1486 * and chip soft reset
1487 */
1488 ret = lan887x_phy_reset(phydev);
1489 if (ret < 0)
1490 return ret;
1491
1492 return lan887x_phy_reconfig(phydev);
1493 }
1494
lan887x_probe(struct phy_device * phydev)1495 static int lan887x_probe(struct phy_device *phydev)
1496 {
1497 struct lan887x_priv *priv;
1498
1499 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1500 if (!priv)
1501 return -ENOMEM;
1502
1503 priv->init_done = false;
1504 phydev->priv = priv;
1505
1506 return lan887x_phy_setup(phydev);
1507 }
1508
lan887x_get_stat(struct phy_device * phydev,int i)1509 static u64 lan887x_get_stat(struct phy_device *phydev, int i)
1510 {
1511 struct lan887x_hw_stat stat = lan887x_hw_stats[i];
1512 struct lan887x_priv *priv = phydev->priv;
1513 int val;
1514 u64 ret;
1515
1516 if (stat.mmd)
1517 val = phy_read_mmd(phydev, stat.mmd, stat.reg);
1518 else
1519 val = phy_read(phydev, stat.reg);
1520
1521 if (val < 0) {
1522 ret = U64_MAX;
1523 } else {
1524 val = val & ((1 << stat.bits) - 1);
1525 priv->stats[i] += val;
1526 ret = priv->stats[i];
1527 }
1528
1529 return ret;
1530 }
1531
lan887x_get_stats(struct phy_device * phydev,struct ethtool_stats * stats,u64 * data)1532 static void lan887x_get_stats(struct phy_device *phydev,
1533 struct ethtool_stats *stats, u64 *data)
1534 {
1535 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1536 data[i] = lan887x_get_stat(phydev, i);
1537 }
1538
lan887x_get_sset_count(struct phy_device * phydev)1539 static int lan887x_get_sset_count(struct phy_device *phydev)
1540 {
1541 return ARRAY_SIZE(lan887x_hw_stats);
1542 }
1543
lan887x_get_strings(struct phy_device * phydev,u8 * data)1544 static void lan887x_get_strings(struct phy_device *phydev, u8 *data)
1545 {
1546 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1547 ethtool_puts(&data, lan887x_hw_stats[i].string);
1548 }
1549
lan887x_config_intr(struct phy_device * phydev)1550 static int lan887x_config_intr(struct phy_device *phydev)
1551 {
1552 struct lan887x_priv *priv = phydev->priv;
1553 int rc;
1554
1555 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1556 /* Clear the interrupt status before enabling interrupts */
1557 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1558 if (rc < 0)
1559 return rc;
1560
1561 /* Unmask for enabling interrupt */
1562 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1563 (u16)~LAN887X_MX_CHIP_TOP_ALL_MSK);
1564 } else {
1565 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1566 GENMASK(15, 0));
1567 if (rc < 0)
1568 return rc;
1569
1570 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1571 }
1572 if (rc < 0)
1573 return rc;
1574
1575 if (phy_is_default_hwtstamp(phydev)) {
1576 return mchp_rds_ptp_top_config_intr(priv->clock,
1577 LAN887X_INT_MSK,
1578 LAN887X_INT_MSK_P1588_MOD_INT_MSK,
1579 (phydev->interrupts ==
1580 PHY_INTERRUPT_ENABLED));
1581 }
1582
1583 return 0;
1584 }
1585
lan887x_handle_interrupt(struct phy_device * phydev)1586 static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev)
1587 {
1588 struct lan887x_priv *priv = phydev->priv;
1589 int rc = IRQ_NONE;
1590 int irq_status;
1591
1592 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1593 if (irq_status < 0) {
1594 phy_error(phydev);
1595 return IRQ_NONE;
1596 }
1597
1598 if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) {
1599 phy_trigger_machine(phydev);
1600 rc = IRQ_HANDLED;
1601 }
1602
1603 if (irq_status & LAN887X_INT_MSK_P1588_MOD_INT_MSK)
1604 rc = mchp_rds_ptp_handle_interrupt(priv->clock);
1605
1606 return rc;
1607 }
1608
lan887x_cd_reset(struct phy_device * phydev,enum cable_diag_state cd_done)1609 static int lan887x_cd_reset(struct phy_device *phydev,
1610 enum cable_diag_state cd_done)
1611 {
1612 u16 val;
1613 int rc;
1614
1615 /* Chip hard-reset */
1616 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,
1617 LAN887X_CHIP_HARD_RST_RESET);
1618 if (rc < 0)
1619 return rc;
1620
1621 /* Wait for reset to complete */
1622 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val,
1623 ((val & GENMASK(15, 4)) ==
1624 (PHY_ID_LAN887X & GENMASK(15, 4))),
1625 5000, 50000, true);
1626 if (rc < 0)
1627 return rc;
1628
1629 if (cd_done == CD_TEST_DONE) {
1630 /* Cable diagnostics complete. Restore PHY. */
1631 rc = lan887x_phy_setup(phydev);
1632 if (rc < 0)
1633 return rc;
1634
1635 rc = lan887x_phy_init(phydev);
1636 if (rc < 0)
1637 return rc;
1638
1639 rc = lan887x_config_intr(phydev);
1640 if (rc < 0)
1641 return rc;
1642
1643 rc = lan887x_phy_reconfig(phydev);
1644 if (rc < 0)
1645 return rc;
1646 }
1647
1648 return 0;
1649 }
1650
lan887x_cable_test_prep(struct phy_device * phydev,enum cable_diag_mode mode)1651 static int lan887x_cable_test_prep(struct phy_device *phydev,
1652 enum cable_diag_mode mode)
1653 {
1654 static const struct lan887x_regwr_map values[] = {
1655 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
1656 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
1657 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
1658 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
1659 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
1660 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
1661 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
1662 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
1663 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
1664
1665 };
1666 int rc;
1667
1668 rc = lan887x_cd_reset(phydev, CD_TEST_INIT);
1669 if (rc < 0)
1670 return rc;
1671
1672 /* Forcing DUT to master mode, as we don't care about
1673 * mode during diagnostics
1674 */
1675 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
1676 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
1677 if (rc < 0)
1678 return rc;
1679
1680 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038);
1681 if (rc < 0)
1682 return rc;
1683
1684 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1685 LAN887X_CALIB_CONFIG_100, 0,
1686 LAN887X_CALIB_CONFIG_100_VAL);
1687 if (rc < 0)
1688 return rc;
1689
1690 for (int i = 0; i < ARRAY_SIZE(values); i++) {
1691 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg,
1692 values[i].val);
1693 if (rc < 0)
1694 return rc;
1695
1696 if (mode &&
1697 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) {
1698 rc = phy_write_mmd(phydev, values[i].mmd,
1699 values[i].reg, 0xa);
1700 if (rc < 0)
1701 return rc;
1702 }
1703 }
1704
1705 if (mode == TEST_MODE_HYBRID) {
1706 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD,
1707 LAN887X_AFE_PORT_TESTBUS_CTRL4,
1708 BIT(0), BIT(0));
1709 if (rc < 0)
1710 return rc;
1711 }
1712
1713 /* HW_INIT 100T1, Get DUT running in 100T1 mode */
1714 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1715 LAN887X_REG_REG26_HW_INIT_SEQ_EN,
1716 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1717 if (rc < 0)
1718 return rc;
1719
1720 /* Cable diag requires hard reset and is sensitive regarding the delays.
1721 * Hard reset is expected into and out of cable diag.
1722 * Wait for 50ms
1723 */
1724 msleep(50);
1725
1726 /* Start cable diag */
1727 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1728 LAN887X_START_CBL_DIAG_100,
1729 LAN887X_CBL_DIAG_START);
1730 }
1731
lan887x_cable_test_chk(struct phy_device * phydev,enum cable_diag_mode mode)1732 static int lan887x_cable_test_chk(struct phy_device *phydev,
1733 enum cable_diag_mode mode)
1734 {
1735 int val;
1736 int rc;
1737
1738 if (mode == TEST_MODE_HYBRID) {
1739 /* Cable diag requires hard reset and is sensitive regarding the delays.
1740 * Hard reset is expected into and out of cable diag.
1741 * Wait for cable diag to complete.
1742 * Minimum wait time is 50ms if the condition is not a match.
1743 */
1744 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1745 LAN887X_START_CBL_DIAG_100, val,
1746 ((val & LAN887X_CBL_DIAG_DONE) ==
1747 LAN887X_CBL_DIAG_DONE),
1748 50000, 500000, false);
1749 if (rc < 0)
1750 return rc;
1751 } else {
1752 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1753 LAN887X_START_CBL_DIAG_100);
1754 if (rc < 0)
1755 return rc;
1756
1757 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE)
1758 return -EAGAIN;
1759 }
1760
1761 /* Stop cable diag */
1762 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1763 LAN887X_START_CBL_DIAG_100,
1764 LAN887X_CBL_DIAG_STOP);
1765 }
1766
lan887x_cable_test_start(struct phy_device * phydev)1767 static int lan887x_cable_test_start(struct phy_device *phydev)
1768 {
1769 int rc, ret;
1770
1771 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL);
1772 if (rc < 0) {
1773 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1774 if (ret < 0)
1775 return ret;
1776
1777 return rc;
1778 }
1779
1780 return 0;
1781 }
1782
lan887x_cable_test_report(struct phy_device * phydev)1783 static int lan887x_cable_test_report(struct phy_device *phydev)
1784 {
1785 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases;
1786 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time;
1787 int neg_peak_cycle, neg_peak_in_phases;
1788 int pos_peak_in_phases_hybrid;
1789 int gain_idx, gain_idx_hybrid;
1790 int pos_peak_phase_hybrid;
1791 int pos_peak, neg_peak;
1792 int distance;
1793 int detect;
1794 int length;
1795 int ret;
1796 int rc;
1797
1798 /* Read non-hybrid results */
1799 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1800 LAN887X_CBL_DIAG_AGC_GAIN_100);
1801 if (gain_idx < 0) {
1802 rc = gain_idx;
1803 goto error;
1804 }
1805
1806 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1807 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100);
1808 if (pos_peak < 0) {
1809 rc = pos_peak;
1810 goto error;
1811 }
1812
1813 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1814 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100);
1815 if (neg_peak < 0) {
1816 rc = neg_peak;
1817 goto error;
1818 }
1819
1820 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1821 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1822 if (pos_peak_time < 0) {
1823 rc = pos_peak_time;
1824 goto error;
1825 }
1826
1827 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1828 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100);
1829 if (neg_peak_time < 0) {
1830 rc = neg_peak_time;
1831 goto error;
1832 }
1833
1834 /* Calculate non-hybrid values */
1835 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f;
1836 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f);
1837 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f;
1838 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f);
1839
1840 /* Deriving the status of cable */
1841 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN &&
1842 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) {
1843 if (pos_peak_in_phases > neg_peak_in_phases &&
1844 ((pos_peak_in_phases - neg_peak_in_phases) >=
1845 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1846 ((pos_peak_in_phases - neg_peak_in_phases) <
1847 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1848 pos_peak_in_phases > 0) {
1849 detect = LAN87XX_CABLE_TEST_SAME_SHORT;
1850 } else if (neg_peak_in_phases > pos_peak_in_phases &&
1851 ((neg_peak_in_phases - pos_peak_in_phases) >=
1852 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1853 ((neg_peak_in_phases - pos_peak_in_phases) <
1854 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1855 neg_peak_in_phases > 0) {
1856 detect = LAN87XX_CABLE_TEST_OPEN;
1857 } else {
1858 detect = LAN87XX_CABLE_TEST_OK;
1859 }
1860 } else {
1861 detect = LAN87XX_CABLE_TEST_OK;
1862 }
1863
1864 if (detect == LAN87XX_CABLE_TEST_OK) {
1865 distance = 0;
1866 goto get_len;
1867 }
1868
1869 /* Re-initialize PHY and start cable diag test */
1870 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID);
1871 if (rc < 0)
1872 goto cd_stop;
1873
1874 /* Wait for cable diag test completion */
1875 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID);
1876 if (rc < 0)
1877 goto cd_stop;
1878
1879 /* Read hybrid results */
1880 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1881 LAN887X_CBL_DIAG_AGC_GAIN_100);
1882 if (gain_idx_hybrid < 0) {
1883 rc = gain_idx_hybrid;
1884 goto error;
1885 }
1886
1887 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1888 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1889 if (pos_peak_time_hybrid < 0) {
1890 rc = pos_peak_time_hybrid;
1891 goto error;
1892 }
1893
1894 /* Calculate hybrid values to derive cable length to fault */
1895 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f;
1896 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f;
1897 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 +
1898 pos_peak_phase_hybrid;
1899
1900 /* Distance to fault calculation.
1901 * distance = (peak_in_phases - peak_in_phases_hybrid) *
1902 * propagationconstant.
1903 * constant to convert number of phases to meters
1904 * propagationconstant = 0.015953
1905 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5)
1906 * Applying constant 1.5953 as ethtool further devides by 100 to
1907 * convert to meters.
1908 */
1909 if (detect == LAN87XX_CABLE_TEST_OPEN) {
1910 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid)
1911 * 15953) / 10000);
1912 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) {
1913 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid)
1914 * 15953) / 10000);
1915 } else {
1916 distance = 0;
1917 }
1918
1919 get_len:
1920 rc = lan887x_cd_reset(phydev, CD_TEST_DONE);
1921 if (rc < 0)
1922 return rc;
1923
1924 length = ((u32)distance & GENMASK(15, 0));
1925 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1926 lan87xx_cable_test_report_trans(detect));
1927 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length);
1928
1929 return 0;
1930
1931 cd_stop:
1932 /* Stop cable diag */
1933 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1934 LAN887X_START_CBL_DIAG_100,
1935 LAN887X_CBL_DIAG_STOP);
1936 if (ret < 0)
1937 return ret;
1938
1939 error:
1940 /* Cable diag test failed */
1941 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1942 if (ret < 0)
1943 return ret;
1944
1945 /* Return error in failure case */
1946 return rc;
1947 }
1948
lan887x_cable_test_get_status(struct phy_device * phydev,bool * finished)1949 static int lan887x_cable_test_get_status(struct phy_device *phydev,
1950 bool *finished)
1951 {
1952 int rc;
1953
1954 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL);
1955 if (rc < 0) {
1956 /* Let PHY statemachine poll again */
1957 if (rc == -EAGAIN)
1958 return 0;
1959 return rc;
1960 }
1961
1962 /* Cable diag test complete */
1963 *finished = true;
1964
1965 /* Retrieve test status and cable length to fault */
1966 return lan887x_cable_test_report(phydev);
1967 }
1968
1969 /* Compare block to sort in ascending order */
sqi_compare(const void * a,const void * b)1970 static int sqi_compare(const void *a, const void *b)
1971 {
1972 return *(u16 *)a - *(u16 *)b;
1973 }
1974
lan887x_get_sqi_100M(struct phy_device * phydev)1975 static int lan887x_get_sqi_100M(struct phy_device *phydev)
1976 {
1977 u16 rawtable[SQI_SAMPLES];
1978 u32 sqiavg = 0;
1979 u8 sqinum = 0;
1980 int rc, i;
1981
1982 /* Configuration of SQI 100M */
1983 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1984 LAN887X_COEFF_PWR_DN_CONFIG_100,
1985 LAN887X_COEFF_PWR_DN_CONFIG_100_V);
1986 if (rc < 0)
1987 return rc;
1988
1989 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100,
1990 LAN887X_SQI_CONFIG_100_V);
1991 if (rc < 0)
1992 return rc;
1993
1994 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100);
1995 if (rc != LAN887X_SQI_CONFIG_100_V)
1996 return -EINVAL;
1997
1998 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
1999 LAN887X_POKE_PEEK_100_EN,
2000 LAN887X_POKE_PEEK_100_EN);
2001 if (rc < 0)
2002 return rc;
2003
2004 /* Required before reading register
2005 * otherwise it will return high value
2006 */
2007 msleep(50);
2008
2009 /* Link check before raw readings */
2010 rc = genphy_c45_read_link(phydev);
2011 if (rc < 0)
2012 return rc;
2013
2014 if (!phydev->link)
2015 return -ENETDOWN;
2016
2017 /* Get 200 SQI raw readings */
2018 for (i = 0; i < SQI_SAMPLES; i++) {
2019 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
2020 LAN887X_POKE_PEEK_100,
2021 LAN887X_POKE_PEEK_100_EN);
2022 if (rc < 0)
2023 return rc;
2024
2025 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
2026 LAN887X_SQI_MSE_100);
2027 if (rc < 0)
2028 return rc;
2029
2030 rawtable[i] = (u16)rc;
2031 }
2032
2033 /* Link check after raw readings */
2034 rc = genphy_c45_read_link(phydev);
2035 if (rc < 0)
2036 return rc;
2037
2038 if (!phydev->link)
2039 return -ENETDOWN;
2040
2041 /* Sort SQI raw readings in ascending order */
2042 sort(rawtable, SQI_SAMPLES, sizeof(u16), sqi_compare, NULL);
2043
2044 /* Keep inliers and discard outliers */
2045 for (i = SQI_INLIERS_START; i < SQI_INLIERS_END; i++)
2046 sqiavg += rawtable[i];
2047
2048 /* Handle invalid samples */
2049 if (sqiavg != 0) {
2050 /* Get SQI average */
2051 sqiavg /= SQI_INLIERS_NUM;
2052
2053 if (sqiavg < 75)
2054 sqinum = 7;
2055 else if (sqiavg < 94)
2056 sqinum = 6;
2057 else if (sqiavg < 119)
2058 sqinum = 5;
2059 else if (sqiavg < 150)
2060 sqinum = 4;
2061 else if (sqiavg < 189)
2062 sqinum = 3;
2063 else if (sqiavg < 237)
2064 sqinum = 2;
2065 else if (sqiavg < 299)
2066 sqinum = 1;
2067 else
2068 sqinum = 0;
2069 }
2070
2071 return sqinum;
2072 }
2073
lan887x_get_sqi(struct phy_device * phydev)2074 static int lan887x_get_sqi(struct phy_device *phydev)
2075 {
2076 int rc, val;
2077
2078 if (phydev->speed != SPEED_1000 &&
2079 phydev->speed != SPEED_100)
2080 return -ENETDOWN;
2081
2082 if (phydev->speed == SPEED_100)
2083 return lan887x_get_sqi_100M(phydev);
2084
2085 /* Writing DCQ_COEFF_EN to trigger a SQI read */
2086 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2087 LAN887X_COEFF_MOD_CONFIG,
2088 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN);
2089 if (rc < 0)
2090 return rc;
2091
2092 /* Wait for DCQ done */
2093 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2094 LAN887X_COEFF_MOD_CONFIG, val, ((val &
2095 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN) !=
2096 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN),
2097 10, 200, true);
2098 if (rc < 0)
2099 return rc;
2100
2101 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS);
2102 if (rc < 0)
2103 return rc;
2104
2105 return FIELD_GET(T1_DCQ_SQI_MSK, rc);
2106 }
2107
2108 static struct phy_driver microchip_t1_phy_driver[] = {
2109 {
2110 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),
2111 .name = "Microchip LAN87xx T1",
2112 .flags = PHY_POLL_CABLE_TEST,
2113 .features = PHY_BASIC_T1_FEATURES,
2114 .config_init = lan87xx_config_init,
2115 .config_intr = lan87xx_phy_config_intr,
2116 .handle_interrupt = lan87xx_handle_interrupt,
2117 .suspend = genphy_suspend,
2118 .resume = genphy_resume,
2119 .config_aneg = lan87xx_config_aneg,
2120 .read_status = lan87xx_read_status,
2121 .get_sqi = lan87xx_get_sqi,
2122 .get_sqi_max = lan87xx_get_sqi_max,
2123 .cable_test_start = lan87xx_cable_test_start,
2124 .cable_test_get_status = lan87xx_cable_test_get_status,
2125 },
2126 {
2127 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X),
2128 .name = "Microchip LAN937x T1",
2129 .flags = PHY_POLL_CABLE_TEST,
2130 .features = PHY_BASIC_T1_FEATURES,
2131 .config_init = lan87xx_config_init,
2132 .config_intr = lan87xx_phy_config_intr,
2133 .handle_interrupt = lan87xx_handle_interrupt,
2134 .suspend = genphy_suspend,
2135 .resume = genphy_resume,
2136 .config_aneg = lan87xx_config_aneg,
2137 .read_status = lan87xx_read_status,
2138 .get_sqi = lan87xx_get_sqi,
2139 .get_sqi_max = lan87xx_get_sqi_max,
2140 .cable_test_start = lan87xx_cable_test_start,
2141 .cable_test_get_status = lan87xx_cable_test_get_status,
2142 },
2143 {
2144 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X),
2145 .name = "Microchip LAN887x T1 PHY",
2146 .flags = PHY_POLL_CABLE_TEST,
2147 .probe = lan887x_probe,
2148 .get_features = lan887x_get_features,
2149 .config_init = lan887x_phy_init,
2150 .config_aneg = lan887x_config_aneg,
2151 .get_stats = lan887x_get_stats,
2152 .get_sset_count = lan887x_get_sset_count,
2153 .get_strings = lan887x_get_strings,
2154 .suspend = genphy_suspend,
2155 .resume = genphy_resume,
2156 .read_status = genphy_c45_read_status,
2157 .cable_test_start = lan887x_cable_test_start,
2158 .cable_test_get_status = lan887x_cable_test_get_status,
2159 .config_intr = lan887x_config_intr,
2160 .handle_interrupt = lan887x_handle_interrupt,
2161 .get_sqi = lan887x_get_sqi,
2162 .get_sqi_max = lan87xx_get_sqi_max,
2163 .set_loopback = genphy_c45_loopback,
2164 }
2165 };
2166
2167 module_phy_driver(microchip_t1_phy_driver);
2168
2169 static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
2170 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
2171 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
2172 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
2173 { }
2174 };
2175
2176 MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl);
2177
2178 MODULE_AUTHOR(DRIVER_AUTHOR);
2179 MODULE_DESCRIPTION(DRIVER_DESC);
2180 MODULE_LICENSE("GPL");
2181