1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for Xilinx Axi Ethernet device driver.
4 *
5 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
7 */
8
9 #ifndef XILINX_AXIENET_H
10 #define XILINX_AXIENET_H
11
12 #include <linux/netdevice.h>
13 #include <linux/spinlock.h>
14 #include <linux/interrupt.h>
15 #include <linux/if_vlan.h>
16 #include <linux/phylink.h>
17 #include <linux/skbuff.h>
18
19 /* Packet size info */
20 #define XAE_HDR_SIZE 14 /* Size of Ethernet header */
21 #define XAE_TRL_SIZE 4 /* Size of Ethernet trailer (FCS) */
22 #define XAE_MTU 1500 /* Max MTU of an Ethernet frame */
23 #define XAE_JUMBO_MTU 9000 /* Max MTU of a jumbo Eth. frame */
24
25 #define XAE_MAX_FRAME_SIZE (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
26 #define XAE_MAX_VLAN_FRAME_SIZE (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)
27 #define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
28
29 /* Configuration options */
30
31 /* Accept all incoming packets. Default: disabled (cleared) */
32 #define XAE_OPTION_PROMISC BIT(0)
33
34 /* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
35 #define XAE_OPTION_JUMBO BIT(1)
36
37 /* VLAN Rx & Tx frame support. Default: disabled (cleared) */
38 #define XAE_OPTION_VLAN BIT(2)
39
40 /* Enable recognition of flow control frames on Rx. Default: enabled (set) */
41 #define XAE_OPTION_FLOW_CONTROL BIT(4)
42
43 /* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
44 * stripped. Default: disabled (set)
45 */
46 #define XAE_OPTION_FCS_STRIP BIT(5)
47
48 /* Generate FCS field and add PAD automatically for outgoing frames.
49 * Default: enabled (set)
50 */
51 #define XAE_OPTION_FCS_INSERT BIT(6)
52
53 /* Enable Length/Type error checking for incoming frames. When this option is
54 * set, the MAC will filter frames that have a mismatched type/length field
55 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
56 * types of frames are encountered. When this option is cleared, the MAC will
57 * allow these types of frames to be received. Default: enabled (set)
58 */
59 #define XAE_OPTION_LENTYPE_ERR BIT(7)
60
61 /* Enable the transmitter. Default: enabled (set) */
62 #define XAE_OPTION_TXEN BIT(11)
63
64 /* Enable the receiver. Default: enabled (set) */
65 #define XAE_OPTION_RXEN BIT(12)
66
67 /* Default options set when device is initialized or reset */
68 #define XAE_OPTION_DEFAULTS \
69 (XAE_OPTION_TXEN | \
70 XAE_OPTION_FLOW_CONTROL | \
71 XAE_OPTION_RXEN)
72
73 /* Axi DMA Register definitions */
74
75 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */
76 #define XAXIDMA_TX_SR_OFFSET 0x00000004 /* Status */
77 #define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
78 #define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
79
80 #define XAXIDMA_RX_CR_OFFSET 0x00000030 /* Channel control */
81 #define XAXIDMA_RX_SR_OFFSET 0x00000034 /* Status */
82 #define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
83 #define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
84
85 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
86 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
87
88 #define XAXIDMA_SR_HALT_MASK 0x00000001 /* Indicates DMA channel halted */
89
90 #define XAXIDMA_BD_NDESC_OFFSET 0x00 /* Next descriptor pointer */
91 #define XAXIDMA_BD_BUFA_OFFSET 0x08 /* Buffer address */
92 #define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /* Control/buffer length */
93 #define XAXIDMA_BD_STS_OFFSET 0x1C /* Status */
94 #define XAXIDMA_BD_USR0_OFFSET 0x20 /* User IP specific word0 */
95 #define XAXIDMA_BD_USR1_OFFSET 0x24 /* User IP specific word1 */
96 #define XAXIDMA_BD_USR2_OFFSET 0x28 /* User IP specific word2 */
97 #define XAXIDMA_BD_USR3_OFFSET 0x2C /* User IP specific word3 */
98 #define XAXIDMA_BD_USR4_OFFSET 0x30 /* User IP specific word4 */
99 #define XAXIDMA_BD_ID_OFFSET 0x34 /* Sw ID */
100 #define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /* Whether has stscntrl strm */
101 #define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /* Whether has DRE */
102
103 #define XAXIDMA_BD_HAS_DRE_SHIFT 8 /* Whether has DRE shift */
104 #define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /* Whether has DRE mask */
105 #define XAXIDMA_BD_WORDLEN_MASK 0xFF /* Whether has DRE mask */
106
107 #define XAXIDMA_BD_CTRL_LENGTH_MASK 0x007FFFFF /* Requested len */
108 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
109 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
110 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
111
112 #define XAXIDMA_DELAY_MASK 0xFF000000 /* Delay timeout counter */
113 #define XAXIDMA_COALESCE_MASK 0x00FF0000 /* Coalesce counter */
114
115 #define XAXIDMA_DELAY_SHIFT 24
116 #define XAXIDMA_COALESCE_SHIFT 16
117
118 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
119 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
120 #define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /* Error interrupt */
121 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
122
123 /* Constant to convert delay counts to microseconds */
124 #define XAXIDMA_DELAY_SCALE (125ULL * USEC_PER_SEC)
125
126 /* Default TX/RX Threshold and delay timer values for SGDMA mode */
127 #define XAXIDMA_DFT_TX_THRESHOLD 24
128 #define XAXIDMA_DFT_TX_USEC 50
129 #define XAXIDMA_DFT_RX_THRESHOLD 1
130 #define XAXIDMA_DFT_RX_USEC 50
131
132 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
133 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
134 #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */
135
136 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
137 #define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /* Completed */
138 #define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /* Decode error */
139 #define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /* Slave error */
140 #define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /* Internal err */
141 #define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /* All errors */
142 #define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /* First rx pkt */
143 #define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /* Last rx pkt */
144 #define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /* All status bits */
145
146 #define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40
147
148 /* Axi Ethernet registers definition */
149 #define XAE_RAF_OFFSET 0x00000000 /* Reset and Address filter */
150 #define XAE_TPF_OFFSET 0x00000004 /* Tx Pause Frame */
151 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
152 #define XAE_IS_OFFSET 0x0000000C /* Interrupt status */
153 #define XAE_IP_OFFSET 0x00000010 /* Interrupt pending */
154 #define XAE_IE_OFFSET 0x00000014 /* Interrupt enable */
155 #define XAE_TTAG_OFFSET 0x00000018 /* Tx VLAN TAG */
156 #define XAE_RTAG_OFFSET 0x0000001C /* Rx VLAN TAG */
157 #define XAE_UAWL_OFFSET 0x00000020 /* Unicast address word lower */
158 #define XAE_UAWU_OFFSET 0x00000024 /* Unicast address word upper */
159 #define XAE_TPID0_OFFSET 0x00000028 /* VLAN TPID0 register */
160 #define XAE_TPID1_OFFSET 0x0000002C /* VLAN TPID1 register */
161 #define XAE_PPST_OFFSET 0x00000030 /* PCS PMA Soft Temac Status Reg */
162 #define XAE_STATS_OFFSET 0x00000200 /* Statistics counters */
163 #define XAE_RCW0_OFFSET 0x00000400 /* Rx Configuration Word 0 */
164 #define XAE_RCW1_OFFSET 0x00000404 /* Rx Configuration Word 1 */
165 #define XAE_TC_OFFSET 0x00000408 /* Tx Configuration */
166 #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */
167 #define XAE_EMMC_OFFSET 0x00000410 /* MAC speed configuration */
168 #define XAE_PHYC_OFFSET 0x00000414 /* RX Max Frame Configuration */
169 #define XAE_ID_OFFSET 0x000004F8 /* Identification register */
170 #define XAE_ABILITY_OFFSET 0x000004FC /* Ability Register offset */
171 #define XAE_MDIO_MC_OFFSET 0x00000500 /* MDIO Setup */
172 #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MDIO Control */
173 #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MDIO Write Data */
174 #define XAE_MDIO_MRD_OFFSET 0x0000050C /* MDIO Read Data */
175 #define XAE_UAW0_OFFSET 0x00000700 /* Unicast address word 0 */
176 #define XAE_UAW1_OFFSET 0x00000704 /* Unicast address word 1 */
177 #define XAE_FMI_OFFSET 0x00000708 /* Frame Filter Control */
178 #define XAE_FFE_OFFSET 0x0000070C /* Frame Filter Enable */
179 #define XAE_AF0_OFFSET 0x00000710 /* Address Filter 0 */
180 #define XAE_AF1_OFFSET 0x00000714 /* Address Filter 1 */
181 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
182 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
183
184 #define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
185 #define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
186 #define XAE_MCAST_TABLE_OFFSET 0x00020000 /* Multicast table address */
187
188 /* Bit Masks for Axi Ethernet RAF register */
189 /* Reject receive multicast destination address */
190 #define XAE_RAF_MCSTREJ_MASK 0x00000002
191 /* Reject receive broadcast destination address */
192 #define XAE_RAF_BCSTREJ_MASK 0x00000004
193 #define XAE_RAF_TXVTAGMODE_MASK 0x00000018 /* Tx VLAN TAG mode */
194 #define XAE_RAF_RXVTAGMODE_MASK 0x00000060 /* Rx VLAN TAG mode */
195 #define XAE_RAF_TXVSTRPMODE_MASK 0x00000180 /* Tx VLAN STRIP mode */
196 #define XAE_RAF_RXVSTRPMODE_MASK 0x00000600 /* Rx VLAN STRIP mode */
197 #define XAE_RAF_NEWFNCENBL_MASK 0x00000800 /* New function mode */
198 /* Extended Multicast Filtering mode */
199 #define XAE_RAF_EMULTIFLTRENBL_MASK 0x00001000
200 #define XAE_RAF_STATSRST_MASK 0x00002000 /* Stats. Counter Reset */
201 #define XAE_RAF_RXBADFRMEN_MASK 0x00004000 /* Recv Bad Frame Enable */
202 #define XAE_RAF_TXVTAGMODE_SHIFT 3 /* Tx Tag mode shift bits */
203 #define XAE_RAF_RXVTAGMODE_SHIFT 5 /* Rx Tag mode shift bits */
204 #define XAE_RAF_TXVSTRPMODE_SHIFT 7 /* Tx strip mode shift bits*/
205 #define XAE_RAF_RXVSTRPMODE_SHIFT 9 /* Rx Strip mode shift bits*/
206
207 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
208 #define XAE_TPF_TPFV_MASK 0x0000FFFF /* Tx pause frame value */
209 /* Transmit inter-frame gap adjustment value */
210 #define XAE_IFGP0_IFGP_MASK 0x0000007F
211
212 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
213 * for all 3 registers.
214 */
215 /* Hard register access complete */
216 #define XAE_INT_HARDACSCMPLT_MASK 0x00000001
217 /* Auto negotiation complete */
218 #define XAE_INT_AUTONEG_MASK 0x00000002
219 #define XAE_INT_RXCMPIT_MASK 0x00000004 /* Rx complete */
220 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
221 #define XAE_INT_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
222 #define XAE_INT_TXCMPIT_MASK 0x00000020 /* Tx complete */
223 #define XAE_INT_RXDCMLOCK_MASK 0x00000040 /* Rx Dcm Lock */
224 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
225 #define XAE_INT_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
226 #define XAE_INT_ALL_MASK 0x0000003F /* All the ints */
227
228 /* INT bits that indicate receive errors */
229 #define XAE_INT_RECV_ERROR_MASK \
230 (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
231
232 /* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
233 #define XAE_TPID_0_MASK 0x0000FFFF /* TPID 0 */
234 #define XAE_TPID_1_MASK 0xFFFF0000 /* TPID 1 */
235
236 /* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
237 #define XAE_TPID_2_MASK 0x0000FFFF /* TPID 0 */
238 #define XAE_TPID_3_MASK 0xFFFF0000 /* TPID 1 */
239
240 /* Bit masks for Axi Ethernet RCW1 register */
241 #define XAE_RCW1_RST_MASK 0x80000000 /* Reset */
242 #define XAE_RCW1_JUM_MASK 0x40000000 /* Jumbo frame enable */
243 /* In-Band FCS enable (FCS not stripped) */
244 #define XAE_RCW1_FCS_MASK 0x20000000
245 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
246 #define XAE_RCW1_VLAN_MASK 0x08000000 /* VLAN frame enable */
247 /* Length/type field valid check disable */
248 #define XAE_RCW1_LT_DIS_MASK 0x02000000
249 /* Control frame Length check disable */
250 #define XAE_RCW1_CL_DIS_MASK 0x01000000
251 /* Pause frame source address bits [47:32]. Bits [31:0] are
252 * stored in register RCW0
253 */
254 #define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
255
256 /* Bit masks for Axi Ethernet TC register */
257 #define XAE_TC_RST_MASK 0x80000000 /* Reset */
258 #define XAE_TC_JUM_MASK 0x40000000 /* Jumbo frame enable */
259 /* In-Band FCS enable (FCS not generated) */
260 #define XAE_TC_FCS_MASK 0x20000000
261 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
262 #define XAE_TC_VLAN_MASK 0x08000000 /* VLAN frame enable */
263 /* Inter-frame gap adjustment enable */
264 #define XAE_TC_IFG_MASK 0x02000000
265
266 /* Bit masks for Axi Ethernet FCC register */
267 #define XAE_FCC_FCRX_MASK 0x20000000 /* Rx flow control enable */
268 #define XAE_FCC_FCTX_MASK 0x40000000 /* Tx flow control enable */
269
270 /* Bit masks for Axi Ethernet EMMC register */
271 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
272 #define XAE_EMMC_RGMII_MASK 0x20000000 /* RGMII mode enable */
273 #define XAE_EMMC_SGMII_MASK 0x10000000 /* SGMII mode enable */
274 #define XAE_EMMC_GPCS_MASK 0x08000000 /* 1000BaseX mode enable */
275 #define XAE_EMMC_HOST_MASK 0x04000000 /* Host interface enable */
276 #define XAE_EMMC_TX16BIT 0x02000000 /* 16 bit Tx client enable */
277 #define XAE_EMMC_RX16BIT 0x01000000 /* 16 bit Rx client enable */
278 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
279 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
280 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
281
282 /* Bit masks for Axi Ethernet PHYC register */
283 #define XAE_PHYC_SGMIILINKSPEED_MASK 0xC0000000 /* SGMII link speed mask*/
284 #define XAE_PHYC_RGMIILINKSPEED_MASK 0x0000000C /* RGMII link speed */
285 #define XAE_PHYC_RGMIIHD_MASK 0x00000002 /* RGMII Half-duplex */
286 #define XAE_PHYC_RGMIILINK_MASK 0x00000001 /* RGMII link status */
287 #define XAE_PHYC_RGLINKSPD_10 0x00000000 /* RGMII link 10 Mbit */
288 #define XAE_PHYC_RGLINKSPD_100 0x00000004 /* RGMII link 100 Mbit */
289 #define XAE_PHYC_RGLINKSPD_1000 0x00000008 /* RGMII link 1000 Mbit */
290 #define XAE_PHYC_SGLINKSPD_10 0x00000000 /* SGMII link 10 Mbit */
291 #define XAE_PHYC_SGLINKSPD_100 0x40000000 /* SGMII link 100 Mbit */
292 #define XAE_PHYC_SGLINKSPD_1000 0x80000000 /* SGMII link 1000 Mbit */
293
294 /* Bit masks for Axi Ethernet ability register */
295 #define XAE_ABILITY_PFC BIT(16)
296 #define XAE_ABILITY_FRAME_FILTER BIT(10)
297 #define XAE_ABILITY_HALF_DUPLEX BIT(9)
298 #define XAE_ABILITY_STATS BIT(8)
299 #define XAE_ABILITY_2_5G BIT(3)
300 #define XAE_ABILITY_1G BIT(2)
301 #define XAE_ABILITY_100M BIT(1)
302 #define XAE_ABILITY_10M BIT(0)
303
304 /* Bit masks for Axi Ethernet MDIO interface MC register */
305 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable */
306 #define XAE_MDIO_MC_CLOCK_DIVIDE_MAX 0x3F /* Maximum MDIO divisor */
307
308 /* Bit masks for Axi Ethernet MDIO interface MCR register */
309 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
310 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
311 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
312 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
313 #define XAE_MDIO_MCR_OP_MASK 0x0000C000 /* Operation Code Mask */
314 #define XAE_MDIO_MCR_OP_SHIFT 13 /* Operation Code Shift */
315 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
316 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
317 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
318 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
319
320 /* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
321 #define XAE_MDIO_INT_MIIM_RDY_MASK 0x00000001 /* MIIM Interrupt */
322
323 /* Bit masks for Axi Ethernet UAW1 register */
324 /* Station address bits [47:32]; Station address
325 * bits [31:0] are stored in register UAW0
326 */
327 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
328
329 /* Bit masks for Axi Ethernet FMC register */
330 #define XAE_FMI_PM_MASK 0x80000000 /* Promis. mode enable */
331 #define XAE_FMI_IND_MASK 0x00000003 /* Index Mask */
332
333 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
334
335 /* Defines for different options for C_PHY_TYPE parameter in Axi Ethernet IP */
336 #define XAE_PHY_TYPE_MII 0
337 #define XAE_PHY_TYPE_GMII 1
338 #define XAE_PHY_TYPE_RGMII_1_3 2
339 #define XAE_PHY_TYPE_RGMII_2_0 3
340 #define XAE_PHY_TYPE_SGMII 4
341 #define XAE_PHY_TYPE_1000BASE_X 5
342
343 /* Total number of entries in the hardware multicast table. */
344 #define XAE_MULTICAST_CAM_TABLE_NUM 4
345
346 /* Axi Ethernet Synthesis features */
347 #define XAE_FEATURE_PARTIAL_RX_CSUM BIT(0)
348 #define XAE_FEATURE_PARTIAL_TX_CSUM BIT(1)
349 #define XAE_FEATURE_FULL_RX_CSUM BIT(2)
350 #define XAE_FEATURE_FULL_TX_CSUM BIT(3)
351 #define XAE_FEATURE_DMA_64BIT BIT(4)
352 #define XAE_FEATURE_STATS BIT(5)
353
354 #define XAE_NO_CSUM_OFFLOAD 0
355
356 #define XAE_FULL_CSUM_STATUS_MASK 0x00000038
357 #define XAE_IP_UDP_CSUM_VALIDATED 0x00000003
358 #define XAE_IP_TCP_CSUM_VALIDATED 0x00000002
359
360 #define DELAY_OF_ONE_MILLISEC 1000
361
362 /* Xilinx PCS/PMA PHY register for switching 1000BaseX or SGMII */
363 #define XLNX_MII_STD_SELECT_REG 0x11
364 #define XLNX_MII_STD_SELECT_SGMII BIT(0)
365
366 /* enum temac_stat - TEMAC statistics counters
367 *
368 * Index of statistics counters within the TEMAC. This must match the
369 * order/offset of hardware registers exactly.
370 */
371 enum temac_stat {
372 STAT_RX_BYTES = 0,
373 STAT_TX_BYTES,
374 STAT_UNDERSIZE_FRAMES,
375 STAT_FRAGMENT_FRAMES,
376 STAT_RX_64_BYTE_FRAMES,
377 STAT_RX_65_127_BYTE_FRAMES,
378 STAT_RX_128_255_BYTE_FRAMES,
379 STAT_RX_256_511_BYTE_FRAMES,
380 STAT_RX_512_1023_BYTE_FRAMES,
381 STAT_RX_1024_MAX_BYTE_FRAMES,
382 STAT_RX_OVERSIZE_FRAMES,
383 STAT_TX_64_BYTE_FRAMES,
384 STAT_TX_65_127_BYTE_FRAMES,
385 STAT_TX_128_255_BYTE_FRAMES,
386 STAT_TX_256_511_BYTE_FRAMES,
387 STAT_TX_512_1023_BYTE_FRAMES,
388 STAT_TX_1024_MAX_BYTE_FRAMES,
389 STAT_TX_OVERSIZE_FRAMES,
390 STAT_RX_GOOD_FRAMES,
391 STAT_RX_FCS_ERRORS,
392 STAT_RX_BROADCAST_FRAMES,
393 STAT_RX_MULTICAST_FRAMES,
394 STAT_RX_CONTROL_FRAMES,
395 STAT_RX_LENGTH_ERRORS,
396 STAT_RX_VLAN_FRAMES,
397 STAT_RX_PAUSE_FRAMES,
398 STAT_RX_CONTROL_OPCODE_ERRORS,
399 STAT_TX_GOOD_FRAMES,
400 STAT_TX_BROADCAST_FRAMES,
401 STAT_TX_MULTICAST_FRAMES,
402 STAT_TX_UNDERRUN_ERRORS,
403 STAT_TX_CONTROL_FRAMES,
404 STAT_TX_VLAN_FRAMES,
405 STAT_TX_PAUSE_FRAMES,
406 STAT_TX_SINGLE_COLLISION_FRAMES,
407 STAT_TX_MULTIPLE_COLLISION_FRAMES,
408 STAT_TX_DEFERRED_FRAMES,
409 STAT_TX_LATE_COLLISIONS,
410 STAT_TX_EXCESS_COLLISIONS,
411 STAT_TX_EXCESS_DEFERRAL,
412 STAT_RX_ALIGNMENT_ERRORS,
413 STAT_TX_PFC_FRAMES,
414 STAT_RX_PFC_FRAMES,
415 STAT_USER_DEFINED0,
416 STAT_USER_DEFINED1,
417 STAT_USER_DEFINED2,
418 STAT_COUNT,
419 };
420
421 /**
422 * struct axidma_bd - Axi Dma buffer descriptor layout
423 * @next: MM2S/S2MM Next Descriptor Pointer
424 * @next_msb: MM2S/S2MM Next Descriptor Pointer (high 32 bits)
425 * @phys: MM2S/S2MM Buffer Address
426 * @phys_msb: MM2S/S2MM Buffer Address (high 32 bits)
427 * @reserved3: Reserved and not used
428 * @reserved4: Reserved and not used
429 * @cntrl: MM2S/S2MM Control value
430 * @status: MM2S/S2MM Status value
431 * @app0: MM2S/S2MM User Application Field 0.
432 * @app1: MM2S/S2MM User Application Field 1.
433 * @app2: MM2S/S2MM User Application Field 2.
434 * @app3: MM2S/S2MM User Application Field 3.
435 * @app4: MM2S/S2MM User Application Field 4.
436 * @skb: Pointer to SKB transferred using DMA
437 */
438 struct axidma_bd {
439 u32 next; /* Physical address of next buffer descriptor */
440 u32 next_msb; /* high 32 bits for IP >= v7.1, reserved on older IP */
441 u32 phys;
442 u32 phys_msb; /* for IP >= v7.1, reserved for older IP */
443 u32 reserved3;
444 u32 reserved4;
445 u32 cntrl;
446 u32 status;
447 u32 app0;
448 u32 app1; /* TX start << 16 | insert */
449 u32 app2; /* TX csum seed */
450 u32 app3;
451 u32 app4; /* Last field used by HW */
452 struct sk_buff *skb;
453 } __aligned(XAXIDMA_BD_MINIMUM_ALIGNMENT);
454
455 #define XAE_NUM_MISC_CLOCKS 3
456
457 /**
458 * struct skbuf_dma_descriptor - skb for each dma descriptor
459 * @sgl: Pointer for sglist.
460 * @desc: Pointer to dma descriptor.
461 * @dma_address: dma address of sglist.
462 * @skb: Pointer to SKB transferred using DMA
463 * @sg_len: number of entries in the sglist.
464 */
465 struct skbuf_dma_descriptor {
466 struct scatterlist sgl[MAX_SKB_FRAGS + 1];
467 struct dma_async_tx_descriptor *desc;
468 dma_addr_t dma_address;
469 struct sk_buff *skb;
470 int sg_len;
471 };
472
473 /**
474 * struct axienet_local - axienet private per device data
475 * @ndev: Pointer for net_device to which it will be attached.
476 * @dev: Pointer to device structure
477 * @phylink: Pointer to phylink instance
478 * @phylink_config: phylink configuration settings
479 * @pcs_phy: Reference to PCS/PMA PHY if used
480 * @pcs: phylink pcs structure for PCS PHY
481 * @switch_x_sgmii: Whether switchable 1000BaseX/SGMII mode is enabled in the core
482 * @axi_clk: AXI4-Lite bus clock
483 * @misc_clks: Misc ethernet clocks (AXI4-Stream, Ref, MGT clocks)
484 * @mii_bus: Pointer to MII bus structure
485 * @mii_clk_div: MII bus clock divider value
486 * @regs_start: Resource start for axienet device addresses
487 * @regs: Base address for the axienet_local device address space
488 * @dma_regs: Base address for the axidma device address space
489 * @napi_rx: NAPI RX control structure
490 * @rx_dma_cr: Nominal content of RX DMA control register
491 * @rx_bd_v: Virtual address of the RX buffer descriptor ring
492 * @rx_bd_p: Physical address(start address) of the RX buffer descr. ring
493 * @rx_bd_num: Size of RX buffer descriptor ring
494 * @rx_bd_ci: Stores the index of the Rx buffer descriptor in the ring being
495 * accessed currently.
496 * @rx_packets: RX packet count for statistics
497 * @rx_bytes: RX byte count for statistics
498 * @rx_stat_sync: Synchronization object for RX stats
499 * @napi_tx: NAPI TX control structure
500 * @tx_dma_cr: Nominal content of TX DMA control register
501 * @tx_bd_v: Virtual address of the TX buffer descriptor ring
502 * @tx_bd_p: Physical address(start address) of the TX buffer descr. ring
503 * @tx_bd_num: Size of TX buffer descriptor ring
504 * @tx_bd_ci: Stores the next Tx buffer descriptor in the ring that may be
505 * complete. Only updated at runtime by TX NAPI poll.
506 * @tx_bd_tail: Stores the index of the next Tx buffer descriptor in the ring
507 * to be populated.
508 * @tx_packets: TX packet count for statistics
509 * @tx_bytes: TX byte count for statistics
510 * @tx_stat_sync: Synchronization object for TX stats
511 * @hw_stat_base: Base offset for statistics counters. This may be nonzero if
512 * the statistics counteres were reset or wrapped around.
513 * @hw_last_counter: Last-seen value of each statistic counter
514 * @reset_in_progress: Set while we are performing a reset and statistics
515 * counters may be invalid
516 * @hw_stats_seqcount: Sequence counter for @hw_stat_base, @hw_last_counter,
517 * and @reset_in_progress.
518 * @stats_lock: Lock for @hw_stats_seqcount
519 * @stats_work: Work for reading the hardware statistics counters often enough
520 * to catch overflows.
521 * @dma_err_task: Work structure to process Axi DMA errors
522 * @stopping: Set when @dma_err_task shouldn't do anything because we are
523 * about to stop the device.
524 * @tx_irq: Axidma TX IRQ number
525 * @rx_irq: Axidma RX IRQ number
526 * @eth_irq: Ethernet core IRQ number
527 * @phy_mode: Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
528 * @options: AxiEthernet option word
529 * @features: Stores the extended features supported by the axienet hw
530 * @max_frm_size: Stores the maximum size of the frame that can be that
531 * Txed/Rxed in the existing hardware. If jumbo option is
532 * supported, the maximum frame size would be 9k. Else it is
533 * 1522 bytes (assuming support for basic VLAN)
534 * @rxmem: Stores rx memory size for jumbo frame handling.
535 * @coalesce_count_rx: Store the irq coalesce on RX side.
536 * @coalesce_usec_rx: IRQ coalesce delay for RX
537 * @coalesce_count_tx: Store the irq coalesce on TX side.
538 * @coalesce_usec_tx: IRQ coalesce delay for TX
539 * @use_dmaengine: flag to check dmaengine framework usage.
540 * @tx_chan: TX DMA channel.
541 * @rx_chan: RX DMA channel.
542 * @tx_skb_ring: Pointer to TX skb ring buffer array.
543 * @rx_skb_ring: Pointer to RX skb ring buffer array.
544 * @tx_ring_head: TX skb ring buffer head index.
545 * @tx_ring_tail: TX skb ring buffer tail index.
546 * @rx_ring_head: RX skb ring buffer head index.
547 * @rx_ring_tail: RX skb ring buffer tail index.
548 */
549 struct axienet_local {
550 struct net_device *ndev;
551 struct device *dev;
552
553 struct phylink *phylink;
554 struct phylink_config phylink_config;
555
556 struct mdio_device *pcs_phy;
557 struct phylink_pcs pcs;
558
559 bool switch_x_sgmii;
560
561 struct clk *axi_clk;
562 struct clk_bulk_data misc_clks[XAE_NUM_MISC_CLOCKS];
563
564 struct mii_bus *mii_bus;
565 u8 mii_clk_div;
566
567 resource_size_t regs_start;
568 void __iomem *regs;
569 void __iomem *dma_regs;
570
571 struct napi_struct napi_rx;
572 u32 rx_dma_cr;
573 struct axidma_bd *rx_bd_v;
574 dma_addr_t rx_bd_p;
575 u32 rx_bd_num;
576 u32 rx_bd_ci;
577 u64_stats_t rx_packets;
578 u64_stats_t rx_bytes;
579 struct u64_stats_sync rx_stat_sync;
580
581 struct napi_struct napi_tx;
582 u32 tx_dma_cr;
583 struct axidma_bd *tx_bd_v;
584 dma_addr_t tx_bd_p;
585 u32 tx_bd_num;
586 u32 tx_bd_ci;
587 u32 tx_bd_tail;
588 u64_stats_t tx_packets;
589 u64_stats_t tx_bytes;
590 struct u64_stats_sync tx_stat_sync;
591
592 u64 hw_stat_base[STAT_COUNT];
593 u32 hw_last_counter[STAT_COUNT];
594 seqcount_mutex_t hw_stats_seqcount;
595 struct mutex stats_lock;
596 struct delayed_work stats_work;
597 bool reset_in_progress;
598
599 struct work_struct dma_err_task;
600 bool stopping;
601
602 int tx_irq;
603 int rx_irq;
604 int eth_irq;
605 phy_interface_t phy_mode;
606
607 u32 options;
608 u32 features;
609
610 u32 max_frm_size;
611 u32 rxmem;
612
613 u32 coalesce_count_rx;
614 u32 coalesce_usec_rx;
615 u32 coalesce_count_tx;
616 u32 coalesce_usec_tx;
617 u8 use_dmaengine;
618 struct dma_chan *tx_chan;
619 struct dma_chan *rx_chan;
620 struct skbuf_dma_descriptor **tx_skb_ring;
621 struct skbuf_dma_descriptor **rx_skb_ring;
622 int tx_ring_head;
623 int tx_ring_tail;
624 int rx_ring_head;
625 int rx_ring_tail;
626 };
627
628 /**
629 * struct axienet_option - Used to set axi ethernet hardware options
630 * @opt: Option to be set.
631 * @reg: Register offset to be written for setting the option
632 * @m_or: Mask to be ORed for setting the option in the register
633 */
634 struct axienet_option {
635 u32 opt;
636 u32 reg;
637 u32 m_or;
638 };
639
640 /**
641 * axienet_ior - Memory mapped Axi Ethernet register read
642 * @lp: Pointer to axienet local structure
643 * @offset: Address offset from the base address of Axi Ethernet core
644 *
645 * Return: The contents of the Axi Ethernet register
646 *
647 * This function returns the contents of the corresponding register.
648 */
axienet_ior(struct axienet_local * lp,off_t offset)649 static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
650 {
651 return ioread32(lp->regs + offset);
652 }
653
axinet_ior_read_mcr(struct axienet_local * lp)654 static inline u32 axinet_ior_read_mcr(struct axienet_local *lp)
655 {
656 return axienet_ior(lp, XAE_MDIO_MCR_OFFSET);
657 }
658
axienet_lock_mii(struct axienet_local * lp)659 static inline void axienet_lock_mii(struct axienet_local *lp)
660 {
661 if (lp->mii_bus)
662 mutex_lock(&lp->mii_bus->mdio_lock);
663 }
664
axienet_unlock_mii(struct axienet_local * lp)665 static inline void axienet_unlock_mii(struct axienet_local *lp)
666 {
667 if (lp->mii_bus)
668 mutex_unlock(&lp->mii_bus->mdio_lock);
669 }
670
671 /**
672 * axienet_iow - Memory mapped Axi Ethernet register write
673 * @lp: Pointer to axienet local structure
674 * @offset: Address offset from the base address of Axi Ethernet core
675 * @value: Value to be written into the Axi Ethernet register
676 *
677 * This function writes the desired value into the corresponding Axi Ethernet
678 * register.
679 */
axienet_iow(struct axienet_local * lp,off_t offset,u32 value)680 static inline void axienet_iow(struct axienet_local *lp, off_t offset,
681 u32 value)
682 {
683 iowrite32(value, lp->regs + offset);
684 }
685
686 /**
687 * axienet_dma_out32 - Memory mapped Axi DMA register write.
688 * @lp: Pointer to axienet local structure
689 * @reg: Address offset from the base address of the Axi DMA core
690 * @value: Value to be written into the Axi DMA register
691 *
692 * This function writes the desired value into the corresponding Axi DMA
693 * register.
694 */
695
axienet_dma_out32(struct axienet_local * lp,off_t reg,u32 value)696 static inline void axienet_dma_out32(struct axienet_local *lp,
697 off_t reg, u32 value)
698 {
699 iowrite32(value, lp->dma_regs + reg);
700 }
701
702 #if defined(CONFIG_64BIT) && defined(iowrite64)
703 /**
704 * axienet_dma_out64 - Memory mapped Axi DMA register write.
705 * @lp: Pointer to axienet local structure
706 * @reg: Address offset from the base address of the Axi DMA core
707 * @value: Value to be written into the Axi DMA register
708 *
709 * This function writes the desired value into the corresponding Axi DMA
710 * register.
711 */
axienet_dma_out64(struct axienet_local * lp,off_t reg,u64 value)712 static inline void axienet_dma_out64(struct axienet_local *lp,
713 off_t reg, u64 value)
714 {
715 iowrite64(value, lp->dma_regs + reg);
716 }
717
axienet_dma_out_addr(struct axienet_local * lp,off_t reg,dma_addr_t addr)718 static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
719 dma_addr_t addr)
720 {
721 if (lp->features & XAE_FEATURE_DMA_64BIT)
722 axienet_dma_out64(lp, reg, addr);
723 else
724 axienet_dma_out32(lp, reg, lower_32_bits(addr));
725 }
726
727 #else /* CONFIG_64BIT */
728
axienet_dma_out_addr(struct axienet_local * lp,off_t reg,dma_addr_t addr)729 static inline void axienet_dma_out_addr(struct axienet_local *lp, off_t reg,
730 dma_addr_t addr)
731 {
732 axienet_dma_out32(lp, reg, lower_32_bits(addr));
733 }
734
735 #endif /* CONFIG_64BIT */
736
737 /* Function prototypes visible in xilinx_axienet_mdio.c for other files */
738 int axienet_mdio_setup(struct axienet_local *lp);
739 void axienet_mdio_teardown(struct axienet_local *lp);
740
741 #endif /* XILINX_AXI_ENET_H */
742