1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for Renesas R-Car MIPI CSI-2 Receiver
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_graph.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/reset.h>
17 #include <linux/sys_soc.h>
18
19 #include <media/mipi-csi2.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-subdev.h>
25
26 struct rcar_csi2;
27
28 /* Register offsets and bits */
29
30 /* Control Timing Select */
31 #define TREF_REG 0x00
32 #define TREF_TREF BIT(0)
33
34 /* Software Reset */
35 #define SRST_REG 0x04
36 #define SRST_SRST BIT(0)
37
38 /* PHY Operation Control */
39 #define PHYCNT_REG 0x08
40 #define PHYCNT_SHUTDOWNZ BIT(17)
41 #define PHYCNT_RSTZ BIT(16)
42 #define PHYCNT_ENABLECLK BIT(4)
43 #define PHYCNT_ENABLE_3 BIT(3)
44 #define PHYCNT_ENABLE_2 BIT(2)
45 #define PHYCNT_ENABLE_1 BIT(1)
46 #define PHYCNT_ENABLE_0 BIT(0)
47
48 /* Checksum Control */
49 #define CHKSUM_REG 0x0c
50 #define CHKSUM_ECC_EN BIT(1)
51 #define CHKSUM_CRC_EN BIT(0)
52
53 /*
54 * Channel Data Type Select
55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
57 */
58 #define VCDT_REG 0x10
59 #define VCDT2_REG 0x14
60 #define VCDT_VCDTN_EN BIT(15)
61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
62 #define VCDT_SEL_DTN_ON BIT(6)
63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
64
65 /* Frame Data Type Select */
66 #define FRDT_REG 0x18
67
68 /* Field Detection Control */
69 #define FLD_REG 0x1c
70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
72 #define FLD_FLD_EN4 BIT(3)
73 #define FLD_FLD_EN3 BIT(2)
74 #define FLD_FLD_EN2 BIT(1)
75 #define FLD_FLD_EN BIT(0)
76
77 /* Automatic Standby Control */
78 #define ASTBY_REG 0x20
79
80 /* Long Data Type Setting 0 */
81 #define LNGDT0_REG 0x28
82
83 /* Long Data Type Setting 1 */
84 #define LNGDT1_REG 0x2c
85
86 /* Interrupt Enable */
87 #define INTEN_REG 0x30
88 #define INTEN_INT_AFIFO_OF BIT(27)
89 #define INTEN_INT_ERRSOTHS BIT(4)
90 #define INTEN_INT_ERRSOTSYNCHS BIT(3)
91
92 /* Interrupt Source Mask */
93 #define INTCLOSE_REG 0x34
94
95 /* Interrupt Status Monitor */
96 #define INTSTATE_REG 0x38
97 #define INTSTATE_INT_ULPS_START BIT(7)
98 #define INTSTATE_INT_ULPS_END BIT(6)
99
100 /* Interrupt Error Status Monitor */
101 #define INTERRSTATE_REG 0x3c
102
103 /* Short Packet Data */
104 #define SHPDAT_REG 0x40
105
106 /* Short Packet Count */
107 #define SHPCNT_REG 0x44
108
109 /* LINK Operation Control */
110 #define LINKCNT_REG 0x48
111 #define LINKCNT_MONITOR_EN BIT(31)
112 #define LINKCNT_REG_MONI_PACT_EN BIT(25)
113 #define LINKCNT_ICLK_NONSTOP BIT(24)
114
115 /* Lane Swap */
116 #define LSWAP_REG 0x4c
117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
121
122 /* PHY Test Interface Write Register */
123 #define PHTW_REG 0x50
124 #define PHTW_DWEN BIT(24)
125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
126 #define PHTW_CWEN BIT(8)
127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
128
129 #define PHYFRX_REG 0x64
130 #define PHYFRX_FORCERX_MODE_3 BIT(3)
131 #define PHYFRX_FORCERX_MODE_2 BIT(2)
132 #define PHYFRX_FORCERX_MODE_1 BIT(1)
133 #define PHYFRX_FORCERX_MODE_0 BIT(0)
134
135 /* V4H BASE registers */
136 #define V4H_N_LANES_REG 0x0004
137 #define V4H_CSI2_RESETN_REG 0x0008
138
139 #define V4H_PHY_MODE_REG 0x001c
140 #define V4H_PHY_MODE_DPHY 0
141 #define V4H_PHY_MODE_CPHY 1
142
143 #define V4H_PHY_SHUTDOWNZ_REG 0x0040
144 #define V4H_DPHY_RSTZ_REG 0x0044
145 #define V4H_FLDC_REG 0x0804
146 #define V4H_FLDD_REG 0x0808
147 #define V4H_IDIC_REG 0x0810
148
149 #define V4H_PHY_EN_REG 0x2000
150 #define V4H_PHY_EN_ENABLE_3 BIT(7)
151 #define V4H_PHY_EN_ENABLE_2 BIT(6)
152 #define V4H_PHY_EN_ENABLE_1 BIT(5)
153 #define V4H_PHY_EN_ENABLE_0 BIT(4)
154 #define V4H_PHY_EN_ENABLE_CLK BIT(0)
155
156 #define V4H_ST_PHYST_REG 0x2814
157 #define V4H_ST_PHYST_ST_PHY_READY BIT(31)
158 #define V4H_ST_PHYST_ST_STOPSTATE_3 BIT(3)
159 #define V4H_ST_PHYST_ST_STOPSTATE_2 BIT(2)
160 #define V4H_ST_PHYST_ST_STOPSTATE_1 BIT(1)
161 #define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0)
162
163 /* V4H PPI registers */
164 #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */
165 #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822
166 #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c
167 #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02
168 #define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04
169 #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06
170 #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a
171 #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c
172 #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10
173 #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c
174 #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80
175 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0
176
177 /* V4H CORE registers */
178 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */
179 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */
180 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */
181 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */
182 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */
183 #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */
184 #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */
185 #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */
186 #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
187
188 /* V4H C-PHY */
189 #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */
190 #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */
191 #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */
192 #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000
193 #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080
194 #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */
195 #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
196 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480
197 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */
198 #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800
199 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880
200 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */
201
202 struct rcsi2_cphy_setting {
203 u16 msps;
204 u16 rx2;
205 u16 trio0;
206 u16 trio1;
207 u16 trio2;
208 u16 lane27;
209 u16 lane29;
210 };
211
212 static const struct rcsi2_cphy_setting cphy_setting_table_r8a779g0[] = {
213 { .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .lane29 = 0x0a24 },
214 { .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .lane29 = 0x0a24 },
215 { .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .lane29 = 0x0a44 },
216 { .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .lane29 = 0x0a44 },
217 { .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .lane29 = 0x0a64 },
218 { .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .lane29 = 0x0a64 },
219 { .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .lane29 = 0x0a64 },
220 { .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .lane29 = 0x0a84 },
221 { .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .lane29 = 0x0a84 },
222 { .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .lane29 = 0x0a84 },
223 { .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .lane29 = 0x0a84 },
224 { .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .lane29 = 0x0a84 },
225 { .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0a84 },
226 { .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .lane29 = 0x0aa4 },
227 { .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
228 { .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .lane29 = 0x0aa4 },
229 { .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .lane29 = 0x0aa4 },
230 { .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
231 { .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
232 { .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .lane29 = 0x0aa4 },
233 { .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .lane29 = 0x0aa4 },
234 { .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
235 { .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
236 { .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
237 { .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .lane29 = 0x0aa4 },
238 { .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0aa4 },
239 { .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
240 { .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
241 { .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
242 { .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
243 { .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
244 { .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
245 { .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
246 { .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
247 { .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
248 { .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .lane29 = 0x0ad4 },
249 { /* sentinel */ },
250 };
251
252 /* V4M registers */
253 #define V4M_OVR1_REG 0x0848
254 #define V4M_OVR1_FORCERXMODE_3 BIT(12)
255 #define V4M_OVR1_FORCERXMODE_2 BIT(11)
256 #define V4M_OVR1_FORCERXMODE_1 BIT(10)
257 #define V4M_OVR1_FORCERXMODE_0 BIT(9)
258
259 #define V4M_FRXM_REG 0x2004
260 #define V4M_FRXM_FORCERXMODE_3 BIT(3)
261 #define V4M_FRXM_FORCERXMODE_2 BIT(2)
262 #define V4M_FRXM_FORCERXMODE_1 BIT(1)
263 #define V4M_FRXM_FORCERXMODE_0 BIT(0)
264
265 #define V4M_PHYPLL_REG 0x02050
266 #define V4M_CSI0CLKFCPR_REG 0x02054
267 #define V4M_PHTW_REG 0x02060
268 #define V4M_PHTR_REG 0x02064
269 #define V4M_PHTC_REG 0x02068
270
271 struct phtw_value {
272 u8 data;
273 u8 code;
274 };
275
276 struct rcsi2_mbps_info {
277 u16 mbps;
278 u8 reg;
279 u16 osc_freq; /* V4M */
280 };
281
282 static const struct rcsi2_mbps_info phtw_mbps_v3u[] = {
283 { .mbps = 1500, .reg = 0xcc },
284 { .mbps = 1550, .reg = 0x1d },
285 { .mbps = 1600, .reg = 0x27 },
286 { .mbps = 1650, .reg = 0x30 },
287 { .mbps = 1700, .reg = 0x39 },
288 { .mbps = 1750, .reg = 0x42 },
289 { .mbps = 1800, .reg = 0x4b },
290 { .mbps = 1850, .reg = 0x55 },
291 { .mbps = 1900, .reg = 0x5e },
292 { .mbps = 1950, .reg = 0x67 },
293 { .mbps = 2000, .reg = 0x71 },
294 { .mbps = 2050, .reg = 0x79 },
295 { .mbps = 2100, .reg = 0x83 },
296 { .mbps = 2150, .reg = 0x8c },
297 { .mbps = 2200, .reg = 0x95 },
298 { .mbps = 2250, .reg = 0x9e },
299 { .mbps = 2300, .reg = 0xa7 },
300 { .mbps = 2350, .reg = 0xb0 },
301 { .mbps = 2400, .reg = 0xba },
302 { .mbps = 2450, .reg = 0xc3 },
303 { .mbps = 2500, .reg = 0xcc },
304 { /* sentinel */ },
305 };
306
307 static const struct rcsi2_mbps_info phtw_mbps_h3_v3h_m3n[] = {
308 { .mbps = 80, .reg = 0x86 },
309 { .mbps = 90, .reg = 0x86 },
310 { .mbps = 100, .reg = 0x87 },
311 { .mbps = 110, .reg = 0x87 },
312 { .mbps = 120, .reg = 0x88 },
313 { .mbps = 130, .reg = 0x88 },
314 { .mbps = 140, .reg = 0x89 },
315 { .mbps = 150, .reg = 0x89 },
316 { .mbps = 160, .reg = 0x8a },
317 { .mbps = 170, .reg = 0x8a },
318 { .mbps = 180, .reg = 0x8b },
319 { .mbps = 190, .reg = 0x8b },
320 { .mbps = 205, .reg = 0x8c },
321 { .mbps = 220, .reg = 0x8d },
322 { .mbps = 235, .reg = 0x8e },
323 { .mbps = 250, .reg = 0x8e },
324 { /* sentinel */ },
325 };
326
327 static const struct rcsi2_mbps_info phtw_mbps_v3m_e3[] = {
328 { .mbps = 80, .reg = 0x00 },
329 { .mbps = 90, .reg = 0x20 },
330 { .mbps = 100, .reg = 0x40 },
331 { .mbps = 110, .reg = 0x02 },
332 { .mbps = 130, .reg = 0x22 },
333 { .mbps = 140, .reg = 0x42 },
334 { .mbps = 150, .reg = 0x04 },
335 { .mbps = 170, .reg = 0x24 },
336 { .mbps = 180, .reg = 0x44 },
337 { .mbps = 200, .reg = 0x06 },
338 { .mbps = 220, .reg = 0x26 },
339 { .mbps = 240, .reg = 0x46 },
340 { .mbps = 250, .reg = 0x08 },
341 { .mbps = 270, .reg = 0x28 },
342 { .mbps = 300, .reg = 0x0a },
343 { .mbps = 330, .reg = 0x2a },
344 { .mbps = 360, .reg = 0x4a },
345 { .mbps = 400, .reg = 0x0c },
346 { .mbps = 450, .reg = 0x2c },
347 { .mbps = 500, .reg = 0x0e },
348 { .mbps = 550, .reg = 0x2e },
349 { .mbps = 600, .reg = 0x10 },
350 { .mbps = 650, .reg = 0x30 },
351 { .mbps = 700, .reg = 0x12 },
352 { .mbps = 750, .reg = 0x32 },
353 { .mbps = 800, .reg = 0x52 },
354 { .mbps = 850, .reg = 0x72 },
355 { .mbps = 900, .reg = 0x14 },
356 { .mbps = 950, .reg = 0x34 },
357 { .mbps = 1000, .reg = 0x54 },
358 { .mbps = 1050, .reg = 0x74 },
359 { .mbps = 1125, .reg = 0x16 },
360 { /* sentinel */ },
361 };
362
363 /* PHY Test Interface Clear */
364 #define PHTC_REG 0x58
365 #define PHTC_TESTCLR BIT(0)
366
367 /* PHY Frequency Control */
368 #define PHYPLL_REG 0x68
369 #define PHYPLL_HSFREQRANGE(n) ((n) << 16)
370
371 static const struct rcsi2_mbps_info hsfreqrange_v3u[] = {
372 { .mbps = 80, .reg = 0x00 },
373 { .mbps = 90, .reg = 0x10 },
374 { .mbps = 100, .reg = 0x20 },
375 { .mbps = 110, .reg = 0x30 },
376 { .mbps = 120, .reg = 0x01 },
377 { .mbps = 130, .reg = 0x11 },
378 { .mbps = 140, .reg = 0x21 },
379 { .mbps = 150, .reg = 0x31 },
380 { .mbps = 160, .reg = 0x02 },
381 { .mbps = 170, .reg = 0x12 },
382 { .mbps = 180, .reg = 0x22 },
383 { .mbps = 190, .reg = 0x32 },
384 { .mbps = 205, .reg = 0x03 },
385 { .mbps = 220, .reg = 0x13 },
386 { .mbps = 235, .reg = 0x23 },
387 { .mbps = 250, .reg = 0x33 },
388 { .mbps = 275, .reg = 0x04 },
389 { .mbps = 300, .reg = 0x14 },
390 { .mbps = 325, .reg = 0x25 },
391 { .mbps = 350, .reg = 0x35 },
392 { .mbps = 400, .reg = 0x05 },
393 { .mbps = 450, .reg = 0x16 },
394 { .mbps = 500, .reg = 0x26 },
395 { .mbps = 550, .reg = 0x37 },
396 { .mbps = 600, .reg = 0x07 },
397 { .mbps = 650, .reg = 0x18 },
398 { .mbps = 700, .reg = 0x28 },
399 { .mbps = 750, .reg = 0x39 },
400 { .mbps = 800, .reg = 0x09 },
401 { .mbps = 850, .reg = 0x19 },
402 { .mbps = 900, .reg = 0x29 },
403 { .mbps = 950, .reg = 0x3a },
404 { .mbps = 1000, .reg = 0x0a },
405 { .mbps = 1050, .reg = 0x1a },
406 { .mbps = 1100, .reg = 0x2a },
407 { .mbps = 1150, .reg = 0x3b },
408 { .mbps = 1200, .reg = 0x0b },
409 { .mbps = 1250, .reg = 0x1b },
410 { .mbps = 1300, .reg = 0x2b },
411 { .mbps = 1350, .reg = 0x3c },
412 { .mbps = 1400, .reg = 0x0c },
413 { .mbps = 1450, .reg = 0x1c },
414 { .mbps = 1500, .reg = 0x2c },
415 { .mbps = 1550, .reg = 0x3d },
416 { .mbps = 1600, .reg = 0x0d },
417 { .mbps = 1650, .reg = 0x1d },
418 { .mbps = 1700, .reg = 0x2e },
419 { .mbps = 1750, .reg = 0x3e },
420 { .mbps = 1800, .reg = 0x0e },
421 { .mbps = 1850, .reg = 0x1e },
422 { .mbps = 1900, .reg = 0x2f },
423 { .mbps = 1950, .reg = 0x3f },
424 { .mbps = 2000, .reg = 0x0f },
425 { .mbps = 2050, .reg = 0x40 },
426 { .mbps = 2100, .reg = 0x41 },
427 { .mbps = 2150, .reg = 0x42 },
428 { .mbps = 2200, .reg = 0x43 },
429 { .mbps = 2300, .reg = 0x45 },
430 { .mbps = 2350, .reg = 0x46 },
431 { .mbps = 2400, .reg = 0x47 },
432 { .mbps = 2450, .reg = 0x48 },
433 { .mbps = 2500, .reg = 0x49 },
434 { /* sentinel */ },
435 };
436
437 static const struct rcsi2_mbps_info hsfreqrange_h3_v3h_m3n[] = {
438 { .mbps = 80, .reg = 0x00 },
439 { .mbps = 90, .reg = 0x10 },
440 { .mbps = 100, .reg = 0x20 },
441 { .mbps = 110, .reg = 0x30 },
442 { .mbps = 120, .reg = 0x01 },
443 { .mbps = 130, .reg = 0x11 },
444 { .mbps = 140, .reg = 0x21 },
445 { .mbps = 150, .reg = 0x31 },
446 { .mbps = 160, .reg = 0x02 },
447 { .mbps = 170, .reg = 0x12 },
448 { .mbps = 180, .reg = 0x22 },
449 { .mbps = 190, .reg = 0x32 },
450 { .mbps = 205, .reg = 0x03 },
451 { .mbps = 220, .reg = 0x13 },
452 { .mbps = 235, .reg = 0x23 },
453 { .mbps = 250, .reg = 0x33 },
454 { .mbps = 275, .reg = 0x04 },
455 { .mbps = 300, .reg = 0x14 },
456 { .mbps = 325, .reg = 0x25 },
457 { .mbps = 350, .reg = 0x35 },
458 { .mbps = 400, .reg = 0x05 },
459 { .mbps = 450, .reg = 0x16 },
460 { .mbps = 500, .reg = 0x26 },
461 { .mbps = 550, .reg = 0x37 },
462 { .mbps = 600, .reg = 0x07 },
463 { .mbps = 650, .reg = 0x18 },
464 { .mbps = 700, .reg = 0x28 },
465 { .mbps = 750, .reg = 0x39 },
466 { .mbps = 800, .reg = 0x09 },
467 { .mbps = 850, .reg = 0x19 },
468 { .mbps = 900, .reg = 0x29 },
469 { .mbps = 950, .reg = 0x3a },
470 { .mbps = 1000, .reg = 0x0a },
471 { .mbps = 1050, .reg = 0x1a },
472 { .mbps = 1100, .reg = 0x2a },
473 { .mbps = 1150, .reg = 0x3b },
474 { .mbps = 1200, .reg = 0x0b },
475 { .mbps = 1250, .reg = 0x1b },
476 { .mbps = 1300, .reg = 0x2b },
477 { .mbps = 1350, .reg = 0x3c },
478 { .mbps = 1400, .reg = 0x0c },
479 { .mbps = 1450, .reg = 0x1c },
480 { .mbps = 1500, .reg = 0x2c },
481 { /* sentinel */ },
482 };
483
484 static const struct rcsi2_mbps_info hsfreqrange_m3w[] = {
485 { .mbps = 80, .reg = 0x00 },
486 { .mbps = 90, .reg = 0x10 },
487 { .mbps = 100, .reg = 0x20 },
488 { .mbps = 110, .reg = 0x30 },
489 { .mbps = 120, .reg = 0x01 },
490 { .mbps = 130, .reg = 0x11 },
491 { .mbps = 140, .reg = 0x21 },
492 { .mbps = 150, .reg = 0x31 },
493 { .mbps = 160, .reg = 0x02 },
494 { .mbps = 170, .reg = 0x12 },
495 { .mbps = 180, .reg = 0x22 },
496 { .mbps = 190, .reg = 0x32 },
497 { .mbps = 205, .reg = 0x03 },
498 { .mbps = 220, .reg = 0x13 },
499 { .mbps = 235, .reg = 0x23 },
500 { .mbps = 250, .reg = 0x33 },
501 { .mbps = 275, .reg = 0x04 },
502 { .mbps = 300, .reg = 0x14 },
503 { .mbps = 325, .reg = 0x05 },
504 { .mbps = 350, .reg = 0x15 },
505 { .mbps = 400, .reg = 0x25 },
506 { .mbps = 450, .reg = 0x06 },
507 { .mbps = 500, .reg = 0x16 },
508 { .mbps = 550, .reg = 0x07 },
509 { .mbps = 600, .reg = 0x17 },
510 { .mbps = 650, .reg = 0x08 },
511 { .mbps = 700, .reg = 0x18 },
512 { .mbps = 750, .reg = 0x09 },
513 { .mbps = 800, .reg = 0x19 },
514 { .mbps = 850, .reg = 0x29 },
515 { .mbps = 900, .reg = 0x39 },
516 { .mbps = 950, .reg = 0x0a },
517 { .mbps = 1000, .reg = 0x1a },
518 { .mbps = 1050, .reg = 0x2a },
519 { .mbps = 1100, .reg = 0x3a },
520 { .mbps = 1150, .reg = 0x0b },
521 { .mbps = 1200, .reg = 0x1b },
522 { .mbps = 1250, .reg = 0x2b },
523 { .mbps = 1300, .reg = 0x3b },
524 { .mbps = 1350, .reg = 0x0c },
525 { .mbps = 1400, .reg = 0x1c },
526 { .mbps = 1450, .reg = 0x2c },
527 { .mbps = 1500, .reg = 0x3c },
528 { /* sentinel */ },
529 };
530
531 static const struct rcsi2_mbps_info hsfreqrange_v4m[] = {
532 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 },
533 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 },
534 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 },
535 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 },
536 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 },
537 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 },
538 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 },
539 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 },
540 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 },
541 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 },
542 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 },
543 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 },
544 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 },
545 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 },
546 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 },
547 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 },
548 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 },
549 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 },
550 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 },
551 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 },
552 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 },
553 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 },
554 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 },
555 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 },
556 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 },
557 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 },
558 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 },
559 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 },
560 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 },
561 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 },
562 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 },
563 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 },
564 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 },
565 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 },
566 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 },
567 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 },
568 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 },
569 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 },
570 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 },
571 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 },
572 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 },
573 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 },
574 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 },
575 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 },
576 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 },
577 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 },
578 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 },
579 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a },
580 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 },
581 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b },
582 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 },
583 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c },
584 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 },
585 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d },
586 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 },
587 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e },
588 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 },
589 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f },
590 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 },
591 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 },
592 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 },
593 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 },
594 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 },
595 { /* sentinel */ },
596 };
597
598 /* PHY ESC Error Monitor */
599 #define PHEERM_REG 0x74
600
601 /* PHY Clock Lane Monitor */
602 #define PHCLM_REG 0x78
603 #define PHCLM_STOPSTATECKL BIT(0)
604
605 /* PHY Data Lane Monitor */
606 #define PHDLM_REG 0x7c
607
608 /* CSI0CLK Frequency Configuration Preset Register */
609 #define CSI0CLKFCPR_REG 0x260
610 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
611
612 struct rcar_csi2_format {
613 u32 code;
614 unsigned int datatype;
615 unsigned int bpp;
616 };
617
618 static const struct rcar_csi2_format rcar_csi2_formats[] = {
619 {
620 .code = MEDIA_BUS_FMT_RGB888_1X24,
621 .datatype = MIPI_CSI2_DT_RGB888,
622 .bpp = 24,
623 }, {
624 .code = MEDIA_BUS_FMT_UYVY8_1X16,
625 .datatype = MIPI_CSI2_DT_YUV422_8B,
626 .bpp = 16,
627 }, {
628 .code = MEDIA_BUS_FMT_YUYV8_1X16,
629 .datatype = MIPI_CSI2_DT_YUV422_8B,
630 .bpp = 16,
631 }, {
632 .code = MEDIA_BUS_FMT_UYVY8_2X8,
633 .datatype = MIPI_CSI2_DT_YUV422_8B,
634 .bpp = 16,
635 }, {
636 .code = MEDIA_BUS_FMT_YUYV10_2X10,
637 .datatype = MIPI_CSI2_DT_YUV422_8B,
638 .bpp = 20,
639 }, {
640 .code = MEDIA_BUS_FMT_Y10_1X10,
641 .datatype = MIPI_CSI2_DT_RAW10,
642 .bpp = 10,
643 }, {
644 .code = MEDIA_BUS_FMT_SBGGR8_1X8,
645 .datatype = MIPI_CSI2_DT_RAW8,
646 .bpp = 8,
647 }, {
648 .code = MEDIA_BUS_FMT_SGBRG8_1X8,
649 .datatype = MIPI_CSI2_DT_RAW8,
650 .bpp = 8,
651 }, {
652 .code = MEDIA_BUS_FMT_SGRBG8_1X8,
653 .datatype = MIPI_CSI2_DT_RAW8,
654 .bpp = 8,
655 }, {
656 .code = MEDIA_BUS_FMT_SRGGB8_1X8,
657 .datatype = MIPI_CSI2_DT_RAW8,
658 .bpp = 8,
659 }, {
660 .code = MEDIA_BUS_FMT_Y8_1X8,
661 .datatype = MIPI_CSI2_DT_RAW8,
662 .bpp = 8,
663 },
664 };
665
rcsi2_code_to_fmt(unsigned int code)666 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
667 {
668 unsigned int i;
669
670 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++)
671 if (rcar_csi2_formats[i].code == code)
672 return &rcar_csi2_formats[i];
673
674 return NULL;
675 }
676
677 struct rcsi2_cphy_line_order {
678 enum v4l2_mbus_csi2_cphy_line_orders_type order;
679 u16 cfg;
680 u16 ctrl29;
681 };
682
683 static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = {
684 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 },
685 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 },
686 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 },
687 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 },
688 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 },
689 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 }
690 };
691
692 enum rcar_csi2_pads {
693 RCAR_CSI2_SINK,
694 RCAR_CSI2_SOURCE_VC0,
695 RCAR_CSI2_SOURCE_VC1,
696 RCAR_CSI2_SOURCE_VC2,
697 RCAR_CSI2_SOURCE_VC3,
698 NR_OF_RCAR_CSI2_PAD,
699 };
700
701 struct rcsi2_register_layout {
702 unsigned int phtw;
703 unsigned int phypll;
704 };
705
706 struct rcar_csi2_info {
707 const struct rcsi2_register_layout *regs;
708 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps);
709 int (*phy_post_init)(struct rcar_csi2 *priv);
710 int (*start_receiver)(struct rcar_csi2 *priv,
711 struct v4l2_subdev_state *state);
712 void (*enter_standby)(struct rcar_csi2 *priv);
713 const struct rcsi2_mbps_info *hsfreqrange;
714 unsigned int csi0clkfreqrange;
715 unsigned int num_channels;
716 bool clear_ulps;
717 bool use_isp;
718 bool support_dphy;
719 bool support_cphy;
720 };
721
722 struct rcar_csi2 {
723 struct device *dev;
724 void __iomem *base;
725 const struct rcar_csi2_info *info;
726 struct reset_control *rstc;
727
728 struct v4l2_subdev subdev;
729 struct media_pad pads[NR_OF_RCAR_CSI2_PAD];
730
731 struct v4l2_async_notifier notifier;
732 struct v4l2_subdev *remote;
733 unsigned int remote_pad;
734
735 int channel_vc[4];
736
737 int stream_count;
738
739 bool cphy;
740 unsigned short lanes;
741 unsigned char lane_swap[4];
742 enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3];
743 };
744
sd_to_csi2(struct v4l2_subdev * sd)745 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
746 {
747 return container_of(sd, struct rcar_csi2, subdev);
748 }
749
notifier_to_csi2(struct v4l2_async_notifier * n)750 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
751 {
752 return container_of(n, struct rcar_csi2, notifier);
753 }
754
rcsi2_num_pads(const struct rcar_csi2 * priv)755 static unsigned int rcsi2_num_pads(const struct rcar_csi2 *priv)
756 {
757 /* Used together with R-Car ISP: one sink and one source pad. */
758 if (priv->info->use_isp)
759 return 2;
760
761 /* Used together with R-Car VIN: one sink and four source pads. */
762 return 5;
763 }
764
rcsi2_read(struct rcar_csi2 * priv,unsigned int reg)765 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg)
766 {
767 return ioread32(priv->base + reg);
768 }
769
rcsi2_write(struct rcar_csi2 * priv,unsigned int reg,u32 data)770 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
771 {
772 iowrite32(data, priv->base + reg);
773 }
774
rcsi2_read16(struct rcar_csi2 * priv,unsigned int reg)775 static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg)
776 {
777 return ioread16(priv->base + reg);
778 }
779
rcsi2_write16(struct rcar_csi2 * priv,unsigned int reg,u16 data)780 static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data)
781 {
782 iowrite16(data, priv->base + reg);
783 }
784
rcsi2_modify16(struct rcar_csi2 * priv,unsigned int reg,u16 data,u16 mask)785 static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask)
786 {
787 u16 val;
788
789 val = rcsi2_read16(priv, reg) & ~mask;
790 rcsi2_write16(priv, reg, val | data);
791 }
792
rcsi2_phtw_write(struct rcar_csi2 * priv,u8 data,u8 code)793 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code)
794 {
795 unsigned int timeout;
796
797 rcsi2_write(priv, priv->info->regs->phtw,
798 PHTW_DWEN | PHTW_TESTDIN_DATA(data) |
799 PHTW_CWEN | PHTW_TESTDIN_CODE(code));
800
801 /* Wait for DWEN and CWEN to be cleared by hardware. */
802 for (timeout = 0; timeout <= 20; timeout++) {
803 if (!(rcsi2_read(priv, priv->info->regs->phtw) & (PHTW_DWEN | PHTW_CWEN)))
804 return 0;
805
806 usleep_range(1000, 2000);
807 }
808
809 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n");
810
811 return -ETIMEDOUT;
812 }
813
rcsi2_phtw_write_array(struct rcar_csi2 * priv,const struct phtw_value * values,unsigned int size)814 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv,
815 const struct phtw_value *values,
816 unsigned int size)
817 {
818 int ret;
819
820 for (unsigned int i = 0; i < size; i++) {
821 ret = rcsi2_phtw_write(priv, values[i].data, values[i].code);
822 if (ret)
823 return ret;
824 }
825
826 return 0;
827 }
828
829 static const struct rcsi2_mbps_info *
rcsi2_mbps_to_info(struct rcar_csi2 * priv,const struct rcsi2_mbps_info * infotable,unsigned int mbps)830 rcsi2_mbps_to_info(struct rcar_csi2 *priv,
831 const struct rcsi2_mbps_info *infotable, unsigned int mbps)
832 {
833 const struct rcsi2_mbps_info *info;
834 const struct rcsi2_mbps_info *prev = NULL;
835
836 if (mbps < infotable->mbps)
837 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps",
838 mbps, infotable->mbps);
839
840 for (info = infotable; info->mbps != 0; info++) {
841 if (info->mbps >= mbps)
842 break;
843 prev = info;
844 }
845
846 if (!info->mbps) {
847 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps);
848 return NULL;
849 }
850
851 if (prev && ((mbps - prev->mbps) <= (info->mbps - mbps)))
852 info = prev;
853
854 return info;
855 }
856
rcsi2_enter_standby_gen3(struct rcar_csi2 * priv)857 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv)
858 {
859 rcsi2_write(priv, PHYCNT_REG, 0);
860 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR);
861 }
862
rcsi2_enter_standby(struct rcar_csi2 * priv)863 static void rcsi2_enter_standby(struct rcar_csi2 *priv)
864 {
865 if (priv->info->enter_standby)
866 priv->info->enter_standby(priv);
867
868 reset_control_assert(priv->rstc);
869 usleep_range(100, 150);
870 pm_runtime_put(priv->dev);
871 }
872
rcsi2_exit_standby(struct rcar_csi2 * priv)873 static int rcsi2_exit_standby(struct rcar_csi2 *priv)
874 {
875 int ret;
876
877 ret = pm_runtime_resume_and_get(priv->dev);
878 if (ret < 0)
879 return ret;
880
881 reset_control_deassert(priv->rstc);
882
883 return 0;
884 }
885
rcsi2_wait_phy_start(struct rcar_csi2 * priv,unsigned int lanes)886 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv,
887 unsigned int lanes)
888 {
889 unsigned int timeout;
890
891 /* Wait for the clock and data lanes to enter LP-11 state. */
892 for (timeout = 0; timeout <= 20; timeout++) {
893 const u32 lane_mask = (1 << lanes) - 1;
894
895 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) &&
896 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask)
897 return 0;
898
899 usleep_range(1000, 2000);
900 }
901
902 dev_err(priv->dev, "Timeout waiting for LP-11 state\n");
903
904 return -ETIMEDOUT;
905 }
906
rcsi2_set_phypll(struct rcar_csi2 * priv,unsigned int mbps)907 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps)
908 {
909 const struct rcsi2_mbps_info *info;
910
911 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps);
912 if (!info)
913 return -ERANGE;
914
915 rcsi2_write(priv, priv->info->regs->phypll, PHYPLL_HSFREQRANGE(info->reg));
916
917 return 0;
918 }
919
rcsi2_calc_mbps(struct rcar_csi2 * priv,unsigned int bpp,unsigned int lanes)920 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp,
921 unsigned int lanes)
922 {
923 struct v4l2_subdev *source;
924 struct v4l2_ctrl *ctrl;
925 u64 mbps;
926
927 if (!priv->remote)
928 return -ENODEV;
929
930 source = priv->remote;
931
932 /* Read the pixel rate control from remote. */
933 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
934 if (!ctrl) {
935 dev_err(priv->dev, "no pixel rate control in subdev %s\n",
936 source->name);
937 return -EINVAL;
938 }
939
940 /*
941 * Calculate the phypll in mbps.
942 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes)
943 * bps = link_freq * 2
944 */
945 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp;
946 do_div(mbps, lanes * 1000000);
947
948 /* Adjust for C-PHY, divide by 2.8. */
949 if (priv->cphy)
950 mbps = div_u64(mbps * 5, 14);
951
952 return mbps;
953 }
954
rcsi2_get_active_lanes(struct rcar_csi2 * priv,unsigned int * lanes)955 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv,
956 unsigned int *lanes)
957 {
958 struct v4l2_mbus_config mbus_config = { 0 };
959 int ret;
960
961 *lanes = priv->lanes;
962
963 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config,
964 priv->remote_pad, &mbus_config);
965 if (ret == -ENOIOCTLCMD) {
966 dev_dbg(priv->dev, "No remote mbus configuration available\n");
967 return 0;
968 }
969
970 if (ret) {
971 dev_err(priv->dev, "Failed to get remote mbus configuration\n");
972 return ret;
973 }
974
975 switch (mbus_config.type) {
976 case V4L2_MBUS_CSI2_CPHY:
977 if (!priv->cphy)
978 return -EINVAL;
979 break;
980 case V4L2_MBUS_CSI2_DPHY:
981 if (priv->cphy)
982 return -EINVAL;
983 break;
984 default:
985 dev_err(priv->dev, "Unsupported media bus type %u\n",
986 mbus_config.type);
987 return -EINVAL;
988 }
989
990 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) {
991 dev_err(priv->dev,
992 "Unsupported mbus config: too many data lanes %u\n",
993 mbus_config.bus.mipi_csi2.num_data_lanes);
994 return -EINVAL;
995 }
996
997 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes;
998
999 return 0;
1000 }
1001
rcsi2_start_receiver_gen3(struct rcar_csi2 * priv,struct v4l2_subdev_state * state)1002 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv,
1003 struct v4l2_subdev_state *state)
1004 {
1005 const struct rcar_csi2_format *format;
1006 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0;
1007 const struct v4l2_mbus_framefmt *fmt;
1008 unsigned int lanes;
1009 unsigned int i;
1010 int mbps, ret;
1011
1012 /* Use the format on the sink pad to compute the receiver config. */
1013 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK);
1014
1015 dev_dbg(priv->dev, "Input size (%ux%u%c)\n",
1016 fmt->width, fmt->height,
1017 fmt->field == V4L2_FIELD_NONE ? 'p' : 'i');
1018
1019 /* Code is validated in set_fmt. */
1020 format = rcsi2_code_to_fmt(fmt->code);
1021 if (!format)
1022 return -EINVAL;
1023
1024 /*
1025 * Enable all supported CSI-2 channels with virtual channel and
1026 * data type matching.
1027 *
1028 * NOTE: It's not possible to get individual datatype for each
1029 * source virtual channel. Once this is possible in V4L2
1030 * it should be used here.
1031 */
1032 for (i = 0; i < priv->info->num_channels; i++) {
1033 u32 vcdt_part;
1034
1035 if (priv->channel_vc[i] < 0)
1036 continue;
1037
1038 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN |
1039 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype);
1040
1041 /* Store in correct reg and offset. */
1042 if (i < 2)
1043 vcdt |= vcdt_part << ((i % 2) * 16);
1044 else
1045 vcdt2 |= vcdt_part << ((i % 2) * 16);
1046 }
1047
1048 if (fmt->field == V4L2_FIELD_ALTERNATE) {
1049 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2
1050 | FLD_FLD_EN;
1051
1052 if (fmt->height == 240)
1053 fld |= FLD_FLD_NUM(0);
1054 else
1055 fld |= FLD_FLD_NUM(1);
1056 }
1057
1058 /*
1059 * Get the number of active data lanes inspecting the remote mbus
1060 * configuration.
1061 */
1062 ret = rcsi2_get_active_lanes(priv, &lanes);
1063 if (ret)
1064 return ret;
1065
1066 phycnt = PHYCNT_ENABLECLK;
1067 phycnt |= (1 << lanes) - 1;
1068
1069 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
1070 if (mbps < 0)
1071 return mbps;
1072
1073 /* Enable interrupts. */
1074 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS
1075 | INTEN_INT_ERRSOTSYNCHS);
1076
1077 /* Init */
1078 rcsi2_write(priv, TREF_REG, TREF_TREF);
1079 rcsi2_write(priv, PHTC_REG, 0);
1080
1081 /* Configure */
1082 if (!priv->info->use_isp) {
1083 rcsi2_write(priv, VCDT_REG, vcdt);
1084 if (vcdt2)
1085 rcsi2_write(priv, VCDT2_REG, vcdt2);
1086 }
1087
1088 /* Lanes are zero indexed. */
1089 rcsi2_write(priv, LSWAP_REG,
1090 LSWAP_L0SEL(priv->lane_swap[0] - 1) |
1091 LSWAP_L1SEL(priv->lane_swap[1] - 1) |
1092 LSWAP_L2SEL(priv->lane_swap[2] - 1) |
1093 LSWAP_L3SEL(priv->lane_swap[3] - 1));
1094
1095 /* Start */
1096 if (priv->info->init_phtw) {
1097 ret = priv->info->init_phtw(priv, mbps);
1098 if (ret)
1099 return ret;
1100 }
1101
1102 if (priv->info->hsfreqrange) {
1103 ret = rcsi2_set_phypll(priv, mbps);
1104 if (ret)
1105 return ret;
1106 }
1107
1108 if (priv->info->csi0clkfreqrange)
1109 rcsi2_write(priv, CSI0CLKFCPR_REG,
1110 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
1111
1112 if (priv->info->use_isp)
1113 rcsi2_write(priv, PHYFRX_REG,
1114 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 |
1115 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0);
1116
1117 rcsi2_write(priv, PHYCNT_REG, phycnt);
1118 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN |
1119 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP);
1120 rcsi2_write(priv, FLD_REG, fld);
1121 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ);
1122 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ);
1123
1124 ret = rcsi2_wait_phy_start(priv, lanes);
1125 if (ret)
1126 return ret;
1127
1128 if (priv->info->use_isp)
1129 rcsi2_write(priv, PHYFRX_REG, 0);
1130
1131 /* Run post PHY start initialization, if needed. */
1132 if (priv->info->phy_post_init) {
1133 ret = priv->info->phy_post_init(priv);
1134 if (ret)
1135 return ret;
1136 }
1137
1138 /* Clear Ultra Low Power interrupt. */
1139 if (priv->info->clear_ulps)
1140 rcsi2_write(priv, INTSTATE_REG,
1141 INTSTATE_INT_ULPS_START |
1142 INTSTATE_INT_ULPS_END);
1143 return 0;
1144 }
1145
rsci2_set_line_order(struct rcar_csi2 * priv,enum v4l2_mbus_csi2_cphy_line_orders_type order,unsigned int cfgreg,unsigned int ctrlreg)1146 static void rsci2_set_line_order(struct rcar_csi2 *priv,
1147 enum v4l2_mbus_csi2_cphy_line_orders_type order,
1148 unsigned int cfgreg, unsigned int ctrlreg)
1149 {
1150 const struct rcsi2_cphy_line_order *info = NULL;
1151
1152 for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) {
1153 if (rcsi2_cphy_line_orders[i].order == order) {
1154 info = &rcsi2_cphy_line_orders[i];
1155 break;
1156 }
1157 }
1158
1159 if (!info)
1160 return;
1161
1162 rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f);
1163 rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100);
1164 }
1165
rcsi2_wait_phy_start_v4h(struct rcar_csi2 * priv,u32 match)1166 static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match)
1167 {
1168 unsigned int timeout;
1169 u32 status;
1170
1171 for (timeout = 0; timeout <= 10; timeout++) {
1172 status = rcsi2_read(priv, V4H_ST_PHYST_REG);
1173 if ((status & match) == match)
1174 return 0;
1175
1176 usleep_range(1000, 2000);
1177 }
1178
1179 return -ETIMEDOUT;
1180 }
1181
rcsi2_c_phy_setting_v4h(struct rcar_csi2 * priv,int msps)1182 static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps)
1183 {
1184 const struct rcsi2_cphy_setting *conf;
1185
1186 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) {
1187 if (conf->msps > msps)
1188 break;
1189 }
1190
1191 if (!conf->msps) {
1192 dev_err(priv->dev, "Unsupported PHY speed for msps setting (%u Msps)", msps);
1193 return -ERANGE;
1194 }
1195
1196 /* C-PHY specific */
1197 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155);
1198 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068);
1199 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010);
1200
1201 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c);
1202 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c);
1203 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c);
1204
1205 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5);
1206 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5);
1207 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5);
1208
1209 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013);
1210 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013);
1211 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013);
1212
1213 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013);
1214 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013);
1215 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013);
1216
1217 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a);
1218 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a);
1219 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a);
1220
1221 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(2), conf->rx2);
1222 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(2), conf->rx2);
1223 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(2), conf->rx2);
1224
1225 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001);
1226 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0);
1227 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001);
1228 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001);
1229 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0);
1230
1231 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0);
1232 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0);
1233 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0);
1234
1235 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(2), conf->trio2);
1236 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(2), conf->trio2);
1237 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(2), conf->trio2);
1238
1239 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(1), conf->trio1);
1240 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1);
1241 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1);
1242
1243 /* Configure data line order. */
1244 rsci2_set_line_order(priv, priv->line_orders[0],
1245 V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG,
1246 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9));
1247 rsci2_set_line_order(priv, priv->line_orders[1],
1248 V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG,
1249 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(9));
1250 rsci2_set_line_order(priv, priv->line_orders[2],
1251 V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG,
1252 V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(9));
1253
1254 /* TODO: This registers is not documented. */
1255 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000);
1256
1257 /* Leave Shutdown mode */
1258 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0));
1259 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0));
1260
1261 /* Wait for calibration */
1262 if (rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_PHY_READY)) {
1263 dev_err(priv->dev, "PHY calibration failed\n");
1264 return -ETIMEDOUT;
1265 }
1266
1267 /* C-PHY setting - analog programing*/
1268 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9), conf->lane29);
1269 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(7), conf->lane27);
1270
1271 return 0;
1272 }
1273
rcsi2_start_receiver_v4h(struct rcar_csi2 * priv,struct v4l2_subdev_state * state)1274 static int rcsi2_start_receiver_v4h(struct rcar_csi2 *priv,
1275 struct v4l2_subdev_state *state)
1276 {
1277 const struct rcar_csi2_format *format;
1278 const struct v4l2_mbus_framefmt *fmt;
1279 unsigned int lanes;
1280 int msps;
1281 int ret;
1282
1283 /* Use the format on the sink pad to compute the receiver config. */
1284 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK);
1285 format = rcsi2_code_to_fmt(fmt->code);
1286 if (!format)
1287 return -EINVAL;
1288
1289 ret = rcsi2_get_active_lanes(priv, &lanes);
1290 if (ret)
1291 return ret;
1292
1293 msps = rcsi2_calc_mbps(priv, format->bpp, lanes);
1294 if (msps < 0)
1295 return msps;
1296
1297 /* Reset LINK and PHY*/
1298 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0);
1299 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0);
1300 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0);
1301
1302 /* PHY static setting */
1303 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK);
1304 rcsi2_write(priv, V4H_FLDC_REG, 0);
1305 rcsi2_write(priv, V4H_FLDD_REG, 0);
1306 rcsi2_write(priv, V4H_IDIC_REG, 0);
1307 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_CPHY);
1308 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1);
1309
1310 /* Reset CSI2 */
1311 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0));
1312
1313 /* Registers static setting through APB */
1314 /* Common setting */
1315 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd);
1316 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233);
1317 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027);
1318 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4);
1319 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013);
1320 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003);
1321 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f);
1322 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320);
1323 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f);
1324 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18);
1325 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c);
1326 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105);
1327 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000);
1328 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003);
1329
1330 /* C-PHY settings */
1331 ret = rcsi2_c_phy_setting_v4h(priv, msps);
1332 if (ret)
1333 return ret;
1334
1335 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 |
1336 V4H_ST_PHYST_ST_STOPSTATE_1 |
1337 V4H_ST_PHYST_ST_STOPSTATE_2);
1338
1339 return 0;
1340 }
1341
rcsi2_d_phy_setting_v4m(struct rcar_csi2 * priv,int data_rate)1342 static int rcsi2_d_phy_setting_v4m(struct rcar_csi2 *priv, int data_rate)
1343 {
1344 unsigned int timeout;
1345 int ret;
1346
1347 static const struct phtw_value step1[] = {
1348 { .data = 0x00, .code = 0x00 },
1349 { .data = 0x00, .code = 0x1e },
1350 };
1351
1352 /* Shutdown and reset PHY. */
1353 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0));
1354 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0));
1355
1356 /* Start internal calibration (POR). */
1357 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));
1358 if (ret)
1359 return ret;
1360
1361 /* Wait for POR to complete. */
1362 for (timeout = 10; timeout > 0; timeout--) {
1363 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000)
1364 break;
1365 usleep_range(1000, 2000);
1366 }
1367
1368 if (!timeout) {
1369 dev_err(priv->dev, "D-PHY calibration failed\n");
1370 return -ETIMEDOUT;
1371 }
1372
1373 return 0;
1374 }
1375
rcsi2_set_osc_freq(struct rcar_csi2 * priv,unsigned int mbps)1376 static int rcsi2_set_osc_freq(struct rcar_csi2 *priv, unsigned int mbps)
1377 {
1378 const struct rcsi2_mbps_info *info;
1379 struct phtw_value steps[] = {
1380 { .data = 0x00, .code = 0x00 },
1381 { .code = 0xe2 }, /* Data filled in below. */
1382 { .code = 0xe3 }, /* Data filled in below. */
1383 { .data = 0x01, .code = 0xe4 },
1384 };
1385
1386 info = rcsi2_mbps_to_info(priv, priv->info->hsfreqrange, mbps);
1387 if (!info)
1388 return -ERANGE;
1389
1390 /* Fill in data for command. */
1391 steps[1].data = (info->osc_freq & 0x00ff) >> 0;
1392 steps[2].data = (info->osc_freq & 0x0f00) >> 8;
1393
1394 return rcsi2_phtw_write_array(priv, steps, ARRAY_SIZE(steps));
1395 }
1396
rcsi2_init_common_v4m(struct rcar_csi2 * priv,unsigned int mbps)1397 static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)
1398 {
1399 int ret;
1400
1401 static const struct phtw_value step1[] = {
1402 { .data = 0x00, .code = 0x00 },
1403 { .data = 0x3c, .code = 0x08 },
1404 };
1405
1406 static const struct phtw_value step2[] = {
1407 { .data = 0x00, .code = 0x00 },
1408 { .data = 0x80, .code = 0xe0 },
1409 { .data = 0x31, .code = 0xe1 },
1410 { .data = 0x06, .code = 0x00 },
1411 { .data = 0x11, .code = 0x11 },
1412 { .data = 0x08, .code = 0x00 },
1413 { .data = 0x11, .code = 0x11 },
1414 { .data = 0x0a, .code = 0x00 },
1415 { .data = 0x11, .code = 0x11 },
1416 { .data = 0x0c, .code = 0x00 },
1417 { .data = 0x11, .code = 0x11 },
1418 { .data = 0x01, .code = 0x00 },
1419 { .data = 0x31, .code = 0xaa },
1420 { .data = 0x05, .code = 0x00 },
1421 { .data = 0x05, .code = 0x09 },
1422 { .data = 0x07, .code = 0x00 },
1423 { .data = 0x05, .code = 0x09 },
1424 { .data = 0x09, .code = 0x00 },
1425 { .data = 0x05, .code = 0x09 },
1426 { .data = 0x0b, .code = 0x00 },
1427 { .data = 0x05, .code = 0x09 },
1428 };
1429
1430 static const struct phtw_value step3[] = {
1431 { .data = 0x01, .code = 0x00 },
1432 { .data = 0x06, .code = 0xab },
1433 };
1434
1435 if (priv->info->hsfreqrange) {
1436 ret = rcsi2_set_phypll(priv, mbps);
1437 if (ret)
1438 return ret;
1439
1440 ret = rcsi2_set_osc_freq(priv, mbps);
1441 if (ret)
1442 return ret;
1443 }
1444
1445 if (mbps <= 1500) {
1446 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));
1447 if (ret)
1448 return ret;
1449 }
1450
1451 if (priv->info->csi0clkfreqrange)
1452 rcsi2_write(priv, V4M_CSI0CLKFCPR_REG,
1453 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange));
1454
1455 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK |
1456 V4H_PHY_EN_ENABLE_0 | V4H_PHY_EN_ENABLE_1 |
1457 V4H_PHY_EN_ENABLE_2 | V4H_PHY_EN_ENABLE_3);
1458
1459 if (mbps > 1500) {
1460 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2));
1461 if (ret)
1462 return ret;
1463 }
1464
1465 return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3));
1466 }
1467
rcsi2_start_receiver_v4m(struct rcar_csi2 * priv,struct v4l2_subdev_state * state)1468 static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv,
1469 struct v4l2_subdev_state *state)
1470 {
1471 const struct rcar_csi2_format *format;
1472 const struct v4l2_mbus_framefmt *fmt;
1473 unsigned int lanes;
1474 int mbps;
1475 int ret;
1476
1477 /* Calculate parameters */
1478 fmt = v4l2_subdev_state_get_format(state, RCAR_CSI2_SINK);
1479 format = rcsi2_code_to_fmt(fmt->code);
1480 if (!format)
1481 return -EINVAL;
1482
1483 ret = rcsi2_get_active_lanes(priv, &lanes);
1484 if (ret)
1485 return ret;
1486
1487 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes);
1488 if (mbps < 0)
1489 return mbps;
1490
1491 /* Reset LINK and PHY */
1492 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0);
1493 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0);
1494 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0);
1495 rcsi2_write(priv, V4M_PHTC_REG, PHTC_TESTCLR);
1496
1497 /* PHY static setting */
1498 rcsi2_write(priv, V4H_PHY_EN_REG, V4H_PHY_EN_ENABLE_CLK);
1499 rcsi2_write(priv, V4H_FLDC_REG, 0);
1500 rcsi2_write(priv, V4H_FLDD_REG, 0);
1501 rcsi2_write(priv, V4H_IDIC_REG, 0);
1502 rcsi2_write(priv, V4H_PHY_MODE_REG, V4H_PHY_MODE_DPHY);
1503 rcsi2_write(priv, V4H_N_LANES_REG, lanes - 1);
1504
1505 rcsi2_write(priv, V4M_FRXM_REG,
1506 V4M_FRXM_FORCERXMODE_0 | V4M_FRXM_FORCERXMODE_1 |
1507 V4M_FRXM_FORCERXMODE_2 | V4M_FRXM_FORCERXMODE_3);
1508 rcsi2_write(priv, V4M_OVR1_REG,
1509 V4M_OVR1_FORCERXMODE_0 | V4M_OVR1_FORCERXMODE_1 |
1510 V4M_OVR1_FORCERXMODE_2 | V4M_OVR1_FORCERXMODE_3);
1511
1512 /* Reset CSI2 */
1513 rcsi2_write(priv, V4M_PHTC_REG, 0);
1514 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0));
1515
1516 /* Common settings */
1517 ret = rcsi2_init_common_v4m(priv, mbps);
1518 if (ret)
1519 return ret;
1520
1521 /* D-PHY settings */
1522 ret = rcsi2_d_phy_setting_v4m(priv, mbps);
1523 if (ret)
1524 return ret;
1525
1526 rcsi2_wait_phy_start_v4h(priv, V4H_ST_PHYST_ST_STOPSTATE_0 |
1527 V4H_ST_PHYST_ST_STOPSTATE_1 |
1528 V4H_ST_PHYST_ST_STOPSTATE_2 |
1529 V4H_ST_PHYST_ST_STOPSTATE_3);
1530
1531 rcsi2_write(priv, V4M_FRXM_REG, 0);
1532
1533 return 0;
1534 }
1535
rcsi2_start(struct rcar_csi2 * priv,struct v4l2_subdev_state * state)1536 static int rcsi2_start(struct rcar_csi2 *priv, struct v4l2_subdev_state *state)
1537 {
1538 int ret;
1539
1540 ret = rcsi2_exit_standby(priv);
1541 if (ret < 0)
1542 return ret;
1543
1544 ret = priv->info->start_receiver(priv, state);
1545 if (ret) {
1546 rcsi2_enter_standby(priv);
1547 return ret;
1548 }
1549
1550 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1);
1551 if (ret) {
1552 rcsi2_enter_standby(priv);
1553 return ret;
1554 }
1555
1556 return 0;
1557 }
1558
rcsi2_stop(struct rcar_csi2 * priv)1559 static void rcsi2_stop(struct rcar_csi2 *priv)
1560 {
1561 rcsi2_enter_standby(priv);
1562 v4l2_subdev_call(priv->remote, video, s_stream, 0);
1563 }
1564
rcsi2_s_stream(struct v4l2_subdev * sd,int enable)1565 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable)
1566 {
1567 struct rcar_csi2 *priv = sd_to_csi2(sd);
1568 struct v4l2_subdev_state *state;
1569 int ret = 0;
1570
1571 if (!priv->remote)
1572 return -ENODEV;
1573
1574 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev);
1575
1576 if (enable && priv->stream_count == 0) {
1577 ret = rcsi2_start(priv, state);
1578 if (ret)
1579 goto out;
1580 } else if (!enable && priv->stream_count == 1) {
1581 rcsi2_stop(priv);
1582 }
1583
1584 priv->stream_count += enable ? 1 : -1;
1585 out:
1586 v4l2_subdev_unlock_state(state);
1587
1588 return ret;
1589 }
1590
rcsi2_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * format)1591 static int rcsi2_set_pad_format(struct v4l2_subdev *sd,
1592 struct v4l2_subdev_state *state,
1593 struct v4l2_subdev_format *format)
1594 {
1595 struct rcar_csi2 *priv = sd_to_csi2(sd);
1596 unsigned int num_pads = rcsi2_num_pads(priv);
1597
1598 if (format->pad > RCAR_CSI2_SINK)
1599 return v4l2_subdev_get_fmt(sd, state, format);
1600
1601 if (!rcsi2_code_to_fmt(format->format.code))
1602 format->format.code = rcar_csi2_formats[0].code;
1603
1604 *v4l2_subdev_state_get_format(state, format->pad) = format->format;
1605
1606 /* Propagate the format to the source pads. */
1607 for (unsigned int i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)
1608 *v4l2_subdev_state_get_format(state, i) = format->format;
1609
1610 return 0;
1611 }
1612
1613 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = {
1614 .s_stream = rcsi2_s_stream,
1615 };
1616
1617 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = {
1618 .set_fmt = rcsi2_set_pad_format,
1619 .get_fmt = v4l2_subdev_get_fmt,
1620 };
1621
1622 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = {
1623 .video = &rcar_csi2_video_ops,
1624 .pad = &rcar_csi2_pad_ops,
1625 };
1626
rcsi2_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)1627 static int rcsi2_init_state(struct v4l2_subdev *sd,
1628 struct v4l2_subdev_state *state)
1629 {
1630 struct rcar_csi2 *priv = sd_to_csi2(sd);
1631 unsigned int num_pads = rcsi2_num_pads(priv);
1632
1633 static const struct v4l2_mbus_framefmt rcar_csi2_default_fmt = {
1634 .width = 1920,
1635 .height = 1080,
1636 .code = MEDIA_BUS_FMT_RGB888_1X24,
1637 .colorspace = V4L2_COLORSPACE_SRGB,
1638 .field = V4L2_FIELD_NONE,
1639 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
1640 .quantization = V4L2_QUANTIZATION_DEFAULT,
1641 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
1642 };
1643
1644 for (unsigned int i = RCAR_CSI2_SINK; i < num_pads; i++)
1645 *v4l2_subdev_state_get_format(state, i) = rcar_csi2_default_fmt;
1646
1647 return 0;
1648 }
1649
1650 static const struct v4l2_subdev_internal_ops rcar_csi2_internal_ops = {
1651 .init_state = rcsi2_init_state,
1652 };
1653
rcsi2_irq(int irq,void * data)1654 static irqreturn_t rcsi2_irq(int irq, void *data)
1655 {
1656 struct rcar_csi2 *priv = data;
1657 u32 status, err_status;
1658
1659 status = rcsi2_read(priv, INTSTATE_REG);
1660 err_status = rcsi2_read(priv, INTERRSTATE_REG);
1661
1662 if (!status)
1663 return IRQ_HANDLED;
1664
1665 rcsi2_write(priv, INTSTATE_REG, status);
1666
1667 if (!err_status)
1668 return IRQ_HANDLED;
1669
1670 rcsi2_write(priv, INTERRSTATE_REG, err_status);
1671
1672 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n");
1673
1674 return IRQ_WAKE_THREAD;
1675 }
1676
rcsi2_irq_thread(int irq,void * data)1677 static irqreturn_t rcsi2_irq_thread(int irq, void *data)
1678 {
1679 struct v4l2_subdev_state *state;
1680 struct rcar_csi2 *priv = data;
1681
1682 state = v4l2_subdev_lock_and_get_active_state(&priv->subdev);
1683
1684 rcsi2_stop(priv);
1685 usleep_range(1000, 2000);
1686 if (rcsi2_start(priv, state))
1687 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n");
1688
1689 v4l2_subdev_unlock_state(state);
1690
1691 return IRQ_HANDLED;
1692 }
1693
1694 /* -----------------------------------------------------------------------------
1695 * Async handling and registration of subdevices and links.
1696 */
1697
rcsi2_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asc)1698 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier,
1699 struct v4l2_subdev *subdev,
1700 struct v4l2_async_connection *asc)
1701 {
1702 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
1703 int pad;
1704
1705 pad = media_entity_get_fwnode_pad(&subdev->entity, asc->match.fwnode,
1706 MEDIA_PAD_FL_SOURCE);
1707 if (pad < 0) {
1708 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name);
1709 return pad;
1710 }
1711
1712 priv->remote = subdev;
1713 priv->remote_pad = pad;
1714
1715 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad);
1716
1717 return media_create_pad_link(&subdev->entity, pad,
1718 &priv->subdev.entity, 0,
1719 MEDIA_LNK_FL_ENABLED |
1720 MEDIA_LNK_FL_IMMUTABLE);
1721 }
1722
rcsi2_notify_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_connection * asc)1723 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier,
1724 struct v4l2_subdev *subdev,
1725 struct v4l2_async_connection *asc)
1726 {
1727 struct rcar_csi2 *priv = notifier_to_csi2(notifier);
1728
1729 priv->remote = NULL;
1730
1731 dev_dbg(priv->dev, "Unbind %s\n", subdev->name);
1732 }
1733
1734 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = {
1735 .bound = rcsi2_notify_bound,
1736 .unbind = rcsi2_notify_unbind,
1737 };
1738
rcsi2_parse_v4l2(struct rcar_csi2 * priv,struct v4l2_fwnode_endpoint * vep)1739 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
1740 struct v4l2_fwnode_endpoint *vep)
1741 {
1742 unsigned int i;
1743
1744 /* Only port 0 endpoint 0 is valid. */
1745 if (vep->base.port || vep->base.id)
1746 return -ENOTCONN;
1747
1748 priv->lanes = vep->bus.mipi_csi2.num_data_lanes;
1749
1750 switch (vep->bus_type) {
1751 case V4L2_MBUS_CSI2_DPHY:
1752 if (!priv->info->support_dphy) {
1753 dev_err(priv->dev, "D-PHY not supported\n");
1754 return -EINVAL;
1755 }
1756
1757 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) {
1758 dev_err(priv->dev,
1759 "Unsupported number of data-lanes for D-PHY: %u\n",
1760 priv->lanes);
1761 return -EINVAL;
1762 }
1763
1764 priv->cphy = false;
1765 break;
1766 case V4L2_MBUS_CSI2_CPHY:
1767 if (!priv->info->support_cphy) {
1768 dev_err(priv->dev, "C-PHY not supported\n");
1769 return -EINVAL;
1770 }
1771
1772 if (priv->lanes != 3) {
1773 dev_err(priv->dev,
1774 "Unsupported number of data-lanes for C-PHY: %u\n",
1775 priv->lanes);
1776 return -EINVAL;
1777 }
1778
1779 priv->cphy = true;
1780 break;
1781 default:
1782 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type);
1783 return -EINVAL;
1784 }
1785
1786 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) {
1787 priv->lane_swap[i] = i < priv->lanes ?
1788 vep->bus.mipi_csi2.data_lanes[i] : i;
1789
1790 /* Check for valid lane number. */
1791 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) {
1792 dev_err(priv->dev, "data-lanes must be in 1-4 range\n");
1793 return -EINVAL;
1794 }
1795 }
1796
1797 for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++)
1798 priv->line_orders[i] = vep->bus.mipi_csi2.line_orders[i];
1799
1800 return 0;
1801 }
1802
rcsi2_parse_dt(struct rcar_csi2 * priv)1803 static int rcsi2_parse_dt(struct rcar_csi2 *priv)
1804 {
1805 struct v4l2_async_connection *asc;
1806 struct fwnode_handle *fwnode;
1807 struct fwnode_handle *ep;
1808 struct v4l2_fwnode_endpoint v4l2_ep = {
1809 .bus_type = V4L2_MBUS_UNKNOWN,
1810 };
1811 int ret;
1812
1813 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0);
1814 if (!ep) {
1815 dev_err(priv->dev, "Not connected to subdevice\n");
1816 return -EINVAL;
1817 }
1818
1819 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
1820 if (ret) {
1821 dev_err(priv->dev, "Could not parse v4l2 endpoint\n");
1822 fwnode_handle_put(ep);
1823 return -EINVAL;
1824 }
1825
1826 ret = rcsi2_parse_v4l2(priv, &v4l2_ep);
1827 if (ret) {
1828 fwnode_handle_put(ep);
1829 return ret;
1830 }
1831
1832 fwnode = fwnode_graph_get_remote_endpoint(ep);
1833 fwnode_handle_put(ep);
1834
1835 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode));
1836
1837 v4l2_async_subdev_nf_init(&priv->notifier, &priv->subdev);
1838 priv->notifier.ops = &rcar_csi2_notify_ops;
1839
1840 asc = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode,
1841 struct v4l2_async_connection);
1842 fwnode_handle_put(fwnode);
1843 if (IS_ERR(asc))
1844 return PTR_ERR(asc);
1845
1846 ret = v4l2_async_nf_register(&priv->notifier);
1847 if (ret)
1848 v4l2_async_nf_cleanup(&priv->notifier);
1849
1850 return ret;
1851 }
1852
1853 /* -----------------------------------------------------------------------------
1854 * PHTW initialization sequences.
1855 *
1856 * NOTE: Magic values are from the datasheet and lack documentation.
1857 */
1858
rcsi2_phtw_write_mbps(struct rcar_csi2 * priv,unsigned int mbps,const struct rcsi2_mbps_info * values,u8 code)1859 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps,
1860 const struct rcsi2_mbps_info *values, u8 code)
1861 {
1862 const struct rcsi2_mbps_info *info;
1863
1864 info = rcsi2_mbps_to_info(priv, values, mbps);
1865 if (!info)
1866 return -ERANGE;
1867
1868 return rcsi2_phtw_write(priv, info->reg, code);
1869 }
1870
__rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1871 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv,
1872 unsigned int mbps)
1873 {
1874 static const struct phtw_value step1[] = {
1875 { .data = 0xcc, .code = 0xe2 },
1876 { .data = 0x01, .code = 0xe3 },
1877 { .data = 0x11, .code = 0xe4 },
1878 { .data = 0x01, .code = 0xe5 },
1879 { .data = 0x10, .code = 0x04 },
1880 };
1881
1882 static const struct phtw_value step2[] = {
1883 { .data = 0x38, .code = 0x08 },
1884 { .data = 0x01, .code = 0x00 },
1885 { .data = 0x4b, .code = 0xac },
1886 { .data = 0x03, .code = 0x00 },
1887 { .data = 0x80, .code = 0x07 },
1888 };
1889
1890 int ret;
1891
1892 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));
1893 if (ret)
1894 return ret;
1895
1896 if (mbps != 0 && mbps <= 250) {
1897 ret = rcsi2_phtw_write(priv, 0x39, 0x05);
1898 if (ret)
1899 return ret;
1900
1901 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n,
1902 0xf1);
1903 if (ret)
1904 return ret;
1905 }
1906
1907 return rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2));
1908 }
1909
rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 * priv,unsigned int mbps)1910 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps)
1911 {
1912 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps);
1913 }
1914
rcsi2_init_phtw_h3es2(struct rcar_csi2 * priv,unsigned int mbps)1915 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps)
1916 {
1917 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0);
1918 }
1919
rcsi2_init_phtw_v3m_e3(struct rcar_csi2 * priv,unsigned int mbps)1920 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps)
1921 {
1922 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44);
1923 }
1924
rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 * priv)1925 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv)
1926 {
1927 static const struct phtw_value step1[] = {
1928 { .data = 0xee, .code = 0x34 },
1929 { .data = 0xee, .code = 0x44 },
1930 { .data = 0xee, .code = 0x54 },
1931 { .data = 0xee, .code = 0x84 },
1932 { .data = 0xee, .code = 0x94 },
1933 };
1934
1935 return rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));
1936 }
1937
rcsi2_init_phtw_v3u(struct rcar_csi2 * priv,unsigned int mbps)1938 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv,
1939 unsigned int mbps)
1940 {
1941 /* In case of 1500Mbps or less */
1942 static const struct phtw_value step1[] = {
1943 { .data = 0xcc, .code = 0xe2 },
1944 };
1945
1946 static const struct phtw_value step2[] = {
1947 { .data = 0x01, .code = 0xe3 },
1948 { .data = 0x11, .code = 0xe4 },
1949 { .data = 0x01, .code = 0xe5 },
1950 };
1951
1952 /* In case of 1500Mbps or less */
1953 static const struct phtw_value step3[] = {
1954 { .data = 0x38, .code = 0x08 },
1955 };
1956
1957 static const struct phtw_value step4[] = {
1958 { .data = 0x01, .code = 0x00 },
1959 { .data = 0x4b, .code = 0xac },
1960 { .data = 0x03, .code = 0x00 },
1961 { .data = 0x80, .code = 0x07 },
1962 };
1963
1964 int ret;
1965
1966 if (mbps != 0 && mbps <= 1500)
1967 ret = rcsi2_phtw_write_array(priv, step1, ARRAY_SIZE(step1));
1968 else
1969 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2);
1970 if (ret)
1971 return ret;
1972
1973 ret = rcsi2_phtw_write_array(priv, step2, ARRAY_SIZE(step2));
1974 if (ret)
1975 return ret;
1976
1977 if (mbps != 0 && mbps <= 1500) {
1978 ret = rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3));
1979 if (ret)
1980 return ret;
1981 }
1982
1983 ret = rcsi2_phtw_write_array(priv, step4, ARRAY_SIZE(step4));
1984 if (ret)
1985 return ret;
1986
1987 return ret;
1988 }
1989
1990 /* -----------------------------------------------------------------------------
1991 * Platform Device Driver.
1992 */
1993
rcsi2_link_setup(struct media_entity * entity,const struct media_pad * local,const struct media_pad * remote,u32 flags)1994 static int rcsi2_link_setup(struct media_entity *entity,
1995 const struct media_pad *local,
1996 const struct media_pad *remote, u32 flags)
1997 {
1998 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1999 struct rcar_csi2 *priv = sd_to_csi2(sd);
2000 struct video_device *vdev;
2001 int channel, vc;
2002 u32 id;
2003
2004 if (!is_media_entity_v4l2_video_device(remote->entity)) {
2005 dev_err(priv->dev, "Remote is not a video device\n");
2006 return -EINVAL;
2007 }
2008
2009 vdev = media_entity_to_video_device(remote->entity);
2010
2011 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) {
2012 dev_err(priv->dev, "No renesas,id, can't configure routing\n");
2013 return -EINVAL;
2014 }
2015
2016 channel = id % 4;
2017
2018 if (flags & MEDIA_LNK_FL_ENABLED) {
2019 if (media_pad_remote_pad_first(local)) {
2020 dev_dbg(priv->dev,
2021 "Each VC can only be routed to one output channel\n");
2022 return -EINVAL;
2023 }
2024
2025 vc = local->index - 1;
2026
2027 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n",
2028 vc, id, channel);
2029 } else {
2030 vc = -1;
2031 }
2032
2033 priv->channel_vc[channel] = vc;
2034
2035 return 0;
2036 }
2037
2038 static const struct media_entity_operations rcar_csi2_entity_ops = {
2039 .link_setup = rcsi2_link_setup,
2040 .link_validate = v4l2_subdev_link_validate,
2041 };
2042
rcsi2_probe_resources(struct rcar_csi2 * priv,struct platform_device * pdev)2043 static int rcsi2_probe_resources(struct rcar_csi2 *priv,
2044 struct platform_device *pdev)
2045 {
2046 int irq, ret;
2047
2048 priv->base = devm_platform_ioremap_resource(pdev, 0);
2049 if (IS_ERR(priv->base))
2050 return PTR_ERR(priv->base);
2051
2052 irq = platform_get_irq(pdev, 0);
2053 if (irq < 0)
2054 return irq;
2055
2056 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq,
2057 rcsi2_irq_thread, IRQF_SHARED,
2058 KBUILD_MODNAME, priv);
2059 if (ret)
2060 return ret;
2061
2062 priv->rstc = devm_reset_control_get(&pdev->dev, NULL);
2063
2064 return PTR_ERR_OR_ZERO(priv->rstc);
2065 }
2066
2067 static const struct rcsi2_register_layout rcsi2_registers_gen3 = {
2068 .phtw = PHTW_REG,
2069 .phypll = PHYPLL_REG,
2070 };
2071
2072 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = {
2073 .regs = &rcsi2_registers_gen3,
2074 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
2075 .start_receiver = rcsi2_start_receiver_gen3,
2076 .enter_standby = rcsi2_enter_standby_gen3,
2077 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
2078 .csi0clkfreqrange = 0x20,
2079 .num_channels = 4,
2080 .clear_ulps = true,
2081 .support_dphy = true,
2082 };
2083
2084 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = {
2085 .regs = &rcsi2_registers_gen3,
2086 .init_phtw = rcsi2_init_phtw_h3es2,
2087 .start_receiver = rcsi2_start_receiver_gen3,
2088 .enter_standby = rcsi2_enter_standby_gen3,
2089 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
2090 .csi0clkfreqrange = 0x20,
2091 .num_channels = 4,
2092 .clear_ulps = true,
2093 .support_dphy = true,
2094 };
2095
2096 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = {
2097 .regs = &rcsi2_registers_gen3,
2098 .start_receiver = rcsi2_start_receiver_gen3,
2099 .enter_standby = rcsi2_enter_standby_gen3,
2100 .hsfreqrange = hsfreqrange_m3w,
2101 .num_channels = 4,
2102 .support_dphy = true,
2103 };
2104
2105 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = {
2106 .regs = &rcsi2_registers_gen3,
2107 .start_receiver = rcsi2_start_receiver_gen3,
2108 .enter_standby = rcsi2_enter_standby_gen3,
2109 .hsfreqrange = hsfreqrange_m3w,
2110 .num_channels = 4,
2111 .support_dphy = true,
2112 };
2113
2114 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = {
2115 .regs = &rcsi2_registers_gen3,
2116 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
2117 .start_receiver = rcsi2_start_receiver_gen3,
2118 .enter_standby = rcsi2_enter_standby_gen3,
2119 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
2120 .csi0clkfreqrange = 0x20,
2121 .num_channels = 4,
2122 .clear_ulps = true,
2123 .support_dphy = true,
2124 };
2125
2126 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = {
2127 .regs = &rcsi2_registers_gen3,
2128 .init_phtw = rcsi2_init_phtw_v3m_e3,
2129 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
2130 .start_receiver = rcsi2_start_receiver_gen3,
2131 .enter_standby = rcsi2_enter_standby_gen3,
2132 .num_channels = 4,
2133 .support_dphy = true,
2134 };
2135
2136 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = {
2137 .regs = &rcsi2_registers_gen3,
2138 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n,
2139 .start_receiver = rcsi2_start_receiver_gen3,
2140 .enter_standby = rcsi2_enter_standby_gen3,
2141 .hsfreqrange = hsfreqrange_h3_v3h_m3n,
2142 .csi0clkfreqrange = 0x20,
2143 .clear_ulps = true,
2144 .support_dphy = true,
2145 };
2146
2147 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = {
2148 .regs = &rcsi2_registers_gen3,
2149 .init_phtw = rcsi2_init_phtw_v3m_e3,
2150 .phy_post_init = rcsi2_phy_post_init_v3m_e3,
2151 .start_receiver = rcsi2_start_receiver_gen3,
2152 .enter_standby = rcsi2_enter_standby_gen3,
2153 .num_channels = 2,
2154 .support_dphy = true,
2155 };
2156
2157 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = {
2158 .regs = &rcsi2_registers_gen3,
2159 .init_phtw = rcsi2_init_phtw_v3u,
2160 .start_receiver = rcsi2_start_receiver_gen3,
2161 .enter_standby = rcsi2_enter_standby_gen3,
2162 .hsfreqrange = hsfreqrange_v3u,
2163 .csi0clkfreqrange = 0x20,
2164 .clear_ulps = true,
2165 .use_isp = true,
2166 .support_dphy = true,
2167 };
2168
2169 static const struct rcar_csi2_info rcar_csi2_info_r8a779g0 = {
2170 .regs = &rcsi2_registers_gen3,
2171 .start_receiver = rcsi2_start_receiver_v4h,
2172 .use_isp = true,
2173 .support_cphy = true,
2174 };
2175
2176 static const struct rcsi2_register_layout rcsi2_registers_v4m = {
2177 .phtw = V4M_PHTW_REG,
2178 .phypll = V4M_PHYPLL_REG,
2179 };
2180
2181 static const struct rcar_csi2_info rcar_csi2_info_r8a779h0 = {
2182 .regs = &rcsi2_registers_v4m,
2183 .start_receiver = rcsi2_start_receiver_v4m,
2184 .hsfreqrange = hsfreqrange_v4m,
2185 .csi0clkfreqrange = 0x0c,
2186 .use_isp = true,
2187 .support_dphy = true,
2188 };
2189
2190 static const struct of_device_id rcar_csi2_of_table[] = {
2191 {
2192 .compatible = "renesas,r8a774a1-csi2",
2193 .data = &rcar_csi2_info_r8a7796,
2194 },
2195 {
2196 .compatible = "renesas,r8a774b1-csi2",
2197 .data = &rcar_csi2_info_r8a77965,
2198 },
2199 {
2200 .compatible = "renesas,r8a774c0-csi2",
2201 .data = &rcar_csi2_info_r8a77990,
2202 },
2203 {
2204 .compatible = "renesas,r8a774e1-csi2",
2205 .data = &rcar_csi2_info_r8a7795,
2206 },
2207 {
2208 .compatible = "renesas,r8a7795-csi2",
2209 .data = &rcar_csi2_info_r8a7795,
2210 },
2211 {
2212 .compatible = "renesas,r8a7796-csi2",
2213 .data = &rcar_csi2_info_r8a7796,
2214 },
2215 {
2216 .compatible = "renesas,r8a77961-csi2",
2217 .data = &rcar_csi2_info_r8a77961,
2218 },
2219 {
2220 .compatible = "renesas,r8a77965-csi2",
2221 .data = &rcar_csi2_info_r8a77965,
2222 },
2223 {
2224 .compatible = "renesas,r8a77970-csi2",
2225 .data = &rcar_csi2_info_r8a77970,
2226 },
2227 {
2228 .compatible = "renesas,r8a77980-csi2",
2229 .data = &rcar_csi2_info_r8a77980,
2230 },
2231 {
2232 .compatible = "renesas,r8a77990-csi2",
2233 .data = &rcar_csi2_info_r8a77990,
2234 },
2235 {
2236 .compatible = "renesas,r8a779a0-csi2",
2237 .data = &rcar_csi2_info_r8a779a0,
2238 },
2239 {
2240 .compatible = "renesas,r8a779g0-csi2",
2241 .data = &rcar_csi2_info_r8a779g0,
2242 },
2243 {
2244 .compatible = "renesas,r8a779h0-csi2",
2245 .data = &rcar_csi2_info_r8a779h0,
2246 },
2247 { /* sentinel */ },
2248 };
2249 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table);
2250
2251 static const struct soc_device_attribute r8a7795[] = {
2252 {
2253 .soc_id = "r8a7795", .revision = "ES2.*",
2254 .data = &rcar_csi2_info_r8a7795es2,
2255 },
2256 { /* sentinel */ }
2257 };
2258
rcsi2_probe(struct platform_device * pdev)2259 static int rcsi2_probe(struct platform_device *pdev)
2260 {
2261 const struct soc_device_attribute *attr;
2262 struct rcar_csi2 *priv;
2263 unsigned int i, num_pads;
2264 int ret;
2265
2266 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2267 if (!priv)
2268 return -ENOMEM;
2269
2270 priv->info = of_device_get_match_data(&pdev->dev);
2271
2272 /*
2273 * The different ES versions of r8a7795 (H3) behave differently but
2274 * share the same compatible string.
2275 */
2276 attr = soc_device_match(r8a7795);
2277 if (attr)
2278 priv->info = attr->data;
2279
2280 priv->dev = &pdev->dev;
2281
2282 priv->stream_count = 0;
2283
2284 ret = rcsi2_probe_resources(priv, pdev);
2285 if (ret) {
2286 dev_err(priv->dev, "Failed to get resources\n");
2287 return ret;
2288 }
2289
2290 platform_set_drvdata(pdev, priv);
2291
2292 ret = rcsi2_parse_dt(priv);
2293 if (ret)
2294 return ret;
2295
2296 priv->subdev.owner = THIS_MODULE;
2297 priv->subdev.dev = &pdev->dev;
2298 priv->subdev.internal_ops = &rcar_csi2_internal_ops;
2299 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops);
2300 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
2301 snprintf(priv->subdev.name, sizeof(priv->subdev.name), "%s %s",
2302 KBUILD_MODNAME, dev_name(&pdev->dev));
2303 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
2304
2305 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
2306 priv->subdev.entity.ops = &rcar_csi2_entity_ops;
2307
2308 num_pads = rcsi2_num_pads(priv);
2309
2310 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
2311 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++)
2312 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE;
2313
2314 ret = media_entity_pads_init(&priv->subdev.entity, num_pads,
2315 priv->pads);
2316 if (ret)
2317 goto error_async;
2318
2319 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++)
2320 priv->channel_vc[i] = -1;
2321
2322 pm_runtime_enable(&pdev->dev);
2323
2324 ret = v4l2_subdev_init_finalize(&priv->subdev);
2325 if (ret)
2326 goto error_pm_runtime;
2327
2328 ret = v4l2_async_register_subdev(&priv->subdev);
2329 if (ret < 0)
2330 goto error_subdev;
2331
2332 dev_info(priv->dev, "%d lanes found\n", priv->lanes);
2333
2334 return 0;
2335
2336 error_subdev:
2337 v4l2_subdev_cleanup(&priv->subdev);
2338 error_pm_runtime:
2339 pm_runtime_disable(&pdev->dev);
2340 error_async:
2341 v4l2_async_nf_unregister(&priv->notifier);
2342 v4l2_async_nf_cleanup(&priv->notifier);
2343
2344 return ret;
2345 }
2346
rcsi2_remove(struct platform_device * pdev)2347 static void rcsi2_remove(struct platform_device *pdev)
2348 {
2349 struct rcar_csi2 *priv = platform_get_drvdata(pdev);
2350
2351 v4l2_async_nf_unregister(&priv->notifier);
2352 v4l2_async_nf_cleanup(&priv->notifier);
2353 v4l2_async_unregister_subdev(&priv->subdev);
2354 v4l2_subdev_cleanup(&priv->subdev);
2355
2356 pm_runtime_disable(&pdev->dev);
2357 }
2358
2359 static struct platform_driver rcar_csi2_pdrv = {
2360 .remove = rcsi2_remove,
2361 .probe = rcsi2_probe,
2362 .driver = {
2363 .name = "rcar-csi2",
2364 .suppress_bind_attrs = true,
2365 .of_match_table = rcar_csi2_of_table,
2366 },
2367 };
2368
2369 module_platform_driver(rcar_csi2_pdrv);
2370
2371 MODULE_AUTHOR("Niklas Söderlund <[email protected]>");
2372 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver");
2373 MODULE_LICENSE("GPL");
2374