1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2020 Intel Corporation.
3
4 #include <linux/unaligned.h>
5 #include <linux/acpi.h>
6 #include <linux/clk.h>
7 #include <linux/delay.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/i2c.h>
10 #include <linux/module.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/nvmem-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/regulator/consumer.h>
15 #include <media/v4l2-ctrls.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-fwnode.h>
18
19 #define OV2740_LINK_FREQ_360MHZ 360000000ULL
20 #define OV2740_LINK_FREQ_180MHZ 180000000ULL
21 #define OV2740_SCLK 72000000LL
22 #define OV2740_MCLK 19200000
23 #define OV2740_DATA_LANES 2
24 #define OV2740_RGB_DEPTH 10
25
26 #define OV2740_REG_CHIP_ID 0x300a
27 #define OV2740_CHIP_ID 0x2740
28
29 #define OV2740_REG_MODE_SELECT 0x0100
30 #define OV2740_MODE_STANDBY 0x00
31 #define OV2740_MODE_STREAMING 0x01
32
33 /* vertical-timings from sensor */
34 #define OV2740_REG_VTS 0x380e
35
36 /* horizontal-timings from sensor */
37 #define OV2740_REG_HTS 0x380c
38
39 /* Exposure controls from sensor */
40 #define OV2740_REG_EXPOSURE 0x3500
41 #define OV2740_EXPOSURE_MIN 4
42 #define OV2740_EXPOSURE_MAX_MARGIN 8
43 #define OV2740_EXPOSURE_STEP 1
44
45 /* Analog gain controls from sensor */
46 #define OV2740_REG_ANALOG_GAIN 0x3508
47 #define OV2740_ANAL_GAIN_MIN 128
48 #define OV2740_ANAL_GAIN_MAX 1983
49 #define OV2740_ANAL_GAIN_STEP 1
50
51 /* Digital gain controls from sensor */
52 #define OV2740_REG_MWB_R_GAIN 0x500a
53 #define OV2740_REG_MWB_G_GAIN 0x500c
54 #define OV2740_REG_MWB_B_GAIN 0x500e
55 #define OV2740_DGTL_GAIN_MIN 1024
56 #define OV2740_DGTL_GAIN_MAX 4095
57 #define OV2740_DGTL_GAIN_STEP 1
58 #define OV2740_DGTL_GAIN_DEFAULT 1024
59
60 /* Test Pattern Control */
61 #define OV2740_REG_TEST_PATTERN 0x5040
62 #define OV2740_TEST_PATTERN_ENABLE BIT(7)
63 #define OV2740_TEST_PATTERN_BAR_SHIFT 2
64
65 /* Group Access */
66 #define OV2740_REG_GROUP_ACCESS 0x3208
67 #define OV2740_GROUP_HOLD_START 0x0
68 #define OV2740_GROUP_HOLD_END 0x10
69 #define OV2740_GROUP_HOLD_LAUNCH 0xa0
70
71 /* ISP CTRL00 */
72 #define OV2740_REG_ISP_CTRL00 0x5000
73 /* ISP CTRL01 */
74 #define OV2740_REG_ISP_CTRL01 0x5001
75 /* Customer Addresses: 0x7010 - 0x710F */
76 #define CUSTOMER_USE_OTP_SIZE 0x100
77 /* OTP registers from sensor */
78 #define OV2740_REG_OTP_CUSTOMER 0x7010
79
80 static const char * const ov2740_supply_name[] = {
81 "AVDD",
82 "DOVDD",
83 "DVDD",
84 };
85
86 #define OV2740_NUM_SUPPLIES ARRAY_SIZE(ov2740_supply_name)
87
88 struct nvm_data {
89 struct nvmem_device *nvmem;
90 struct regmap *regmap;
91 char *nvm_buffer;
92 };
93
94 enum {
95 OV2740_LINK_FREQ_360MHZ_INDEX,
96 OV2740_LINK_FREQ_180MHZ_INDEX,
97 };
98
99 struct ov2740_reg {
100 u16 address;
101 u8 val;
102 };
103
104 struct ov2740_reg_list {
105 u32 num_of_regs;
106 const struct ov2740_reg *regs;
107 };
108
109 struct ov2740_link_freq_config {
110 const struct ov2740_reg_list reg_list;
111 };
112
113 struct ov2740_mode {
114 /* Frame width in pixels */
115 u32 width;
116
117 /* Frame height in pixels */
118 u32 height;
119
120 /* Horizontal timining size */
121 u32 hts;
122
123 /* Default vertical timining size */
124 u32 vts_def;
125
126 /* Min vertical timining size */
127 u32 vts_min;
128
129 /* Max vertical timining size */
130 u32 vts_max;
131
132 /* Link frequency needed for this resolution */
133 u32 link_freq_index;
134
135 /* Sensor register settings for this resolution */
136 const struct ov2740_reg_list reg_list;
137 };
138
139 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
140 {0x0302, 0x4b},
141 {0x030d, 0x4b},
142 {0x030e, 0x02},
143 {0x030a, 0x01},
144 {0x0312, 0x11},
145 };
146
147 static const struct ov2740_reg mipi_data_rate_360mbps[] = {
148 {0x0302, 0x4b},
149 {0x0303, 0x01},
150 {0x030d, 0x4b},
151 {0x030e, 0x02},
152 {0x030a, 0x01},
153 {0x0312, 0x11},
154 {0x4837, 0x2c},
155 };
156
157 static const struct ov2740_reg mode_1932x1092_regs_360mhz[] = {
158 {0x3000, 0x00},
159 {0x3018, 0x32},
160 {0x3031, 0x0a},
161 {0x3080, 0x08},
162 {0x3083, 0xB4},
163 {0x3103, 0x00},
164 {0x3104, 0x01},
165 {0x3106, 0x01},
166 {0x3500, 0x00},
167 {0x3501, 0x44},
168 {0x3502, 0x40},
169 {0x3503, 0x88},
170 {0x3507, 0x00},
171 {0x3508, 0x00},
172 {0x3509, 0x80},
173 {0x350c, 0x00},
174 {0x350d, 0x80},
175 {0x3510, 0x00},
176 {0x3511, 0x00},
177 {0x3512, 0x20},
178 {0x3632, 0x00},
179 {0x3633, 0x10},
180 {0x3634, 0x10},
181 {0x3635, 0x10},
182 {0x3645, 0x13},
183 {0x3646, 0x81},
184 {0x3636, 0x10},
185 {0x3651, 0x0a},
186 {0x3656, 0x02},
187 {0x3659, 0x04},
188 {0x365a, 0xda},
189 {0x365b, 0xa2},
190 {0x365c, 0x04},
191 {0x365d, 0x1d},
192 {0x365e, 0x1a},
193 {0x3662, 0xd7},
194 {0x3667, 0x78},
195 {0x3669, 0x0a},
196 {0x366a, 0x92},
197 {0x3700, 0x54},
198 {0x3702, 0x10},
199 {0x3706, 0x42},
200 {0x3709, 0x30},
201 {0x370b, 0xc2},
202 {0x3714, 0x63},
203 {0x3715, 0x01},
204 {0x3716, 0x00},
205 {0x371a, 0x3e},
206 {0x3732, 0x0e},
207 {0x3733, 0x10},
208 {0x375f, 0x0e},
209 {0x3768, 0x30},
210 {0x3769, 0x44},
211 {0x376a, 0x22},
212 {0x377b, 0x20},
213 {0x377c, 0x00},
214 {0x377d, 0x0c},
215 {0x3798, 0x00},
216 {0x37a1, 0x55},
217 {0x37a8, 0x6d},
218 {0x37c2, 0x04},
219 {0x37c5, 0x00},
220 {0x37c8, 0x00},
221 {0x3800, 0x00},
222 {0x3801, 0x00},
223 {0x3802, 0x00},
224 {0x3803, 0x00},
225 {0x3804, 0x07},
226 {0x3805, 0x8f},
227 {0x3806, 0x04},
228 {0x3807, 0x47},
229 {0x3808, 0x07},
230 {0x3809, 0x88},
231 {0x380a, 0x04},
232 {0x380b, 0x40},
233 {0x380c, 0x04},
234 {0x380d, 0x38},
235 {0x380e, 0x04},
236 {0x380f, 0x60},
237 {0x3810, 0x00},
238 {0x3811, 0x04},
239 {0x3812, 0x00},
240 {0x3813, 0x04},
241 {0x3814, 0x01},
242 {0x3815, 0x01},
243 {0x3820, 0x80},
244 {0x3821, 0x46},
245 {0x3822, 0x84},
246 {0x3829, 0x00},
247 {0x382a, 0x01},
248 {0x382b, 0x01},
249 {0x3830, 0x04},
250 {0x3836, 0x01},
251 {0x3837, 0x08},
252 {0x3839, 0x01},
253 {0x383a, 0x00},
254 {0x383b, 0x08},
255 {0x383c, 0x00},
256 {0x3f0b, 0x00},
257 {0x4001, 0x20},
258 {0x4009, 0x07},
259 {0x4003, 0x10},
260 {0x4010, 0xe0},
261 {0x4016, 0x00},
262 {0x4017, 0x10},
263 {0x4044, 0x02},
264 {0x4304, 0x08},
265 {0x4307, 0x30},
266 {0x4320, 0x80},
267 {0x4322, 0x00},
268 {0x4323, 0x00},
269 {0x4324, 0x00},
270 {0x4325, 0x00},
271 {0x4326, 0x00},
272 {0x4327, 0x00},
273 {0x4328, 0x00},
274 {0x4329, 0x00},
275 {0x432c, 0x03},
276 {0x432d, 0x81},
277 {0x4501, 0x84},
278 {0x4502, 0x40},
279 {0x4503, 0x18},
280 {0x4504, 0x04},
281 {0x4508, 0x02},
282 {0x4601, 0x10},
283 {0x4800, 0x00},
284 {0x4816, 0x52},
285 {0x4837, 0x16},
286 {0x5000, 0x7f},
287 {0x5001, 0x00},
288 {0x5005, 0x38},
289 {0x501e, 0x0d},
290 {0x5040, 0x00},
291 {0x5901, 0x00},
292 {0x3800, 0x00},
293 {0x3801, 0x00},
294 {0x3802, 0x00},
295 {0x3803, 0x00},
296 {0x3804, 0x07},
297 {0x3805, 0x8f},
298 {0x3806, 0x04},
299 {0x3807, 0x47},
300 {0x3808, 0x07},
301 {0x3809, 0x8c},
302 {0x380a, 0x04},
303 {0x380b, 0x44},
304 {0x3810, 0x00},
305 {0x3811, 0x00},
306 {0x3812, 0x00},
307 {0x3813, 0x01},
308 };
309
310 static const struct ov2740_reg mode_1932x1092_regs_180mhz[] = {
311 {0x3000, 0x00},
312 {0x3018, 0x32}, /* 0x32 for 2 lanes, 0x12 for 1 lane */
313 {0x3031, 0x0a},
314 {0x3080, 0x08},
315 {0x3083, 0xB4},
316 {0x3103, 0x00},
317 {0x3104, 0x01},
318 {0x3106, 0x01},
319 {0x3500, 0x00},
320 {0x3501, 0x44},
321 {0x3502, 0x40},
322 {0x3503, 0x88},
323 {0x3507, 0x00},
324 {0x3508, 0x00},
325 {0x3509, 0x80},
326 {0x350c, 0x00},
327 {0x350d, 0x80},
328 {0x3510, 0x00},
329 {0x3511, 0x00},
330 {0x3512, 0x20},
331 {0x3632, 0x00},
332 {0x3633, 0x10},
333 {0x3634, 0x10},
334 {0x3635, 0x10},
335 {0x3645, 0x13},
336 {0x3646, 0x81},
337 {0x3636, 0x10},
338 {0x3651, 0x0a},
339 {0x3656, 0x02},
340 {0x3659, 0x04},
341 {0x365a, 0xda},
342 {0x365b, 0xa2},
343 {0x365c, 0x04},
344 {0x365d, 0x1d},
345 {0x365e, 0x1a},
346 {0x3662, 0xd7},
347 {0x3667, 0x78},
348 {0x3669, 0x0a},
349 {0x366a, 0x92},
350 {0x3700, 0x54},
351 {0x3702, 0x10},
352 {0x3706, 0x42},
353 {0x3709, 0x30},
354 {0x370b, 0xc2},
355 {0x3714, 0x63},
356 {0x3715, 0x01},
357 {0x3716, 0x00},
358 {0x371a, 0x3e},
359 {0x3732, 0x0e},
360 {0x3733, 0x10},
361 {0x375f, 0x0e},
362 {0x3768, 0x30},
363 {0x3769, 0x44},
364 {0x376a, 0x22},
365 {0x377b, 0x20},
366 {0x377c, 0x00},
367 {0x377d, 0x0c},
368 {0x3798, 0x00},
369 {0x37a1, 0x55},
370 {0x37a8, 0x6d},
371 {0x37c2, 0x04},
372 {0x37c5, 0x00},
373 {0x37c8, 0x00},
374 {0x3800, 0x00},
375 {0x3801, 0x00},
376 {0x3802, 0x00},
377 {0x3803, 0x00},
378 {0x3804, 0x07},
379 {0x3805, 0x8f},
380 {0x3806, 0x04},
381 {0x3807, 0x47},
382 {0x3808, 0x07},
383 {0x3809, 0x88},
384 {0x380a, 0x04},
385 {0x380b, 0x40},
386 {0x380c, 0x08},
387 {0x380d, 0x70},
388 {0x380e, 0x04},
389 {0x380f, 0x56},
390 {0x3810, 0x00},
391 {0x3811, 0x04},
392 {0x3812, 0x00},
393 {0x3813, 0x04},
394 {0x3814, 0x01},
395 {0x3815, 0x01},
396 {0x3820, 0x80},
397 {0x3821, 0x46},
398 {0x3822, 0x84},
399 {0x3829, 0x00},
400 {0x382a, 0x01},
401 {0x382b, 0x01},
402 {0x3830, 0x04},
403 {0x3836, 0x01},
404 {0x3837, 0x08},
405 {0x3839, 0x01},
406 {0x383a, 0x00},
407 {0x383b, 0x08},
408 {0x383c, 0x00},
409 {0x3f0b, 0x00},
410 {0x4001, 0x20},
411 {0x4009, 0x07},
412 {0x4003, 0x10},
413 {0x4010, 0xe0},
414 {0x4016, 0x00},
415 {0x4017, 0x10},
416 {0x4044, 0x02},
417 {0x4304, 0x08},
418 {0x4307, 0x30},
419 {0x4320, 0x80},
420 {0x4322, 0x00},
421 {0x4323, 0x00},
422 {0x4324, 0x00},
423 {0x4325, 0x00},
424 {0x4326, 0x00},
425 {0x4327, 0x00},
426 {0x4328, 0x00},
427 {0x4329, 0x00},
428 {0x432c, 0x03},
429 {0x432d, 0x81},
430 {0x4501, 0x84},
431 {0x4502, 0x40},
432 {0x4503, 0x18},
433 {0x4504, 0x04},
434 {0x4508, 0x02},
435 {0x4601, 0x10},
436 {0x4800, 0x00},
437 {0x4816, 0x52},
438 {0x5000, 0x73}, /* 0x7f enable DPC */
439 {0x5001, 0x00},
440 {0x5005, 0x38},
441 {0x501e, 0x0d},
442 {0x5040, 0x00},
443 {0x5901, 0x00},
444 {0x3800, 0x00},
445 {0x3801, 0x00},
446 {0x3802, 0x00},
447 {0x3803, 0x00},
448 {0x3804, 0x07},
449 {0x3805, 0x8f},
450 {0x3806, 0x04},
451 {0x3807, 0x47},
452 {0x3808, 0x07},
453 {0x3809, 0x8c},
454 {0x380a, 0x04},
455 {0x380b, 0x44},
456 {0x3810, 0x00},
457 {0x3811, 0x00},
458 {0x3812, 0x00},
459 {0x3813, 0x01},
460 {0x4003, 0x40}, /* set Black level to 0x40 */
461 };
462
463 static const char * const ov2740_test_pattern_menu[] = {
464 "Disabled",
465 "Color Bar",
466 "Top-Bottom Darker Color Bar",
467 "Right-Left Darker Color Bar",
468 "Bottom-Top Darker Color Bar",
469 };
470
471 static const s64 link_freq_menu_items[] = {
472 OV2740_LINK_FREQ_360MHZ,
473 OV2740_LINK_FREQ_180MHZ,
474 };
475
476 static const struct ov2740_link_freq_config link_freq_configs[] = {
477 [OV2740_LINK_FREQ_360MHZ_INDEX] = {
478 .reg_list = {
479 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
480 .regs = mipi_data_rate_720mbps,
481 }
482 },
483 [OV2740_LINK_FREQ_180MHZ_INDEX] = {
484 .reg_list = {
485 .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),
486 .regs = mipi_data_rate_360mbps,
487 }
488 },
489 };
490
491 static const struct ov2740_mode supported_modes_360mhz[] = {
492 {
493 .width = 1932,
494 .height = 1092,
495 .hts = 2160,
496 .vts_min = 1120,
497 .vts_def = 2186,
498 .vts_max = 32767,
499 .reg_list = {
500 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_360mhz),
501 .regs = mode_1932x1092_regs_360mhz,
502 },
503 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
504 },
505 };
506
507 static const struct ov2740_mode supported_modes_180mhz[] = {
508 {
509 .width = 1932,
510 .height = 1092,
511 .hts = 2160,
512 .vts_min = 1110,
513 .vts_def = 1110,
514 .vts_max = 2047,
515 .reg_list = {
516 .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs_180mhz),
517 .regs = mode_1932x1092_regs_180mhz,
518 },
519 .link_freq_index = OV2740_LINK_FREQ_180MHZ_INDEX,
520 },
521 };
522
523 struct ov2740 {
524 struct v4l2_subdev sd;
525 struct media_pad pad;
526 struct v4l2_ctrl_handler ctrl_handler;
527
528 /* V4L2 Controls */
529 struct v4l2_ctrl *link_freq;
530 struct v4l2_ctrl *pixel_rate;
531 struct v4l2_ctrl *vblank;
532 struct v4l2_ctrl *hblank;
533 struct v4l2_ctrl *exposure;
534
535 /* GPIOs, clocks, regulators */
536 struct gpio_desc *reset_gpio;
537 struct gpio_desc *powerdown_gpio;
538 struct clk *clk;
539 struct regulator_bulk_data supplies[OV2740_NUM_SUPPLIES];
540
541 /* Current mode */
542 const struct ov2740_mode *cur_mode;
543
544 /* NVM data information */
545 struct nvm_data *nvm;
546
547 /* Supported modes */
548 const struct ov2740_mode *supported_modes;
549 int supported_modes_count;
550
551 /* True if the device has been identified */
552 bool identified;
553 };
554
to_ov2740(struct v4l2_subdev * subdev)555 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
556 {
557 return container_of(subdev, struct ov2740, sd);
558 }
559
to_pixel_rate(u32 f_index)560 static u64 to_pixel_rate(u32 f_index)
561 {
562 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
563
564 do_div(pixel_rate, OV2740_RGB_DEPTH);
565
566 return pixel_rate;
567 }
568
ov2740_read_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 * val)569 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
570 {
571 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
572 struct i2c_msg msgs[2];
573 u8 addr_buf[2];
574 u8 data_buf[4] = {0};
575 int ret;
576
577 if (len > sizeof(data_buf))
578 return -EINVAL;
579
580 put_unaligned_be16(reg, addr_buf);
581 msgs[0].addr = client->addr;
582 msgs[0].flags = 0;
583 msgs[0].len = sizeof(addr_buf);
584 msgs[0].buf = addr_buf;
585 msgs[1].addr = client->addr;
586 msgs[1].flags = I2C_M_RD;
587 msgs[1].len = len;
588 msgs[1].buf = &data_buf[sizeof(data_buf) - len];
589
590 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
591 if (ret != ARRAY_SIZE(msgs))
592 return ret < 0 ? ret : -EIO;
593
594 *val = get_unaligned_be32(data_buf);
595
596 return 0;
597 }
598
ov2740_write_reg(struct ov2740 * ov2740,u16 reg,u16 len,u32 val)599 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
600 {
601 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
602 u8 buf[6];
603 int ret;
604
605 if (len > 4)
606 return -EINVAL;
607
608 put_unaligned_be16(reg, buf);
609 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
610
611 ret = i2c_master_send(client, buf, len + 2);
612 if (ret != len + 2)
613 return ret < 0 ? ret : -EIO;
614
615 return 0;
616 }
617
ov2740_write_reg_list(struct ov2740 * ov2740,const struct ov2740_reg_list * r_list)618 static int ov2740_write_reg_list(struct ov2740 *ov2740,
619 const struct ov2740_reg_list *r_list)
620 {
621 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
622 unsigned int i;
623 int ret;
624
625 for (i = 0; i < r_list->num_of_regs; i++) {
626 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
627 r_list->regs[i].val);
628 if (ret) {
629 dev_err_ratelimited(&client->dev,
630 "write reg 0x%4.4x return err = %d\n",
631 r_list->regs[i].address, ret);
632 return ret;
633 }
634 }
635
636 return 0;
637 }
638
ov2740_identify_module(struct ov2740 * ov2740)639 static int ov2740_identify_module(struct ov2740 *ov2740)
640 {
641 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
642 int ret;
643 u32 val;
644
645 if (ov2740->identified)
646 return 0;
647
648 ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
649 if (ret)
650 return ret;
651
652 if (val != OV2740_CHIP_ID) {
653 dev_err(&client->dev, "chip id mismatch: %x != %x\n",
654 OV2740_CHIP_ID, val);
655 return -ENXIO;
656 }
657
658 dev_dbg(&client->dev, "chip id: %x\n", val);
659
660 ov2740->identified = true;
661
662 return 0;
663 }
664
ov2740_update_digital_gain(struct ov2740 * ov2740,u32 d_gain)665 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
666 {
667 int ret;
668
669 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
670 OV2740_GROUP_HOLD_START);
671 if (ret)
672 return ret;
673
674 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
675 if (ret)
676 return ret;
677
678 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
679 if (ret)
680 return ret;
681
682 ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
683 if (ret)
684 return ret;
685
686 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
687 OV2740_GROUP_HOLD_END);
688 if (ret)
689 return ret;
690
691 ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
692 OV2740_GROUP_HOLD_LAUNCH);
693 return ret;
694 }
695
ov2740_test_pattern(struct ov2740 * ov2740,u32 pattern)696 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
697 {
698 if (pattern)
699 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
700 OV2740_TEST_PATTERN_ENABLE;
701
702 return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
703 }
704
ov2740_set_ctrl(struct v4l2_ctrl * ctrl)705 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
706 {
707 struct ov2740 *ov2740 = container_of(ctrl->handler,
708 struct ov2740, ctrl_handler);
709 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
710 s64 exposure_max;
711 int ret;
712
713 /* Propagate change of current control to all related controls */
714 if (ctrl->id == V4L2_CID_VBLANK) {
715 /* Update max exposure while meeting expected vblanking */
716 exposure_max = ov2740->cur_mode->height + ctrl->val -
717 OV2740_EXPOSURE_MAX_MARGIN;
718 __v4l2_ctrl_modify_range(ov2740->exposure,
719 ov2740->exposure->minimum,
720 exposure_max, ov2740->exposure->step,
721 exposure_max);
722 }
723
724 /* V4L2 controls values will be applied only when power is already up */
725 if (!pm_runtime_get_if_in_use(&client->dev))
726 return 0;
727
728 switch (ctrl->id) {
729 case V4L2_CID_ANALOGUE_GAIN:
730 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
731 ctrl->val);
732 break;
733
734 case V4L2_CID_DIGITAL_GAIN:
735 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
736 break;
737
738 case V4L2_CID_EXPOSURE:
739 /* 4 least significant bits of expsoure are fractional part */
740 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
741 ctrl->val << 4);
742 break;
743
744 case V4L2_CID_VBLANK:
745 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
746 ov2740->cur_mode->height + ctrl->val);
747 break;
748
749 case V4L2_CID_TEST_PATTERN:
750 ret = ov2740_test_pattern(ov2740, ctrl->val);
751 break;
752
753 default:
754 ret = -EINVAL;
755 break;
756 }
757
758 pm_runtime_put(&client->dev);
759
760 return ret;
761 }
762
763 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
764 .s_ctrl = ov2740_set_ctrl,
765 };
766
ov2740_init_controls(struct ov2740 * ov2740)767 static int ov2740_init_controls(struct ov2740 *ov2740)
768 {
769 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
770 struct v4l2_ctrl_handler *ctrl_hdlr;
771 const struct ov2740_mode *cur_mode;
772 s64 exposure_max, h_blank, pixel_rate;
773 u32 vblank_min, vblank_max, vblank_default;
774 struct v4l2_fwnode_device_properties props;
775 int size;
776 int ret;
777
778 ctrl_hdlr = &ov2740->ctrl_handler;
779 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
780 if (ret)
781 return ret;
782
783 cur_mode = ov2740->cur_mode;
784 size = ARRAY_SIZE(link_freq_menu_items);
785
786 ov2740->link_freq =
787 v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
788 V4L2_CID_LINK_FREQ, size - 1,
789 ov2740->supported_modes->link_freq_index,
790 link_freq_menu_items);
791 if (ov2740->link_freq)
792 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
793
794 pixel_rate = to_pixel_rate(ov2740->supported_modes->link_freq_index);
795 ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
796 V4L2_CID_PIXEL_RATE, 0,
797 pixel_rate, 1, pixel_rate);
798
799 vblank_min = cur_mode->vts_min - cur_mode->height;
800 vblank_max = cur_mode->vts_max - cur_mode->height;
801 vblank_default = cur_mode->vts_def - cur_mode->height;
802 ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
803 V4L2_CID_VBLANK, vblank_min,
804 vblank_max, 1, vblank_default);
805
806 h_blank = cur_mode->hts - cur_mode->width;
807 ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
808 V4L2_CID_HBLANK, h_blank, h_blank, 1,
809 h_blank);
810 if (ov2740->hblank)
811 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
812
813 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
814 OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
815 OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
816 v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
817 OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
818 OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
819 exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
820 ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
821 V4L2_CID_EXPOSURE,
822 OV2740_EXPOSURE_MIN, exposure_max,
823 OV2740_EXPOSURE_STEP,
824 exposure_max);
825 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
826 V4L2_CID_TEST_PATTERN,
827 ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
828 0, 0, ov2740_test_pattern_menu);
829
830 ret = v4l2_fwnode_device_parse(&client->dev, &props);
831 if (ret)
832 return ret;
833
834 v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov2740_ctrl_ops, &props);
835
836 if (ctrl_hdlr->error) {
837 v4l2_ctrl_handler_free(ctrl_hdlr);
838 return ctrl_hdlr->error;
839 }
840
841 ov2740->sd.ctrl_handler = ctrl_hdlr;
842
843 return 0;
844 }
845
ov2740_update_pad_format(const struct ov2740_mode * mode,struct v4l2_mbus_framefmt * fmt)846 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
847 struct v4l2_mbus_framefmt *fmt)
848 {
849 fmt->width = mode->width;
850 fmt->height = mode->height;
851 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
852 fmt->field = V4L2_FIELD_NONE;
853 }
854
ov2740_load_otp_data(struct nvm_data * nvm)855 static int ov2740_load_otp_data(struct nvm_data *nvm)
856 {
857 struct device *dev = regmap_get_device(nvm->regmap);
858 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
859 u32 isp_ctrl00 = 0;
860 u32 isp_ctrl01 = 0;
861 int ret;
862
863 if (nvm->nvm_buffer)
864 return 0;
865
866 nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
867 if (!nvm->nvm_buffer)
868 return -ENOMEM;
869
870 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
871 if (ret) {
872 dev_err(dev, "failed to read ISP CTRL00\n");
873 goto err;
874 }
875
876 ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
877 if (ret) {
878 dev_err(dev, "failed to read ISP CTRL01\n");
879 goto err;
880 }
881
882 /* Clear bit 5 of ISP CTRL00 */
883 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
884 isp_ctrl00 & ~BIT(5));
885 if (ret) {
886 dev_err(dev, "failed to set ISP CTRL00\n");
887 goto err;
888 }
889
890 /* Clear bit 7 of ISP CTRL01 */
891 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
892 isp_ctrl01 & ~BIT(7));
893 if (ret) {
894 dev_err(dev, "failed to set ISP CTRL01\n");
895 goto err;
896 }
897
898 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
899 OV2740_MODE_STREAMING);
900 if (ret) {
901 dev_err(dev, "failed to set streaming mode\n");
902 goto err;
903 }
904
905 /*
906 * Users are not allowed to access OTP-related registers and memory
907 * during the 20 ms period after streaming starts (0x100 = 0x01).
908 */
909 msleep(20);
910
911 ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
912 nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
913 if (ret) {
914 dev_err(dev, "failed to read OTP data, ret %d\n", ret);
915 goto err;
916 }
917
918 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
919 OV2740_MODE_STANDBY);
920 if (ret) {
921 dev_err(dev, "failed to set streaming mode\n");
922 goto err;
923 }
924
925 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
926 if (ret) {
927 dev_err(dev, "failed to set ISP CTRL01\n");
928 goto err;
929 }
930
931 ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
932 if (ret) {
933 dev_err(dev, "failed to set ISP CTRL00\n");
934 goto err;
935 }
936
937 return 0;
938 err:
939 kfree(nvm->nvm_buffer);
940 nvm->nvm_buffer = NULL;
941
942 return ret;
943 }
944
ov2740_start_streaming(struct ov2740 * ov2740)945 static int ov2740_start_streaming(struct ov2740 *ov2740)
946 {
947 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
948 const struct ov2740_reg_list *reg_list;
949 int link_freq_index;
950 int ret;
951
952 ret = ov2740_identify_module(ov2740);
953 if (ret)
954 return ret;
955
956 if (ov2740->nvm)
957 ov2740_load_otp_data(ov2740->nvm);
958
959 /* Reset the sensor */
960 ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);
961 if (ret) {
962 dev_err(&client->dev, "failed to reset\n");
963 return ret;
964 }
965
966 usleep_range(10000, 15000);
967
968 link_freq_index = ov2740->cur_mode->link_freq_index;
969 reg_list = &link_freq_configs[link_freq_index].reg_list;
970 ret = ov2740_write_reg_list(ov2740, reg_list);
971 if (ret) {
972 dev_err(&client->dev, "failed to set plls\n");
973 return ret;
974 }
975
976 reg_list = &ov2740->cur_mode->reg_list;
977 ret = ov2740_write_reg_list(ov2740, reg_list);
978 if (ret) {
979 dev_err(&client->dev, "failed to set mode\n");
980 return ret;
981 }
982
983 ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
984 if (ret)
985 return ret;
986
987 ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
988 OV2740_MODE_STREAMING);
989 if (ret)
990 dev_err(&client->dev, "failed to start streaming\n");
991
992 return ret;
993 }
994
ov2740_stop_streaming(struct ov2740 * ov2740)995 static void ov2740_stop_streaming(struct ov2740 *ov2740)
996 {
997 struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
998
999 if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
1000 OV2740_MODE_STANDBY))
1001 dev_err(&client->dev, "failed to stop streaming\n");
1002 }
1003
ov2740_set_stream(struct v4l2_subdev * sd,int enable)1004 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
1005 {
1006 struct ov2740 *ov2740 = to_ov2740(sd);
1007 struct i2c_client *client = v4l2_get_subdevdata(sd);
1008 struct v4l2_subdev_state *sd_state;
1009 int ret = 0;
1010
1011 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
1012
1013 if (enable) {
1014 ret = pm_runtime_resume_and_get(&client->dev);
1015 if (ret < 0)
1016 goto out_unlock;
1017
1018 ret = ov2740_start_streaming(ov2740);
1019 if (ret) {
1020 enable = 0;
1021 ov2740_stop_streaming(ov2740);
1022 pm_runtime_put(&client->dev);
1023 }
1024 } else {
1025 ov2740_stop_streaming(ov2740);
1026 pm_runtime_put(&client->dev);
1027 }
1028
1029 out_unlock:
1030 v4l2_subdev_unlock_state(sd_state);
1031
1032 return ret;
1033 }
1034
ov2740_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1035 static int ov2740_set_format(struct v4l2_subdev *sd,
1036 struct v4l2_subdev_state *sd_state,
1037 struct v4l2_subdev_format *fmt)
1038 {
1039 struct ov2740 *ov2740 = to_ov2740(sd);
1040 const struct ov2740_mode *mode;
1041 s32 vblank_def, h_blank;
1042
1043 mode = v4l2_find_nearest_size(ov2740->supported_modes,
1044 ov2740->supported_modes_count,
1045 width, height,
1046 fmt->format.width, fmt->format.height);
1047
1048 ov2740_update_pad_format(mode, &fmt->format);
1049 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
1050
1051 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1052 return 0;
1053
1054 ov2740->cur_mode = mode;
1055 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
1056 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
1057 to_pixel_rate(mode->link_freq_index));
1058
1059 /* Update limits and set FPS to default */
1060 vblank_def = mode->vts_def - mode->height;
1061 __v4l2_ctrl_modify_range(ov2740->vblank,
1062 mode->vts_min - mode->height,
1063 mode->vts_max - mode->height, 1, vblank_def);
1064 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
1065 h_blank = mode->hts - mode->width;
1066 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1, h_blank);
1067
1068 return 0;
1069 }
1070
ov2740_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1071 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
1072 struct v4l2_subdev_state *sd_state,
1073 struct v4l2_subdev_mbus_code_enum *code)
1074 {
1075 if (code->index > 0)
1076 return -EINVAL;
1077
1078 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1079
1080 return 0;
1081 }
1082
ov2740_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1083 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
1084 struct v4l2_subdev_state *sd_state,
1085 struct v4l2_subdev_frame_size_enum *fse)
1086 {
1087 struct ov2740 *ov2740 = to_ov2740(sd);
1088 const struct ov2740_mode *supported_modes = ov2740->supported_modes;
1089
1090 if (fse->index >= ov2740->supported_modes_count)
1091 return -EINVAL;
1092
1093 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1094 return -EINVAL;
1095
1096 fse->min_width = supported_modes[fse->index].width;
1097 fse->max_width = fse->min_width;
1098 fse->min_height = supported_modes[fse->index].height;
1099 fse->max_height = fse->min_height;
1100
1101 return 0;
1102 }
1103
ov2740_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state)1104 static int ov2740_init_state(struct v4l2_subdev *sd,
1105 struct v4l2_subdev_state *sd_state)
1106 {
1107 struct ov2740 *ov2740 = to_ov2740(sd);
1108
1109 ov2740_update_pad_format(&ov2740->supported_modes[0],
1110 v4l2_subdev_state_get_format(sd_state, 0));
1111 return 0;
1112 }
1113
1114 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
1115 .s_stream = ov2740_set_stream,
1116 };
1117
1118 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
1119 .get_fmt = v4l2_subdev_get_fmt,
1120 .set_fmt = ov2740_set_format,
1121 .enum_mbus_code = ov2740_enum_mbus_code,
1122 .enum_frame_size = ov2740_enum_frame_size,
1123 };
1124
1125 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
1126 .video = &ov2740_video_ops,
1127 .pad = &ov2740_pad_ops,
1128 };
1129
1130 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
1131 .init_state = ov2740_init_state,
1132 };
1133
1134 static const struct media_entity_operations ov2740_subdev_entity_ops = {
1135 .link_validate = v4l2_subdev_link_validate,
1136 };
1137
ov2740_check_hwcfg(struct device * dev)1138 static int ov2740_check_hwcfg(struct device *dev)
1139 {
1140 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1141 struct ov2740 *ov2740 = to_ov2740(sd);
1142 struct fwnode_handle *ep;
1143 struct fwnode_handle *fwnode = dev_fwnode(dev);
1144 struct v4l2_fwnode_endpoint bus_cfg = {
1145 .bus_type = V4L2_MBUS_CSI2_DPHY
1146 };
1147 u32 mclk;
1148 int ret;
1149 unsigned int i, j;
1150
1151 /*
1152 * Sometimes the fwnode graph is initialized by the bridge driver,
1153 * wait for this.
1154 */
1155 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1156 if (!ep)
1157 return dev_err_probe(dev, -EPROBE_DEFER,
1158 "waiting for fwnode graph endpoint\n");
1159
1160 ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1161 if (ret) {
1162 fwnode_handle_put(ep);
1163 return dev_err_probe(dev, ret,
1164 "reading clock-frequency property\n");
1165 }
1166
1167 if (mclk != OV2740_MCLK) {
1168 fwnode_handle_put(ep);
1169 return dev_err_probe(dev, -EINVAL,
1170 "external clock %d is not supported\n",
1171 mclk);
1172 }
1173
1174 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1175 fwnode_handle_put(ep);
1176 if (ret)
1177 return dev_err_probe(dev, ret, "parsing endpoint failed\n");
1178
1179 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1180 ret = dev_err_probe(dev, -EINVAL,
1181 "number of CSI2 data lanes %d is not supported\n",
1182 bus_cfg.bus.mipi_csi2.num_data_lanes);
1183 goto check_hwcfg_error;
1184 }
1185
1186 if (!bus_cfg.nr_of_link_frequencies) {
1187 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n");
1188 goto check_hwcfg_error;
1189 }
1190
1191 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1192 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1193 if (link_freq_menu_items[i] ==
1194 bus_cfg.link_frequencies[j])
1195 break;
1196 }
1197
1198 if (j == bus_cfg.nr_of_link_frequencies)
1199 continue;
1200
1201 switch (i) {
1202 case OV2740_LINK_FREQ_360MHZ_INDEX:
1203 ov2740->supported_modes = supported_modes_360mhz;
1204 ov2740->supported_modes_count =
1205 ARRAY_SIZE(supported_modes_360mhz);
1206 break;
1207 case OV2740_LINK_FREQ_180MHZ_INDEX:
1208 ov2740->supported_modes = supported_modes_180mhz;
1209 ov2740->supported_modes_count =
1210 ARRAY_SIZE(supported_modes_180mhz);
1211 break;
1212 }
1213
1214 break; /* Prefer modes from first available link-freq */
1215 }
1216
1217 if (!ov2740->supported_modes)
1218 ret = dev_err_probe(dev, -EINVAL,
1219 "no supported link frequencies\n");
1220
1221 check_hwcfg_error:
1222 v4l2_fwnode_endpoint_free(&bus_cfg);
1223
1224 return ret;
1225 }
1226
ov2740_remove(struct i2c_client * client)1227 static void ov2740_remove(struct i2c_client *client)
1228 {
1229 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1230
1231 v4l2_async_unregister_subdev(sd);
1232 media_entity_cleanup(&sd->entity);
1233 v4l2_subdev_cleanup(sd);
1234 v4l2_ctrl_handler_free(sd->ctrl_handler);
1235 pm_runtime_disable(&client->dev);
1236 }
1237
ov2740_nvmem_read(void * priv,unsigned int off,void * val,size_t count)1238 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1239 size_t count)
1240 {
1241 struct nvm_data *nvm = priv;
1242 struct device *dev = regmap_get_device(nvm->regmap);
1243 struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
1244 struct v4l2_subdev_state *sd_state;
1245 int ret = 0;
1246
1247 /* Serialise sensor access */
1248 sd_state = v4l2_subdev_lock_and_get_active_state(&ov2740->sd);
1249
1250 if (nvm->nvm_buffer) {
1251 memcpy(val, nvm->nvm_buffer + off, count);
1252 goto exit;
1253 }
1254
1255 ret = pm_runtime_resume_and_get(dev);
1256 if (ret < 0) {
1257 goto exit;
1258 }
1259
1260 ret = ov2740_load_otp_data(nvm);
1261 if (!ret)
1262 memcpy(val, nvm->nvm_buffer + off, count);
1263
1264 pm_runtime_put(dev);
1265 exit:
1266 v4l2_subdev_unlock_state(sd_state);
1267 return ret;
1268 }
1269
ov2740_register_nvmem(struct i2c_client * client,struct ov2740 * ov2740)1270 static int ov2740_register_nvmem(struct i2c_client *client,
1271 struct ov2740 *ov2740)
1272 {
1273 struct nvm_data *nvm;
1274 struct regmap_config regmap_config = { };
1275 struct nvmem_config nvmem_config = { };
1276 struct regmap *regmap;
1277 struct device *dev = &client->dev;
1278
1279 nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1280 if (!nvm)
1281 return -ENOMEM;
1282
1283 regmap_config.val_bits = 8;
1284 regmap_config.reg_bits = 16;
1285 regmap_config.disable_locking = true;
1286 regmap = devm_regmap_init_i2c(client, ®map_config);
1287 if (IS_ERR(regmap))
1288 return PTR_ERR(regmap);
1289
1290 nvm->regmap = regmap;
1291
1292 nvmem_config.name = dev_name(dev);
1293 nvmem_config.dev = dev;
1294 nvmem_config.read_only = true;
1295 nvmem_config.root_only = true;
1296 nvmem_config.owner = THIS_MODULE;
1297 nvmem_config.compat = true;
1298 nvmem_config.base_dev = dev;
1299 nvmem_config.reg_read = ov2740_nvmem_read;
1300 nvmem_config.reg_write = NULL;
1301 nvmem_config.priv = nvm;
1302 nvmem_config.stride = 1;
1303 nvmem_config.word_size = 1;
1304 nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1305
1306 nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1307 if (IS_ERR(nvm->nvmem))
1308 return PTR_ERR(nvm->nvmem);
1309
1310 ov2740->nvm = nvm;
1311 return 0;
1312 }
1313
ov2740_suspend(struct device * dev)1314 static int ov2740_suspend(struct device *dev)
1315 {
1316 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1317 struct ov2740 *ov2740 = to_ov2740(sd);
1318
1319 gpiod_set_value_cansleep(ov2740->reset_gpio, 1);
1320 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 1);
1321 clk_disable_unprepare(ov2740->clk);
1322 regulator_bulk_disable(OV2740_NUM_SUPPLIES, ov2740->supplies);
1323 return 0;
1324 }
1325
ov2740_resume(struct device * dev)1326 static int ov2740_resume(struct device *dev)
1327 {
1328 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1329 struct ov2740 *ov2740 = to_ov2740(sd);
1330 int ret;
1331
1332 ret = regulator_bulk_enable(OV2740_NUM_SUPPLIES, ov2740->supplies);
1333 if (ret)
1334 return ret;
1335
1336 ret = clk_prepare_enable(ov2740->clk);
1337 if (ret) {
1338 regulator_bulk_disable(OV2740_NUM_SUPPLIES, ov2740->supplies);
1339 return ret;
1340 }
1341
1342 gpiod_set_value_cansleep(ov2740->powerdown_gpio, 0);
1343 gpiod_set_value_cansleep(ov2740->reset_gpio, 0);
1344 msleep(20);
1345
1346 return 0;
1347 }
1348
ov2740_probe(struct i2c_client * client)1349 static int ov2740_probe(struct i2c_client *client)
1350 {
1351 struct device *dev = &client->dev;
1352 struct ov2740 *ov2740;
1353 bool full_power;
1354 int i, ret;
1355
1356 ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1357 if (!ov2740)
1358 return -ENOMEM;
1359
1360 v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1361 ov2740->sd.internal_ops = &ov2740_internal_ops;
1362
1363 ret = ov2740_check_hwcfg(dev);
1364 if (ret)
1365 return ret;
1366
1367 ov2740->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1368 if (IS_ERR(ov2740->reset_gpio)) {
1369 return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio),
1370 "failed to get reset GPIO\n");
1371 }
1372
1373 ov2740->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
1374 if (IS_ERR(ov2740->powerdown_gpio)) {
1375 return dev_err_probe(dev, PTR_ERR(ov2740->powerdown_gpio),
1376 "failed to get powerdown GPIO\n");
1377 }
1378
1379 if (ov2740->reset_gpio || ov2740->powerdown_gpio) {
1380 /*
1381 * Ensure reset/powerdown is asserted for at least 20 ms before
1382 * ov2740_resume() deasserts it.
1383 */
1384 msleep(20);
1385 }
1386
1387 ov2740->clk = devm_clk_get_optional(dev, "clk");
1388 if (IS_ERR(ov2740->clk))
1389 return dev_err_probe(dev, PTR_ERR(ov2740->clk),
1390 "failed to get clock\n");
1391
1392 for (i = 0; i < OV2740_NUM_SUPPLIES; i++)
1393 ov2740->supplies[i].supply = ov2740_supply_name[i];
1394
1395 ret = devm_regulator_bulk_get(dev, OV2740_NUM_SUPPLIES, ov2740->supplies);
1396 if (ret)
1397 return dev_err_probe(dev, ret, "failed to get regulators\n");
1398
1399 full_power = acpi_dev_state_d0(&client->dev);
1400 if (full_power) {
1401 /* ACPI does not always clear the reset GPIO / enable the clock */
1402 ret = ov2740_resume(dev);
1403 if (ret)
1404 return dev_err_probe(dev, ret, "failed to power on sensor\n");
1405
1406 ret = ov2740_identify_module(ov2740);
1407 if (ret) {
1408 dev_err_probe(dev, ret, "failed to find sensor\n");
1409 goto probe_error_power_off;
1410 }
1411 }
1412
1413 ov2740->cur_mode = &ov2740->supported_modes[0];
1414 ret = ov2740_init_controls(ov2740);
1415 if (ret) {
1416 dev_err_probe(dev, ret, "failed to init controls\n");
1417 goto probe_error_v4l2_ctrl_handler_free;
1418 }
1419
1420 ov2740->sd.state_lock = ov2740->ctrl_handler.lock;
1421 ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1422 ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1423 ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1424 ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1425 ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1426 if (ret) {
1427 dev_err_probe(dev, ret, "failed to init entity pads\n");
1428 goto probe_error_v4l2_ctrl_handler_free;
1429 }
1430
1431 ret = v4l2_subdev_init_finalize(&ov2740->sd);
1432 if (ret)
1433 goto probe_error_media_entity_cleanup;
1434
1435 /* Set the device's state to active if it's in D0 state. */
1436 if (full_power)
1437 pm_runtime_set_active(&client->dev);
1438 pm_runtime_enable(&client->dev);
1439 pm_runtime_idle(&client->dev);
1440
1441 ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1442 if (ret < 0) {
1443 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
1444 goto probe_error_v4l2_subdev_cleanup;
1445 }
1446
1447 ret = ov2740_register_nvmem(client, ov2740);
1448 if (ret)
1449 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1450
1451 return 0;
1452
1453 probe_error_v4l2_subdev_cleanup:
1454 v4l2_subdev_cleanup(&ov2740->sd);
1455
1456 probe_error_media_entity_cleanup:
1457 media_entity_cleanup(&ov2740->sd.entity);
1458 pm_runtime_disable(&client->dev);
1459 pm_runtime_set_suspended(&client->dev);
1460
1461 probe_error_v4l2_ctrl_handler_free:
1462 v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1463
1464 probe_error_power_off:
1465 if (full_power)
1466 ov2740_suspend(dev);
1467
1468 return ret;
1469 }
1470
1471 static DEFINE_RUNTIME_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume,
1472 NULL);
1473
1474 static const struct acpi_device_id ov2740_acpi_ids[] = {
1475 {"INT3474"},
1476 {}
1477 };
1478
1479 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1480
1481 static struct i2c_driver ov2740_i2c_driver = {
1482 .driver = {
1483 .name = "ov2740",
1484 .acpi_match_table = ov2740_acpi_ids,
1485 .pm = pm_sleep_ptr(&ov2740_pm_ops),
1486 },
1487 .probe = ov2740_probe,
1488 .remove = ov2740_remove,
1489 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1490 };
1491
1492 module_i2c_driver(ov2740_i2c_driver);
1493
1494 MODULE_AUTHOR("Qiu, Tianshu <[email protected]>");
1495 MODULE_AUTHOR("Shawn Tu");
1496 MODULE_AUTHOR("Bingbu Cao <[email protected]>");
1497 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1498 MODULE_LICENSE("GPL v2");
1499