1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * A V4L2 driver for Sony IMX219 cameras.
4 * Copyright (C) 2019, Raspberry Pi (Trading) Ltd
5 *
6 * Based on Sony imx258 camera driver
7 * Copyright (C) 2018 Intel Corporation
8 *
9 * DT / fwnode changes, and regulator / GPIO control taken from imx214 driver
10 * Copyright 2018 Qtechnology A/S
11 *
12 * Flip handling taken from the Sony IMX319 driver.
13 * Copyright (C) 2018 Intel Corporation
14 *
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/i2c.h>
21 #include <linux/minmax.h>
22 #include <linux/module.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regulator/consumer.h>
25
26 #include <media/v4l2-cci.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-device.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
31
32 /* Chip ID */
33 #define IMX219_REG_CHIP_ID CCI_REG16(0x0000)
34 #define IMX219_CHIP_ID 0x0219
35
36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
37 #define IMX219_MODE_STANDBY 0x00
38 #define IMX219_MODE_STREAMING 0x01
39
40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
41 #define IMX219_CSI_2_LANE_MODE 0x01
42 #define IMX219_CSI_4_LANE_MODE 0x03
43
44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
45 #define IMX219_DPHY_CTRL_TIMING_AUTO 0
46 #define IMX219_DPHY_CTRL_TIMING_MANUAL 1
47
48 #define IMX219_REG_EXCK_FREQ CCI_REG16(0x012a)
49 #define IMX219_EXCK_FREQ(n) ((n) * 256) /* n expressed in MHz */
50
51 /* Analog gain control */
52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
53 #define IMX219_ANA_GAIN_MIN 0
54 #define IMX219_ANA_GAIN_MAX 232
55 #define IMX219_ANA_GAIN_STEP 1
56 #define IMX219_ANA_GAIN_DEFAULT 0x0
57
58 /* Digital gain control */
59 #define IMX219_REG_DIGITAL_GAIN CCI_REG16(0x0158)
60 #define IMX219_DGTL_GAIN_MIN 0x0100
61 #define IMX219_DGTL_GAIN_MAX 0x0fff
62 #define IMX219_DGTL_GAIN_DEFAULT 0x0100
63 #define IMX219_DGTL_GAIN_STEP 1
64
65 /* Exposure control */
66 #define IMX219_REG_EXPOSURE CCI_REG16(0x015a)
67 #define IMX219_EXPOSURE_MIN 4
68 #define IMX219_EXPOSURE_STEP 1
69 #define IMX219_EXPOSURE_DEFAULT 0x640
70 #define IMX219_EXPOSURE_MAX 65535
71
72 /* V_TIMING internal */
73 #define IMX219_REG_VTS CCI_REG16(0x0160)
74 #define IMX219_VTS_MAX 0xffff
75
76 #define IMX219_VBLANK_MIN 4
77
78 /* HBLANK control - read only */
79 #define IMX219_PPL_DEFAULT 3448
80
81 #define IMX219_REG_LINE_LENGTH_A CCI_REG16(0x0162)
82 #define IMX219_REG_X_ADD_STA_A CCI_REG16(0x0164)
83 #define IMX219_REG_X_ADD_END_A CCI_REG16(0x0166)
84 #define IMX219_REG_Y_ADD_STA_A CCI_REG16(0x0168)
85 #define IMX219_REG_Y_ADD_END_A CCI_REG16(0x016a)
86 #define IMX219_REG_X_OUTPUT_SIZE CCI_REG16(0x016c)
87 #define IMX219_REG_Y_OUTPUT_SIZE CCI_REG16(0x016e)
88 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
89 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
90 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
91
92 /* Binning Mode */
93 #define IMX219_REG_BINNING_MODE_H CCI_REG8(0x0174)
94 #define IMX219_REG_BINNING_MODE_V CCI_REG8(0x0175)
95 #define IMX219_BINNING_NONE 0x00
96 #define IMX219_BINNING_X2 0x01
97 #define IMX219_BINNING_X2_ANALOG 0x03
98
99 #define IMX219_REG_CSI_DATA_FORMAT_A CCI_REG16(0x018c)
100
101 /* PLL Settings */
102 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
103 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
104 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
105 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
106 #define IMX219_REG_PLL_VT_MPY CCI_REG16(0x0306)
107 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
108 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
109 #define IMX219_REG_PLL_OP_MPY CCI_REG16(0x030c)
110
111 /* Test Pattern Control */
112 #define IMX219_REG_TEST_PATTERN CCI_REG16(0x0600)
113 #define IMX219_TEST_PATTERN_DISABLE 0
114 #define IMX219_TEST_PATTERN_SOLID_COLOR 1
115 #define IMX219_TEST_PATTERN_COLOR_BARS 2
116 #define IMX219_TEST_PATTERN_GREY_COLOR 3
117 #define IMX219_TEST_PATTERN_PN9 4
118
119 /* Test pattern colour components */
120 #define IMX219_REG_TESTP_RED CCI_REG16(0x0602)
121 #define IMX219_REG_TESTP_GREENR CCI_REG16(0x0604)
122 #define IMX219_REG_TESTP_BLUE CCI_REG16(0x0606)
123 #define IMX219_REG_TESTP_GREENB CCI_REG16(0x0608)
124 #define IMX219_TESTP_COLOUR_MIN 0
125 #define IMX219_TESTP_COLOUR_MAX 0x03ff
126 #define IMX219_TESTP_COLOUR_STEP 1
127
128 #define IMX219_REG_TP_WINDOW_WIDTH CCI_REG16(0x0624)
129 #define IMX219_REG_TP_WINDOW_HEIGHT CCI_REG16(0x0626)
130
131 /* External clock frequency is 24.0M */
132 #define IMX219_XCLK_FREQ 24000000
133
134 /* Pixel rate is fixed for all the modes */
135 #define IMX219_PIXEL_RATE 182400000
136 #define IMX219_PIXEL_RATE_4LANE 281600000
137
138 #define IMX219_DEFAULT_LINK_FREQ 456000000
139 #define IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED 363000000
140 #define IMX219_DEFAULT_LINK_FREQ_4LANE 364000000
141
142 /* IMX219 native and active pixel array size. */
143 #define IMX219_NATIVE_WIDTH 3296U
144 #define IMX219_NATIVE_HEIGHT 2480U
145 #define IMX219_PIXEL_ARRAY_LEFT 8U
146 #define IMX219_PIXEL_ARRAY_TOP 8U
147 #define IMX219_PIXEL_ARRAY_WIDTH 3280U
148 #define IMX219_PIXEL_ARRAY_HEIGHT 2464U
149
150 /* Mode : resolution and related config&values */
151 struct imx219_mode {
152 /* Frame width */
153 unsigned int width;
154 /* Frame height */
155 unsigned int height;
156
157 /* V-timing */
158 unsigned int vts_def;
159 };
160
161 static const struct cci_reg_sequence imx219_common_regs[] = {
162 { IMX219_REG_MODE_SELECT, 0x00 }, /* Mode Select */
163
164 /* To Access Addresses 3000-5fff, send the following commands */
165 { CCI_REG8(0x30eb), 0x05 },
166 { CCI_REG8(0x30eb), 0x0c },
167 { CCI_REG8(0x300a), 0xff },
168 { CCI_REG8(0x300b), 0xff },
169 { CCI_REG8(0x30eb), 0x05 },
170 { CCI_REG8(0x30eb), 0x09 },
171
172 /* Undocumented registers */
173 { CCI_REG8(0x455e), 0x00 },
174 { CCI_REG8(0x471e), 0x4b },
175 { CCI_REG8(0x4767), 0x0f },
176 { CCI_REG8(0x4750), 0x14 },
177 { CCI_REG8(0x4540), 0x00 },
178 { CCI_REG8(0x47b4), 0x14 },
179 { CCI_REG8(0x4713), 0x30 },
180 { CCI_REG8(0x478b), 0x10 },
181 { CCI_REG8(0x478f), 0x10 },
182 { CCI_REG8(0x4793), 0x10 },
183 { CCI_REG8(0x4797), 0x0e },
184 { CCI_REG8(0x479b), 0x0e },
185
186 /* Frame Bank Register Group "A" */
187 { IMX219_REG_LINE_LENGTH_A, 3448 },
188 { IMX219_REG_X_ODD_INC_A, 1 },
189 { IMX219_REG_Y_ODD_INC_A, 1 },
190
191 /* Output setup registers */
192 { IMX219_REG_DPHY_CTRL, IMX219_DPHY_CTRL_TIMING_AUTO },
193 { IMX219_REG_EXCK_FREQ, IMX219_EXCK_FREQ(IMX219_XCLK_FREQ / 1000000) },
194 };
195
196 static const struct cci_reg_sequence imx219_2lane_regs[] = {
197 /* PLL Clock Table */
198 { IMX219_REG_VTPXCK_DIV, 5 },
199 { IMX219_REG_VTSYCK_DIV, 1 },
200 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
201 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
202 { IMX219_REG_PLL_VT_MPY, 57 },
203 { IMX219_REG_OPSYCK_DIV, 1 },
204 { IMX219_REG_PLL_OP_MPY, 114 },
205
206 /* 2-Lane CSI Mode */
207 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_2_LANE_MODE },
208 };
209
210 static const struct cci_reg_sequence imx219_4lane_regs[] = {
211 /* PLL Clock Table */
212 { IMX219_REG_VTPXCK_DIV, 5 },
213 { IMX219_REG_VTSYCK_DIV, 1 },
214 { IMX219_REG_PREPLLCK_VT_DIV, 3 }, /* 0x03 = AUTO set */
215 { IMX219_REG_PREPLLCK_OP_DIV, 3 }, /* 0x03 = AUTO set */
216 { IMX219_REG_PLL_VT_MPY, 88 },
217 { IMX219_REG_OPSYCK_DIV, 1 },
218 { IMX219_REG_PLL_OP_MPY, 91 },
219
220 /* 4-Lane CSI Mode */
221 { IMX219_REG_CSI_LANE_MODE, IMX219_CSI_4_LANE_MODE },
222 };
223
224 static const s64 imx219_link_freq_menu[] = {
225 IMX219_DEFAULT_LINK_FREQ,
226 };
227
228 static const s64 imx219_link_freq_4lane_menu[] = {
229 IMX219_DEFAULT_LINK_FREQ_4LANE,
230 /*
231 * This will never be advertised to userspace, but will be used for
232 * v4l2_link_freq_to_bitmap
233 */
234 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED,
235 };
236
237 static const char * const imx219_test_pattern_menu[] = {
238 "Disabled",
239 "Color Bars",
240 "Solid Color",
241 "Grey Color Bars",
242 "PN9"
243 };
244
245 static const int imx219_test_pattern_val[] = {
246 IMX219_TEST_PATTERN_DISABLE,
247 IMX219_TEST_PATTERN_COLOR_BARS,
248 IMX219_TEST_PATTERN_SOLID_COLOR,
249 IMX219_TEST_PATTERN_GREY_COLOR,
250 IMX219_TEST_PATTERN_PN9,
251 };
252
253 /* regulator supplies */
254 static const char * const imx219_supply_name[] = {
255 /* Supplies can be enabled in any order */
256 "VANA", /* Analog (2.8V) supply */
257 "VDIG", /* Digital Core (1.8V) supply */
258 "VDDL", /* IF (1.2V) supply */
259 };
260
261 #define IMX219_NUM_SUPPLIES ARRAY_SIZE(imx219_supply_name)
262
263 /*
264 * The supported formats.
265 * This table MUST contain 4 entries per format, to cover the various flip
266 * combinations in the order
267 * - no flip
268 * - h flip
269 * - v flip
270 * - h&v flips
271 */
272 static const u32 imx219_mbus_formats[] = {
273 MEDIA_BUS_FMT_SRGGB10_1X10,
274 MEDIA_BUS_FMT_SGRBG10_1X10,
275 MEDIA_BUS_FMT_SGBRG10_1X10,
276 MEDIA_BUS_FMT_SBGGR10_1X10,
277
278 MEDIA_BUS_FMT_SRGGB8_1X8,
279 MEDIA_BUS_FMT_SGRBG8_1X8,
280 MEDIA_BUS_FMT_SGBRG8_1X8,
281 MEDIA_BUS_FMT_SBGGR8_1X8,
282 };
283
284 /*
285 * Initialisation delay between XCLR low->high and the moment when the sensor
286 * can start capture (i.e. can leave software stanby) must be not less than:
287 * t4 + max(t5, t6 + <time to initialize the sensor register over I2C>)
288 * where
289 * t4 is fixed, and is max 200uS,
290 * t5 is fixed, and is 6000uS,
291 * t6 depends on the sensor external clock, and is max 32000 clock periods.
292 * As per sensor datasheet, the external clock must be from 6MHz to 27MHz.
293 * So for any acceptable external clock t6 is always within the range of
294 * 1185 to 5333 uS, and is always less than t5.
295 * For this reason this is always safe to wait (t4 + t5) = 6200 uS, then
296 * initialize the sensor over I2C, and then exit the software standby.
297 *
298 * This start-up time can be optimized a bit more, if we start the writes
299 * over I2C after (t4+t6), but before (t4+t5) expires. But then sensor
300 * initialization over I2C may complete before (t4+t5) expires, and we must
301 * ensure that capture is not started before (t4+t5).
302 *
303 * This delay doesn't account for the power supply startup time. If needed,
304 * this should be taken care of via the regulator framework. E.g. in the
305 * case of DT for regulator-fixed one should define the startup-delay-us
306 * property.
307 */
308 #define IMX219_XCLR_MIN_DELAY_US 6200
309 #define IMX219_XCLR_DELAY_RANGE_US 1000
310
311 /* Mode configs */
312 static const struct imx219_mode supported_modes[] = {
313 {
314 /* 8MPix 15fps mode */
315 .width = 3280,
316 .height = 2464,
317 .vts_def = 3526,
318 },
319 {
320 /* 1080P 30fps cropped */
321 .width = 1920,
322 .height = 1080,
323 .vts_def = 1763,
324 },
325 {
326 /* 2x2 binned 30fps mode */
327 .width = 1640,
328 .height = 1232,
329 .vts_def = 1763,
330 },
331 {
332 /* 640x480 30fps mode */
333 .width = 640,
334 .height = 480,
335 .vts_def = 1763,
336 },
337 };
338
339 struct imx219 {
340 struct v4l2_subdev sd;
341 struct media_pad pad;
342
343 struct regmap *regmap;
344 struct clk *xclk; /* system clock to IMX219 */
345 u32 xclk_freq;
346
347 struct gpio_desc *reset_gpio;
348 struct regulator_bulk_data supplies[IMX219_NUM_SUPPLIES];
349
350 struct v4l2_ctrl_handler ctrl_handler;
351 /* V4L2 Controls */
352 struct v4l2_ctrl *pixel_rate;
353 struct v4l2_ctrl *link_freq;
354 struct v4l2_ctrl *exposure;
355 struct v4l2_ctrl *vflip;
356 struct v4l2_ctrl *hflip;
357 struct v4l2_ctrl *vblank;
358 struct v4l2_ctrl *hblank;
359
360 /* Two or Four lanes */
361 u8 lanes;
362 };
363
to_imx219(struct v4l2_subdev * _sd)364 static inline struct imx219 *to_imx219(struct v4l2_subdev *_sd)
365 {
366 return container_of(_sd, struct imx219, sd);
367 }
368
369 /* Get bayer order based on flip setting. */
imx219_get_format_code(struct imx219 * imx219,u32 code)370 static u32 imx219_get_format_code(struct imx219 *imx219, u32 code)
371 {
372 unsigned int i;
373
374 for (i = 0; i < ARRAY_SIZE(imx219_mbus_formats); i++)
375 if (imx219_mbus_formats[i] == code)
376 break;
377
378 if (i >= ARRAY_SIZE(imx219_mbus_formats))
379 i = 0;
380
381 i = (i & ~3) | (imx219->vflip->val ? 2 : 0) |
382 (imx219->hflip->val ? 1 : 0);
383
384 return imx219_mbus_formats[i];
385 }
386
387 /* -----------------------------------------------------------------------------
388 * Controls
389 */
390
imx219_set_ctrl(struct v4l2_ctrl * ctrl)391 static int imx219_set_ctrl(struct v4l2_ctrl *ctrl)
392 {
393 struct imx219 *imx219 =
394 container_of(ctrl->handler, struct imx219, ctrl_handler);
395 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
396 const struct v4l2_mbus_framefmt *format;
397 struct v4l2_subdev_state *state;
398 int ret = 0;
399
400 state = v4l2_subdev_get_locked_active_state(&imx219->sd);
401 format = v4l2_subdev_state_get_format(state, 0);
402
403 if (ctrl->id == V4L2_CID_VBLANK) {
404 int exposure_max, exposure_def;
405
406 /* Update max exposure while meeting expected vblanking */
407 exposure_max = format->height + ctrl->val - 4;
408 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
409 exposure_max : IMX219_EXPOSURE_DEFAULT;
410 __v4l2_ctrl_modify_range(imx219->exposure,
411 imx219->exposure->minimum,
412 exposure_max, imx219->exposure->step,
413 exposure_def);
414 }
415
416 /*
417 * Applying V4L2 control value only happens
418 * when power is up for streaming
419 */
420 if (pm_runtime_get_if_in_use(&client->dev) == 0)
421 return 0;
422
423 switch (ctrl->id) {
424 case V4L2_CID_ANALOGUE_GAIN:
425 cci_write(imx219->regmap, IMX219_REG_ANALOG_GAIN,
426 ctrl->val, &ret);
427 break;
428 case V4L2_CID_EXPOSURE:
429 cci_write(imx219->regmap, IMX219_REG_EXPOSURE,
430 ctrl->val, &ret);
431 break;
432 case V4L2_CID_DIGITAL_GAIN:
433 cci_write(imx219->regmap, IMX219_REG_DIGITAL_GAIN,
434 ctrl->val, &ret);
435 break;
436 case V4L2_CID_TEST_PATTERN:
437 cci_write(imx219->regmap, IMX219_REG_TEST_PATTERN,
438 imx219_test_pattern_val[ctrl->val], &ret);
439 break;
440 case V4L2_CID_HFLIP:
441 case V4L2_CID_VFLIP:
442 cci_write(imx219->regmap, IMX219_REG_ORIENTATION,
443 imx219->hflip->val | imx219->vflip->val << 1, &ret);
444 break;
445 case V4L2_CID_VBLANK:
446 cci_write(imx219->regmap, IMX219_REG_VTS,
447 format->height + ctrl->val, &ret);
448 break;
449 case V4L2_CID_TEST_PATTERN_RED:
450 cci_write(imx219->regmap, IMX219_REG_TESTP_RED,
451 ctrl->val, &ret);
452 break;
453 case V4L2_CID_TEST_PATTERN_GREENR:
454 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENR,
455 ctrl->val, &ret);
456 break;
457 case V4L2_CID_TEST_PATTERN_BLUE:
458 cci_write(imx219->regmap, IMX219_REG_TESTP_BLUE,
459 ctrl->val, &ret);
460 break;
461 case V4L2_CID_TEST_PATTERN_GREENB:
462 cci_write(imx219->regmap, IMX219_REG_TESTP_GREENB,
463 ctrl->val, &ret);
464 break;
465 default:
466 dev_info(&client->dev,
467 "ctrl(id:0x%x,val:0x%x) is not handled\n",
468 ctrl->id, ctrl->val);
469 ret = -EINVAL;
470 break;
471 }
472
473 pm_runtime_put(&client->dev);
474
475 return ret;
476 }
477
478 static const struct v4l2_ctrl_ops imx219_ctrl_ops = {
479 .s_ctrl = imx219_set_ctrl,
480 };
481
imx219_get_pixel_rate(struct imx219 * imx219)482 static unsigned long imx219_get_pixel_rate(struct imx219 *imx219)
483 {
484 return (imx219->lanes == 2) ? IMX219_PIXEL_RATE : IMX219_PIXEL_RATE_4LANE;
485 }
486
487 /* Initialize control handlers */
imx219_init_controls(struct imx219 * imx219)488 static int imx219_init_controls(struct imx219 *imx219)
489 {
490 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
491 const struct imx219_mode *mode = &supported_modes[0];
492 struct v4l2_ctrl_handler *ctrl_hdlr;
493 struct v4l2_fwnode_device_properties props;
494 int exposure_max, exposure_def, hblank;
495 int i, ret;
496
497 ctrl_hdlr = &imx219->ctrl_handler;
498 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 12);
499 if (ret)
500 return ret;
501
502 /* By default, PIXEL_RATE is read only */
503 imx219->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
504 V4L2_CID_PIXEL_RATE,
505 imx219_get_pixel_rate(imx219),
506 imx219_get_pixel_rate(imx219), 1,
507 imx219_get_pixel_rate(imx219));
508
509 imx219->link_freq =
510 v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx219_ctrl_ops,
511 V4L2_CID_LINK_FREQ,
512 ARRAY_SIZE(imx219_link_freq_menu) - 1, 0,
513 (imx219->lanes == 2) ? imx219_link_freq_menu :
514 imx219_link_freq_4lane_menu);
515 if (imx219->link_freq)
516 imx219->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
517
518 /* Initial vblank/hblank/exposure parameters based on current mode */
519 imx219->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
520 V4L2_CID_VBLANK, IMX219_VBLANK_MIN,
521 IMX219_VTS_MAX - mode->height, 1,
522 mode->vts_def - mode->height);
523 hblank = IMX219_PPL_DEFAULT - mode->width;
524 imx219->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
525 V4L2_CID_HBLANK, hblank, hblank,
526 1, hblank);
527 if (imx219->hblank)
528 imx219->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
529 exposure_max = mode->vts_def - 4;
530 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
531 exposure_max : IMX219_EXPOSURE_DEFAULT;
532 imx219->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
533 V4L2_CID_EXPOSURE,
534 IMX219_EXPOSURE_MIN, exposure_max,
535 IMX219_EXPOSURE_STEP,
536 exposure_def);
537
538 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
539 IMX219_ANA_GAIN_MIN, IMX219_ANA_GAIN_MAX,
540 IMX219_ANA_GAIN_STEP, IMX219_ANA_GAIN_DEFAULT);
541
542 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
543 IMX219_DGTL_GAIN_MIN, IMX219_DGTL_GAIN_MAX,
544 IMX219_DGTL_GAIN_STEP, IMX219_DGTL_GAIN_DEFAULT);
545
546 imx219->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
547 V4L2_CID_HFLIP, 0, 1, 1, 0);
548 if (imx219->hflip)
549 imx219->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
550
551 imx219->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
552 V4L2_CID_VFLIP, 0, 1, 1, 0);
553 if (imx219->vflip)
554 imx219->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
555
556 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx219_ctrl_ops,
557 V4L2_CID_TEST_PATTERN,
558 ARRAY_SIZE(imx219_test_pattern_menu) - 1,
559 0, 0, imx219_test_pattern_menu);
560 for (i = 0; i < 4; i++) {
561 /*
562 * The assumption is that
563 * V4L2_CID_TEST_PATTERN_GREENR == V4L2_CID_TEST_PATTERN_RED + 1
564 * V4L2_CID_TEST_PATTERN_BLUE == V4L2_CID_TEST_PATTERN_RED + 2
565 * V4L2_CID_TEST_PATTERN_GREENB == V4L2_CID_TEST_PATTERN_RED + 3
566 */
567 v4l2_ctrl_new_std(ctrl_hdlr, &imx219_ctrl_ops,
568 V4L2_CID_TEST_PATTERN_RED + i,
569 IMX219_TESTP_COLOUR_MIN,
570 IMX219_TESTP_COLOUR_MAX,
571 IMX219_TESTP_COLOUR_STEP,
572 IMX219_TESTP_COLOUR_MAX);
573 /* The "Solid color" pattern is white by default */
574 }
575
576 if (ctrl_hdlr->error) {
577 ret = ctrl_hdlr->error;
578 dev_err_probe(&client->dev, ret, "Control init failed\n");
579 goto error;
580 }
581
582 ret = v4l2_fwnode_device_parse(&client->dev, &props);
583 if (ret)
584 goto error;
585
586 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx219_ctrl_ops,
587 &props);
588 if (ret)
589 goto error;
590
591 imx219->sd.ctrl_handler = ctrl_hdlr;
592
593 return 0;
594
595 error:
596 v4l2_ctrl_handler_free(ctrl_hdlr);
597
598 return ret;
599 }
600
imx219_free_controls(struct imx219 * imx219)601 static void imx219_free_controls(struct imx219 *imx219)
602 {
603 v4l2_ctrl_handler_free(imx219->sd.ctrl_handler);
604 }
605
606 /* -----------------------------------------------------------------------------
607 * Subdev operations
608 */
609
imx219_set_framefmt(struct imx219 * imx219,struct v4l2_subdev_state * state)610 static int imx219_set_framefmt(struct imx219 *imx219,
611 struct v4l2_subdev_state *state)
612 {
613 const struct v4l2_mbus_framefmt *format;
614 const struct v4l2_rect *crop;
615 unsigned int bpp;
616 u64 bin_h, bin_v;
617 int ret = 0;
618
619 format = v4l2_subdev_state_get_format(state, 0);
620 crop = v4l2_subdev_state_get_crop(state, 0);
621
622 switch (format->code) {
623 case MEDIA_BUS_FMT_SRGGB8_1X8:
624 case MEDIA_BUS_FMT_SGRBG8_1X8:
625 case MEDIA_BUS_FMT_SGBRG8_1X8:
626 case MEDIA_BUS_FMT_SBGGR8_1X8:
627 bpp = 8;
628 break;
629
630 case MEDIA_BUS_FMT_SRGGB10_1X10:
631 case MEDIA_BUS_FMT_SGRBG10_1X10:
632 case MEDIA_BUS_FMT_SGBRG10_1X10:
633 case MEDIA_BUS_FMT_SBGGR10_1X10:
634 default:
635 bpp = 10;
636 break;
637 }
638
639 cci_write(imx219->regmap, IMX219_REG_X_ADD_STA_A,
640 crop->left - IMX219_PIXEL_ARRAY_LEFT, &ret);
641 cci_write(imx219->regmap, IMX219_REG_X_ADD_END_A,
642 crop->left - IMX219_PIXEL_ARRAY_LEFT + crop->width - 1, &ret);
643 cci_write(imx219->regmap, IMX219_REG_Y_ADD_STA_A,
644 crop->top - IMX219_PIXEL_ARRAY_TOP, &ret);
645 cci_write(imx219->regmap, IMX219_REG_Y_ADD_END_A,
646 crop->top - IMX219_PIXEL_ARRAY_TOP + crop->height - 1, &ret);
647
648 switch (crop->width / format->width) {
649 case 1:
650 default:
651 bin_h = IMX219_BINNING_NONE;
652 break;
653 case 2:
654 bin_h = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
655 break;
656 }
657
658 switch (crop->height / format->height) {
659 case 1:
660 default:
661 bin_v = IMX219_BINNING_NONE;
662 break;
663 case 2:
664 bin_v = bpp == 8 ? IMX219_BINNING_X2_ANALOG : IMX219_BINNING_X2;
665 break;
666 }
667
668 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_H, bin_h, &ret);
669 cci_write(imx219->regmap, IMX219_REG_BINNING_MODE_V, bin_v, &ret);
670
671 cci_write(imx219->regmap, IMX219_REG_X_OUTPUT_SIZE,
672 format->width, &ret);
673 cci_write(imx219->regmap, IMX219_REG_Y_OUTPUT_SIZE,
674 format->height, &ret);
675
676 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_WIDTH,
677 format->width, &ret);
678 cci_write(imx219->regmap, IMX219_REG_TP_WINDOW_HEIGHT,
679 format->height, &ret);
680
681 cci_write(imx219->regmap, IMX219_REG_CSI_DATA_FORMAT_A,
682 (bpp << 8) | bpp, &ret);
683 cci_write(imx219->regmap, IMX219_REG_OPPXCK_DIV, bpp, &ret);
684
685 return ret;
686 }
687
imx219_configure_lanes(struct imx219 * imx219)688 static int imx219_configure_lanes(struct imx219 *imx219)
689 {
690 /* Write the appropriate PLL settings for the number of MIPI lanes */
691 return cci_multi_reg_write(imx219->regmap,
692 imx219->lanes == 2 ? imx219_2lane_regs : imx219_4lane_regs,
693 imx219->lanes == 2 ? ARRAY_SIZE(imx219_2lane_regs) :
694 ARRAY_SIZE(imx219_4lane_regs), NULL);
695 };
696
imx219_start_streaming(struct imx219 * imx219,struct v4l2_subdev_state * state)697 static int imx219_start_streaming(struct imx219 *imx219,
698 struct v4l2_subdev_state *state)
699 {
700 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
701 int ret;
702
703 ret = pm_runtime_resume_and_get(&client->dev);
704 if (ret < 0)
705 return ret;
706
707 /* Send all registers that are common to all modes */
708 ret = cci_multi_reg_write(imx219->regmap, imx219_common_regs,
709 ARRAY_SIZE(imx219_common_regs), NULL);
710 if (ret) {
711 dev_err(&client->dev, "%s failed to send mfg header\n", __func__);
712 goto err_rpm_put;
713 }
714
715 /* Configure two or four Lane mode */
716 ret = imx219_configure_lanes(imx219);
717 if (ret) {
718 dev_err(&client->dev, "%s failed to configure lanes\n", __func__);
719 goto err_rpm_put;
720 }
721
722 /* Apply format and crop settings. */
723 ret = imx219_set_framefmt(imx219, state);
724 if (ret) {
725 dev_err(&client->dev, "%s failed to set frame format: %d\n",
726 __func__, ret);
727 goto err_rpm_put;
728 }
729
730 /* Apply customized values from user */
731 ret = __v4l2_ctrl_handler_setup(imx219->sd.ctrl_handler);
732 if (ret)
733 goto err_rpm_put;
734
735 /* set stream on register */
736 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
737 IMX219_MODE_STREAMING, NULL);
738 if (ret)
739 goto err_rpm_put;
740
741 /* vflip and hflip cannot change during streaming */
742 __v4l2_ctrl_grab(imx219->vflip, true);
743 __v4l2_ctrl_grab(imx219->hflip, true);
744
745 return 0;
746
747 err_rpm_put:
748 pm_runtime_put(&client->dev);
749 return ret;
750 }
751
imx219_stop_streaming(struct imx219 * imx219)752 static void imx219_stop_streaming(struct imx219 *imx219)
753 {
754 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
755 int ret;
756
757 /* set stream off register */
758 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
759 IMX219_MODE_STANDBY, NULL);
760 if (ret)
761 dev_err(&client->dev, "%s failed to set stream\n", __func__);
762
763 __v4l2_ctrl_grab(imx219->vflip, false);
764 __v4l2_ctrl_grab(imx219->hflip, false);
765
766 pm_runtime_put(&client->dev);
767 }
768
imx219_set_stream(struct v4l2_subdev * sd,int enable)769 static int imx219_set_stream(struct v4l2_subdev *sd, int enable)
770 {
771 struct imx219 *imx219 = to_imx219(sd);
772 struct v4l2_subdev_state *state;
773 int ret = 0;
774
775 state = v4l2_subdev_lock_and_get_active_state(sd);
776
777 if (enable)
778 ret = imx219_start_streaming(imx219, state);
779 else
780 imx219_stop_streaming(imx219);
781
782 v4l2_subdev_unlock_state(state);
783 return ret;
784 }
785
imx219_update_pad_format(struct imx219 * imx219,const struct imx219_mode * mode,struct v4l2_mbus_framefmt * fmt,u32 code)786 static void imx219_update_pad_format(struct imx219 *imx219,
787 const struct imx219_mode *mode,
788 struct v4l2_mbus_framefmt *fmt, u32 code)
789 {
790 /* Bayer order varies with flips */
791 fmt->code = imx219_get_format_code(imx219, code);
792 fmt->width = mode->width;
793 fmt->height = mode->height;
794 fmt->field = V4L2_FIELD_NONE;
795 fmt->colorspace = V4L2_COLORSPACE_RAW;
796 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
797 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
798 fmt->xfer_func = V4L2_XFER_FUNC_NONE;
799 }
800
imx219_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_mbus_code_enum * code)801 static int imx219_enum_mbus_code(struct v4l2_subdev *sd,
802 struct v4l2_subdev_state *state,
803 struct v4l2_subdev_mbus_code_enum *code)
804 {
805 struct imx219 *imx219 = to_imx219(sd);
806
807 if (code->index >= (ARRAY_SIZE(imx219_mbus_formats) / 4))
808 return -EINVAL;
809
810 code->code = imx219_get_format_code(imx219, imx219_mbus_formats[code->index * 4]);
811
812 return 0;
813 }
814
imx219_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_frame_size_enum * fse)815 static int imx219_enum_frame_size(struct v4l2_subdev *sd,
816 struct v4l2_subdev_state *state,
817 struct v4l2_subdev_frame_size_enum *fse)
818 {
819 struct imx219 *imx219 = to_imx219(sd);
820 u32 code;
821
822 if (fse->index >= ARRAY_SIZE(supported_modes))
823 return -EINVAL;
824
825 code = imx219_get_format_code(imx219, fse->code);
826 if (fse->code != code)
827 return -EINVAL;
828
829 fse->min_width = supported_modes[fse->index].width;
830 fse->max_width = fse->min_width;
831 fse->min_height = supported_modes[fse->index].height;
832 fse->max_height = fse->min_height;
833
834 return 0;
835 }
836
imx219_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_format * fmt)837 static int imx219_set_pad_format(struct v4l2_subdev *sd,
838 struct v4l2_subdev_state *state,
839 struct v4l2_subdev_format *fmt)
840 {
841 struct imx219 *imx219 = to_imx219(sd);
842 const struct imx219_mode *mode;
843 struct v4l2_mbus_framefmt *format;
844 struct v4l2_rect *crop;
845 unsigned int bin_h, bin_v;
846
847 mode = v4l2_find_nearest_size(supported_modes,
848 ARRAY_SIZE(supported_modes),
849 width, height,
850 fmt->format.width, fmt->format.height);
851
852 imx219_update_pad_format(imx219, mode, &fmt->format, fmt->format.code);
853
854 format = v4l2_subdev_state_get_format(state, 0);
855 *format = fmt->format;
856
857 /*
858 * Use binning to maximize the crop rectangle size, and centre it in the
859 * sensor.
860 */
861 bin_h = min(IMX219_PIXEL_ARRAY_WIDTH / format->width, 2U);
862 bin_v = min(IMX219_PIXEL_ARRAY_HEIGHT / format->height, 2U);
863
864 crop = v4l2_subdev_state_get_crop(state, 0);
865 crop->width = format->width * bin_h;
866 crop->height = format->height * bin_v;
867 crop->left = (IMX219_NATIVE_WIDTH - crop->width) / 2;
868 crop->top = (IMX219_NATIVE_HEIGHT - crop->height) / 2;
869
870 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
871 int exposure_max;
872 int exposure_def;
873 int hblank;
874
875 /* Update limits and set FPS to default */
876 __v4l2_ctrl_modify_range(imx219->vblank, IMX219_VBLANK_MIN,
877 IMX219_VTS_MAX - mode->height, 1,
878 mode->vts_def - mode->height);
879 __v4l2_ctrl_s_ctrl(imx219->vblank,
880 mode->vts_def - mode->height);
881 /* Update max exposure while meeting expected vblanking */
882 exposure_max = mode->vts_def - 4;
883 exposure_def = (exposure_max < IMX219_EXPOSURE_DEFAULT) ?
884 exposure_max : IMX219_EXPOSURE_DEFAULT;
885 __v4l2_ctrl_modify_range(imx219->exposure,
886 imx219->exposure->minimum,
887 exposure_max, imx219->exposure->step,
888 exposure_def);
889 /*
890 * Currently PPL is fixed to IMX219_PPL_DEFAULT, so hblank
891 * depends on mode->width only, and is not changeble in any
892 * way other than changing the mode.
893 */
894 hblank = IMX219_PPL_DEFAULT - mode->width;
895 __v4l2_ctrl_modify_range(imx219->hblank, hblank, hblank, 1,
896 hblank);
897 }
898
899 return 0;
900 }
901
imx219_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_selection * sel)902 static int imx219_get_selection(struct v4l2_subdev *sd,
903 struct v4l2_subdev_state *state,
904 struct v4l2_subdev_selection *sel)
905 {
906 switch (sel->target) {
907 case V4L2_SEL_TGT_CROP: {
908 sel->r = *v4l2_subdev_state_get_crop(state, 0);
909 return 0;
910 }
911
912 case V4L2_SEL_TGT_NATIVE_SIZE:
913 sel->r.top = 0;
914 sel->r.left = 0;
915 sel->r.width = IMX219_NATIVE_WIDTH;
916 sel->r.height = IMX219_NATIVE_HEIGHT;
917
918 return 0;
919
920 case V4L2_SEL_TGT_CROP_DEFAULT:
921 case V4L2_SEL_TGT_CROP_BOUNDS:
922 sel->r.top = IMX219_PIXEL_ARRAY_TOP;
923 sel->r.left = IMX219_PIXEL_ARRAY_LEFT;
924 sel->r.width = IMX219_PIXEL_ARRAY_WIDTH;
925 sel->r.height = IMX219_PIXEL_ARRAY_HEIGHT;
926
927 return 0;
928 }
929
930 return -EINVAL;
931 }
932
imx219_init_state(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)933 static int imx219_init_state(struct v4l2_subdev *sd,
934 struct v4l2_subdev_state *state)
935 {
936 struct v4l2_subdev_format fmt = {
937 .which = V4L2_SUBDEV_FORMAT_TRY,
938 .pad = 0,
939 .format = {
940 .code = MEDIA_BUS_FMT_SRGGB10_1X10,
941 .width = supported_modes[0].width,
942 .height = supported_modes[0].height,
943 },
944 };
945
946 imx219_set_pad_format(sd, state, &fmt);
947
948 return 0;
949 }
950
951 static const struct v4l2_subdev_video_ops imx219_video_ops = {
952 .s_stream = imx219_set_stream,
953 };
954
955 static const struct v4l2_subdev_pad_ops imx219_pad_ops = {
956 .enum_mbus_code = imx219_enum_mbus_code,
957 .get_fmt = v4l2_subdev_get_fmt,
958 .set_fmt = imx219_set_pad_format,
959 .get_selection = imx219_get_selection,
960 .enum_frame_size = imx219_enum_frame_size,
961 };
962
963 static const struct v4l2_subdev_ops imx219_subdev_ops = {
964 .video = &imx219_video_ops,
965 .pad = &imx219_pad_ops,
966 };
967
968 static const struct v4l2_subdev_internal_ops imx219_internal_ops = {
969 .init_state = imx219_init_state,
970 };
971
972 /* -----------------------------------------------------------------------------
973 * Power management
974 */
975
imx219_power_on(struct device * dev)976 static int imx219_power_on(struct device *dev)
977 {
978 struct v4l2_subdev *sd = dev_get_drvdata(dev);
979 struct imx219 *imx219 = to_imx219(sd);
980 int ret;
981
982 ret = regulator_bulk_enable(IMX219_NUM_SUPPLIES,
983 imx219->supplies);
984 if (ret) {
985 dev_err(dev, "%s: failed to enable regulators\n",
986 __func__);
987 return ret;
988 }
989
990 ret = clk_prepare_enable(imx219->xclk);
991 if (ret) {
992 dev_err(dev, "%s: failed to enable clock\n",
993 __func__);
994 goto reg_off;
995 }
996
997 gpiod_set_value_cansleep(imx219->reset_gpio, 1);
998 usleep_range(IMX219_XCLR_MIN_DELAY_US,
999 IMX219_XCLR_MIN_DELAY_US + IMX219_XCLR_DELAY_RANGE_US);
1000
1001 return 0;
1002
1003 reg_off:
1004 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1005
1006 return ret;
1007 }
1008
imx219_power_off(struct device * dev)1009 static int imx219_power_off(struct device *dev)
1010 {
1011 struct v4l2_subdev *sd = dev_get_drvdata(dev);
1012 struct imx219 *imx219 = to_imx219(sd);
1013
1014 gpiod_set_value_cansleep(imx219->reset_gpio, 0);
1015 regulator_bulk_disable(IMX219_NUM_SUPPLIES, imx219->supplies);
1016 clk_disable_unprepare(imx219->xclk);
1017
1018 return 0;
1019 }
1020
1021 /* -----------------------------------------------------------------------------
1022 * Probe & remove
1023 */
1024
imx219_get_regulators(struct imx219 * imx219)1025 static int imx219_get_regulators(struct imx219 *imx219)
1026 {
1027 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1028 unsigned int i;
1029
1030 for (i = 0; i < IMX219_NUM_SUPPLIES; i++)
1031 imx219->supplies[i].supply = imx219_supply_name[i];
1032
1033 return devm_regulator_bulk_get(&client->dev,
1034 IMX219_NUM_SUPPLIES,
1035 imx219->supplies);
1036 }
1037
1038 /* Verify chip ID */
imx219_identify_module(struct imx219 * imx219)1039 static int imx219_identify_module(struct imx219 *imx219)
1040 {
1041 struct i2c_client *client = v4l2_get_subdevdata(&imx219->sd);
1042 int ret;
1043 u64 val;
1044
1045 ret = cci_read(imx219->regmap, IMX219_REG_CHIP_ID, &val, NULL);
1046 if (ret)
1047 return dev_err_probe(&client->dev, ret,
1048 "failed to read chip id %x\n",
1049 IMX219_CHIP_ID);
1050
1051 if (val != IMX219_CHIP_ID)
1052 return dev_err_probe(&client->dev, -EIO,
1053 "chip id mismatch: %x!=%llx\n",
1054 IMX219_CHIP_ID, val);
1055
1056 return 0;
1057 }
1058
imx219_check_hwcfg(struct device * dev,struct imx219 * imx219)1059 static int imx219_check_hwcfg(struct device *dev, struct imx219 *imx219)
1060 {
1061 struct fwnode_handle *endpoint;
1062 struct v4l2_fwnode_endpoint ep_cfg = {
1063 .bus_type = V4L2_MBUS_CSI2_DPHY
1064 };
1065 unsigned long link_freq_bitmap;
1066 int ret = -EINVAL;
1067
1068 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
1069 if (!endpoint)
1070 return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
1071
1072 if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &ep_cfg)) {
1073 dev_err_probe(dev, -EINVAL, "could not parse endpoint\n");
1074 goto error_out;
1075 }
1076
1077 /* Check the number of MIPI CSI2 data lanes */
1078 if (ep_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
1079 ep_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1080 dev_err_probe(dev, -EINVAL,
1081 "only 2 or 4 data lanes are currently supported\n");
1082 goto error_out;
1083 }
1084 imx219->lanes = ep_cfg.bus.mipi_csi2.num_data_lanes;
1085
1086 /* Check the link frequency set in device tree */
1087 switch (imx219->lanes) {
1088 case 2:
1089 ret = v4l2_link_freq_to_bitmap(dev,
1090 ep_cfg.link_frequencies,
1091 ep_cfg.nr_of_link_frequencies,
1092 imx219_link_freq_menu,
1093 ARRAY_SIZE(imx219_link_freq_menu),
1094 &link_freq_bitmap);
1095 break;
1096 case 4:
1097 ret = v4l2_link_freq_to_bitmap(dev,
1098 ep_cfg.link_frequencies,
1099 ep_cfg.nr_of_link_frequencies,
1100 imx219_link_freq_4lane_menu,
1101 ARRAY_SIZE(imx219_link_freq_4lane_menu),
1102 &link_freq_bitmap);
1103
1104 if (!ret && (link_freq_bitmap & BIT(1))) {
1105 dev_warn(dev, "Link frequency of %d not supported, but has been incorrectly advertised previously\n",
1106 IMX219_DEFAULT_LINK_FREQ_4LANE_UNSUPPORTED);
1107 dev_warn(dev, "Using link frequency of %d\n",
1108 IMX219_DEFAULT_LINK_FREQ_4LANE);
1109 link_freq_bitmap |= BIT(0);
1110 }
1111 break;
1112 }
1113
1114 if (ret || !(link_freq_bitmap & BIT(0))) {
1115 ret = -EINVAL;
1116 dev_err_probe(dev, -EINVAL,
1117 "Link frequency not supported: %lld\n",
1118 ep_cfg.link_frequencies[0]);
1119 }
1120
1121 error_out:
1122 v4l2_fwnode_endpoint_free(&ep_cfg);
1123 fwnode_handle_put(endpoint);
1124
1125 return ret;
1126 }
1127
imx219_probe(struct i2c_client * client)1128 static int imx219_probe(struct i2c_client *client)
1129 {
1130 struct device *dev = &client->dev;
1131 struct imx219 *imx219;
1132 int ret;
1133
1134 imx219 = devm_kzalloc(&client->dev, sizeof(*imx219), GFP_KERNEL);
1135 if (!imx219)
1136 return -ENOMEM;
1137
1138 v4l2_i2c_subdev_init(&imx219->sd, client, &imx219_subdev_ops);
1139 imx219->sd.internal_ops = &imx219_internal_ops;
1140
1141 /* Check the hardware configuration in device tree */
1142 if (imx219_check_hwcfg(dev, imx219))
1143 return -EINVAL;
1144
1145 imx219->regmap = devm_cci_regmap_init_i2c(client, 16);
1146 if (IS_ERR(imx219->regmap))
1147 return dev_err_probe(dev, PTR_ERR(imx219->regmap),
1148 "failed to initialize CCI\n");
1149
1150 /* Get system clock (xclk) */
1151 imx219->xclk = devm_clk_get(dev, NULL);
1152 if (IS_ERR(imx219->xclk))
1153 return dev_err_probe(dev, PTR_ERR(imx219->xclk),
1154 "failed to get xclk\n");
1155
1156 imx219->xclk_freq = clk_get_rate(imx219->xclk);
1157 if (imx219->xclk_freq != IMX219_XCLK_FREQ)
1158 return dev_err_probe(dev, -EINVAL,
1159 "xclk frequency not supported: %d Hz\n",
1160 imx219->xclk_freq);
1161
1162 ret = imx219_get_regulators(imx219);
1163 if (ret)
1164 return dev_err_probe(dev, ret, "failed to get regulators\n");
1165
1166 /* Request optional enable pin */
1167 imx219->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1168 GPIOD_OUT_HIGH);
1169
1170 /*
1171 * The sensor must be powered for imx219_identify_module()
1172 * to be able to read the CHIP_ID register
1173 */
1174 ret = imx219_power_on(dev);
1175 if (ret)
1176 return ret;
1177
1178 ret = imx219_identify_module(imx219);
1179 if (ret)
1180 goto error_power_off;
1181
1182 /*
1183 * Sensor doesn't enter LP-11 state upon power up until and unless
1184 * streaming is started, so upon power up switch the modes to:
1185 * streaming -> standby
1186 */
1187 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1188 IMX219_MODE_STREAMING, NULL);
1189 if (ret < 0)
1190 goto error_power_off;
1191
1192 usleep_range(100, 110);
1193
1194 /* put sensor back to standby mode */
1195 ret = cci_write(imx219->regmap, IMX219_REG_MODE_SELECT,
1196 IMX219_MODE_STANDBY, NULL);
1197 if (ret < 0)
1198 goto error_power_off;
1199
1200 usleep_range(100, 110);
1201
1202 ret = imx219_init_controls(imx219);
1203 if (ret)
1204 goto error_power_off;
1205
1206 /* Initialize subdev */
1207 imx219->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1208 imx219->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1209
1210 /* Initialize source pad */
1211 imx219->pad.flags = MEDIA_PAD_FL_SOURCE;
1212
1213 ret = media_entity_pads_init(&imx219->sd.entity, 1, &imx219->pad);
1214 if (ret) {
1215 dev_err_probe(dev, ret, "failed to init entity pads\n");
1216 goto error_handler_free;
1217 }
1218
1219 imx219->sd.state_lock = imx219->ctrl_handler.lock;
1220 ret = v4l2_subdev_init_finalize(&imx219->sd);
1221 if (ret < 0) {
1222 dev_err_probe(dev, ret, "subdev init error\n");
1223 goto error_media_entity;
1224 }
1225
1226 pm_runtime_set_active(dev);
1227 pm_runtime_enable(dev);
1228
1229 ret = v4l2_async_register_subdev_sensor(&imx219->sd);
1230 if (ret < 0) {
1231 dev_err_probe(dev, ret,
1232 "failed to register sensor sub-device\n");
1233 goto error_subdev_cleanup;
1234 }
1235
1236 pm_runtime_idle(dev);
1237
1238 return 0;
1239
1240 error_subdev_cleanup:
1241 v4l2_subdev_cleanup(&imx219->sd);
1242 pm_runtime_disable(dev);
1243 pm_runtime_set_suspended(dev);
1244
1245 error_media_entity:
1246 media_entity_cleanup(&imx219->sd.entity);
1247
1248 error_handler_free:
1249 imx219_free_controls(imx219);
1250
1251 error_power_off:
1252 imx219_power_off(dev);
1253
1254 return ret;
1255 }
1256
imx219_remove(struct i2c_client * client)1257 static void imx219_remove(struct i2c_client *client)
1258 {
1259 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1260 struct imx219 *imx219 = to_imx219(sd);
1261
1262 v4l2_async_unregister_subdev(sd);
1263 v4l2_subdev_cleanup(sd);
1264 media_entity_cleanup(&sd->entity);
1265 imx219_free_controls(imx219);
1266
1267 pm_runtime_disable(&client->dev);
1268 if (!pm_runtime_status_suspended(&client->dev)) {
1269 imx219_power_off(&client->dev);
1270 pm_runtime_set_suspended(&client->dev);
1271 }
1272 }
1273
1274 static const struct of_device_id imx219_dt_ids[] = {
1275 { .compatible = "sony,imx219" },
1276 { /* sentinel */ }
1277 };
1278 MODULE_DEVICE_TABLE(of, imx219_dt_ids);
1279
1280 static const struct dev_pm_ops imx219_pm_ops = {
1281 SET_RUNTIME_PM_OPS(imx219_power_off, imx219_power_on, NULL)
1282 };
1283
1284 static struct i2c_driver imx219_i2c_driver = {
1285 .driver = {
1286 .name = "imx219",
1287 .of_match_table = imx219_dt_ids,
1288 .pm = &imx219_pm_ops,
1289 },
1290 .probe = imx219_probe,
1291 .remove = imx219_remove,
1292 };
1293
1294 module_i2c_driver(imx219_i2c_driver);
1295
1296 MODULE_AUTHOR("Dave Stevenson <[email protected]");
1297 MODULE_DESCRIPTION("Sony IMX219 sensor driver");
1298 MODULE_LICENSE("GPL v2");
1299